Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6202318 |
1 |
|
|
T1 |
17726 |
|
T3 |
3498 |
|
T4 |
28362 |
auto[1] |
9476373 |
1 |
|
|
T1 |
25458 |
|
T3 |
6590 |
|
T4 |
41090 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
15647568 |
1 |
|
|
T1 |
43101 |
|
T3 |
10029 |
|
T4 |
69329 |
triple_byte_access |
10309 |
1 |
|
|
T1 |
32 |
|
T3 |
11 |
|
T4 |
38 |
halfword_access |
10425 |
1 |
|
|
T1 |
27 |
|
T3 |
23 |
|
T4 |
44 |
byte_access |
10389 |
1 |
|
|
T1 |
24 |
|
T3 |
25 |
|
T4 |
41 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
6171195 |
1 |
|
|
T1 |
17643 |
|
T3 |
3439 |
|
T4 |
28239 |
auto[0] |
triple_byte_access |
10309 |
1 |
|
|
T1 |
32 |
|
T3 |
11 |
|
T4 |
38 |
auto[0] |
halfword_access |
10425 |
1 |
|
|
T1 |
27 |
|
T3 |
23 |
|
T4 |
44 |
auto[0] |
byte_access |
10389 |
1 |
|
|
T1 |
24 |
|
T3 |
25 |
|
T4 |
41 |
auto[1] |
word_access |
9476373 |
1 |
|
|
T1 |
25458 |
|
T3 |
6590 |
|
T4 |
41090 |