Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	12826845	1			T2	16059		T3	2433		T9	2391
all_values[1]	12826845	1			T2	16059		T3	2433		T9	2391
all_values[2]	12826845	1			T2	16059		T3	2433		T9	2391

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

426984

1

T2

596

T3

103

T9

804

auto[1]

38053551

1

T2

47581

T3

7196

T9

6369

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38272233

1

T2

47691

T3

6594

T9

7089

auto[1]

208302

1

T2

486

T3

705

T9

84

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	127164	1			T3	38		T9	543		T14	420
all_values[0]	auto[0]	auto[1]	1274	1			T3	6		T9	12		T14	6
all_values[0]	auto[1]	auto[0]	12630247	1			T2	15897		T3	2160		T9	1820
all_values[0]	auto[1]	auto[1]	68160	1			T2	162		T3	229		T9	16
all_values[1]	auto[0]	auto[0]	157390	1			T2	591		T3	52		T9	245
all_values[1]	auto[0]	auto[1]	924	1			T2	5		T3	7		T9	4
all_values[1]	auto[1]	auto[0]	12600021	1			T2	15306		T3	2146		T9	2118
all_values[1]	auto[1]	auto[1]	68510	1			T2	157		T3	228		T9	24
all_values[2]	auto[0]	auto[0]	139382	1			T28	7		T29	1		T42	3
all_values[2]	auto[0]	auto[1]	850	1			T28	1		T135	3		T163	7
all_values[2]	auto[1]	auto[0]	12618029	1			T2	15897		T3	2198		T9	2363
all_values[2]	auto[1]	auto[1]	68584	1			T2	162		T3	235		T9	28