Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51014 |
1 |
|
|
T1 |
2 |
|
T2 |
212 |
|
T3 |
304 |
auto[1] |
54220 |
1 |
|
|
T14 |
56 |
|
T18 |
4 |
|
T28 |
30 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
26273 |
1 |
|
|
T2 |
44 |
|
T3 |
76 |
|
T9 |
8 |
lower_val |
25826 |
1 |
|
|
T1 |
1 |
|
T2 |
38 |
|
T3 |
85 |
zero_val |
799 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
52638 |
1 |
|
|
T2 |
104 |
|
T3 |
144 |
|
T9 |
22 |
lower_val |
52590 |
1 |
|
|
T1 |
2 |
|
T2 |
108 |
|
T3 |
160 |
zero_val |
6 |
1 |
|
|
T27 |
2 |
|
T151 |
2 |
|
T152 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
6324 |
1 |
|
|
T2 |
24 |
|
T3 |
38 |
|
T9 |
2 |
higher_val |
higher_val |
auto[1] |
6819 |
1 |
|
|
T14 |
11 |
|
T28 |
4 |
|
T30 |
20 |
higher_val |
lower_val |
auto[0] |
6163 |
1 |
|
|
T2 |
20 |
|
T3 |
38 |
|
T9 |
6 |
higher_val |
lower_val |
auto[1] |
6966 |
1 |
|
|
T14 |
12 |
|
T28 |
2 |
|
T30 |
20 |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T27 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
6279 |
1 |
|
|
T2 |
25 |
|
T3 |
42 |
|
T9 |
9 |
lower_val |
higher_val |
auto[1] |
6649 |
1 |
|
|
T14 |
6 |
|
T28 |
6 |
|
T30 |
11 |
lower_val |
lower_val |
auto[0] |
6193 |
1 |
|
|
T1 |
1 |
|
T2 |
13 |
|
T3 |
43 |
lower_val |
lower_val |
auto[1] |
6702 |
1 |
|
|
T14 |
4 |
|
T28 |
1 |
|
T30 |
14 |
lower_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T151 |
1 |
|
T152 |
1 |
|
- |
- |
lower_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T27 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
319 |
1 |
|
|
T2 |
1 |
|
T15 |
1 |
|
T16 |
1 |
zero_val |
higher_val |
auto[1] |
76 |
1 |
|
|
T69 |
1 |
|
T27 |
1 |
|
T153 |
1 |
zero_val |
lower_val |
auto[0] |
330 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
1 |
zero_val |
lower_val |
auto[1] |
74 |
1 |
|
|
T28 |
1 |
|
T27 |
3 |
|
T153 |
1 |