Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	12826845	1			T2	16059		T3	2433		T9	2391
all_pins[1]	12826845	1			T2	16059		T3	2433		T9	2391
all_pins[2]	12826845	1			T2	16059		T3	2433		T9	2391

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	38124003	1			T2	48015		T3	7070		T9	7157
values[0x1]	356532	1			T2	162		T3	229		T9	16
transitions[0x0=>0x1]	354797	1			T2	162		T3	229		T9	16
transitions[0x1=>0x0]	354821	1			T2	162		T3	229		T9	16

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	12758685	1			T2	15897		T3	2204		T9	2375
all_pins[0]	values[0x1]	68160	1			T2	162		T3	229		T9	16
all_pins[0]	transitions[0x0=>0x1]	68142	1			T2	162		T3	229		T9	16
all_pins[0]	transitions[0x1=>0x0]	68	1			T44	2		T164	3		T165	6
all_pins[1]	values[0x0]	12826759	1			T2	16059		T3	2433		T9	2391
all_pins[1]	values[0x1]	86	1			T44	2		T164	3		T165	6
all_pins[1]	transitions[0x0=>0x1]	70	1			T44	2		T164	3		T165	6
all_pins[1]	transitions[0x1=>0x0]	288270	1			T14	120		T15	425		T30	266
all_pins[2]	values[0x0]	12538559	1			T2	16059		T3	2433		T9	2391
all_pins[2]	values[0x1]	288286	1			T14	120		T15	425		T30	266
all_pins[2]	transitions[0x0=>0x1]	286585	1			T14	120		T15	424		T30	265
all_pins[2]	transitions[0x1=>0x0]	66483	1			T2	162		T3	229		T9	16