Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14329680	1			T2	1271		T3	8649		T4	12079
all_values[1]	14329680	1			T2	1271		T3	8649		T4	12079
all_values[2]	14329680	1			T2	1271		T3	8649		T4	12079

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

525021

1

T2

528

T3

446

T4

184

auto[1]

42464019

1

T2

3285

T3

25501

T4

36053

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42769176

1

T2

3786

T3

25722

T4

35871

auto[1]

219864

1

T2

27

T3

225

T4

366

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	183202	1			T3	292		T4	90		T14	126
all_values[0]	auto[0]	auto[1]	1370	1			T3	8		T4	2		T14	2
all_values[0]	auto[1]	auto[0]	14073190	1			T2	1262		T3	8282		T4	11867
all_values[0]	auto[1]	auto[1]	71918	1			T2	9		T3	67		T4	120
all_values[1]	auto[0]	auto[0]	178550	1			T2	526		T3	49		T4	90
all_values[1]	auto[0]	auto[1]	1004	1			T2	2		T3	2		T4	2
all_values[1]	auto[1]	auto[0]	14077842	1			T2	736		T3	8525		T4	11867
all_values[1]	auto[1]	auto[1]	72284	1			T2	7		T3	73		T4	120
all_values[2]	auto[0]	auto[0]	159926	1			T3	91		T14	126		T71	32
all_values[2]	auto[0]	auto[1]	969	1			T3	4		T14	2		T71	3
all_values[2]	auto[1]	auto[0]	14096466	1			T2	1262		T3	8483		T4	11957
all_values[2]	auto[1]	auto[1]	72319	1			T2	9		T3	71		T4	122