Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55124 |
1 |
|
|
T2 |
2 |
|
T3 |
2 |
|
T4 |
158 |
auto[1] |
55710 |
1 |
|
|
T2 |
22 |
|
T3 |
98 |
|
T14 |
298 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
27210 |
1 |
|
|
T2 |
6 |
|
T3 |
28 |
|
T4 |
44 |
lower_val |
27589 |
1 |
|
|
T2 |
6 |
|
T3 |
26 |
|
T4 |
41 |
zero_val |
913 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
1 |
2 |
66.67 |
User Defined Bins for wait_timer_val
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
zero_val |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
55820 |
1 |
|
|
T2 |
10 |
|
T3 |
50 |
|
T4 |
88 |
lower_val |
55014 |
1 |
|
|
T2 |
14 |
|
T3 |
50 |
|
T4 |
70 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
6 |
12 |
66.67 |
6 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
* |
[zero_val] |
* |
-- |
-- |
6 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
6936 |
1 |
|
|
T4 |
26 |
|
T15 |
20 |
|
T17 |
52 |
higher_val |
higher_val |
auto[1] |
6904 |
1 |
|
|
T2 |
3 |
|
T3 |
12 |
|
T14 |
38 |
higher_val |
lower_val |
auto[0] |
6488 |
1 |
|
|
T4 |
18 |
|
T15 |
30 |
|
T17 |
50 |
higher_val |
lower_val |
auto[1] |
6882 |
1 |
|
|
T2 |
3 |
|
T3 |
16 |
|
T14 |
48 |
lower_val |
higher_val |
auto[0] |
6905 |
1 |
|
|
T4 |
28 |
|
T15 |
24 |
|
T17 |
50 |
lower_val |
higher_val |
auto[1] |
6927 |
1 |
|
|
T2 |
3 |
|
T3 |
13 |
|
T14 |
35 |
lower_val |
lower_val |
auto[0] |
6871 |
1 |
|
|
T3 |
1 |
|
T4 |
13 |
|
T15 |
29 |
lower_val |
lower_val |
auto[1] |
6886 |
1 |
|
|
T2 |
3 |
|
T3 |
12 |
|
T14 |
34 |
zero_val |
higher_val |
auto[0] |
352 |
1 |
|
|
T4 |
1 |
|
T14 |
1 |
|
T17 |
1 |
zero_val |
higher_val |
auto[1] |
89 |
1 |
|
|
T23 |
2 |
|
T144 |
1 |
|
T24 |
1 |
zero_val |
lower_val |
auto[0] |
380 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T15 |
1 |
zero_val |
lower_val |
auto[1] |
92 |
1 |
|
|
T23 |
2 |
|
T144 |
5 |
|
T24 |
1 |