Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	14329680	1			T2	1271		T3	8649		T4	12079
all_pins[1]	14329680	1			T2	1271		T3	8649		T4	12079
all_pins[2]	14329680	1			T2	1271		T3	8649		T4	12079

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	42612181	1			T2	3804		T3	25880		T4	36117
values[0x1]	376859	1			T2	9		T3	67		T4	120
transitions[0x0=>0x1]	374928	1			T2	9		T3	67		T4	120
transitions[0x1=>0x0]	374953	1			T2	9		T3	67		T4	120

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	14257762	1			T2	1262		T3	8582		T4	11959
all_pins[0]	values[0x1]	71918	1			T2	9		T3	67		T4	120
all_pins[0]	transitions[0x0=>0x1]	71909	1			T2	9		T3	67		T4	120
all_pins[0]	transitions[0x1=>0x0]	54	1			T24	4		T157	3		T110	2
all_pins[1]	values[0x0]	14329617	1			T2	1271		T3	8649		T4	12079
all_pins[1]	values[0x1]	63	1			T24	4		T157	3		T110	2
all_pins[1]	transitions[0x0=>0x1]	50	1			T24	4		T157	3		T110	1
all_pins[1]	transitions[0x1=>0x0]	304865	1			T23	3386		T27	454		T28	780
all_pins[2]	values[0x0]	14024802	1			T2	1271		T3	8649		T4	12079
all_pins[2]	values[0x1]	304878	1			T23	3386		T27	454		T28	780
all_pins[2]	transitions[0x0=>0x1]	302969	1			T23	3368		T27	454		T28	780
all_pins[2]	transitions[0x1=>0x0]	70034	1			T2	9		T3	67		T4	120