Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6232655 |
1 |
|
|
T2 |
1664 |
|
T3 |
9124 |
|
T4 |
12425 |
auto[1] |
9551460 |
1 |
|
|
T2 |
2378 |
|
T3 |
13354 |
|
T4 |
17472 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
15751447 |
1 |
|
|
T2 |
4035 |
|
T3 |
22436 |
|
T4 |
29836 |
triple_byte_access |
11050 |
1 |
|
|
T2 |
5 |
|
T3 |
16 |
|
T4 |
20 |
halfword_access |
10800 |
1 |
|
|
T2 |
1 |
|
T3 |
11 |
|
T4 |
22 |
byte_access |
10818 |
1 |
|
|
T2 |
1 |
|
T3 |
15 |
|
T4 |
19 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
6199987 |
1 |
|
|
T2 |
1657 |
|
T3 |
9082 |
|
T4 |
12364 |
auto[0] |
triple_byte_access |
11050 |
1 |
|
|
T2 |
5 |
|
T3 |
16 |
|
T4 |
20 |
auto[0] |
halfword_access |
10800 |
1 |
|
|
T2 |
1 |
|
T3 |
11 |
|
T4 |
22 |
auto[0] |
byte_access |
10818 |
1 |
|
|
T2 |
1 |
|
T3 |
15 |
|
T4 |
19 |
auto[1] |
word_access |
9551460 |
1 |
|
|
T2 |
2378 |
|
T3 |
13354 |
|
T4 |
17472 |