Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 272 1 T110 4 T111 4 T112 7
all_values[1] 272 1 T110 4 T111 4 T112 7
all_values[2] 272 1 T110 4 T111 4 T112 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 451 1 T110 4 T111 8 T112 16
auto[1] 365 1 T110 8 T111 4 T112 5


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 368 1 T110 6 T111 3 T112 5
auto[1] 448 1 T110 6 T111 9 T112 16


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 470 1 T110 8 T111 6 T112 10
auto[1] 346 1 T110 4 T111 6 T112 11


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 55 1 T112 2 T152 2 T153 1
all_values[0] auto[0] auto[0] auto[1] 26 1 T112 1 T152 1 T153 1
all_values[0] auto[0] auto[1] auto[0] 57 1 T110 3 T152 1 T142 1
all_values[0] auto[0] auto[1] auto[1] 21 1 T111 1 T112 1 T152 1
all_values[0] auto[1] auto[0] auto[1] 71 1 T110 1 T111 3 T112 3
all_values[0] auto[1] auto[1] auto[1] 42 1 T152 1 T142 2 T154 1
all_values[1] auto[0] auto[0] auto[0] 74 1 T111 2 T152 1 T141 2
all_values[1] auto[0] auto[1] auto[0] 81 1 T110 2 T111 1 T112 2
all_values[1] auto[1] auto[0] auto[1] 64 1 T110 1 T111 1 T112 3
all_values[1] auto[1] auto[1] auto[1] 53 1 T110 1 T112 2 T142 2
all_values[2] auto[0] auto[0] auto[0] 67 1 T110 1 T112 1 T152 2
all_values[2] auto[0] auto[0] auto[1] 31 1 T111 1 T112 3 T152 1
all_values[2] auto[0] auto[1] auto[0] 34 1 T152 1 T155 2 T156 2
all_values[2] auto[0] auto[1] auto[1] 24 1 T110 2 T111 1 T141 1
all_values[2] auto[1] auto[0] auto[1] 63 1 T110 1 T111 1 T112 3
all_values[2] auto[1] auto[1] auto[1] 53 1 T111 1 T152 1 T142 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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