Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	16475559	1			T1	10131		T2	86		T3	70
all_values[1]	16475559	1			T1	10131		T2	86		T3	70
all_values[2]	16475559	1			T1	10131		T2	86		T3	70

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

484661

1

T1

221

T2

98

T3

8

auto[1]

48942016

1

T1

30172

T2

160

T3

202

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49204890

1

T1

30117

T2

240

T3

198

auto[1]

221787

1

T1

276

T2

18

T3

12

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	162988	1			T2	80		T12	4		T15	62
all_values[0]	auto[0]	auto[1]	1171	1			T2	6		T12	2		T15	6
all_values[0]	auto[1]	auto[0]	16238642	1			T1	10039		T3	66		T12	73
all_values[0]	auto[1]	auto[1]	72758	1			T1	92		T3	4		T12	2
all_values[1]	auto[0]	auto[0]	141066	1			T2	4		T3	7		T12	10
all_values[1]	auto[0]	auto[1]	966	1			T2	2		T3	1		T12	3
all_values[1]	auto[1]	auto[0]	16260564	1			T1	10039		T2	76		T3	59
all_values[1]	auto[1]	auto[1]	72963	1			T1	92		T2	4		T3	3
all_values[2]	auto[0]	auto[0]	177633	1			T1	220		T2	4		T12	77
all_values[2]	auto[0]	auto[1]	837	1			T1	1		T2	2		T12	4
all_values[2]	auto[1]	auto[0]	16223997	1			T1	9819		T2	76		T3	66
all_values[2]	auto[1]	auto[1]	73092	1			T1	91		T2	4		T3	4