Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	16475559	1			T1	10131		T2	86		T3	70
all_pins[1]	16475559	1			T1	10131		T2	86		T3	70
all_pins[2]	16475559	1			T1	10131		T2	86		T3	70

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	49070247	1			T1	30301		T2	258		T3	206
values[0x1]	356430	1			T1	92		T3	4		T12	2
transitions[0x0=>0x1]	354699	1			T1	92		T3	4		T12	2
transitions[0x1=>0x0]	354729	1			T1	92		T3	4		T12	2

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	16402801	1			T1	10039		T2	86		T3	66
all_pins[0]	values[0x1]	72758	1			T1	92		T3	4		T12	2
all_pins[0]	transitions[0x0=>0x1]	72745	1			T1	92		T3	4		T12	2
all_pins[0]	transitions[0x1=>0x0]	57	1			T163	4		T164	4		T165	2
all_pins[1]	values[0x0]	16475489	1			T1	10131		T2	86		T3	70
all_pins[1]	values[0x1]	70	1			T163	4		T164	4		T165	2
all_pins[1]	transitions[0x0=>0x1]	58	1			T163	4		T164	4		T165	2
all_pins[1]	transitions[0x1=>0x0]	283590	1			T36	5879		T51	94		T37	9799
all_pins[2]	values[0x0]	16191957	1			T1	10131		T2	86		T3	70
all_pins[2]	values[0x1]	283602	1			T36	5879		T51	94		T37	9799
all_pins[2]	transitions[0x0=>0x1]	281896	1			T36	5844		T51	94		T37	9731
all_pins[2]	transitions[0x1=>0x0]	71082	1			T1	92		T3	4		T12	2