Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	656	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5582	1			T1	8		T21	3		T22	3
len_601_800	12204	1			T1	23		T16	1		T21	5
len_401_600	8415	1			T1	20		T16	1		T21	4
len_201_400	4745	1			T1	4		T22	1		T36	5
len_65_200	7260	1			T1	5		T57	6		T71	79
len_min_for_xof_require_squeeze	77	1			T71	1		T75	1		T47	1
len_keccak_block_sizes[72]	76	1			T184	1		T24	1		T185	5
len_keccak_block_sizes[104]	74	1			T75	1		T186	1		T187	1
len_keccak_block_sizes[136]	54	1			T71	2		T75	1		T185	5
len_keccak_block_sizes[144]	48	1			T71	1		T75	2		T185	5
len_keccak_block_sizes[168]	43	1			T71	1		T36	1		T188	2
len_datapath_width	1003	1			T1	1		T57	2		T71	3
len_2_63	14540	1			T1	2		T2	3		T3	3
len_1	67	1			T71	1		T75	2		T103	1