Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15055165	1			T1	81		T2	71		T3	4
all_values[1]	15055165	1			T1	81		T2	71		T3	4
all_values[2]	15055165	1			T1	81		T2	71		T3	4

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

539797

1

T2

7

T3

4

T14

37

auto[1]

44625698

1

T1

243

T2

206

T3

8

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44936334

1

T1

231

T2

198

T3

12

auto[1]

229161

1

T1

12

T2

15

T13

315

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Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	154990	1			T2	5		T14	8		T16	1
all_values[0]	auto[0]	auto[1]	1178	1			T2	2		T14	2		T90	4
all_values[0]	auto[1]	auto[0]	14823788	1			T1	77		T2	61		T3	4
all_values[0]	auto[1]	auto[1]	75209	1			T1	4		T2	3		T13	105
all_values[1]	auto[0]	auto[0]	172372	1			T3	4		T14	22		T16	2
all_values[1]	auto[0]	auto[1]	926	1			T14	5		T17	4		T91	1
all_values[1]	auto[1]	auto[0]	14806406	1			T1	77		T2	66		T12	27
all_values[1]	auto[1]	auto[1]	75461	1			T1	4		T2	5		T13	105
all_values[2]	auto[0]	auto[0]	209331	1			T16	139		T90	6		T91	9
all_values[2]	auto[0]	auto[1]	1000	1			T16	2		T90	5		T91	6
all_values[2]	auto[1]	auto[0]	14769447	1			T1	77		T2	66		T3	4
all_values[2]	auto[1]	auto[1]	75387	1			T1	4		T2	5		T13	105