Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56404 |
1 |
|
|
T1 |
2 |
|
T2 |
6 |
|
T3 |
2 |
auto[1] |
59274 |
1 |
|
|
T1 |
4 |
|
T12 |
50 |
|
T13 |
144 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
28356 |
1 |
|
|
T12 |
8 |
|
T13 |
30 |
|
T14 |
6 |
lower_val |
28762 |
1 |
|
|
T1 |
3 |
|
T2 |
3 |
|
T12 |
18 |
zero_val |
872 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
57558 |
1 |
|
|
T2 |
2 |
|
T12 |
26 |
|
T13 |
60 |
lower_val |
58118 |
1 |
|
|
T1 |
6 |
|
T2 |
4 |
|
T3 |
2 |
zero_val |
2 |
1 |
|
|
T152 |
2 |
|
- |
- |
|
- |
- |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
5 |
13 |
72.22 |
5 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[lower_val , zero_val] |
[zero_val] |
* |
-- |
-- |
4 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
6776 |
1 |
|
|
T16 |
2 |
|
T90 |
20 |
|
T91 |
28 |
higher_val |
higher_val |
auto[1] |
7284 |
1 |
|
|
T12 |
6 |
|
T13 |
9 |
|
T14 |
3 |
higher_val |
lower_val |
auto[0] |
7022 |
1 |
|
|
T16 |
2 |
|
T90 |
28 |
|
T91 |
27 |
higher_val |
lower_val |
auto[1] |
7273 |
1 |
|
|
T12 |
2 |
|
T13 |
21 |
|
T14 |
3 |
higher_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T152 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
6785 |
1 |
|
|
T2 |
1 |
|
T13 |
1 |
|
T16 |
2 |
lower_val |
higher_val |
auto[1] |
7472 |
1 |
|
|
T12 |
9 |
|
T13 |
14 |
|
T14 |
2 |
lower_val |
lower_val |
auto[0] |
6941 |
1 |
|
|
T2 |
2 |
|
T16 |
4 |
|
T90 |
16 |
lower_val |
lower_val |
auto[1] |
7564 |
1 |
|
|
T1 |
3 |
|
T12 |
9 |
|
T13 |
27 |
zero_val |
higher_val |
auto[0] |
351 |
1 |
|
|
T12 |
1 |
|
T13 |
1 |
|
T14 |
1 |
zero_val |
higher_val |
auto[1] |
79 |
1 |
|
|
T49 |
2 |
|
T168 |
1 |
|
T111 |
3 |
zero_val |
lower_val |
auto[0] |
352 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
lower_val |
auto[1] |
90 |
1 |
|
|
T62 |
2 |
|
T94 |
2 |
|
T168 |
1 |