Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::error_cg

Group : kmac_env_pkg::kmac_env_cov::error_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
89.66	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::error_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	3	18	85.71
Crosses	8	0	8	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::error_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cmd	4	0	4	100.00	100	1	1	0
kmac_err_code	9	3	6	66.67	100	1	1	0
mode	3	0	3	100.00	100	1	1	0
strength	5	0	5	100.00	100	1	1	0

Crosses for Group kmac_env_pkg::kmac_env_cov::error_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_invalid_cmd_in_app_active	1	0	1	100.00	100	1	1	0
all_invalid_mode_strength_cfgs	7	0	7	100.00	100	1	1	0

Summary for Variable cmd

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cmd

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[CmdNone]	0	Excluded
ignore	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[CmdStart]	610	1			T30	7		T42	2		T26	17
auto[CmdProcess]	94	1			T26	2		T27	1		T28	3
auto[CmdManualRun]	328	1			T26	10		T27	5		T28	15
auto[CmdDone]	1261	1			T30	15		T42	7		T26	22

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Summary for Variable kmac_err_code

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	9	3	6	66.67

Automatically Generated Bins for kmac_err_code

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[ErrFatalError]	0	1	1
auto[ErrPackerIntegrity]	0	1	1
auto[ErrMsgFifoIntegrity]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[ErrNone]	0	Excluded
auto[ErrWaitTimerExpired]	0	Illegal
auto[ErrIncorrectEntropyMode]	0	Illegal
auto[ErrSwHashingWithoutEntropyReady]	0	Illegal
auto[ErrShadowRegUpdate]	0	Illegal
il	0	Illegal
ignore	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ErrKeyNotValid]	50	1			T4	1		T20	1		T21	1
auto[ErrSwPushedMsgFifo]	49	1			T30	1		T27	2		T28	1
auto[ErrSwIssuedCmdInAppActive]	45	1			T26	2		T27	1		T28	1
auto[ErrUnexpectedModeStrength]	547	1			T30	7		T42	3		T26	12
auto[ErrIncorrectFunctionName]	524	1			T30	7		T42	2		T26	15
auto[ErrSwCmdSequence]	1129	1			T30	7		T42	4		T26	22

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Summary for Variable mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[Sha3]	358	1			T30	1		T26	10		T27	5
auto[Shake]	370	1			T30	7		T26	2		T27	11
auto[CShake]	1566	1			T30	14		T42	9		T26	39

---

Summary for Variable strength

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for strength

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[L128]	803	1			T30	3		T42	1		T26	24
auto[L224]	252	1			T30	9		T26	6		T27	8
auto[L256]	760	1			T4	1		T20	1		T30	7
auto[L384]	272	1			T30	3		T42	1		T27	5
auto[L512]	257	1			T42	6		T26	3		T27	4

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Summary for Cross all_invalid_cmd_in_app_active

Samples crossed: kmac_err_code cmd

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for all_invalid_cmd_in_app_active

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

invalid_cmds

45

1

T26

2

T27

1

T28

1

---

Summary for Cross all_invalid_mode_strength_cfgs

Samples crossed: kmac_err_code mode strength

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	7	0	7	100.00

User Defined Cross Bins for all_invalid_mode_strength_cfgs

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha3_128_cfgs	156	1			T30	1		T26	5		T27	2
shake_224_invalid_cfg	35	1			T30	2		T27	1		T28	1
shake_384_invalid_cfg	24	1			T27	3		T28	2		T175	1
shake_512_invalid_cfg	27	1			T176	1		T177	1		T178	1
cshake_224_invalid_cfg	95	1			T30	3		T26	4		T27	3
cshake_384_invalid_cfg	108	1			T30	1		T42	1		T28	3
cshake_512_invalid_cfg	102	1			T42	2		T26	3		T27	2