Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	15055165	1			T1	81		T2	71		T3	4
all_pins[1]	15055165	1			T1	81		T2	71		T3	4
all_pins[2]	15055165	1			T1	81		T2	71		T3	4

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	44818321	1			T1	239		T2	210		T3	12
values[0x1]	347174	1			T1	4		T2	3		T13	105
transitions[0x0=>0x1]	345512	1			T1	4		T2	3		T13	105
transitions[0x1=>0x0]	345543	1			T1	4		T2	3		T13	105

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	14979956	1			T1	77		T2	68		T3	4
all_pins[0]	values[0x1]	75209	1			T1	4		T2	3		T13	105
all_pins[0]	transitions[0x0=>0x1]	75198	1			T1	4		T2	3		T13	105
all_pins[0]	transitions[0x1=>0x0]	70	1			T51	2		T52	3		T54	2
all_pins[1]	values[0x0]	15055084	1			T1	81		T2	71		T3	4
all_pins[1]	values[0x1]	81	1			T51	2		T52	3		T54	2
all_pins[1]	transitions[0x0=>0x1]	66	1			T51	2		T52	3		T54	2
all_pins[1]	transitions[0x1=>0x0]	271869	1			T30	301		T36	7232		T37	9874
all_pins[2]	values[0x0]	14783281	1			T1	81		T2	71		T3	4
all_pins[2]	values[0x1]	271884	1			T30	301		T36	7232		T37	9874
all_pins[2]	transitions[0x0=>0x1]	270248	1			T30	301		T36	7179		T37	9799
all_pins[2]	transitions[0x1=>0x0]	73604	1			T1	4		T2	3		T13	105