Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 287 1 T127 4 T128 4 T179 4
all_values[1] 287 1 T127 4 T128 4 T179 4
all_values[2] 287 1 T127 4 T128 4 T179 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 452 1 T127 9 T128 7 T179 7
auto[1] 409 1 T127 3 T128 5 T179 5


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 362 1 T127 5 T128 5 T179 3
auto[1] 499 1 T127 7 T128 7 T179 9


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 499 1 T127 8 T128 6 T179 6
auto[1] 362 1 T127 4 T128 6 T179 6


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 57 1 T128 2 T166 3 T180 2
all_values[0] auto[0] auto[0] auto[1] 28 1 T127 1 T179 1 T181 1
all_values[0] auto[0] auto[1] auto[0] 53 1 T128 2 T166 1 T182 2
all_values[0] auto[0] auto[1] auto[1] 33 1 T127 1 T180 2 T183 1
all_values[0] auto[1] auto[0] auto[1] 67 1 T179 3 T166 3 T180 2
all_values[0] auto[1] auto[1] auto[1] 49 1 T127 2 T180 1 T182 1
all_values[1] auto[0] auto[0] auto[0] 90 1 T127 3 T128 1 T179 1
all_values[1] auto[0] auto[1] auto[0] 75 1 T179 1 T180 1 T182 4
all_values[1] auto[1] auto[0] auto[1] 62 1 T127 1 T128 1 T179 2
all_values[1] auto[1] auto[1] auto[1] 60 1 T128 2 T166 1 T180 1
all_values[2] auto[0] auto[0] auto[0] 46 1 T127 2 T182 1 T184 5
all_values[2] auto[0] auto[0] auto[1] 33 1 T127 1 T180 3 T182 1
all_values[2] auto[0] auto[1] auto[0] 41 1 T179 1 T166 4 T182 1
all_values[2] auto[0] auto[1] auto[1] 43 1 T128 1 T179 2 T166 1
all_values[2] auto[1] auto[0] auto[1] 69 1 T127 1 T128 3 T180 4
all_values[2] auto[1] auto[1] auto[1] 55 1 T179 1 T166 2 T182 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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