Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	16600953	1			T1	87		T2	68		T12	85
all_values[1]	16600953	1			T1	87		T2	68		T12	85
all_values[2]	16600953	1			T1	87		T2	68		T12	85

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

580771

1

T1

12

T12

85

T15

18

auto[1]

49222088

1

T1

249

T2

204

T12

170

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49588200

1

T1

249

T2

195

T12

237

auto[1]

214659

1

T1

12

T2

9

T12

18

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	187186	1			T12	79		T17	4		T35	5
all_values[0]	auto[0]	auto[1]	1334	1			T12	6		T17	2		T174	2
all_values[0]	auto[1]	auto[0]	16342214	1			T1	83		T2	65		T13	4994
all_values[0]	auto[1]	auto[1]	70219	1			T1	4		T2	3		T13	53
all_values[1]	auto[0]	auto[0]	210212	1			T1	5		T15	10		T16	5
all_values[1]	auto[0]	auto[1]	1038	1			T1	1		T15	2		T16	1
all_values[1]	auto[1]	auto[0]	16319188	1			T1	78		T2	65		T12	79
all_values[1]	auto[1]	auto[1]	70515	1			T1	3		T2	3		T12	6
all_values[2]	auto[0]	auto[0]	180006	1			T1	5		T15	5		T16	81
all_values[2]	auto[0]	auto[1]	995	1			T1	1		T15	1		T16	5
all_values[2]	auto[1]	auto[0]	16349394	1			T1	78		T2	65		T12	79
all_values[2]	auto[1]	auto[1]	70558	1			T1	3		T2	3		T12	6