Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50138 |
1 |
|
|
T1 |
2 |
|
T2 |
6 |
|
T4 |
2 |
auto[1] |
59432 |
1 |
|
|
T1 |
4 |
|
T13 |
142 |
|
T14 |
132 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
27164 |
1 |
|
|
T1 |
4 |
|
T2 |
2 |
|
T13 |
40 |
lower_val |
26596 |
1 |
|
|
T12 |
3 |
|
T13 |
32 |
|
T14 |
27 |
zero_val |
885 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
1 |
2 |
66.67 |
User Defined Bins for wait_timer_val
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
zero_val |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
54888 |
1 |
|
|
T1 |
2 |
|
T2 |
4 |
|
T4 |
2 |
lower_val |
54682 |
1 |
|
|
T1 |
4 |
|
T2 |
2 |
|
T12 |
6 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
6 |
12 |
66.67 |
6 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
* |
[zero_val] |
* |
-- |
-- |
6 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
6204 |
1 |
|
|
T2 |
2 |
|
T14 |
1 |
|
T16 |
1 |
higher_val |
higher_val |
auto[1] |
7432 |
1 |
|
|
T1 |
1 |
|
T13 |
24 |
|
T14 |
23 |
higher_val |
lower_val |
auto[0] |
6047 |
1 |
|
|
T1 |
1 |
|
T13 |
1 |
|
T5 |
2 |
higher_val |
lower_val |
auto[1] |
7481 |
1 |
|
|
T1 |
2 |
|
T13 |
15 |
|
T14 |
20 |
lower_val |
higher_val |
auto[0] |
6125 |
1 |
|
|
T16 |
3 |
|
T80 |
14 |
|
T81 |
20 |
lower_val |
higher_val |
auto[1] |
7245 |
1 |
|
|
T13 |
17 |
|
T14 |
12 |
|
T35 |
10 |
lower_val |
lower_val |
auto[0] |
6016 |
1 |
|
|
T12 |
3 |
|
T16 |
1 |
|
T5 |
2 |
lower_val |
lower_val |
auto[1] |
7210 |
1 |
|
|
T13 |
15 |
|
T14 |
15 |
|
T35 |
10 |
zero_val |
higher_val |
auto[0] |
341 |
1 |
|
|
T4 |
1 |
|
T14 |
1 |
|
T15 |
1 |
zero_val |
higher_val |
auto[1] |
96 |
1 |
|
|
T77 |
1 |
|
T111 |
2 |
|
T160 |
2 |
zero_val |
lower_val |
auto[0] |
333 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T12 |
1 |
zero_val |
lower_val |
auto[1] |
115 |
1 |
|
|
T77 |
1 |
|
T78 |
2 |
|
T161 |
1 |