Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	16600953	1			T1	87		T2	68		T12	85
all_pins[1]	16600953	1			T1	87		T2	68		T12	85
all_pins[2]	16600953	1			T1	87		T2	68		T12	85

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	49442964	1			T1	257		T2	201		T12	255
values[0x1]	359895	1			T1	4		T2	3		T13	53
transitions[0x0=>0x1]	358122	1			T1	4		T2	3		T13	53
transitions[0x1=>0x0]	358145	1			T1	4		T2	3		T13	53

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	16530734	1			T1	83		T2	65		T12	85
all_pins[0]	values[0x1]	70219	1			T1	4		T2	3		T13	53
all_pins[0]	transitions[0x0=>0x1]	70208	1			T1	4		T2	3		T13	53
all_pins[0]	transitions[0x1=>0x0]	77	1			T47	3		T175	3		T176	2
all_pins[1]	values[0x0]	16600865	1			T1	87		T2	68		T12	85
all_pins[1]	values[0x1]	88	1			T47	3		T175	3		T176	2
all_pins[1]	transitions[0x0=>0x1]	76	1			T47	3		T175	3		T176	2
all_pins[1]	transitions[0x1=>0x0]	289576	1			T14	6637		T27	1441		T34	6528
all_pins[2]	values[0x0]	16311365	1			T1	87		T2	68		T12	85
all_pins[2]	values[0x1]	289588	1			T14	6637		T27	1441		T34	6528
all_pins[2]	transitions[0x0=>0x1]	287838	1			T14	6586		T27	1428		T34	6486
all_pins[2]	transitions[0x1=>0x0]	68492	1			T1	4		T2	3		T13	53