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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.24 95.89 92.27 100.00 68.60 94.11 98.84 96.01


Total test records in report: 879
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T760 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.651305112 Aug 25 07:28:05 AM UTC 24 Aug 25 07:28:08 AM UTC 24 91304395 ps
T761 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.2125432333 Aug 25 07:28:03 AM UTC 24 Aug 25 07:28:08 AM UTC 24 389985329 ps
T762 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.1208685005 Aug 25 07:28:05 AM UTC 24 Aug 25 07:28:08 AM UTC 24 40216285 ps
T763 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.1342067939 Aug 25 07:28:06 AM UTC 24 Aug 25 07:28:09 AM UTC 24 14309182 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.3734388034 Aug 25 07:28:05 AM UTC 24 Aug 25 07:28:10 AM UTC 24 552899419 ps
T764 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.1121750190 Aug 25 07:28:07 AM UTC 24 Aug 25 07:28:10 AM UTC 24 33611338 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.3762596145 Aug 25 07:28:05 AM UTC 24 Aug 25 07:28:10 AM UTC 24 159552467 ps
T765 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.3034154036 Aug 25 07:28:07 AM UTC 24 Aug 25 07:28:11 AM UTC 24 48171298 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.2939939416 Aug 25 07:28:05 AM UTC 24 Aug 25 07:28:11 AM UTC 24 205537423 ps
T766 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.3107491419 Aug 25 07:28:09 AM UTC 24 Aug 25 07:28:12 AM UTC 24 343497077 ps
T767 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.3346526937 Aug 25 07:28:11 AM UTC 24 Aug 25 07:28:13 AM UTC 24 14407489 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.4116218096 Aug 25 07:28:10 AM UTC 24 Aug 25 07:28:13 AM UTC 24 52340560 ps
T768 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.1649712159 Aug 25 07:28:09 AM UTC 24 Aug 25 07:28:13 AM UTC 24 72937678 ps
T769 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.221100305 Aug 25 07:28:12 AM UTC 24 Aug 25 07:28:14 AM UTC 24 58265401 ps
T770 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.3993780894 Aug 25 07:28:10 AM UTC 24 Aug 25 07:28:15 AM UTC 24 101942001 ps
T771 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.1282463120 Aug 25 07:28:12 AM UTC 24 Aug 25 07:28:15 AM UTC 24 61535075 ps
T772 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3813278972 Aug 25 07:28:12 AM UTC 24 Aug 25 07:28:16 AM UTC 24 166087854 ps
T773 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.1245330068 Aug 25 07:28:15 AM UTC 24 Aug 25 07:28:18 AM UTC 24 15466576 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.959968064 Aug 25 07:28:11 AM UTC 24 Aug 25 07:28:18 AM UTC 24 1346263117 ps
T774 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.600622621 Aug 25 07:28:16 AM UTC 24 Aug 25 07:28:18 AM UTC 24 77894109 ps
T775 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.900634163 Aug 25 07:28:15 AM UTC 24 Aug 25 07:28:18 AM UTC 24 92801743 ps
T776 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.802080979 Aug 25 07:28:15 AM UTC 24 Aug 25 07:28:19 AM UTC 24 409736386 ps
T777 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.2270913089 Aug 25 07:27:47 AM UTC 24 Aug 25 07:28:20 AM UTC 24 2610682554 ps
T778 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2849255143 Aug 25 07:28:17 AM UTC 24 Aug 25 07:28:20 AM UTC 24 39585113 ps
T779 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.1415718709 Aug 25 07:28:17 AM UTC 24 Aug 25 07:28:20 AM UTC 24 117428223 ps
T780 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.2556134880 Aug 25 07:28:16 AM UTC 24 Aug 25 07:28:21 AM UTC 24 109296792 ps
T781 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.1041811736 Aug 25 07:28:19 AM UTC 24 Aug 25 07:28:21 AM UTC 24 31997600 ps
T782 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3530711677 Aug 25 07:28:15 AM UTC 24 Aug 25 07:28:22 AM UTC 24 795065883 ps
T783 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.761332127 Aug 25 07:28:20 AM UTC 24 Aug 25 07:28:23 AM UTC 24 42972611 ps
T784 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.829941834 Aug 25 07:28:19 AM UTC 24 Aug 25 07:28:24 AM UTC 24 146435756 ps
T785 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.577397571 Aug 25 07:28:21 AM UTC 24 Aug 25 07:28:24 AM UTC 24 28302643 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.1642004416 Aug 25 07:28:15 AM UTC 24 Aug 25 07:28:24 AM UTC 24 2180774782 ps
T786 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.3461601853 Aug 25 07:28:19 AM UTC 24 Aug 25 07:28:25 AM UTC 24 995642876 ps
T787 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.4276586050 Aug 25 07:28:21 AM UTC 24 Aug 25 07:28:25 AM UTC 24 227543650 ps
T788 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.4151281665 Aug 25 07:28:21 AM UTC 24 Aug 25 07:28:25 AM UTC 24 222775782 ps
T789 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.1546925900 Aug 25 07:28:23 AM UTC 24 Aug 25 07:28:26 AM UTC 24 39415844 ps
T790 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.3589007159 Aug 25 07:28:22 AM UTC 24 Aug 25 07:28:26 AM UTC 24 34136394 ps
T791 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3489977272 Aug 25 07:28:21 AM UTC 24 Aug 25 07:28:26 AM UTC 24 114985504 ps
T792 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.74486215 Aug 25 07:28:25 AM UTC 24 Aug 25 07:28:27 AM UTC 24 19416284 ps
T793 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.2930117864 Aug 25 07:28:25 AM UTC 24 Aug 25 07:28:28 AM UTC 24 33981244 ps
T794 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.1510517465 Aug 25 07:28:19 AM UTC 24 Aug 25 07:28:28 AM UTC 24 263528598 ps
T795 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1312903792 Aug 25 07:28:26 AM UTC 24 Aug 25 07:28:28 AM UTC 24 17022526 ps
T796 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.1556413061 Aug 25 07:28:41 AM UTC 24 Aug 25 07:28:44 AM UTC 24 18179691 ps
T797 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.587100050 Aug 25 07:28:26 AM UTC 24 Aug 25 07:28:29 AM UTC 24 149553021 ps
T798 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.3431505660 Aug 25 07:28:27 AM UTC 24 Aug 25 07:28:29 AM UTC 24 18552081 ps
T799 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.2561715138 Aug 25 07:28:27 AM UTC 24 Aug 25 07:28:30 AM UTC 24 21784719 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.1920222545 Aug 25 07:28:22 AM UTC 24 Aug 25 07:28:31 AM UTC 24 4757794341 ps
T800 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2674261974 Aug 25 07:28:26 AM UTC 24 Aug 25 07:28:31 AM UTC 24 131241515 ps
T801 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.1972895734 Aug 25 07:28:27 AM UTC 24 Aug 25 07:28:32 AM UTC 24 57860211 ps
T802 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1151754579 Aug 25 07:28:29 AM UTC 24 Aug 25 07:28:32 AM UTC 24 21244868 ps
T803 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.3207476629 Aug 25 07:28:27 AM UTC 24 Aug 25 07:28:33 AM UTC 24 213797760 ps
T804 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.1123080689 Aug 25 07:28:29 AM UTC 24 Aug 25 07:28:33 AM UTC 24 58132520 ps
T805 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.159952121 Aug 25 07:28:31 AM UTC 24 Aug 25 07:28:33 AM UTC 24 19883373 ps
T806 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.2173611494 Aug 25 07:28:31 AM UTC 24 Aug 25 07:28:33 AM UTC 24 34586612 ps
T807 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3302430229 Aug 25 07:28:29 AM UTC 24 Aug 25 07:28:33 AM UTC 24 67649935 ps
T808 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.2173886030 Aug 25 07:28:30 AM UTC 24 Aug 25 07:28:33 AM UTC 24 67671873 ps
T809 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3017451486 Aug 25 07:28:29 AM UTC 24 Aug 25 07:28:34 AM UTC 24 84665861 ps
T810 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.3917432632 Aug 25 07:28:32 AM UTC 24 Aug 25 07:28:35 AM UTC 24 92454565 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.1838600008 Aug 25 07:28:30 AM UTC 24 Aug 25 07:28:35 AM UTC 24 110894449 ps
T811 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.1134602289 Aug 25 07:28:33 AM UTC 24 Aug 25 07:28:36 AM UTC 24 51475832 ps
T812 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.3434597848 Aug 25 07:28:34 AM UTC 24 Aug 25 07:28:36 AM UTC 24 37377430 ps
T813 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1518990198 Aug 25 07:28:32 AM UTC 24 Aug 25 07:28:37 AM UTC 24 33501434 ps
T814 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.1454942510 Aug 25 07:28:34 AM UTC 24 Aug 25 07:28:37 AM UTC 24 21475347 ps
T815 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.593367934 Aug 25 07:28:33 AM UTC 24 Aug 25 07:28:38 AM UTC 24 243914865 ps
T816 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1615260934 Aug 25 07:28:34 AM UTC 24 Aug 25 07:28:38 AM UTC 24 243957082 ps
T817 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.3174663442 Aug 25 07:28:34 AM UTC 24 Aug 25 07:28:38 AM UTC 24 186775388 ps
T818 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.2764974480 Aug 25 07:28:35 AM UTC 24 Aug 25 07:28:39 AM UTC 24 173030503 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.2541243113 Aug 25 07:28:34 AM UTC 24 Aug 25 07:28:39 AM UTC 24 380063115 ps
T819 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.2227015805 Aug 25 07:28:34 AM UTC 24 Aug 25 07:28:39 AM UTC 24 446394183 ps
T820 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.4171464706 Aug 25 07:28:36 AM UTC 24 Aug 25 07:28:40 AM UTC 24 21532429 ps
T821 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.604004915 Aug 25 07:28:38 AM UTC 24 Aug 25 07:28:40 AM UTC 24 27356327 ps
T822 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.3353469008 Aug 25 07:28:38 AM UTC 24 Aug 25 07:28:40 AM UTC 24 37066976 ps
T823 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.4240198903 Aug 25 07:28:36 AM UTC 24 Aug 25 07:28:41 AM UTC 24 58451689 ps
T824 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.6973518 Aug 25 07:28:39 AM UTC 24 Aug 25 07:28:42 AM UTC 24 283723822 ps
T825 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.4158345339 Aug 25 07:28:39 AM UTC 24 Aug 25 07:28:42 AM UTC 24 92324760 ps
T826 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.1991798943 Aug 25 07:28:40 AM UTC 24 Aug 25 07:28:42 AM UTC 24 18137893 ps
T827 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.2612115126 Aug 25 07:28:38 AM UTC 24 Aug 25 07:28:42 AM UTC 24 38117186 ps
T828 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.4203773841 Aug 25 07:28:38 AM UTC 24 Aug 25 07:28:43 AM UTC 24 104471605 ps
T829 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.3235318731 Aug 25 07:28:40 AM UTC 24 Aug 25 07:28:44 AM UTC 24 59945612 ps
T830 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.3749388624 Aug 25 07:28:39 AM UTC 24 Aug 25 07:28:44 AM UTC 24 39478608 ps
T831 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.3898564101 Aug 25 07:28:41 AM UTC 24 Aug 25 07:28:44 AM UTC 24 72856519 ps
T832 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.2173793184 Aug 25 07:28:41 AM UTC 24 Aug 25 07:28:45 AM UTC 24 40814683 ps
T833 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3246773141 Aug 25 07:28:41 AM UTC 24 Aug 25 07:28:45 AM UTC 24 272705421 ps
T834 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.3907629223 Aug 25 07:28:40 AM UTC 24 Aug 25 07:28:45 AM UTC 24 103962153 ps
T835 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.1216304347 Aug 25 07:28:44 AM UTC 24 Aug 25 07:28:46 AM UTC 24 17372755 ps
T836 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.3825357816 Aug 25 07:28:45 AM UTC 24 Aug 25 07:28:47 AM UTC 24 31948338 ps
T837 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.1007838883 Aug 25 07:28:43 AM UTC 24 Aug 25 07:28:47 AM UTC 24 55034922 ps
T838 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.1822952425 Aug 25 07:28:42 AM UTC 24 Aug 25 07:28:47 AM UTC 24 47865791 ps
T839 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.2036985458 Aug 25 07:28:45 AM UTC 24 Aug 25 07:28:47 AM UTC 24 55253170 ps
T840 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.416451488 Aug 25 07:28:45 AM UTC 24 Aug 25 07:28:48 AM UTC 24 78762432 ps
T841 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.2295150997 Aug 25 07:28:46 AM UTC 24 Aug 25 07:28:49 AM UTC 24 16276961 ps
T842 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.745804601 Aug 25 07:28:45 AM UTC 24 Aug 25 07:28:49 AM UTC 24 40418779 ps
T843 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.2079488702 Aug 25 07:28:47 AM UTC 24 Aug 25 07:28:49 AM UTC 24 79981521 ps
T844 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.3318532720 Aug 25 07:28:45 AM UTC 24 Aug 25 07:28:49 AM UTC 24 161480818 ps
T845 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.1782582378 Aug 25 07:28:46 AM UTC 24 Aug 25 07:28:50 AM UTC 24 90934886 ps
T846 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.4212284256 Aug 25 07:28:48 AM UTC 24 Aug 25 07:28:51 AM UTC 24 14755777 ps
T847 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.2984960938 Aug 25 07:28:48 AM UTC 24 Aug 25 07:28:51 AM UTC 24 14838426 ps
T848 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.2326898912 Aug 25 07:28:44 AM UTC 24 Aug 25 07:28:51 AM UTC 24 233643456 ps
T849 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.2190250894 Aug 25 07:28:48 AM UTC 24 Aug 25 07:28:51 AM UTC 24 267909795 ps
T850 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.3224193070 Aug 25 07:28:50 AM UTC 24 Aug 25 07:28:52 AM UTC 24 49159806 ps
T851 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.201220827 Aug 25 07:28:49 AM UTC 24 Aug 25 07:28:52 AM UTC 24 27350659 ps
T852 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.1309577587 Aug 25 07:28:50 AM UTC 24 Aug 25 07:28:52 AM UTC 24 40785258 ps
T853 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.80235064 Aug 25 07:28:48 AM UTC 24 Aug 25 07:28:52 AM UTC 24 243803101 ps
T854 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.3584679149 Aug 25 07:28:51 AM UTC 24 Aug 25 07:28:53 AM UTC 24 16333159 ps
T855 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.825669127 Aug 25 07:28:51 AM UTC 24 Aug 25 07:28:53 AM UTC 24 14297948 ps
T856 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.3850766390 Aug 25 07:28:51 AM UTC 24 Aug 25 07:28:53 AM UTC 24 50311867 ps
T857 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.2225451930 Aug 25 07:28:52 AM UTC 24 Aug 25 07:28:54 AM UTC 24 18023828 ps
T858 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.2857426706 Aug 25 07:28:52 AM UTC 24 Aug 25 07:28:54 AM UTC 24 12151385 ps
T859 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.2104168290 Aug 25 07:28:52 AM UTC 24 Aug 25 07:28:54 AM UTC 24 43697788 ps
T860 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.2021662757 Aug 25 07:28:52 AM UTC 24 Aug 25 07:28:54 AM UTC 24 17780867 ps
T861 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.12599004 Aug 25 07:28:46 AM UTC 24 Aug 25 07:28:54 AM UTC 24 771732729 ps
T862 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.3401627800 Aug 25 07:28:53 AM UTC 24 Aug 25 07:28:55 AM UTC 24 13976720 ps
T863 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.2449412857 Aug 25 07:28:53 AM UTC 24 Aug 25 07:28:55 AM UTC 24 13279560 ps
T864 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.3650233407 Aug 25 07:28:53 AM UTC 24 Aug 25 07:28:56 AM UTC 24 45135754 ps
T865 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.3802078530 Aug 25 07:28:53 AM UTC 24 Aug 25 07:28:56 AM UTC 24 23857883 ps
T866 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.1864697985 Aug 25 07:28:54 AM UTC 24 Aug 25 07:28:56 AM UTC 24 87048875 ps
T867 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.1001318204 Aug 25 07:28:54 AM UTC 24 Aug 25 07:28:56 AM UTC 24 62096683 ps
T868 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.3453949317 Aug 25 07:28:54 AM UTC 24 Aug 25 07:28:57 AM UTC 24 49993454 ps
T869 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.3804727459 Aug 25 07:28:56 AM UTC 24 Aug 25 07:28:58 AM UTC 24 64745931 ps
T870 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.224398943 Aug 25 07:28:56 AM UTC 24 Aug 25 07:28:58 AM UTC 24 20262979 ps
T871 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.1661568369 Aug 25 07:28:56 AM UTC 24 Aug 25 07:28:58 AM UTC 24 19881896 ps
T872 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.463590007 Aug 25 07:28:55 AM UTC 24 Aug 25 07:28:58 AM UTC 24 38673140 ps
T873 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.3206814461 Aug 25 07:28:56 AM UTC 24 Aug 25 07:28:58 AM UTC 24 24783973 ps
T874 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.3497747862 Aug 25 07:28:56 AM UTC 24 Aug 25 07:28:58 AM UTC 24 209542361 ps
T875 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.2682487631 Aug 25 07:28:57 AM UTC 24 Aug 25 07:28:59 AM UTC 24 43218740 ps
T876 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.939005203 Aug 25 07:28:57 AM UTC 24 Aug 25 07:28:59 AM UTC 24 45517427 ps
T877 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.3407459003 Aug 25 07:28:57 AM UTC 24 Aug 25 07:28:59 AM UTC 24 11029222 ps
T878 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.2459110733 Aug 25 07:28:57 AM UTC 24 Aug 25 07:28:59 AM UTC 24 106285354 ps
T879 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.1737745457 Aug 25 07:28:57 AM UTC 24 Aug 25 07:28:59 AM UTC 24 44061314 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/3.kmac_mubi.787451563
Short name T14
Test name
Test status
Simulation time 5742036045 ps
CPU time 118.04 seconds
Started Aug 25 09:47:14 AM UTC 24
Finished Aug 25 09:49:15 AM UTC 24
Peak memory 268576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787451563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.787451563 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_intg_err.611571710
Short name T114
Test name
Test status
Simulation time 345359401 ps
CPU time 4.3 seconds
Started Aug 25 07:26:58 AM UTC 24
Finished Aug 25 07:27:04 AM UTC 24
Peak memory 219344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611571710 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.611571710 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/0.kmac_sec_cm.315389648
Short name T9
Test name
Test status
Simulation time 6662716719 ps
CPU time 42.14 seconds
Started Aug 25 09:46:14 AM UTC 24
Finished Aug 25 09:47:18 AM UTC 24
Peak memory 275636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315389648 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.315389648 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/5.kmac_stress_all_with_rand_reset.788142083
Short name T56
Test name
Test status
Simulation time 1458216436 ps
CPU time 139.31 seconds
Started Aug 25 09:49:45 AM UTC 24
Finished Aug 25 09:52:07 AM UTC 24
Peak memory 268184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres
s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=788142083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all_w
ith_rand_reset.788142083 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/0.kmac_app_with_partial_data.1165068727
Short name T13
Test name
Test status
Simulation time 6932704475 ps
CPU time 143.54 seconds
Started Aug 25 09:46:11 AM UTC 24
Finished Aug 25 09:48:55 AM UTC 24
Peak memory 309200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165068727 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.1165068727 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/0.kmac_key_error.3085360119
Short name T20
Test name
Test status
Simulation time 3788012124 ps
CPU time 10.09 seconds
Started Aug 25 09:46:12 AM UTC 24
Finished Aug 25 09:46:40 AM UTC 24
Peak memory 230440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085360119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.3085360119 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/4.kmac_lc_escalation.2050067962
Short name T7
Test name
Test status
Simulation time 50857715 ps
CPU time 1.54 seconds
Started Aug 25 09:48:35 AM UTC 24
Finished Aug 25 09:48:38 AM UTC 24
Peak memory 229784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050067962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.2050067962 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/4.kmac_error.3210724945
Short name T25
Test name
Test status
Simulation time 43929413175 ps
CPU time 286.21 seconds
Started Aug 25 09:48:03 AM UTC 24
Finished Aug 25 09:52:55 AM UTC 24
Peak memory 333780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210724945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.3210724945 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/23.kmac_lc_escalation.3760310735
Short name T97
Test name
Test status
Simulation time 96743466 ps
CPU time 2.05 seconds
Started Aug 25 10:01:08 AM UTC 24
Finished Aug 25 10:01:11 AM UTC 24
Peak memory 235156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760310735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.3760310735 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/23.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.1189158723
Short name T109
Test name
Test status
Simulation time 36448416 ps
CPU time 1.75 seconds
Started Aug 25 07:27:56 AM UTC 24
Finished Aug 25 07:27:59 AM UTC 24
Peak memory 228728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189158723 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors.1189158723 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_intr_test.2420919733
Short name T116
Test name
Test status
Simulation time 14483115 ps
CPU time 1.18 seconds
Started Aug 25 07:26:32 AM UTC 24
Finished Aug 25 07:26:35 AM UTC 24
Peak memory 218916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420919733 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.2420919733 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/42.kmac_lc_escalation.437137882
Short name T61
Test name
Test status
Simulation time 1720146464 ps
CPU time 56.43 seconds
Started Aug 25 10:17:53 AM UTC 24
Finished Aug 25 10:18:52 AM UTC 24
Peak memory 255776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437137882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.437137882 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/42.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/2.kmac_lc_escalation.1535336680
Short name T6
Test name
Test status
Simulation time 153746115 ps
CPU time 2.02 seconds
Started Aug 25 09:46:49 AM UTC 24
Finished Aug 25 09:46:52 AM UTC 24
Peak memory 230496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535336680 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.1535336680 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/49.kmac_lc_escalation.1499202574
Short name T96
Test name
Test status
Simulation time 76498502 ps
CPU time 1.81 seconds
Started Aug 25 10:26:03 AM UTC 24
Finished Aug 25 10:26:06 AM UTC 24
Peak memory 229716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499202574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.1499202574 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/49.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_512.2089799335
Short name T80
Test name
Test status
Simulation time 262080301 ps
CPU time 14.39 seconds
Started Aug 25 09:46:11 AM UTC 24
Finished Aug 25 09:46:50 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089799335 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.2089799335
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/4.kmac_burst_write.2365654319
Short name T44
Test name
Test status
Simulation time 9954627968 ps
CPU time 292.43 seconds
Started Aug 25 09:47:33 AM UTC 24
Finished Aug 25 09:52:31 AM UTC 24
Peak memory 239384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365654319 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.2365654319 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/0.kmac_alert_test.1352143755
Short name T19
Test name
Test status
Simulation time 165426671 ps
CPU time 1.02 seconds
Started Aug 25 09:46:14 AM UTC 24
Finished Aug 25 09:46:36 AM UTC 24
Peak memory 214272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352143755 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.1352143755 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_partial_access.2519401228
Short name T140
Test name
Test status
Simulation time 424401943 ps
CPU time 2.83 seconds
Started Aug 25 07:26:56 AM UTC 24
Finished Aug 25 07:27:00 AM UTC 24
Peak memory 229508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519401228 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial_access.2519401228 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors.995197517
Short name T100
Test name
Test status
Simulation time 176478108 ps
CPU time 1.67 seconds
Started Aug 25 07:26:52 AM UTC 24
Finished Aug 25 07:26:55 AM UTC 24
Peak memory 228788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995197517 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors.995197517 +enable_masking
=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/3.kmac_lc_escalation.162212326
Short name T39
Test name
Test status
Simulation time 50278954 ps
CPU time 1.72 seconds
Started Aug 25 09:47:27 AM UTC 24
Finished Aug 25 09:47:29 AM UTC 24
Peak memory 229840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162212326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.162212326 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/4.kmac_app_with_partial_data.2047562161
Short name T22
Test name
Test status
Simulation time 2696559327 ps
CPU time 72.02 seconds
Started Aug 25 09:47:55 AM UTC 24
Finished Aug 25 09:49:09 AM UTC 24
Peak memory 268120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047562161 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.2047562161 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.959968064
Short name T185
Test name
Test status
Simulation time 1346263117 ps
CPU time 5.95 seconds
Started Aug 25 07:28:11 AM UTC 24
Finished Aug 25 07:28:18 AM UTC 24
Peak memory 229584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959968064 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.959968064 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/9.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/1.kmac_smoke.2848322515
Short name T138
Test name
Test status
Simulation time 10309887693 ps
CPU time 72.74 seconds
Started Aug 25 09:46:14 AM UTC 24
Finished Aug 25 09:47:49 AM UTC 24
Peak memory 232616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848322515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.2848322515 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_intr_test.2725154476
Short name T121
Test name
Test status
Simulation time 22766668 ps
CPU time 1.24 seconds
Started Aug 25 07:27:00 AM UTC 24
Finished Aug 25 07:27:03 AM UTC 24
Peak memory 218916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725154476 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.2725154476 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.2541243113
Short name T180
Test name
Test status
Simulation time 380063115 ps
CPU time 3.68 seconds
Started Aug 25 07:28:34 AM UTC 24
Finished Aug 25 07:28:39 AM UTC 24
Peak memory 219264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541243113 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.2541243113 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/15.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/15.kmac_error.3218242301
Short name T372
Test name
Test status
Simulation time 8713114084 ps
CPU time 473.64 seconds
Started Aug 25 09:54:19 AM UTC 24
Finished Aug 25 10:02:20 AM UTC 24
Peak memory 392988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218242301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.3218242301 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/15.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.2573224524
Short name T104
Test name
Test status
Simulation time 644878352 ps
CPU time 2.92 seconds
Started Aug 25 07:27:11 AM UTC 24
Finished Aug 25 07:27:15 AM UTC 24
Peak memory 229908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573224524 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors_with_csr_rw.
2573224524 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.1838600008
Short name T183
Test name
Test status
Simulation time 110894449 ps
CPU time 4.65 seconds
Started Aug 25 07:28:30 AM UTC 24
Finished Aug 25 07:28:35 AM UTC 24
Peak memory 229504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838600008 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.1838600008 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/14.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.1475582264
Short name T177
Test name
Test status
Simulation time 66543260 ps
CPU time 3.9 seconds
Started Aug 25 07:27:53 AM UTC 24
Finished Aug 25 07:27:58 AM UTC 24
Peak memory 229568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475582264 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.1475582264 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/5.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/0.kmac_sideload.1138396759
Short name T30
Test name
Test status
Simulation time 6127373321 ps
CPU time 312.8 seconds
Started Aug 25 09:46:11 AM UTC 24
Finished Aug 25 09:51:52 AM UTC 24
Peak memory 343380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138396759 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.1138396759 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/0.kmac_smoke.2851361687
Short name T74
Test name
Test status
Simulation time 1005162533 ps
CPU time 55.51 seconds
Started Aug 25 09:46:09 AM UTC 24
Finished Aug 25 09:47:26 AM UTC 24
Peak memory 234772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851361687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.2851361687 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_refresh.1638001645
Short name T111
Test name
Test status
Simulation time 9600000947 ps
CPU time 134.74 seconds
Started Aug 25 09:46:11 AM UTC 24
Finished Aug 25 09:48:46 AM UTC 24
Peak memory 317328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638001645 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.1638001645 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/18.kmac_sideload.284633894
Short name T379
Test name
Test status
Simulation time 12734966488 ps
CPU time 386.02 seconds
Started Aug 25 09:56:23 AM UTC 24
Finished Aug 25 10:02:55 AM UTC 24
Peak memory 515996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284633894 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.284633894 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/18.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_ready_error.1642675317
Short name T53
Test name
Test status
Simulation time 13825351281 ps
CPU time 41.51 seconds
Started Aug 25 09:46:12 AM UTC 24
Finished Aug 25 09:47:12 AM UTC 24
Peak memory 230704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642675317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.1642675317 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/17.kmac_error.1425535538
Short name T36
Test name
Test status
Simulation time 8997363146 ps
CPU time 423.53 seconds
Started Aug 25 09:56:03 AM UTC 24
Finished Aug 25 10:03:13 AM UTC 24
Peak memory 378776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425535538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.1425535538 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/17.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_aliasing.2374286237
Short name T186
Test name
Test status
Simulation time 546687049 ps
CPU time 6.36 seconds
Started Aug 25 07:26:39 AM UTC 24
Finished Aug 25 07:26:46 AM UTC 24
Peak memory 219388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374286237 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.2374286237 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.1233463490
Short name T729
Test name
Test status
Simulation time 1165064685 ps
CPU time 20.96 seconds
Started Aug 25 07:26:37 AM UTC 24
Finished Aug 25 07:26:59 AM UTC 24
Peak memory 219344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233463490 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.1233463490 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_hw_reset.2501680814
Short name T117
Test name
Test status
Simulation time 103305577 ps
CPU time 1.47 seconds
Started Aug 25 07:26:34 AM UTC 24
Finished Aug 25 07:26:36 AM UTC 24
Peak memory 218916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501680814 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.2501680814 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.876223566
Short name T113
Test name
Test status
Simulation time 84712029 ps
CPU time 3.03 seconds
Started Aug 25 07:26:49 AM UTC 24
Finished Aug 25 07:26:53 AM UTC 24
Peak memory 229576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=876223566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_m
em_rw_with_rand_reset.876223566 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_rw.1622916331
Short name T187
Test name
Test status
Simulation time 143521986 ps
CPU time 1.48 seconds
Started Aug 25 07:26:36 AM UTC 24
Finished Aug 25 07:26:38 AM UTC 24
Peak memory 218860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622916331 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.1622916331 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_partial_access.1018030842
Short name T139
Test name
Test status
Simulation time 26599844 ps
CPU time 1.6 seconds
Started Aug 25 07:26:18 AM UTC 24
Finished Aug 25 07:26:21 AM UTC 24
Peak memory 228860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018030842 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial_access.1018030842 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_walk.2186920984
Short name T726
Test name
Test status
Simulation time 29573417 ps
CPU time 1.06 seconds
Started Aug 25 07:26:15 AM UTC 24
Finished Aug 25 07:26:17 AM UTC 24
Peak memory 218976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186920984 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.2186920984 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_same_csr_outstanding.938968674
Short name T727
Test name
Test status
Simulation time 89473752 ps
CPU time 2.27 seconds
Started Aug 25 07:26:49 AM UTC 24
Finished Aug 25 07:26:52 AM UTC 24
Peak memory 229668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938968674 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_outstanding.938968674 +enable_m
asking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors.2337801388
Short name T98
Test name
Test status
Simulation time 30244600 ps
CPU time 1.32 seconds
Started Aug 25 07:26:06 AM UTC 24
Finished Aug 25 07:26:09 AM UTC 24
Peak memory 218612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337801388 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors.2337801388 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.3104959157
Short name T99
Test name
Test status
Simulation time 156716982 ps
CPU time 3.28 seconds
Started Aug 25 07:26:10 AM UTC 24
Finished Aug 25 07:26:15 AM UTC 24
Peak memory 230032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104959157 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors_with_csr_rw.
3104959157 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_errors.4264086166
Short name T57
Test name
Test status
Simulation time 290468454 ps
CPU time 2.9 seconds
Started Aug 25 07:26:21 AM UTC 24
Finished Aug 25 07:26:25 AM UTC 24
Peak memory 229724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264086166 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.4264086166 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_intg_err.2328762704
Short name T58
Test name
Test status
Simulation time 110402386 ps
CPU time 3.85 seconds
Started Aug 25 07:26:26 AM UTC 24
Finished Aug 25 07:26:32 AM UTC 24
Peak memory 229572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328762704 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.2328762704 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_aliasing.947138059
Short name T732
Test name
Test status
Simulation time 77545935 ps
CPU time 5.61 seconds
Started Aug 25 07:27:05 AM UTC 24
Finished Aug 25 07:27:11 AM UTC 24
Peak memory 219328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947138059 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.947138059 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.2304617822
Short name T737
Test name
Test status
Simulation time 2104688007 ps
CPU time 29.87 seconds
Started Aug 25 07:27:05 AM UTC 24
Finished Aug 25 07:27:36 AM UTC 24
Peak memory 219388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304617822 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.2304617822 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_hw_reset.150126444
Short name T730
Test name
Test status
Simulation time 29168404 ps
CPU time 1.61 seconds
Started Aug 25 07:27:02 AM UTC 24
Finished Aug 25 07:27:05 AM UTC 24
Peak memory 218872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150126444 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.150126444 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.3159262391
Short name T126
Test name
Test status
Simulation time 31571656 ps
CPU time 2.9 seconds
Started Aug 25 07:27:07 AM UTC 24
Finished Aug 25 07:27:11 AM UTC 24
Peak memory 231620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3159262391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_
mem_rw_with_rand_reset.3159262391 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_rw.2582043354
Short name T153
Test name
Test status
Simulation time 36226391 ps
CPU time 1.98 seconds
Started Aug 25 07:27:05 AM UTC 24
Finished Aug 25 07:27:08 AM UTC 24
Peak memory 218876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582043354 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.2582043354 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_walk.1963049021
Short name T728
Test name
Test status
Simulation time 35812710 ps
CPU time 1.06 seconds
Started Aug 25 07:26:54 AM UTC 24
Finished Aug 25 07:26:56 AM UTC 24
Peak memory 218868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963049021 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.1963049021 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_same_csr_outstanding.1446457139
Short name T731
Test name
Test status
Simulation time 53639066 ps
CPU time 2.16 seconds
Started Aug 25 07:27:07 AM UTC 24
Finished Aug 25 07:27:11 AM UTC 24
Peak memory 229508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446457139 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_outstanding.1446457139 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.4079167271
Short name T101
Test name
Test status
Simulation time 303811684 ps
CPU time 2.67 seconds
Started Aug 25 07:26:54 AM UTC 24
Finished Aug 25 07:26:58 AM UTC 24
Peak memory 229884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079167271 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors_with_csr_rw.
4079167271 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_errors.2362085661
Short name T118
Test name
Test status
Simulation time 109150669 ps
CPU time 4.53 seconds
Started Aug 25 07:26:58 AM UTC 24
Finished Aug 25 07:27:04 AM UTC 24
Peak memory 229628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362085661 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.2362085661 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2849255143
Short name T778
Test name
Test status
Simulation time 39585113 ps
CPU time 2.17 seconds
Started Aug 25 07:28:17 AM UTC 24
Finished Aug 25 07:28:20 AM UTC 24
Peak memory 229700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2849255143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr
_mem_rw_with_rand_reset.2849255143 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.600622621
Short name T774
Test name
Test status
Simulation time 77894109 ps
CPU time 1.45 seconds
Started Aug 25 07:28:16 AM UTC 24
Finished Aug 25 07:28:18 AM UTC 24
Peak memory 218860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600622621 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.600622621 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/10.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.1245330068
Short name T773
Test name
Test status
Simulation time 15466576 ps
CPU time 1.17 seconds
Started Aug 25 07:28:15 AM UTC 24
Finished Aug 25 07:28:18 AM UTC 24
Peak memory 218980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245330068 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.1245330068 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/10.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.2556134880
Short name T780
Test name
Test status
Simulation time 109296792 ps
CPU time 3.96 seconds
Started Aug 25 07:28:16 AM UTC 24
Finished Aug 25 07:28:21 AM UTC 24
Peak memory 229508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556134880 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr_outstanding.2556134880 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/10.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.900634163
Short name T775
Test name
Test status
Simulation time 92801743 ps
CPU time 1.86 seconds
Started Aug 25 07:28:15 AM UTC 24
Finished Aug 25 07:28:18 AM UTC 24
Peak memory 228524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900634163 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors.900634163 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3530711677
Short name T782
Test name
Test status
Simulation time 795065883 ps
CPU time 5.02 seconds
Started Aug 25 07:28:15 AM UTC 24
Finished Aug 25 07:28:22 AM UTC 24
Peak memory 229932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530711677 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors_with_csr_rw
.3530711677 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.802080979
Short name T776
Test name
Test status
Simulation time 409736386 ps
CPU time 2.7 seconds
Started Aug 25 07:28:15 AM UTC 24
Finished Aug 25 07:28:19 AM UTC 24
Peak memory 229640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802080979 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.802080979 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/10.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.1642004416
Short name T182
Test name
Test status
Simulation time 2180774782 ps
CPU time 7.73 seconds
Started Aug 25 07:28:15 AM UTC 24
Finished Aug 25 07:28:24 AM UTC 24
Peak memory 229696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642004416 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.1642004416 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/10.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.4276586050
Short name T787
Test name
Test status
Simulation time 227543650 ps
CPU time 2.87 seconds
Started Aug 25 07:28:21 AM UTC 24
Finished Aug 25 07:28:25 AM UTC 24
Peak memory 229636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4276586050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr
_mem_rw_with_rand_reset.4276586050 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.761332127
Short name T783
Test name
Test status
Simulation time 42972611 ps
CPU time 1.55 seconds
Started Aug 25 07:28:20 AM UTC 24
Finished Aug 25 07:28:23 AM UTC 24
Peak memory 218820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761332127 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.761332127 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/11.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.1041811736
Short name T781
Test name
Test status
Simulation time 31997600 ps
CPU time 1.16 seconds
Started Aug 25 07:28:19 AM UTC 24
Finished Aug 25 07:28:21 AM UTC 24
Peak memory 218920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041811736 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.1041811736 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/11.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3489977272
Short name T791
Test name
Test status
Simulation time 114985504 ps
CPU time 3.99 seconds
Started Aug 25 07:28:21 AM UTC 24
Finished Aug 25 07:28:26 AM UTC 24
Peak memory 229508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489977272 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr_outstanding.3489977272 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/11.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.1415718709
Short name T779
Test name
Test status
Simulation time 117428223 ps
CPU time 2.33 seconds
Started Aug 25 07:28:17 AM UTC 24
Finished Aug 25 07:28:20 AM UTC 24
Peak memory 230048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415718709 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors.1415718709 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/11.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.3461601853
Short name T786
Test name
Test status
Simulation time 995642876 ps
CPU time 4.67 seconds
Started Aug 25 07:28:19 AM UTC 24
Finished Aug 25 07:28:25 AM UTC 24
Peak memory 229976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461601853 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors_with_csr_rw
.3461601853 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.829941834
Short name T784
Test name
Test status
Simulation time 146435756 ps
CPU time 3.64 seconds
Started Aug 25 07:28:19 AM UTC 24
Finished Aug 25 07:28:24 AM UTC 24
Peak memory 229688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829941834 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.829941834 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/11.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.1510517465
Short name T794
Test name
Test status
Simulation time 263528598 ps
CPU time 7.89 seconds
Started Aug 25 07:28:19 AM UTC 24
Finished Aug 25 07:28:28 AM UTC 24
Peak memory 219192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510517465 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.1510517465 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/11.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.587100050
Short name T797
Test name
Test status
Simulation time 149553021 ps
CPU time 1.98 seconds
Started Aug 25 07:28:26 AM UTC 24
Finished Aug 25 07:28:29 AM UTC 24
Peak memory 228856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=587100050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_
mem_rw_with_rand_reset.587100050 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.74486215
Short name T792
Test name
Test status
Simulation time 19416284 ps
CPU time 1.36 seconds
Started Aug 25 07:28:25 AM UTC 24
Finished Aug 25 07:28:27 AM UTC 24
Peak memory 228900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74486215 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.74486215 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/12.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.1546925900
Short name T789
Test name
Test status
Simulation time 39415844 ps
CPU time 1.08 seconds
Started Aug 25 07:28:23 AM UTC 24
Finished Aug 25 07:28:26 AM UTC 24
Peak memory 218920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546925900 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.1546925900 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/12.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.2930117864
Short name T793
Test name
Test status
Simulation time 33981244 ps
CPU time 1.99 seconds
Started Aug 25 07:28:25 AM UTC 24
Finished Aug 25 07:28:28 AM UTC 24
Peak memory 228860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930117864 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr_outstanding.2930117864 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/12.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.577397571
Short name T785
Test name
Test status
Simulation time 28302643 ps
CPU time 1.41 seconds
Started Aug 25 07:28:21 AM UTC 24
Finished Aug 25 07:28:24 AM UTC 24
Peak memory 218616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577397571 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors.577397571 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/12.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.4151281665
Short name T788
Test name
Test status
Simulation time 222775782 ps
CPU time 3.09 seconds
Started Aug 25 07:28:21 AM UTC 24
Finished Aug 25 07:28:25 AM UTC 24
Peak memory 229992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151281665 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors_with_csr_rw
.4151281665 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.3589007159
Short name T790
Test name
Test status
Simulation time 34136394 ps
CPU time 2.73 seconds
Started Aug 25 07:28:22 AM UTC 24
Finished Aug 25 07:28:26 AM UTC 24
Peak memory 229692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589007159 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.3589007159 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/12.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.1920222545
Short name T181
Test name
Test status
Simulation time 4757794341 ps
CPU time 7.32 seconds
Started Aug 25 07:28:22 AM UTC 24
Finished Aug 25 07:28:31 AM UTC 24
Peak memory 229696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920222545 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.1920222545 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/12.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3017451486
Short name T809
Test name
Test status
Simulation time 84665861 ps
CPU time 3.36 seconds
Started Aug 25 07:28:29 AM UTC 24
Finished Aug 25 07:28:34 AM UTC 24
Peak memory 231620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3017451486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr
_mem_rw_with_rand_reset.3017451486 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.2561715138
Short name T799
Test name
Test status
Simulation time 21784719 ps
CPU time 1.58 seconds
Started Aug 25 07:28:27 AM UTC 24
Finished Aug 25 07:28:30 AM UTC 24
Peak memory 218920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561715138 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.2561715138 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/13.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.3431505660
Short name T798
Test name
Test status
Simulation time 18552081 ps
CPU time 1.23 seconds
Started Aug 25 07:28:27 AM UTC 24
Finished Aug 25 07:28:29 AM UTC 24
Peak memory 218920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431505660 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.3431505660 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/13.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3302430229
Short name T807
Test name
Test status
Simulation time 67649935 ps
CPU time 2.69 seconds
Started Aug 25 07:28:29 AM UTC 24
Finished Aug 25 07:28:33 AM UTC 24
Peak memory 229544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302430229 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr_outstanding.3302430229 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/13.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1312903792
Short name T795
Test name
Test status
Simulation time 17022526 ps
CPU time 1.27 seconds
Started Aug 25 07:28:26 AM UTC 24
Finished Aug 25 07:28:28 AM UTC 24
Peak memory 218676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312903792 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors.1312903792 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/13.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2674261974
Short name T800
Test name
Test status
Simulation time 131241515 ps
CPU time 4.11 seconds
Started Aug 25 07:28:26 AM UTC 24
Finished Aug 25 07:28:31 AM UTC 24
Peak memory 229996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674261974 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors_with_csr_rw
.2674261974 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.3207476629
Short name T803
Test name
Test status
Simulation time 213797760 ps
CPU time 4.49 seconds
Started Aug 25 07:28:27 AM UTC 24
Finished Aug 25 07:28:33 AM UTC 24
Peak memory 229696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207476629 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.3207476629 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/13.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.1972895734
Short name T801
Test name
Test status
Simulation time 57860211 ps
CPU time 3.45 seconds
Started Aug 25 07:28:27 AM UTC 24
Finished Aug 25 07:28:32 AM UTC 24
Peak memory 229564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972895734 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.1972895734 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/13.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1518990198
Short name T813
Test name
Test status
Simulation time 33501434 ps
CPU time 3.49 seconds
Started Aug 25 07:28:32 AM UTC 24
Finished Aug 25 07:28:37 AM UTC 24
Peak memory 231620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1518990198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr
_mem_rw_with_rand_reset.1518990198 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.2173611494
Short name T806
Test name
Test status
Simulation time 34586612 ps
CPU time 1.4 seconds
Started Aug 25 07:28:31 AM UTC 24
Finished Aug 25 07:28:33 AM UTC 24
Peak memory 218876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173611494 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.2173611494 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/14.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.159952121
Short name T805
Test name
Test status
Simulation time 19883373 ps
CPU time 1.18 seconds
Started Aug 25 07:28:31 AM UTC 24
Finished Aug 25 07:28:33 AM UTC 24
Peak memory 218788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159952121 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.159952121 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/14.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.3917432632
Short name T810
Test name
Test status
Simulation time 92454565 ps
CPU time 2.14 seconds
Started Aug 25 07:28:32 AM UTC 24
Finished Aug 25 07:28:35 AM UTC 24
Peak memory 229508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917432632 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr_outstanding.3917432632 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/14.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1151754579
Short name T802
Test name
Test status
Simulation time 21244868 ps
CPU time 1.63 seconds
Started Aug 25 07:28:29 AM UTC 24
Finished Aug 25 07:28:32 AM UTC 24
Peak memory 228596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151754579 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors.1151754579 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/14.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.1123080689
Short name T804
Test name
Test status
Simulation time 58132520 ps
CPU time 2.21 seconds
Started Aug 25 07:28:29 AM UTC 24
Finished Aug 25 07:28:33 AM UTC 24
Peak memory 230040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123080689 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors_with_csr_rw
.1123080689 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.2173886030
Short name T808
Test name
Test status
Simulation time 67671873 ps
CPU time 2.6 seconds
Started Aug 25 07:28:30 AM UTC 24
Finished Aug 25 07:28:33 AM UTC 24
Peak memory 229628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173886030 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.2173886030 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/14.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1615260934
Short name T816
Test name
Test status
Simulation time 243957082 ps
CPU time 2.62 seconds
Started Aug 25 07:28:34 AM UTC 24
Finished Aug 25 07:28:38 AM UTC 24
Peak memory 231684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1615260934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr
_mem_rw_with_rand_reset.1615260934 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.1454942510
Short name T814
Test name
Test status
Simulation time 21475347 ps
CPU time 1.38 seconds
Started Aug 25 07:28:34 AM UTC 24
Finished Aug 25 07:28:37 AM UTC 24
Peak memory 218920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454942510 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.1454942510 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/15.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.3434597848
Short name T812
Test name
Test status
Simulation time 37377430 ps
CPU time 1.15 seconds
Started Aug 25 07:28:34 AM UTC 24
Finished Aug 25 07:28:36 AM UTC 24
Peak memory 218920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434597848 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.3434597848 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/15.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.3174663442
Short name T817
Test name
Test status
Simulation time 186775388 ps
CPU time 2.71 seconds
Started Aug 25 07:28:34 AM UTC 24
Finished Aug 25 07:28:38 AM UTC 24
Peak memory 229508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174663442 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr_outstanding.3174663442 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/15.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.1134602289
Short name T811
Test name
Test status
Simulation time 51475832 ps
CPU time 2.21 seconds
Started Aug 25 07:28:33 AM UTC 24
Finished Aug 25 07:28:36 AM UTC 24
Peak memory 229920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134602289 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors.1134602289 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/15.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.593367934
Short name T815
Test name
Test status
Simulation time 243914865 ps
CPU time 3.84 seconds
Started Aug 25 07:28:33 AM UTC 24
Finished Aug 25 07:28:38 AM UTC 24
Peak memory 237036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593367934 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors_with_csr_rw.
593367934 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.2227015805
Short name T819
Test name
Test status
Simulation time 446394183 ps
CPU time 4.28 seconds
Started Aug 25 07:28:34 AM UTC 24
Finished Aug 25 07:28:39 AM UTC 24
Peak memory 229632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227015805 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.2227015805 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/15.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.3749388624
Short name T830
Test name
Test status
Simulation time 39478608 ps
CPU time 3.83 seconds
Started Aug 25 07:28:39 AM UTC 24
Finished Aug 25 07:28:44 AM UTC 24
Peak memory 231660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3749388624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr
_mem_rw_with_rand_reset.3749388624 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.3353469008
Short name T822
Test name
Test status
Simulation time 37066976 ps
CPU time 1.44 seconds
Started Aug 25 07:28:38 AM UTC 24
Finished Aug 25 07:28:40 AM UTC 24
Peak memory 218848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353469008 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.3353469008 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/16.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.604004915
Short name T821
Test name
Test status
Simulation time 27356327 ps
CPU time 1.2 seconds
Started Aug 25 07:28:38 AM UTC 24
Finished Aug 25 07:28:40 AM UTC 24
Peak memory 218860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604004915 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.604004915 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/16.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.2612115126
Short name T827
Test name
Test status
Simulation time 38117186 ps
CPU time 3.22 seconds
Started Aug 25 07:28:38 AM UTC 24
Finished Aug 25 07:28:42 AM UTC 24
Peak memory 229420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612115126 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr_outstanding.2612115126 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/16.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.2764974480
Short name T818
Test name
Test status
Simulation time 173030503 ps
CPU time 2.18 seconds
Started Aug 25 07:28:35 AM UTC 24
Finished Aug 25 07:28:39 AM UTC 24
Peak memory 229920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764974480 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors.2764974480 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/16.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.4240198903
Short name T823
Test name
Test status
Simulation time 58451689 ps
CPU time 3.01 seconds
Started Aug 25 07:28:36 AM UTC 24
Finished Aug 25 07:28:41 AM UTC 24
Peak memory 229996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240198903 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors_with_csr_rw
.4240198903 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.4171464706
Short name T820
Test name
Test status
Simulation time 21532429 ps
CPU time 2.01 seconds
Started Aug 25 07:28:36 AM UTC 24
Finished Aug 25 07:28:40 AM UTC 24
Peak memory 229632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171464706 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.4171464706 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/16.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.4203773841
Short name T828
Test name
Test status
Simulation time 104471605 ps
CPU time 4.38 seconds
Started Aug 25 07:28:38 AM UTC 24
Finished Aug 25 07:28:43 AM UTC 24
Peak memory 219392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203773841 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.4203773841 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/16.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.2173793184
Short name T832
Test name
Test status
Simulation time 40814683 ps
CPU time 2.11 seconds
Started Aug 25 07:28:41 AM UTC 24
Finished Aug 25 07:28:45 AM UTC 24
Peak memory 229700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2173793184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr
_mem_rw_with_rand_reset.2173793184 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.1556413061
Short name T796
Test name
Test status
Simulation time 18179691 ps
CPU time 1.64 seconds
Started Aug 25 07:28:41 AM UTC 24
Finished Aug 25 07:28:44 AM UTC 24
Peak memory 218880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556413061 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.1556413061 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/17.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.1991798943
Short name T826
Test name
Test status
Simulation time 18137893 ps
CPU time 1.11 seconds
Started Aug 25 07:28:40 AM UTC 24
Finished Aug 25 07:28:42 AM UTC 24
Peak memory 218920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991798943 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.1991798943 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/17.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3246773141
Short name T833
Test name
Test status
Simulation time 272705421 ps
CPU time 2.37 seconds
Started Aug 25 07:28:41 AM UTC 24
Finished Aug 25 07:28:45 AM UTC 24
Peak memory 229672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246773141 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr_outstanding.3246773141 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/17.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.6973518
Short name T824
Test name
Test status
Simulation time 283723822 ps
CPU time 1.72 seconds
Started Aug 25 07:28:39 AM UTC 24
Finished Aug 25 07:28:42 AM UTC 24
Peak memory 228596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6973518 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors.6973518 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/17.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.4158345339
Short name T825
Test name
Test status
Simulation time 92324760 ps
CPU time 2.08 seconds
Started Aug 25 07:28:39 AM UTC 24
Finished Aug 25 07:28:42 AM UTC 24
Peak memory 230060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158345339 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors_with_csr_rw
.4158345339 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.3235318731
Short name T829
Test name
Test status
Simulation time 59945612 ps
CPU time 2.64 seconds
Started Aug 25 07:28:40 AM UTC 24
Finished Aug 25 07:28:44 AM UTC 24
Peak memory 229692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235318731 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.3235318731 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/17.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.3907629223
Short name T834
Test name
Test status
Simulation time 103962153 ps
CPU time 4.08 seconds
Started Aug 25 07:28:40 AM UTC 24
Finished Aug 25 07:28:45 AM UTC 24
Peak memory 229564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907629223 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.3907629223 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/17.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.416451488
Short name T840
Test name
Test status
Simulation time 78762432 ps
CPU time 2.16 seconds
Started Aug 25 07:28:45 AM UTC 24
Finished Aug 25 07:28:48 AM UTC 24
Peak memory 229572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=416451488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_
mem_rw_with_rand_reset.416451488 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.3825357816
Short name T836
Test name
Test status
Simulation time 31948338 ps
CPU time 1.3 seconds
Started Aug 25 07:28:45 AM UTC 24
Finished Aug 25 07:28:47 AM UTC 24
Peak memory 218920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825357816 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.3825357816 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/18.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.1216304347
Short name T835
Test name
Test status
Simulation time 17372755 ps
CPU time 1.15 seconds
Started Aug 25 07:28:44 AM UTC 24
Finished Aug 25 07:28:46 AM UTC 24
Peak memory 218980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216304347 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.1216304347 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/18.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.3318532720
Short name T844
Test name
Test status
Simulation time 161480818 ps
CPU time 3.66 seconds
Started Aug 25 07:28:45 AM UTC 24
Finished Aug 25 07:28:49 AM UTC 24
Peak memory 229508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318532720 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr_outstanding.3318532720 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/18.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.3898564101
Short name T831
Test name
Test status
Simulation time 72856519 ps
CPU time 1.58 seconds
Started Aug 25 07:28:41 AM UTC 24
Finished Aug 25 07:28:44 AM UTC 24
Peak memory 228792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898564101 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors.3898564101 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/18.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.1822952425
Short name T838
Test name
Test status
Simulation time 47865791 ps
CPU time 3.79 seconds
Started Aug 25 07:28:42 AM UTC 24
Finished Aug 25 07:28:47 AM UTC 24
Peak memory 237064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822952425 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors_with_csr_rw
.1822952425 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.1007838883
Short name T837
Test name
Test status
Simulation time 55034922 ps
CPU time 2.54 seconds
Started Aug 25 07:28:43 AM UTC 24
Finished Aug 25 07:28:47 AM UTC 24
Peak memory 229632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007838883 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.1007838883 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/18.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.2326898912
Short name T848
Test name
Test status
Simulation time 233643456 ps
CPU time 6.42 seconds
Started Aug 25 07:28:44 AM UTC 24
Finished Aug 25 07:28:51 AM UTC 24
Peak memory 229568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326898912 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.2326898912 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/18.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.80235064
Short name T853
Test name
Test status
Simulation time 243803101 ps
CPU time 2.52 seconds
Started Aug 25 07:28:48 AM UTC 24
Finished Aug 25 07:28:52 AM UTC 24
Peak memory 229640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=80235064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_m
em_rw_with_rand_reset.80235064 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.2079488702
Short name T843
Test name
Test status
Simulation time 79981521 ps
CPU time 1.24 seconds
Started Aug 25 07:28:47 AM UTC 24
Finished Aug 25 07:28:49 AM UTC 24
Peak memory 218920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079488702 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.2079488702 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/19.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.2295150997
Short name T841
Test name
Test status
Simulation time 16276961 ps
CPU time 1.26 seconds
Started Aug 25 07:28:46 AM UTC 24
Finished Aug 25 07:28:49 AM UTC 24
Peak memory 218980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295150997 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.2295150997 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/19.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.2190250894
Short name T849
Test name
Test status
Simulation time 267909795 ps
CPU time 1.95 seconds
Started Aug 25 07:28:48 AM UTC 24
Finished Aug 25 07:28:51 AM UTC 24
Peak memory 228860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190250894 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr_outstanding.2190250894 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/19.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.2036985458
Short name T839
Test name
Test status
Simulation time 55253170 ps
CPU time 1.47 seconds
Started Aug 25 07:28:45 AM UTC 24
Finished Aug 25 07:28:47 AM UTC 24
Peak memory 218552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036985458 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors.2036985458 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/19.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.745804601
Short name T842
Test name
Test status
Simulation time 40418779 ps
CPU time 3.11 seconds
Started Aug 25 07:28:45 AM UTC 24
Finished Aug 25 07:28:49 AM UTC 24
Peak memory 236588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745804601 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors_with_csr_rw.
745804601 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.1782582378
Short name T845
Test name
Test status
Simulation time 90934886 ps
CPU time 3.32 seconds
Started Aug 25 07:28:46 AM UTC 24
Finished Aug 25 07:28:50 AM UTC 24
Peak memory 229760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782582378 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.1782582378 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/19.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.12599004
Short name T861
Test name
Test status
Simulation time 771732729 ps
CPU time 7.04 seconds
Started Aug 25 07:28:46 AM UTC 24
Finished Aug 25 07:28:54 AM UTC 24
Peak memory 229564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12599004 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.12599004 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/19.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.2700589882
Short name T736
Test name
Test status
Simulation time 839226611 ps
CPU time 6.17 seconds
Started Aug 25 07:27:25 AM UTC 24
Finished Aug 25 07:27:32 AM UTC 24
Peak memory 219328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700589882 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.2700589882 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.170867004
Short name T739
Test name
Test status
Simulation time 295872771 ps
CPU time 11.5 seconds
Started Aug 25 07:27:25 AM UTC 24
Finished Aug 25 07:27:37 AM UTC 24
Peak memory 219476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170867004 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.170867004 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_hw_reset.588031408
Short name T734
Test name
Test status
Simulation time 23114823 ps
CPU time 1.37 seconds
Started Aug 25 07:27:18 AM UTC 24
Finished Aug 25 07:27:20 AM UTC 24
Peak memory 218856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588031408 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.588031408 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.2698253184
Short name T125
Test name
Test status
Simulation time 23621305 ps
CPU time 3.08 seconds
Started Aug 25 07:27:25 AM UTC 24
Finished Aug 25 07:27:29 AM UTC 24
Peak memory 229636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2698253184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_
mem_rw_with_rand_reset.2698253184 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_rw.2244145055
Short name T154
Test name
Test status
Simulation time 21500494 ps
CPU time 1.38 seconds
Started Aug 25 07:27:25 AM UTC 24
Finished Aug 25 07:27:27 AM UTC 24
Peak memory 218860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244145055 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.2244145055 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_intr_test.1936168261
Short name T168
Test name
Test status
Simulation time 16220551 ps
CPU time 1.22 seconds
Started Aug 25 07:27:18 AM UTC 24
Finished Aug 25 07:27:20 AM UTC 24
Peak memory 218916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936168261 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.1936168261 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_partial_access.3350041114
Short name T141
Test name
Test status
Simulation time 254420856 ps
CPU time 1.92 seconds
Started Aug 25 07:27:14 AM UTC 24
Finished Aug 25 07:27:17 AM UTC 24
Peak memory 228860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350041114 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial_access.3350041114 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_walk.1171719321
Short name T733
Test name
Test status
Simulation time 14839114 ps
CPU time 1.19 seconds
Started Aug 25 07:27:14 AM UTC 24
Finished Aug 25 07:27:16 AM UTC 24
Peak memory 218976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171719321 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.1171719321 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_same_csr_outstanding.1877224420
Short name T155
Test name
Test status
Simulation time 58921019 ps
CPU time 2.52 seconds
Started Aug 25 07:27:25 AM UTC 24
Finished Aug 25 07:27:28 AM UTC 24
Peak memory 229484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877224420 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_outstanding.1877224420 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors.1488566036
Short name T102
Test name
Test status
Simulation time 29380985 ps
CPU time 1.77 seconds
Started Aug 25 07:27:09 AM UTC 24
Finished Aug 25 07:27:12 AM UTC 24
Peak memory 228728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488566036 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors.1488566036 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_errors.2957310652
Short name T120
Test name
Test status
Simulation time 1076725267 ps
CPU time 4.35 seconds
Started Aug 25 07:27:14 AM UTC 24
Finished Aug 25 07:27:19 AM UTC 24
Peak memory 229640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957310652 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.2957310652 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_intg_err.1557280865
Short name T115
Test name
Test status
Simulation time 435254303 ps
CPU time 4.07 seconds
Started Aug 25 07:27:18 AM UTC 24
Finished Aug 25 07:27:23 AM UTC 24
Peak memory 229696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557280865 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.1557280865 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.4212284256
Short name T846
Test name
Test status
Simulation time 14755777 ps
CPU time 1.16 seconds
Started Aug 25 07:28:48 AM UTC 24
Finished Aug 25 07:28:51 AM UTC 24
Peak memory 218920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212284256 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.4212284256 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/20.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.2984960938
Short name T847
Test name
Test status
Simulation time 14838426 ps
CPU time 1.19 seconds
Started Aug 25 07:28:48 AM UTC 24
Finished Aug 25 07:28:51 AM UTC 24
Peak memory 218920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984960938 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.2984960938 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/21.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.201220827
Short name T851
Test name
Test status
Simulation time 27350659 ps
CPU time 1.15 seconds
Started Aug 25 07:28:49 AM UTC 24
Finished Aug 25 07:28:52 AM UTC 24
Peak memory 218860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201220827 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.201220827 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/22.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.3224193070
Short name T850
Test name
Test status
Simulation time 49159806 ps
CPU time 1.04 seconds
Started Aug 25 07:28:50 AM UTC 24
Finished Aug 25 07:28:52 AM UTC 24
Peak memory 218920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224193070 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.3224193070 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/23.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.1309577587
Short name T852
Test name
Test status
Simulation time 40785258 ps
CPU time 1.16 seconds
Started Aug 25 07:28:50 AM UTC 24
Finished Aug 25 07:28:52 AM UTC 24
Peak memory 218920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309577587 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.1309577587 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/24.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.3584679149
Short name T854
Test name
Test status
Simulation time 16333159 ps
CPU time 1.17 seconds
Started Aug 25 07:28:51 AM UTC 24
Finished Aug 25 07:28:53 AM UTC 24
Peak memory 218920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584679149 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.3584679149 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/25.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.825669127
Short name T855
Test name
Test status
Simulation time 14297948 ps
CPU time 1.16 seconds
Started Aug 25 07:28:51 AM UTC 24
Finished Aug 25 07:28:53 AM UTC 24
Peak memory 218920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825669127 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.825669127 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/26.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.3850766390
Short name T856
Test name
Test status
Simulation time 50311867 ps
CPU time 1.25 seconds
Started Aug 25 07:28:51 AM UTC 24
Finished Aug 25 07:28:53 AM UTC 24
Peak memory 218980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850766390 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.3850766390 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/27.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.2225451930
Short name T857
Test name
Test status
Simulation time 18023828 ps
CPU time 1.09 seconds
Started Aug 25 07:28:52 AM UTC 24
Finished Aug 25 07:28:54 AM UTC 24
Peak memory 218920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225451930 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.2225451930 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/28.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.2857426706
Short name T858
Test name
Test status
Simulation time 12151385 ps
CPU time 1.09 seconds
Started Aug 25 07:28:52 AM UTC 24
Finished Aug 25 07:28:54 AM UTC 24
Peak memory 218692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857426706 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.2857426706 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/29.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.2152762225
Short name T157
Test name
Test status
Simulation time 1161043884 ps
CPU time 7.7 seconds
Started Aug 25 07:27:38 AM UTC 24
Finished Aug 25 07:27:47 AM UTC 24
Peak memory 229568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152762225 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.2152762225 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.494993609
Short name T745
Test name
Test status
Simulation time 1931412260 ps
CPU time 14.85 seconds
Started Aug 25 07:27:36 AM UTC 24
Finished Aug 25 07:27:53 AM UTC 24
Peak memory 219268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494993609 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.494993609 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_hw_reset.2550166512
Short name T738
Test name
Test status
Simulation time 220180419 ps
CPU time 1.79 seconds
Started Aug 25 07:27:33 AM UTC 24
Finished Aug 25 07:27:37 AM UTC 24
Peak memory 218876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550166512 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.2550166512 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.2100465586
Short name T134
Test name
Test status
Simulation time 61915558 ps
CPU time 2.86 seconds
Started Aug 25 07:27:39 AM UTC 24
Finished Aug 25 07:27:43 AM UTC 24
Peak memory 231620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2100465586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_
mem_rw_with_rand_reset.2100465586 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_rw.1766907217
Short name T740
Test name
Test status
Simulation time 15972463 ps
CPU time 1.39 seconds
Started Aug 25 07:27:36 AM UTC 24
Finished Aug 25 07:27:39 AM UTC 24
Peak memory 218860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766907217 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.1766907217 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_intr_test.4207073491
Short name T171
Test name
Test status
Simulation time 15798020 ps
CPU time 1.25 seconds
Started Aug 25 07:27:33 AM UTC 24
Finished Aug 25 07:27:36 AM UTC 24
Peak memory 218916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207073491 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.4207073491 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_partial_access.3475507920
Short name T142
Test name
Test status
Simulation time 76381358 ps
CPU time 2.39 seconds
Started Aug 25 07:27:29 AM UTC 24
Finished Aug 25 07:27:32 AM UTC 24
Peak memory 229508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475507920 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial_access.3475507920 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_walk.3188559463
Short name T735
Test name
Test status
Simulation time 12928160 ps
CPU time 1.06 seconds
Started Aug 25 07:27:29 AM UTC 24
Finished Aug 25 07:27:31 AM UTC 24
Peak memory 218976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188559463 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.3188559463 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_same_csr_outstanding.2703216505
Short name T156
Test name
Test status
Simulation time 221386235 ps
CPU time 3.66 seconds
Started Aug 25 07:27:39 AM UTC 24
Finished Aug 25 07:27:43 AM UTC 24
Peak memory 229508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703216505 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_outstanding.2703216505 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors.1296690958
Short name T105
Test name
Test status
Simulation time 32992300 ps
CPU time 1.82 seconds
Started Aug 25 07:27:25 AM UTC 24
Finished Aug 25 07:27:28 AM UTC 24
Peak memory 228728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296690958 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors.1296690958 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.1632992235
Short name T110
Test name
Test status
Simulation time 104198327 ps
CPU time 3.73 seconds
Started Aug 25 07:27:29 AM UTC 24
Finished Aug 25 07:27:34 AM UTC 24
Peak memory 229972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632992235 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors_with_csr_rw.
1632992235 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_errors.1000308453
Short name T119
Test name
Test status
Simulation time 105617234 ps
CPU time 5.26 seconds
Started Aug 25 07:27:31 AM UTC 24
Finished Aug 25 07:27:38 AM UTC 24
Peak memory 229628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000308453 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.1000308453 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_intg_err.2862202802
Short name T135
Test name
Test status
Simulation time 103639117 ps
CPU time 4.35 seconds
Started Aug 25 07:27:33 AM UTC 24
Finished Aug 25 07:27:39 AM UTC 24
Peak memory 229588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862202802 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.2862202802 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.2021662757
Short name T860
Test name
Test status
Simulation time 17780867 ps
CPU time 1.13 seconds
Started Aug 25 07:28:52 AM UTC 24
Finished Aug 25 07:28:54 AM UTC 24
Peak memory 218920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021662757 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.2021662757 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/30.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.2104168290
Short name T859
Test name
Test status
Simulation time 43697788 ps
CPU time 1.04 seconds
Started Aug 25 07:28:52 AM UTC 24
Finished Aug 25 07:28:54 AM UTC 24
Peak memory 218980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104168290 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.2104168290 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/31.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.3401627800
Short name T862
Test name
Test status
Simulation time 13976720 ps
CPU time 1.05 seconds
Started Aug 25 07:28:53 AM UTC 24
Finished Aug 25 07:28:55 AM UTC 24
Peak memory 218920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401627800 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.3401627800 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/32.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.2449412857
Short name T863
Test name
Test status
Simulation time 13279560 ps
CPU time 1.18 seconds
Started Aug 25 07:28:53 AM UTC 24
Finished Aug 25 07:28:55 AM UTC 24
Peak memory 218920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449412857 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.2449412857 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/33.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.3802078530
Short name T865
Test name
Test status
Simulation time 23857883 ps
CPU time 1.28 seconds
Started Aug 25 07:28:53 AM UTC 24
Finished Aug 25 07:28:56 AM UTC 24
Peak memory 218980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802078530 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.3802078530 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/34.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.3650233407
Short name T864
Test name
Test status
Simulation time 45135754 ps
CPU time 1.19 seconds
Started Aug 25 07:28:53 AM UTC 24
Finished Aug 25 07:28:56 AM UTC 24
Peak memory 218980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650233407 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.3650233407 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/35.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.1864697985
Short name T866
Test name
Test status
Simulation time 87048875 ps
CPU time 1.05 seconds
Started Aug 25 07:28:54 AM UTC 24
Finished Aug 25 07:28:56 AM UTC 24
Peak memory 218980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864697985 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.1864697985 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/36.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.3453949317
Short name T868
Test name
Test status
Simulation time 49993454 ps
CPU time 1.21 seconds
Started Aug 25 07:28:54 AM UTC 24
Finished Aug 25 07:28:57 AM UTC 24
Peak memory 218920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453949317 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.3453949317 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/37.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.1001318204
Short name T867
Test name
Test status
Simulation time 62096683 ps
CPU time 0.95 seconds
Started Aug 25 07:28:54 AM UTC 24
Finished Aug 25 07:28:56 AM UTC 24
Peak memory 218920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001318204 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.1001318204 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/38.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.463590007
Short name T872
Test name
Test status
Simulation time 38673140 ps
CPU time 1.28 seconds
Started Aug 25 07:28:55 AM UTC 24
Finished Aug 25 07:28:58 AM UTC 24
Peak memory 218860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463590007 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.463590007 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/39.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.2439769259
Short name T748
Test name
Test status
Simulation time 79790429 ps
CPU time 5.81 seconds
Started Aug 25 07:27:48 AM UTC 24
Finished Aug 25 07:27:56 AM UTC 24
Peak memory 219268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439769259 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.2439769259 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.2270913089
Short name T777
Test name
Test status
Simulation time 2610682554 ps
CPU time 30.94 seconds
Started Aug 25 07:27:47 AM UTC 24
Finished Aug 25 07:28:20 AM UTC 24
Peak memory 219392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270913089 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.2270913089 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_hw_reset.119705976
Short name T742
Test name
Test status
Simulation time 30175811 ps
CPU time 1.69 seconds
Started Aug 25 07:27:44 AM UTC 24
Finished Aug 25 07:27:47 AM UTC 24
Peak memory 228792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119705976 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.119705976 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.1896092382
Short name T744
Test name
Test status
Simulation time 29004143 ps
CPU time 2.74 seconds
Started Aug 25 07:27:48 AM UTC 24
Finished Aug 25 07:27:53 AM UTC 24
Peak memory 229636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1896092382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_
mem_rw_with_rand_reset.1896092382 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.2988820987
Short name T159
Test name
Test status
Simulation time 73707308 ps
CPU time 1.28 seconds
Started Aug 25 07:27:46 AM UTC 24
Finished Aug 25 07:27:48 AM UTC 24
Peak memory 218860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988820987 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.2988820987 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_intr_test.3950472173
Short name T158
Test name
Test status
Simulation time 46496993 ps
CPU time 1.1 seconds
Started Aug 25 07:27:44 AM UTC 24
Finished Aug 25 07:27:46 AM UTC 24
Peak memory 218976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950472173 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.3950472173 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_partial_access.4195642156
Short name T143
Test name
Test status
Simulation time 45946923 ps
CPU time 2.65 seconds
Started Aug 25 07:27:42 AM UTC 24
Finished Aug 25 07:27:46 AM UTC 24
Peak memory 229508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195642156 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial_access.4195642156 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_walk.4291444721
Short name T741
Test name
Test status
Simulation time 11875127 ps
CPU time 1.11 seconds
Started Aug 25 07:27:41 AM UTC 24
Finished Aug 25 07:27:43 AM UTC 24
Peak memory 218976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291444721 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.4291444721 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.1546014261
Short name T743
Test name
Test status
Simulation time 61209006 ps
CPU time 2.24 seconds
Started Aug 25 07:27:48 AM UTC 24
Finished Aug 25 07:27:52 AM UTC 24
Peak memory 229572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546014261 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_outstanding.1546014261 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors.197609642
Short name T106
Test name
Test status
Simulation time 39744721 ps
CPU time 1.92 seconds
Started Aug 25 07:27:39 AM UTC 24
Finished Aug 25 07:27:42 AM UTC 24
Peak memory 228728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197609642 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors.197609642 +enable_masking
=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.1417520273
Short name T108
Test name
Test status
Simulation time 231706634 ps
CPU time 4.27 seconds
Started Aug 25 07:27:41 AM UTC 24
Finished Aug 25 07:27:47 AM UTC 24
Peak memory 237120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417520273 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors_with_csr_rw.
1417520273 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.1982985361
Short name T124
Test name
Test status
Simulation time 603708093 ps
CPU time 6.03 seconds
Started Aug 25 07:27:43 AM UTC 24
Finished Aug 25 07:27:50 AM UTC 24
Peak memory 229664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982985361 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.1982985361 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.431138061
Short name T136
Test name
Test status
Simulation time 145593322 ps
CPU time 4.52 seconds
Started Aug 25 07:27:44 AM UTC 24
Finished Aug 25 07:27:50 AM UTC 24
Peak memory 229648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431138061 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.431138061 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.3804727459
Short name T869
Test name
Test status
Simulation time 64745931 ps
CPU time 1.02 seconds
Started Aug 25 07:28:56 AM UTC 24
Finished Aug 25 07:28:58 AM UTC 24
Peak memory 218980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804727459 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.3804727459 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/40.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.224398943
Short name T870
Test name
Test status
Simulation time 20262979 ps
CPU time 1.13 seconds
Started Aug 25 07:28:56 AM UTC 24
Finished Aug 25 07:28:58 AM UTC 24
Peak memory 218860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224398943 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.224398943 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/41.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.1661568369
Short name T871
Test name
Test status
Simulation time 19881896 ps
CPU time 1.08 seconds
Started Aug 25 07:28:56 AM UTC 24
Finished Aug 25 07:28:58 AM UTC 24
Peak memory 218920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661568369 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.1661568369 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/42.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.3206814461
Short name T873
Test name
Test status
Simulation time 24783973 ps
CPU time 1.06 seconds
Started Aug 25 07:28:56 AM UTC 24
Finished Aug 25 07:28:58 AM UTC 24
Peak memory 218980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206814461 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.3206814461 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/43.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.3497747862
Short name T874
Test name
Test status
Simulation time 209542361 ps
CPU time 1.19 seconds
Started Aug 25 07:28:56 AM UTC 24
Finished Aug 25 07:28:58 AM UTC 24
Peak memory 218920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497747862 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.3497747862 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/44.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.939005203
Short name T876
Test name
Test status
Simulation time 45517427 ps
CPU time 1.19 seconds
Started Aug 25 07:28:57 AM UTC 24
Finished Aug 25 07:28:59 AM UTC 24
Peak memory 218860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939005203 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.939005203 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/45.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.3407459003
Short name T877
Test name
Test status
Simulation time 11029222 ps
CPU time 1.18 seconds
Started Aug 25 07:28:57 AM UTC 24
Finished Aug 25 07:28:59 AM UTC 24
Peak memory 218980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407459003 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.3407459003 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/46.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.2682487631
Short name T875
Test name
Test status
Simulation time 43218740 ps
CPU time 1.16 seconds
Started Aug 25 07:28:57 AM UTC 24
Finished Aug 25 07:28:59 AM UTC 24
Peak memory 218920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682487631 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.2682487631 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/47.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.1737745457
Short name T879
Test name
Test status
Simulation time 44061314 ps
CPU time 1.23 seconds
Started Aug 25 07:28:57 AM UTC 24
Finished Aug 25 07:28:59 AM UTC 24
Peak memory 218908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737745457 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.1737745457 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/48.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.2459110733
Short name T878
Test name
Test status
Simulation time 106285354 ps
CPU time 1.04 seconds
Started Aug 25 07:28:57 AM UTC 24
Finished Aug 25 07:28:59 AM UTC 24
Peak memory 218908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459110733 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.2459110733 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/49.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.1550509859
Short name T751
Test name
Test status
Simulation time 95825879 ps
CPU time 2.43 seconds
Started Aug 25 07:27:55 AM UTC 24
Finished Aug 25 07:27:59 AM UTC 24
Peak memory 229636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1550509859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_
mem_rw_with_rand_reset.1550509859 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_rw.3134412975
Short name T749
Test name
Test status
Simulation time 32908696 ps
CPU time 1.7 seconds
Started Aug 25 07:27:54 AM UTC 24
Finished Aug 25 07:27:57 AM UTC 24
Peak memory 218876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134412975 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.3134412975 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/5.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.714941125
Short name T169
Test name
Test status
Simulation time 25603961 ps
CPU time 1.25 seconds
Started Aug 25 07:27:53 AM UTC 24
Finished Aug 25 07:27:55 AM UTC 24
Peak memory 218864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714941125 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.714941125 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/5.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_same_csr_outstanding.4039523131
Short name T750
Test name
Test status
Simulation time 213168679 ps
CPU time 2.89 seconds
Started Aug 25 07:27:54 AM UTC 24
Finished Aug 25 07:27:58 AM UTC 24
Peak memory 229572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039523131 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_outstanding.4039523131 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/5.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.4095036757
Short name T107
Test name
Test status
Simulation time 42012829 ps
CPU time 1.55 seconds
Started Aug 25 07:27:49 AM UTC 24
Finished Aug 25 07:27:52 AM UTC 24
Peak memory 218612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095036757 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors.4095036757 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.332332503
Short name T746
Test name
Test status
Simulation time 76499644 ps
CPU time 2.56 seconds
Started Aug 25 07:27:51 AM UTC 24
Finished Aug 25 07:27:55 AM UTC 24
Peak memory 229916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332332503 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors_with_csr_rw.3
32332503 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.265007893
Short name T747
Test name
Test status
Simulation time 72754609 ps
CPU time 3.53 seconds
Started Aug 25 07:27:51 AM UTC 24
Finished Aug 25 07:27:56 AM UTC 24
Peak memory 229808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265007893 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.265007893 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/5.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2314126893
Short name T757
Test name
Test status
Simulation time 72366053 ps
CPU time 3.23 seconds
Started Aug 25 07:28:00 AM UTC 24
Finished Aug 25 07:28:04 AM UTC 24
Peak memory 231620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2314126893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_
mem_rw_with_rand_reset.2314126893 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_rw.1405072765
Short name T754
Test name
Test status
Simulation time 52927329 ps
CPU time 1.25 seconds
Started Aug 25 07:27:59 AM UTC 24
Finished Aug 25 07:28:01 AM UTC 24
Peak memory 218672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405072765 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.1405072765 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/6.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_intr_test.2860469698
Short name T172
Test name
Test status
Simulation time 21478233 ps
CPU time 1.18 seconds
Started Aug 25 07:27:59 AM UTC 24
Finished Aug 25 07:28:01 AM UTC 24
Peak memory 218792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860469698 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.2860469698 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/6.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.2751609861
Short name T756
Test name
Test status
Simulation time 148233983 ps
CPU time 3.13 seconds
Started Aug 25 07:27:59 AM UTC 24
Finished Aug 25 07:28:03 AM UTC 24
Peak memory 229484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751609861 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_outstanding.2751609861 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/6.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.2143890960
Short name T753
Test name
Test status
Simulation time 32065794 ps
CPU time 2.6 seconds
Started Aug 25 07:27:56 AM UTC 24
Finished Aug 25 07:28:00 AM UTC 24
Peak memory 229908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143890960 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors_with_csr_rw.
2143890960 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.998368742
Short name T752
Test name
Test status
Simulation time 97726481 ps
CPU time 2.57 seconds
Started Aug 25 07:27:56 AM UTC 24
Finished Aug 25 07:28:00 AM UTC 24
Peak memory 229616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998368742 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.998368742 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/6.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.535097389
Short name T179
Test name
Test status
Simulation time 105451958 ps
CPU time 3.63 seconds
Started Aug 25 07:27:57 AM UTC 24
Finished Aug 25 07:28:02 AM UTC 24
Peak memory 229564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535097389 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.535097389 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/6.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.1208685005
Short name T762
Test name
Test status
Simulation time 40216285 ps
CPU time 2.25 seconds
Started Aug 25 07:28:05 AM UTC 24
Finished Aug 25 07:28:08 AM UTC 24
Peak memory 229572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1208685005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_
mem_rw_with_rand_reset.1208685005 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.1898339535
Short name T759
Test name
Test status
Simulation time 55960154 ps
CPU time 1.65 seconds
Started Aug 25 07:28:03 AM UTC 24
Finished Aug 25 07:28:06 AM UTC 24
Peak memory 218820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898339535 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.1898339535 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/7.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.904455420
Short name T170
Test name
Test status
Simulation time 25989004 ps
CPU time 1.07 seconds
Started Aug 25 07:28:02 AM UTC 24
Finished Aug 25 07:28:04 AM UTC 24
Peak memory 218864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904455420 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.904455420 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/7.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.2125432333
Short name T761
Test name
Test status
Simulation time 389985329 ps
CPU time 3.61 seconds
Started Aug 25 07:28:03 AM UTC 24
Finished Aug 25 07:28:08 AM UTC 24
Peak memory 229508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125432333 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_outstanding.2125432333 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/7.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors.3490091066
Short name T755
Test name
Test status
Simulation time 38030564 ps
CPU time 1.88 seconds
Started Aug 25 07:28:00 AM UTC 24
Finished Aug 25 07:28:03 AM UTC 24
Peak memory 228788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490091066 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors.3490091066 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.2275913976
Short name T758
Test name
Test status
Simulation time 90711538 ps
CPU time 2.44 seconds
Started Aug 25 07:28:01 AM UTC 24
Finished Aug 25 07:28:05 AM UTC 24
Peak memory 229636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275913976 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors_with_csr_rw.
2275913976 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.3032829192
Short name T173
Test name
Test status
Simulation time 46892615 ps
CPU time 4.25 seconds
Started Aug 25 07:28:01 AM UTC 24
Finished Aug 25 07:28:06 AM UTC 24
Peak memory 229204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032829192 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.3032829192 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/7.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.1141896706
Short name T178
Test name
Test status
Simulation time 146552034 ps
CPU time 3.34 seconds
Started Aug 25 07:28:02 AM UTC 24
Finished Aug 25 07:28:07 AM UTC 24
Peak memory 219328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141896706 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.1141896706 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/7.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.1649712159
Short name T768
Test name
Test status
Simulation time 72937678 ps
CPU time 3.44 seconds
Started Aug 25 07:28:09 AM UTC 24
Finished Aug 25 07:28:13 AM UTC 24
Peak memory 231620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1649712159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_
mem_rw_with_rand_reset.1649712159 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.1121750190
Short name T764
Test name
Test status
Simulation time 33611338 ps
CPU time 1.75 seconds
Started Aug 25 07:28:07 AM UTC 24
Finished Aug 25 07:28:10 AM UTC 24
Peak memory 218876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121750190 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.1121750190 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/8.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.1342067939
Short name T763
Test name
Test status
Simulation time 14309182 ps
CPU time 1.12 seconds
Started Aug 25 07:28:06 AM UTC 24
Finished Aug 25 07:28:09 AM UTC 24
Peak memory 218916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342067939 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.1342067939 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/8.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.3034154036
Short name T765
Test name
Test status
Simulation time 48171298 ps
CPU time 2.22 seconds
Started Aug 25 07:28:07 AM UTC 24
Finished Aug 25 07:28:11 AM UTC 24
Peak memory 229508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034154036 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_outstanding.3034154036 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/8.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.651305112
Short name T760
Test name
Test status
Simulation time 91304395 ps
CPU time 1.37 seconds
Started Aug 25 07:28:05 AM UTC 24
Finished Aug 25 07:28:08 AM UTC 24
Peak memory 228596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651305112 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors.651305112 +enable_masking
=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.3734388034
Short name T103
Test name
Test status
Simulation time 552899419 ps
CPU time 3.64 seconds
Started Aug 25 07:28:05 AM UTC 24
Finished Aug 25 07:28:10 AM UTC 24
Peak memory 229908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734388034 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors_with_csr_rw.
3734388034 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.2939939416
Short name T122
Test name
Test status
Simulation time 205537423 ps
CPU time 4.59 seconds
Started Aug 25 07:28:05 AM UTC 24
Finished Aug 25 07:28:11 AM UTC 24
Peak memory 229604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939939416 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.2939939416 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/8.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.3762596145
Short name T184
Test name
Test status
Simulation time 159552467 ps
CPU time 4.11 seconds
Started Aug 25 07:28:05 AM UTC 24
Finished Aug 25 07:28:10 AM UTC 24
Peak memory 219328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762596145 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.3762596145 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/8.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3813278972
Short name T772
Test name
Test status
Simulation time 166087854 ps
CPU time 2.8 seconds
Started Aug 25 07:28:12 AM UTC 24
Finished Aug 25 07:28:16 AM UTC 24
Peak memory 236652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3813278972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_
mem_rw_with_rand_reset.3813278972 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.221100305
Short name T769
Test name
Test status
Simulation time 58265401 ps
CPU time 1.36 seconds
Started Aug 25 07:28:12 AM UTC 24
Finished Aug 25 07:28:14 AM UTC 24
Peak memory 218920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221100305 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.221100305 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/9.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.3346526937
Short name T767
Test name
Test status
Simulation time 14407489 ps
CPU time 1.08 seconds
Started Aug 25 07:28:11 AM UTC 24
Finished Aug 25 07:28:13 AM UTC 24
Peak memory 218976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346526937 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.3346526937 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/9.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.1282463120
Short name T771
Test name
Test status
Simulation time 61535075 ps
CPU time 2.4 seconds
Started Aug 25 07:28:12 AM UTC 24
Finished Aug 25 07:28:15 AM UTC 24
Peak memory 229568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282463120 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_outstanding.1282463120 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/9.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.3107491419
Short name T766
Test name
Test status
Simulation time 343497077 ps
CPU time 2.1 seconds
Started Aug 25 07:28:09 AM UTC 24
Finished Aug 25 07:28:12 AM UTC 24
Peak memory 219676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107491419 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors.3107491419 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.3993780894
Short name T770
Test name
Test status
Simulation time 101942001 ps
CPU time 4.07 seconds
Started Aug 25 07:28:10 AM UTC 24
Finished Aug 25 07:28:15 AM UTC 24
Peak memory 236936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993780894 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors_with_csr_rw.
3993780894 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.4116218096
Short name T123
Test name
Test status
Simulation time 52340560 ps
CPU time 2.37 seconds
Started Aug 25 07:28:10 AM UTC 24
Finished Aug 25 07:28:13 AM UTC 24
Peak memory 229628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116218096 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.4116218096 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/9.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/0.kmac_app.1411403867
Short name T212
Test name
Test status
Simulation time 33012422574 ps
CPU time 200.1 seconds
Started Aug 25 09:46:11 AM UTC 24
Finished Aug 25 09:49:52 AM UTC 24
Peak memory 366360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411403867 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.1411403867 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/0.kmac_burst_write.612352158
Short name T137
Test name
Test status
Simulation time 2958369435 ps
CPU time 72.37 seconds
Started Aug 25 09:46:11 AM UTC 24
Finished Aug 25 09:47:49 AM UTC 24
Peak memory 235340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612352158 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.612352158 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/0.kmac_edn_timeout_error.4111351977
Short name T76
Test name
Test status
Simulation time 1604997796 ps
CPU time 56.39 seconds
Started Aug 25 09:46:12 AM UTC 24
Finished Aug 25 09:47:27 AM UTC 24
Peak memory 235220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111351977 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.4111351977 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_mode_error.11886679
Short name T91
Test name
Test status
Simulation time 7834585122 ps
CPU time 34.25 seconds
Started Aug 25 09:46:12 AM UTC 24
Finished Aug 25 09:47:05 AM UTC 24
Peak memory 235152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11886679 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.11886679 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/0.kmac_error.805964253
Short name T24
Test name
Test status
Simulation time 3271913693 ps
CPU time 363.38 seconds
Started Aug 25 09:46:11 AM UTC 24
Finished Aug 25 09:52:38 AM UTC 24
Peak memory 354144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805964253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.805964253 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/0.kmac_lc_escalation.2327101512
Short name T4
Test name
Test status
Simulation time 106694746 ps
CPU time 1.42 seconds
Started Aug 25 09:46:12 AM UTC 24
Finished Aug 25 09:46:31 AM UTC 24
Peak memory 229820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327101512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.2327101512 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/0.kmac_long_msg_and_output.1275956090
Short name T441
Test name
Test status
Simulation time 27943251547 ps
CPU time 1268.49 seconds
Started Aug 25 09:46:11 AM UTC 24
Finished Aug 25 10:08:01 AM UTC 24
Peak memory 1430720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275956090 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_and_output.1275956090 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/0.kmac_mubi.2649727360
Short name T34
Test name
Test status
Simulation time 23977899297 ps
CPU time 119.57 seconds
Started Aug 25 09:46:11 AM UTC 24
Finished Aug 25 09:48:31 AM UTC 24
Peak memory 274588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649727360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.2649727360 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/0.kmac_stress_all.4244714156
Short name T391
Test name
Test status
Simulation time 47001565202 ps
CPU time 1022.88 seconds
Started Aug 25 09:46:12 AM UTC 24
Finished Aug 25 10:03:46 AM UTC 24
Peak memory 384680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244714156 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.4244714156 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac.1768914146
Short name T1
Test name
Test status
Simulation time 167971660 ps
CPU time 1.74 seconds
Started Aug 25 09:46:11 AM UTC 24
Finished Aug 25 09:46:21 AM UTC 24
Peak memory 230140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768914146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac.1768914146 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac_xof.3558227730
Short name T12
Test name
Test status
Simulation time 31966306 ps
CPU time 2.54 seconds
Started Aug 25 09:46:11 AM UTC 24
Finished Aug 25 09:46:32 AM UTC 24
Peak memory 230532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558227730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.3558227730 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_224.2668552668
Short name T147
Test name
Test status
Simulation time 25089183597 ps
CPU time 76.73 seconds
Started Aug 25 09:46:11 AM UTC 24
Finished Aug 25 09:47:53 AM UTC 24
Peak memory 257792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668552668 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.2668552668
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_256.1712690173
Short name T586
Test name
Test status
Simulation time 75436109031 ps
CPU time 2066.71 seconds
Started Aug 25 09:46:11 AM UTC 24
Finished Aug 25 10:21:18 AM UTC 24
Peak memory 1127956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712690173 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.1712690173
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_384.1604576773
Short name T188
Test name
Test status
Simulation time 1475738080 ps
CPU time 36.85 seconds
Started Aug 25 09:46:11 AM UTC 24
Finished Aug 25 09:47:07 AM UTC 24
Peak memory 239356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604576773 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.1604576773
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_128.3296489581
Short name T220
Test name
Test status
Simulation time 169539749937 ps
CPU time 251.58 seconds
Started Aug 25 09:46:11 AM UTC 24
Finished Aug 25 09:50:44 AM UTC 24
Peak memory 440192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296489581 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.3296489
581 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_256.3354641789
Short name T160
Test name
Test status
Simulation time 6851914305 ps
CPU time 137.42 seconds
Started Aug 25 09:46:11 AM UTC 24
Finished Aug 25 09:48:48 AM UTC 24
Peak memory 263932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354641789 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.3354641
789 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/1.kmac_alert_test.1517238079
Short name T18
Test name
Test status
Simulation time 30633822 ps
CPU time 1.04 seconds
Started Aug 25 09:46:29 AM UTC 24
Finished Aug 25 09:46:31 AM UTC 24
Peak memory 214260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517238079 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.1517238079 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/1.kmac_app.1409651070
Short name T28
Test name
Test status
Simulation time 1558649415 ps
CPU time 31.27 seconds
Started Aug 25 09:46:18 AM UTC 24
Finished Aug 25 09:47:01 AM UTC 24
Peak memory 249616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409651070 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.1409651070 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/1.kmac_app_with_partial_data.12001180
Short name T29
Test name
Test status
Simulation time 45263125518 ps
CPU time 231.48 seconds
Started Aug 25 09:46:20 AM UTC 24
Finished Aug 25 09:50:19 AM UTC 24
Peak memory 382672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12001180 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.12001180 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/1.kmac_burst_write.1783305739
Short name T496
Test name
Test status
Simulation time 33057629732 ps
CPU time 1487.36 seconds
Started Aug 25 09:46:14 AM UTC 24
Finished Aug 25 10:11:42 AM UTC 24
Peak memory 273700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783305739 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.1783305739 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/1.kmac_edn_timeout_error.3194099766
Short name T48
Test name
Test status
Simulation time 1212091849 ps
CPU time 18.8 seconds
Started Aug 25 09:46:23 AM UTC 24
Finished Aug 25 09:46:54 AM UTC 24
Peak memory 235092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194099766 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.3194099766 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_mode_error.576767408
Short name T92
Test name
Test status
Simulation time 4552617706 ps
CPU time 45.2 seconds
Started Aug 25 09:46:23 AM UTC 24
Finished Aug 25 09:47:11 AM UTC 24
Peak memory 235108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576767408 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.576767408 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_ready_error.3143274570
Short name T35
Test name
Test status
Simulation time 3919080119 ps
CPU time 15.97 seconds
Started Aug 25 09:46:23 AM UTC 24
Finished Aug 25 09:46:51 AM UTC 24
Peak memory 230488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143274570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.3143274570 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_refresh.3157392284
Short name T263
Test name
Test status
Simulation time 73594063033 ps
CPU time 442.92 seconds
Started Aug 25 09:46:20 AM UTC 24
Finished Aug 25 09:53:53 AM UTC 24
Peak memory 519948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157392284 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.3157392284 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/1.kmac_error.3073059135
Short name T322
Test name
Test status
Simulation time 21786278170 ps
CPU time 647.06 seconds
Started Aug 25 09:46:20 AM UTC 24
Finished Aug 25 09:57:20 AM UTC 24
Peak memory 667484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073059135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.3073059135 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/1.kmac_key_error.2035528901
Short name T3
Test name
Test status
Simulation time 428212520 ps
CPU time 3.01 seconds
Started Aug 25 09:46:20 AM UTC 24
Finished Aug 25 09:46:28 AM UTC 24
Peak memory 230432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035528901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.2035528901 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/1.kmac_lc_escalation.3654096410
Short name T5
Test name
Test status
Simulation time 570295050 ps
CPU time 4 seconds
Started Aug 25 09:46:23 AM UTC 24
Finished Aug 25 09:46:39 AM UTC 24
Peak memory 232832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654096410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.3654096410 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/1.kmac_long_msg_and_output.3741267742
Short name T335
Test name
Test status
Simulation time 5932216837 ps
CPU time 710.32 seconds
Started Aug 25 09:46:14 AM UTC 24
Finished Aug 25 09:58:36 AM UTC 24
Peak memory 593296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741267742 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_and_output.3741267742 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/1.kmac_mubi.1045088658
Short name T27
Test name
Test status
Simulation time 1243048856 ps
CPU time 28.15 seconds
Started Aug 25 09:46:20 AM UTC 24
Finished Aug 25 09:46:53 AM UTC 24
Peak memory 251944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045088658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.1045088658 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/1.kmac_sec_cm.2292276151
Short name T10
Test name
Test status
Simulation time 34227419523 ps
CPU time 59.6 seconds
Started Aug 25 09:46:27 AM UTC 24
Finished Aug 25 09:47:35 AM UTC 24
Peak memory 263392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292276151 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.2292276151 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/1.kmac_sideload.1562941531
Short name T149
Test name
Test status
Simulation time 5675508961 ps
CPU time 77.46 seconds
Started Aug 25 09:46:14 AM UTC 24
Finished Aug 25 09:47:54 AM UTC 24
Peak memory 286752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562941531 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.1562941531 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/1.kmac_stress_all.4206870762
Short name T150
Test name
Test status
Simulation time 13817971093 ps
CPU time 637.42 seconds
Started Aug 25 09:46:25 AM UTC 24
Finished Aug 25 09:57:21 AM UTC 24
Peak memory 376932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206870762 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.4206870762 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac.3147076384
Short name T16
Test name
Test status
Simulation time 98836472 ps
CPU time 2.57 seconds
Started Aug 25 09:46:14 AM UTC 24
Finished Aug 25 09:46:38 AM UTC 24
Peak memory 230588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147076384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac.3147076384 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac_xof.2263510475
Short name T2
Test name
Test status
Simulation time 51585973 ps
CPU time 1.51 seconds
Started Aug 25 09:46:16 AM UTC 24
Finished Aug 25 09:46:26 AM UTC 24
Peak memory 229716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263510475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.2263510475 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_224.1948750643
Short name T78
Test name
Test status
Simulation time 2623997778 ps
CPU time 65.59 seconds
Started Aug 25 09:46:14 AM UTC 24
Finished Aug 25 09:47:32 AM UTC 24
Peak memory 255688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948750643 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.1948750643
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_256.2320926068
Short name T144
Test name
Test status
Simulation time 8643399978 ps
CPU time 62.12 seconds
Started Aug 25 09:46:14 AM UTC 24
Finished Aug 25 09:47:38 AM UTC 24
Peak memory 251636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320926068 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.2320926068
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_384.2610835073
Short name T189
Test name
Test status
Simulation time 1431239804 ps
CPU time 32.46 seconds
Started Aug 25 09:46:14 AM UTC 24
Finished Aug 25 09:47:08 AM UTC 24
Peak memory 230508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610835073 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.2610835073
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_512.1976551986
Short name T81
Test name
Test status
Simulation time 277895788 ps
CPU time 16.91 seconds
Started Aug 25 09:46:14 AM UTC 24
Finished Aug 25 09:46:53 AM UTC 24
Peak memory 228048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976551986 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.1976551986
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_128.2771196604
Short name T706
Test name
Test status
Simulation time 441232953582 ps
CPU time 4222.01 seconds
Started Aug 25 09:46:14 AM UTC 24
Finished Aug 25 10:57:51 AM UTC 24
Peak memory 3613532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771196604 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.2771196
604 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_256.1489036947
Short name T191
Test name
Test status
Simulation time 19004550188 ps
CPU time 162.4 seconds
Started Aug 25 09:46:14 AM UTC 24
Finished Aug 25 09:49:20 AM UTC 24
Peak memory 360208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489036947 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.1489036
947 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/10.kmac_alert_test.834906588
Short name T240
Test name
Test status
Simulation time 11997976 ps
CPU time 1.1 seconds
Started Aug 25 09:52:18 AM UTC 24
Finished Aug 25 09:52:20 AM UTC 24
Peak memory 214268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834906588 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.834906588 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/10.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/10.kmac_app.4115733457
Short name T307
Test name
Test status
Simulation time 9707053822 ps
CPU time 253.44 seconds
Started Aug 25 09:52:08 AM UTC 24
Finished Aug 25 09:56:26 AM UTC 24
Peak memory 399204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115733457 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.4115733457 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/10.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/10.kmac_burst_write.2254811505
Short name T409
Test name
Test status
Simulation time 6357943892 ps
CPU time 759.18 seconds
Started Aug 25 09:52:03 AM UTC 24
Finished Aug 25 10:04:53 AM UTC 24
Peak memory 247580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254811505 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.2254811505 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/10.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/10.kmac_edn_timeout_error.1566617597
Short name T251
Test name
Test status
Simulation time 6161713590 ps
CPU time 52.48 seconds
Started Aug 25 09:52:12 AM UTC 24
Finished Aug 25 09:53:06 AM UTC 24
Peak memory 235112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566617597 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.1566617597 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/10.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/10.kmac_entropy_mode_error.1673600242
Short name T242
Test name
Test status
Simulation time 178638934 ps
CPU time 15.83 seconds
Started Aug 25 09:52:12 AM UTC 24
Finished Aug 25 09:52:29 AM UTC 24
Peak memory 235164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673600242 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.1673600242 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/10.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/10.kmac_entropy_refresh.336018277
Short name T166
Test name
Test status
Simulation time 2516915131 ps
CPU time 94.13 seconds
Started Aug 25 09:52:08 AM UTC 24
Finished Aug 25 09:53:44 AM UTC 24
Peak memory 268100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336018277 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.336018277 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/10.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/10.kmac_error.920823872
Short name T32
Test name
Test status
Simulation time 13293701601 ps
CPU time 249.2 seconds
Started Aug 25 09:52:08 AM UTC 24
Finished Aug 25 09:56:21 AM UTC 24
Peak memory 421920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920823872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.920823872 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/10.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/10.kmac_key_error.544039162
Short name T241
Test name
Test status
Simulation time 1252286886 ps
CPU time 12.33 seconds
Started Aug 25 09:52:12 AM UTC 24
Finished Aug 25 09:52:25 AM UTC 24
Peak memory 230372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544039162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.544039162 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/10.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/10.kmac_lc_escalation.1139829007
Short name T133
Test name
Test status
Simulation time 42961434 ps
CPU time 1.75 seconds
Started Aug 25 09:52:14 AM UTC 24
Finished Aug 25 09:52:17 AM UTC 24
Peak memory 229788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139829007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.1139829007 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/10.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/10.kmac_long_msg_and_output.2813554162
Short name T684
Test name
Test status
Simulation time 21771509856 ps
CPU time 2888.76 seconds
Started Aug 25 09:52:01 AM UTC 24
Finished Aug 25 10:40:50 AM UTC 24
Peak memory 1582940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813554162 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_and_output.2813554162 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/10.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/10.kmac_sideload.3118876568
Short name T266
Test name
Test status
Simulation time 2874853728 ps
CPU time 115.12 seconds
Started Aug 25 09:52:03 AM UTC 24
Finished Aug 25 09:54:01 AM UTC 24
Peak memory 304992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118876568 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.3118876568 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/10.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/10.kmac_smoke.3483950164
Short name T127
Test name
Test status
Simulation time 124568275 ps
CPU time 4.68 seconds
Started Aug 25 09:52:01 AM UTC 24
Finished Aug 25 09:52:07 AM UTC 24
Peak memory 230640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483950164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.3483950164 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/10.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/10.kmac_stress_all.1568845223
Short name T673
Test name
Test status
Simulation time 206454438352 ps
CPU time 2507.63 seconds
Started Aug 25 09:52:16 AM UTC 24
Finished Aug 25 10:34:36 AM UTC 24
Peak memory 1186072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568845223 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.1568845223 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/10.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/11.kmac_alert_test.2225194163
Short name T248
Test name
Test status
Simulation time 52346724 ps
CPU time 1.12 seconds
Started Aug 25 09:52:48 AM UTC 24
Finished Aug 25 09:52:50 AM UTC 24
Peak memory 214264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225194163 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.2225194163 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/11.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/11.kmac_app.3865758841
Short name T326
Test name
Test status
Simulation time 42584962831 ps
CPU time 310.49 seconds
Started Aug 25 09:52:27 AM UTC 24
Finished Aug 25 09:57:42 AM UTC 24
Peak memory 403228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865758841 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.3865758841 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/11.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/11.kmac_burst_write.75804697
Short name T45
Test name
Test status
Simulation time 2292971346 ps
CPU time 270.91 seconds
Started Aug 25 09:52:23 AM UTC 24
Finished Aug 25 09:56:58 AM UTC 24
Peak memory 237412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75804697 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.75804697 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/11.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/11.kmac_edn_timeout_error.4265244731
Short name T252
Test name
Test status
Simulation time 748050523 ps
CPU time 33.87 seconds
Started Aug 25 09:52:32 AM UTC 24
Finished Aug 25 09:53:07 AM UTC 24
Peak memory 235156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265244731 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.4265244731 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/11.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/11.kmac_entropy_mode_error.189850323
Short name T249
Test name
Test status
Simulation time 477546277 ps
CPU time 13.45 seconds
Started Aug 25 09:52:36 AM UTC 24
Finished Aug 25 09:52:51 AM UTC 24
Peak memory 235168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189850323 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.189850323 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/11.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/11.kmac_entropy_refresh.683191187
Short name T318
Test name
Test status
Simulation time 79466495281 ps
CPU time 278.56 seconds
Started Aug 25 09:52:27 AM UTC 24
Finished Aug 25 09:57:10 AM UTC 24
Peak memory 397140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683191187 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.683191187 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/11.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/11.kmac_error.2675032346
Short name T94
Test name
Test status
Simulation time 1659912260 ps
CPU time 79.06 seconds
Started Aug 25 09:52:30 AM UTC 24
Finished Aug 25 09:53:51 AM UTC 24
Peak memory 268004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675032346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.2675032346 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/11.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/11.kmac_key_error.1795348669
Short name T247
Test name
Test status
Simulation time 1900614639 ps
CPU time 14.81 seconds
Started Aug 25 09:52:32 AM UTC 24
Finished Aug 25 09:52:48 AM UTC 24
Peak memory 230376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795348669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.1795348669 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/11.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/11.kmac_lc_escalation.4128200225
Short name T59
Test name
Test status
Simulation time 936101546 ps
CPU time 56.89 seconds
Started Aug 25 09:52:39 AM UTC 24
Finished Aug 25 09:53:38 AM UTC 24
Peak memory 255832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128200225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.4128200225 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/11.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/11.kmac_long_msg_and_output.2870533725
Short name T285
Test name
Test status
Simulation time 17289877235 ps
CPU time 154.56 seconds
Started Aug 25 09:52:18 AM UTC 24
Finished Aug 25 09:54:56 AM UTC 24
Peak memory 415828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870533725 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_and_output.2870533725 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/11.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/11.kmac_sideload.603617296
Short name T33
Test name
Test status
Simulation time 381883690 ps
CPU time 40.05 seconds
Started Aug 25 09:52:20 AM UTC 24
Finished Aug 25 09:53:02 AM UTC 24
Peak memory 241500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603617296 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.603617296 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/11.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/11.kmac_smoke.1334028538
Short name T257
Test name
Test status
Simulation time 2636127195 ps
CPU time 77.19 seconds
Started Aug 25 09:52:18 AM UTC 24
Finished Aug 25 09:53:37 AM UTC 24
Peak memory 232756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334028538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.1334028538 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/11.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/11.kmac_stress_all.2168336317
Short name T680
Test name
Test status
Simulation time 484287662392 ps
CPU time 2786.29 seconds
Started Aug 25 09:52:44 AM UTC 24
Finished Aug 25 10:39:47 AM UTC 24
Peak memory 1431844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168336317 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.2168336317 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/11.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/12.kmac_alert_test.3065799207
Short name T255
Test name
Test status
Simulation time 16089535 ps
CPU time 1.22 seconds
Started Aug 25 09:53:20 AM UTC 24
Finished Aug 25 09:53:22 AM UTC 24
Peak memory 214264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065799207 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.3065799207 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/12.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/12.kmac_app.984743930
Short name T264
Test name
Test status
Simulation time 8181664929 ps
CPU time 57.59 seconds
Started Aug 25 09:52:56 AM UTC 24
Finished Aug 25 09:53:55 AM UTC 24
Peak memory 257892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984743930 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.984743930 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/12.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/12.kmac_burst_write.2881361779
Short name T151
Test name
Test status
Simulation time 62471348831 ps
CPU time 291.43 seconds
Started Aug 25 09:52:53 AM UTC 24
Finished Aug 25 09:57:49 AM UTC 24
Peak memory 237412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881361779 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.2881361779 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/12.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/12.kmac_edn_timeout_error.1911189192
Short name T268
Test name
Test status
Simulation time 1719602344 ps
CPU time 55.71 seconds
Started Aug 25 09:53:07 AM UTC 24
Finished Aug 25 09:54:05 AM UTC 24
Peak memory 235356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911189192 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.1911189192 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/12.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/12.kmac_entropy_mode_error.1647180205
Short name T262
Test name
Test status
Simulation time 5721453030 ps
CPU time 41.12 seconds
Started Aug 25 09:53:08 AM UTC 24
Finished Aug 25 09:53:51 AM UTC 24
Peak memory 235284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647180205 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.1647180205 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/12.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/12.kmac_entropy_refresh.2653057014
Short name T344
Test name
Test status
Simulation time 15055440668 ps
CPU time 382.21 seconds
Started Aug 25 09:53:01 AM UTC 24
Finished Aug 25 09:59:29 AM UTC 24
Peak memory 356176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653057014 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.2653057014 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/12.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/12.kmac_error.4213623003
Short name T387
Test name
Test status
Simulation time 38007597721 ps
CPU time 609.16 seconds
Started Aug 25 09:53:03 AM UTC 24
Finished Aug 25 10:03:22 AM UTC 24
Peak memory 640796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213623003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.4213623003 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/12.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/12.kmac_key_error.3362449622
Short name T253
Test name
Test status
Simulation time 1142481803 ps
CPU time 12.74 seconds
Started Aug 25 09:53:04 AM UTC 24
Finished Aug 25 09:53:19 AM UTC 24
Peak memory 230368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362449622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.3362449622 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/12.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/12.kmac_lc_escalation.1855648819
Short name T42
Test name
Test status
Simulation time 235545425 ps
CPU time 1.87 seconds
Started Aug 25 09:53:12 AM UTC 24
Finished Aug 25 09:53:14 AM UTC 24
Peak memory 229720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855648819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.1855648819 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/12.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/12.kmac_long_msg_and_output.8372851
Short name T630
Test name
Test status
Simulation time 30148231620 ps
CPU time 1917.82 seconds
Started Aug 25 09:52:51 AM UTC 24
Finished Aug 25 10:25:15 AM UTC 24
Peak memory 1148480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8372851 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_and_output.8372851 +enable_masking=
0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/12.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/12.kmac_sideload.1489913336
Short name T393
Test name
Test status
Simulation time 84128606327 ps
CPU time 648.37 seconds
Started Aug 25 09:52:51 AM UTC 24
Finished Aug 25 10:03:49 AM UTC 24
Peak memory 650732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489913336 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.1489913336 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/12.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/12.kmac_smoke.3953634626
Short name T265
Test name
Test status
Simulation time 1080220272 ps
CPU time 68.72 seconds
Started Aug 25 09:52:48 AM UTC 24
Finished Aug 25 09:53:59 AM UTC 24
Peak memory 230572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953634626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.3953634626 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/12.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/12.kmac_stress_all.3587482390
Short name T246
Test name
Test status
Simulation time 850941542 ps
CPU time 26.95 seconds
Started Aug 25 09:53:16 AM UTC 24
Finished Aug 25 09:53:44 AM UTC 24
Peak memory 243604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587482390 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.3587482390 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/12.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/13.kmac_alert_test.1633845955
Short name T261
Test name
Test status
Simulation time 23773244 ps
CPU time 1.28 seconds
Started Aug 25 09:53:45 AM UTC 24
Finished Aug 25 09:53:47 AM UTC 24
Peak memory 214264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633845955 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.1633845955 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/13.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/13.kmac_app.2132242930
Short name T305
Test name
Test status
Simulation time 2351179090 ps
CPU time 163.3 seconds
Started Aug 25 09:53:35 AM UTC 24
Finished Aug 25 09:56:22 AM UTC 24
Peak memory 284568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132242930 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.2132242930 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/13.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/13.kmac_burst_write.2968770928
Short name T481
Test name
Test status
Simulation time 7975850206 ps
CPU time 999.5 seconds
Started Aug 25 09:53:29 AM UTC 24
Finished Aug 25 10:10:23 AM UTC 24
Peak memory 251700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968770928 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.2968770928 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/13.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/13.kmac_edn_timeout_error.1998775573
Short name T269
Test name
Test status
Simulation time 1750954917 ps
CPU time 21.97 seconds
Started Aug 25 09:53:41 AM UTC 24
Finished Aug 25 09:54:05 AM UTC 24
Peak memory 235112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998775573 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.1998775573 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/13.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/13.kmac_entropy_mode_error.1755828395
Short name T273
Test name
Test status
Simulation time 307581830 ps
CPU time 27.29 seconds
Started Aug 25 09:53:43 AM UTC 24
Finished Aug 25 09:54:12 AM UTC 24
Peak memory 230512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755828395 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.1755828395 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/13.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/13.kmac_entropy_refresh.932674760
Short name T360
Test name
Test status
Simulation time 14995348993 ps
CPU time 432.7 seconds
Started Aug 25 09:53:37 AM UTC 24
Finished Aug 25 10:00:57 AM UTC 24
Peak memory 505712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932674760 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.932674760 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/13.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/13.kmac_error.821725927
Short name T311
Test name
Test status
Simulation time 3987297983 ps
CPU time 184.65 seconds
Started Aug 25 09:53:38 AM UTC 24
Finished Aug 25 09:56:46 AM UTC 24
Peak memory 294744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821725927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.821725927 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/13.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/13.kmac_key_error.322996925
Short name T258
Test name
Test status
Simulation time 43514126 ps
CPU time 1.54 seconds
Started Aug 25 09:53:38 AM UTC 24
Finished Aug 25 09:53:41 AM UTC 24
Peak memory 229844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322996925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.322996925 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/13.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/13.kmac_lc_escalation.492837056
Short name T62
Test name
Test status
Simulation time 123014782 ps
CPU time 1.8 seconds
Started Aug 25 09:53:45 AM UTC 24
Finished Aug 25 09:53:47 AM UTC 24
Peak memory 229744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492837056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.492837056 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/13.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/13.kmac_long_msg_and_output.3420263132
Short name T380
Test name
Test status
Simulation time 18817228296 ps
CPU time 564.79 seconds
Started Aug 25 09:53:23 AM UTC 24
Finished Aug 25 10:02:56 AM UTC 24
Peak memory 511888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420263132 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_and_output.3420263132 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/13.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/13.kmac_sideload.3121257372
Short name T382
Test name
Test status
Simulation time 37016024279 ps
CPU time 576.22 seconds
Started Aug 25 09:53:25 AM UTC 24
Finished Aug 25 10:03:10 AM UTC 24
Peak memory 624540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121257372 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.3121257372 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/13.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/13.kmac_smoke.3989405758
Short name T259
Test name
Test status
Simulation time 2459730264 ps
CPU time 20.8 seconds
Started Aug 25 09:53:21 AM UTC 24
Finished Aug 25 09:53:43 AM UTC 24
Peak memory 230832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989405758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.3989405758 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/13.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/13.kmac_stress_all.3176638965
Short name T152
Test name
Test status
Simulation time 36609595397 ps
CPU time 322.58 seconds
Started Aug 25 09:53:45 AM UTC 24
Finished Aug 25 09:59:12 AM UTC 24
Peak memory 341796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176638965 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.3176638965 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/13.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/14.kmac_alert_test.1806529846
Short name T274
Test name
Test status
Simulation time 224353929 ps
CPU time 1.24 seconds
Started Aug 25 09:54:11 AM UTC 24
Finished Aug 25 09:54:13 AM UTC 24
Peak memory 216392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806529846 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.1806529846 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/14.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/14.kmac_app.1395456212
Short name T270
Test name
Test status
Simulation time 573297179 ps
CPU time 14.61 seconds
Started Aug 25 09:53:54 AM UTC 24
Finished Aug 25 09:54:10 AM UTC 24
Peak memory 232612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395456212 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.1395456212 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/14.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/14.kmac_burst_write.4238706843
Short name T287
Test name
Test status
Simulation time 3375880673 ps
CPU time 77.79 seconds
Started Aug 25 09:53:52 AM UTC 24
Finished Aug 25 09:55:12 AM UTC 24
Peak memory 235528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238706843 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.4238706843 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/14.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/14.kmac_edn_timeout_error.2324691185
Short name T272
Test name
Test status
Simulation time 101127111 ps
CPU time 7.54 seconds
Started Aug 25 09:54:02 AM UTC 24
Finished Aug 25 09:54:11 AM UTC 24
Peak memory 228448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324691185 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.2324691185 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/14.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/14.kmac_entropy_mode_error.1245560410
Short name T286
Test name
Test status
Simulation time 1660842992 ps
CPU time 51.41 seconds
Started Aug 25 09:54:05 AM UTC 24
Finished Aug 25 09:54:58 AM UTC 24
Peak memory 235084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245560410 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.1245560410 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/14.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/14.kmac_entropy_refresh.4163318401
Short name T332
Test name
Test status
Simulation time 35336947737 ps
CPU time 264.71 seconds
Started Aug 25 09:53:56 AM UTC 24
Finished Aug 25 09:58:25 AM UTC 24
Peak memory 378636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163318401 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.4163318401 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/14.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/14.kmac_error.2630617564
Short name T299
Test name
Test status
Simulation time 19023230806 ps
CPU time 121.58 seconds
Started Aug 25 09:54:00 AM UTC 24
Finished Aug 25 09:56:04 AM UTC 24
Peak memory 327452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630617564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.2630617564 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/14.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/14.kmac_key_error.2428671833
Short name T276
Test name
Test status
Simulation time 1496820362 ps
CPU time 13.85 seconds
Started Aug 25 09:54:02 AM UTC 24
Finished Aug 25 09:54:17 AM UTC 24
Peak memory 230368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428671833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.2428671833 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/14.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/14.kmac_lc_escalation.2435265071
Short name T8
Test name
Test status
Simulation time 52255260 ps
CPU time 1.85 seconds
Started Aug 25 09:54:05 AM UTC 24
Finished Aug 25 09:54:08 AM UTC 24
Peak memory 229668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435265071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.2435265071 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/14.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/14.kmac_long_msg_and_output.299610022
Short name T607
Test name
Test status
Simulation time 14007957420 ps
CPU time 1729.59 seconds
Started Aug 25 09:53:49 AM UTC 24
Finished Aug 25 10:23:02 AM UTC 24
Peak memory 1081112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299610022 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_and_output.299610022 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/14.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/14.kmac_sideload.4134392270
Short name T297
Test name
Test status
Simulation time 5076446945 ps
CPU time 120.62 seconds
Started Aug 25 09:53:52 AM UTC 24
Finished Aug 25 09:55:55 AM UTC 24
Peak memory 272148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134392270 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.4134392270 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/14.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/14.kmac_smoke.1887363183
Short name T278
Test name
Test status
Simulation time 1249495190 ps
CPU time 42.93 seconds
Started Aug 25 09:53:48 AM UTC 24
Finished Aug 25 09:54:32 AM UTC 24
Peak memory 230744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887363183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.1887363183 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/14.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/14.kmac_stress_all.2826301247
Short name T90
Test name
Test status
Simulation time 817893578 ps
CPU time 34.8 seconds
Started Aug 25 09:54:10 AM UTC 24
Finished Aug 25 09:54:46 AM UTC 24
Peak memory 247348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826301247 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.2826301247 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/14.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/15.kmac_alert_test.1201868361
Short name T283
Test name
Test status
Simulation time 15931591 ps
CPU time 1.12 seconds
Started Aug 25 09:54:50 AM UTC 24
Finished Aug 25 09:54:53 AM UTC 24
Peak memory 214264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201868361 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.1201868361 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/15.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/15.kmac_app.3084667813
Short name T347
Test name
Test status
Simulation time 10464796304 ps
CPU time 311.53 seconds
Started Aug 25 09:54:16 AM UTC 24
Finished Aug 25 09:59:33 AM UTC 24
Peak memory 325572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084667813 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.3084667813 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/15.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/15.kmac_burst_write.596014755
Short name T192
Test name
Test status
Simulation time 5795667785 ps
CPU time 606.08 seconds
Started Aug 25 09:54:14 AM UTC 24
Finished Aug 25 10:04:29 AM UTC 24
Peak memory 251748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596014755 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.596014755 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/15.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/15.kmac_edn_timeout_error.1390898516
Short name T289
Test name
Test status
Simulation time 647846947 ps
CPU time 41.29 seconds
Started Aug 25 09:54:33 AM UTC 24
Finished Aug 25 09:55:16 AM UTC 24
Peak memory 245292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390898516 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.1390898516 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/15.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/15.kmac_entropy_mode_error.2393746335
Short name T282
Test name
Test status
Simulation time 958458774 ps
CPU time 8.18 seconds
Started Aug 25 09:54:40 AM UTC 24
Finished Aug 25 09:54:50 AM UTC 24
Peak memory 235148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393746335 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.2393746335 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/15.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/15.kmac_entropy_refresh.2838235209
Short name T284
Test name
Test status
Simulation time 33302524159 ps
CPU time 34.45 seconds
Started Aug 25 09:54:18 AM UTC 24
Finished Aug 25 09:54:54 AM UTC 24
Peak memory 247616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838235209 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.2838235209 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/15.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/15.kmac_key_error.1316859327
Short name T279
Test name
Test status
Simulation time 644477151 ps
CPU time 5.82 seconds
Started Aug 25 09:54:32 AM UTC 24
Finished Aug 25 09:54:39 AM UTC 24
Peak memory 230364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316859327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.1316859327 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/15.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/15.kmac_lc_escalation.1029012430
Short name T280
Test name
Test status
Simulation time 59662096 ps
CPU time 2.03 seconds
Started Aug 25 09:54:46 AM UTC 24
Finished Aug 25 09:54:50 AM UTC 24
Peak memory 230504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029012430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.1029012430 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/15.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/15.kmac_long_msg_and_output.4064055273
Short name T704
Test name
Test status
Simulation time 187174054962 ps
CPU time 3707.35 seconds
Started Aug 25 09:54:12 AM UTC 24
Finished Aug 25 10:56:48 AM UTC 24
Peak memory 3405652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064055273 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_and_output.4064055273 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/15.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/15.kmac_sideload.1915838237
Short name T363
Test name
Test status
Simulation time 48810425226 ps
CPU time 421.8 seconds
Started Aug 25 09:54:13 AM UTC 24
Finished Aug 25 10:01:22 AM UTC 24
Peak memory 509780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915838237 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.1915838237 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/15.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/15.kmac_smoke.3283791047
Short name T295
Test name
Test status
Simulation time 13515178537 ps
CPU time 91.75 seconds
Started Aug 25 09:54:12 AM UTC 24
Finished Aug 25 09:55:46 AM UTC 24
Peak memory 235464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283791047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.3283791047 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/15.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/15.kmac_stress_all.1144722515
Short name T532
Test name
Test status
Simulation time 28095001604 ps
CPU time 1209.63 seconds
Started Aug 25 09:54:50 AM UTC 24
Finished Aug 25 10:15:17 AM UTC 24
Peak memory 663668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144722515 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.1144722515 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/15.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/16.kmac_alert_test.1727764496
Short name T292
Test name
Test status
Simulation time 46414855 ps
CPU time 1.16 seconds
Started Aug 25 09:55:26 AM UTC 24
Finished Aug 25 09:55:29 AM UTC 24
Peak memory 214264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727764496 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.1727764496 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/16.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/16.kmac_app.2062731101
Short name T296
Test name
Test status
Simulation time 3378915496 ps
CPU time 50.83 seconds
Started Aug 25 09:54:58 AM UTC 24
Finished Aug 25 09:55:50 AM UTC 24
Peak memory 243524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062731101 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.2062731101 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/16.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/16.kmac_burst_write.3184671766
Short name T460
Test name
Test status
Simulation time 38906244209 ps
CPU time 836.64 seconds
Started Aug 25 09:54:57 AM UTC 24
Finished Aug 25 10:09:06 AM UTC 24
Peak memory 249640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184671766 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.3184671766 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/16.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/16.kmac_edn_timeout_error.3761553792
Short name T298
Test name
Test status
Simulation time 1312147523 ps
CPU time 45.41 seconds
Started Aug 25 09:55:15 AM UTC 24
Finished Aug 25 09:56:02 AM UTC 24
Peak memory 232544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761553792 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.3761553792 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/16.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/16.kmac_entropy_mode_error.3542103415
Short name T293
Test name
Test status
Simulation time 648942086 ps
CPU time 15.94 seconds
Started Aug 25 09:55:17 AM UTC 24
Finished Aug 25 09:55:34 AM UTC 24
Peak memory 235104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542103415 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.3542103415 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/16.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/16.kmac_entropy_refresh.2532053695
Short name T308
Test name
Test status
Simulation time 7343394983 ps
CPU time 87.57 seconds
Started Aug 25 09:54:59 AM UTC 24
Finished Aug 25 09:56:29 AM UTC 24
Peak memory 257944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532053695 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.2532053695 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/16.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/16.kmac_error.962500968
Short name T365
Test name
Test status
Simulation time 12015858980 ps
CPU time 385.78 seconds
Started Aug 25 09:55:01 AM UTC 24
Finished Aug 25 10:01:33 AM UTC 24
Peak memory 497436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962500968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.962500968 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/16.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/16.kmac_key_error.3810761420
Short name T291
Test name
Test status
Simulation time 2142207246 ps
CPU time 11.64 seconds
Started Aug 25 09:55:13 AM UTC 24
Finished Aug 25 09:55:26 AM UTC 24
Peak memory 230556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810761420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.3810761420 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/16.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/16.kmac_lc_escalation.1338306798
Short name T82
Test name
Test status
Simulation time 171504114 ps
CPU time 1.73 seconds
Started Aug 25 09:55:21 AM UTC 24
Finished Aug 25 09:55:24 AM UTC 24
Peak memory 233752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338306798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.1338306798 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/16.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/16.kmac_long_msg_and_output.2946435504
Short name T703
Test name
Test status
Simulation time 119693770151 ps
CPU time 3450.42 seconds
Started Aug 25 09:54:54 AM UTC 24
Finished Aug 25 10:53:13 AM UTC 24
Peak memory 1937340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946435504 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_and_output.2946435504 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/16.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/16.kmac_sideload.2772523841
Short name T290
Test name
Test status
Simulation time 8052231149 ps
CPU time 24.79 seconds
Started Aug 25 09:54:55 AM UTC 24
Finished Aug 25 09:55:21 AM UTC 24
Peak memory 251740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772523841 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.2772523841 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/16.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/16.kmac_smoke.3766523291
Short name T288
Test name
Test status
Simulation time 4522036357 ps
CPU time 21.96 seconds
Started Aug 25 09:54:50 AM UTC 24
Finished Aug 25 09:55:14 AM UTC 24
Peak memory 230700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766523291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.3766523291 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/16.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/16.kmac_stress_all.3192845701
Short name T632
Test name
Test status
Simulation time 87175782685 ps
CPU time 1775.29 seconds
Started Aug 25 09:55:24 AM UTC 24
Finished Aug 25 10:25:23 AM UTC 24
Peak memory 1194088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192845701 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.3192845701 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/16.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/17.kmac_alert_test.2152322309
Short name T306
Test name
Test status
Simulation time 19656327 ps
CPU time 1.08 seconds
Started Aug 25 09:56:19 AM UTC 24
Finished Aug 25 09:56:22 AM UTC 24
Peak memory 214264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152322309 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.2152322309 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/17.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/17.kmac_app.2464786631
Short name T301
Test name
Test status
Simulation time 660644497 ps
CPU time 15.75 seconds
Started Aug 25 09:55:51 AM UTC 24
Finished Aug 25 09:56:08 AM UTC 24
Peak memory 230520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464786631 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.2464786631 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/17.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/17.kmac_burst_write.2147535197
Short name T176
Test name
Test status
Simulation time 4053459778 ps
CPU time 407.05 seconds
Started Aug 25 09:55:47 AM UTC 24
Finished Aug 25 10:02:40 AM UTC 24
Peak memory 243556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147535197 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.2147535197 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/17.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/17.kmac_edn_timeout_error.4097421553
Short name T303
Test name
Test status
Simulation time 111787824 ps
CPU time 11.16 seconds
Started Aug 25 09:56:05 AM UTC 24
Finished Aug 25 09:56:17 AM UTC 24
Peak memory 232424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097421553 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.4097421553 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/17.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/17.kmac_entropy_mode_error.3041227335
Short name T317
Test name
Test status
Simulation time 7798885825 ps
CPU time 57.62 seconds
Started Aug 25 09:56:08 AM UTC 24
Finished Aug 25 09:57:08 AM UTC 24
Peak memory 235272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041227335 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.3041227335 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/17.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/17.kmac_entropy_refresh.1632342939
Short name T359
Test name
Test status
Simulation time 6625280035 ps
CPU time 295.13 seconds
Started Aug 25 09:55:56 AM UTC 24
Finished Aug 25 10:00:56 AM UTC 24
Peak memory 321300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632342939 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.1632342939 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/17.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/17.kmac_key_error.3502519459
Short name T302
Test name
Test status
Simulation time 4459198177 ps
CPU time 9.41 seconds
Started Aug 25 09:56:05 AM UTC 24
Finished Aug 25 09:56:16 AM UTC 24
Peak memory 230440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502519459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.3502519459 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/17.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/17.kmac_lc_escalation.2353394615
Short name T63
Test name
Test status
Simulation time 153690217 ps
CPU time 2.2 seconds
Started Aug 25 09:56:16 AM UTC 24
Finished Aug 25 09:56:20 AM UTC 24
Peak memory 232420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353394615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.2353394615 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/17.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/17.kmac_long_msg_and_output.2564283381
Short name T570
Test name
Test status
Simulation time 22816666372 ps
CPU time 1374.39 seconds
Started Aug 25 09:55:36 AM UTC 24
Finished Aug 25 10:18:48 AM UTC 24
Peak memory 944036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564283381 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_and_output.2564283381 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/17.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/17.kmac_sideload.4096347118
Short name T338
Test name
Test status
Simulation time 14804264139 ps
CPU time 182.37 seconds
Started Aug 25 09:55:45 AM UTC 24
Finished Aug 25 09:58:50 AM UTC 24
Peak memory 294808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096347118 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.4096347118 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/17.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/17.kmac_smoke.333500750
Short name T304
Test name
Test status
Simulation time 12999978801 ps
CPU time 47.26 seconds
Started Aug 25 09:55:29 AM UTC 24
Finished Aug 25 09:56:18 AM UTC 24
Peak memory 235340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333500750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.333500750 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/17.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/17.kmac_stress_all.492179413
Short name T488
Test name
Test status
Simulation time 57489344222 ps
CPU time 885.89 seconds
Started Aug 25 09:56:18 AM UTC 24
Finished Aug 25 10:11:18 AM UTC 24
Peak memory 360596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492179413 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.492179413 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/17.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/18.kmac_alert_test.2770056049
Short name T315
Test name
Test status
Simulation time 20724962 ps
CPU time 1.29 seconds
Started Aug 25 09:57:02 AM UTC 24
Finished Aug 25 09:57:05 AM UTC 24
Peak memory 214264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770056049 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.2770056049 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/18.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/18.kmac_app.653632179
Short name T310
Test name
Test status
Simulation time 610652599 ps
CPU time 12.64 seconds
Started Aug 25 09:56:27 AM UTC 24
Finished Aug 25 09:56:41 AM UTC 24
Peak memory 230572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653632179 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.653632179 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/18.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/18.kmac_burst_write.2662365517
Short name T46
Test name
Test status
Simulation time 1308590324 ps
CPU time 156.98 seconds
Started Aug 25 09:56:23 AM UTC 24
Finished Aug 25 09:59:03 AM UTC 24
Peak memory 235292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662365517 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.2662365517 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/18.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/18.kmac_edn_timeout_error.430811207
Short name T319
Test name
Test status
Simulation time 234785672 ps
CPU time 21.56 seconds
Started Aug 25 09:56:47 AM UTC 24
Finished Aug 25 09:57:10 AM UTC 24
Peak memory 230420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430811207 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.430811207 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/18.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/18.kmac_entropy_mode_error.2719249822
Short name T316
Test name
Test status
Simulation time 61797054 ps
CPU time 5.74 seconds
Started Aug 25 09:56:58 AM UTC 24
Finished Aug 25 09:57:05 AM UTC 24
Peak memory 228496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719249822 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.2719249822 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/18.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/18.kmac_entropy_refresh.1036572823
Short name T383
Test name
Test status
Simulation time 67357204326 ps
CPU time 393.85 seconds
Started Aug 25 09:56:30 AM UTC 24
Finished Aug 25 10:03:10 AM UTC 24
Peak memory 483160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036572823 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.1036572823 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/18.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/18.kmac_error.4140250138
Short name T390
Test name
Test status
Simulation time 112778554923 ps
CPU time 414.24 seconds
Started Aug 25 09:56:35 AM UTC 24
Finished Aug 25 10:03:36 AM UTC 24
Peak memory 530364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140250138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.4140250138 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/18.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/18.kmac_key_error.3189935385
Short name T312
Test name
Test status
Simulation time 6306667643 ps
CPU time 13.67 seconds
Started Aug 25 09:56:42 AM UTC 24
Finished Aug 25 09:56:57 AM UTC 24
Peak memory 230624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189935385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.3189935385 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/18.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/18.kmac_lc_escalation.4076283964
Short name T314
Test name
Test status
Simulation time 124738174 ps
CPU time 2.26 seconds
Started Aug 25 09:56:58 AM UTC 24
Finished Aug 25 09:57:02 AM UTC 24
Peak memory 235052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076283964 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.4076283964 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/18.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/18.kmac_long_msg_and_output.3852175647
Short name T718
Test name
Test status
Simulation time 404354020121 ps
CPU time 4892.3 seconds
Started Aug 25 09:56:23 AM UTC 24
Finished Aug 25 11:19:00 AM UTC 24
Peak memory 4226888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852175647 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_and_output.3852175647 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/18.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/18.kmac_smoke.1818514117
Short name T313
Test name
Test status
Simulation time 2650746603 ps
CPU time 34.99 seconds
Started Aug 25 09:56:21 AM UTC 24
Finished Aug 25 09:56:57 AM UTC 24
Peak memory 234772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818514117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.1818514117 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/18.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/18.kmac_stress_all.452556430
Short name T670
Test name
Test status
Simulation time 185776060477 ps
CPU time 2189.08 seconds
Started Aug 25 09:56:59 AM UTC 24
Finished Aug 25 10:33:57 AM UTC 24
Peak memory 690244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452556430 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.452556430 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/18.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/19.kmac_alert_test.2386234434
Short name T327
Test name
Test status
Simulation time 33568581 ps
CPU time 1.16 seconds
Started Aug 25 09:57:43 AM UTC 24
Finished Aug 25 09:57:46 AM UTC 24
Peak memory 214264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386234434 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.2386234434 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/19.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/19.kmac_app.3119560737
Short name T352
Test name
Test status
Simulation time 10692311978 ps
CPU time 182.66 seconds
Started Aug 25 09:57:11 AM UTC 24
Finished Aug 25 10:00:17 AM UTC 24
Peak memory 296728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119560737 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.3119560737 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/19.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/19.kmac_burst_write.1534843046
Short name T473
Test name
Test status
Simulation time 27490069137 ps
CPU time 753.04 seconds
Started Aug 25 09:57:11 AM UTC 24
Finished Aug 25 10:09:55 AM UTC 24
Peak memory 247592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534843046 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.1534843046 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/19.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/19.kmac_edn_timeout_error.3360294397
Short name T328
Test name
Test status
Simulation time 921294720 ps
CPU time 38.99 seconds
Started Aug 25 09:57:22 AM UTC 24
Finished Aug 25 09:58:03 AM UTC 24
Peak memory 235076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360294397 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.3360294397 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/19.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/19.kmac_entropy_mode_error.2807648933
Short name T330
Test name
Test status
Simulation time 4757005057 ps
CPU time 46.4 seconds
Started Aug 25 09:57:28 AM UTC 24
Finished Aug 25 09:58:16 AM UTC 24
Peak memory 235116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807648933 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.2807648933 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/19.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/19.kmac_entropy_refresh.1238080795
Short name T334
Test name
Test status
Simulation time 2627987189 ps
CPU time 75.38 seconds
Started Aug 25 09:57:18 AM UTC 24
Finished Aug 25 09:58:35 AM UTC 24
Peak memory 245796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238080795 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.1238080795 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/19.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/19.kmac_error.2213860882
Short name T367
Test name
Test status
Simulation time 62092826051 ps
CPU time 255.34 seconds
Started Aug 25 09:57:20 AM UTC 24
Finished Aug 25 10:01:40 AM UTC 24
Peak memory 403352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213860882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.2213860882 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/19.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/19.kmac_key_error.4146694051
Short name T323
Test name
Test status
Simulation time 398978753 ps
CPU time 5.09 seconds
Started Aug 25 09:57:21 AM UTC 24
Finished Aug 25 09:57:27 AM UTC 24
Peak memory 232476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146694051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.4146694051 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/19.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/19.kmac_lc_escalation.3796144475
Short name T325
Test name
Test status
Simulation time 56752462 ps
CPU time 1.89 seconds
Started Aug 25 09:57:32 AM UTC 24
Finished Aug 25 09:57:35 AM UTC 24
Peak memory 229784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796144475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.3796144475 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/19.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/19.kmac_long_msg_and_output.1804805355
Short name T324
Test name
Test status
Simulation time 2023200610 ps
CPU time 24.09 seconds
Started Aug 25 09:57:06 AM UTC 24
Finished Aug 25 09:57:31 AM UTC 24
Peak memory 253644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804805355 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_and_output.1804805355 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/19.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/19.kmac_sideload.566246156
Short name T331
Test name
Test status
Simulation time 2860506710 ps
CPU time 67.01 seconds
Started Aug 25 09:57:09 AM UTC 24
Finished Aug 25 09:58:18 AM UTC 24
Peak memory 268168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566246156 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.566246156 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/19.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/19.kmac_smoke.2426245130
Short name T329
Test name
Test status
Simulation time 4011631373 ps
CPU time 68.06 seconds
Started Aug 25 09:57:06 AM UTC 24
Finished Aug 25 09:58:15 AM UTC 24
Peak memory 235512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426245130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.2426245130 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/19.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/19.kmac_stress_all.369489134
Short name T687
Test name
Test status
Simulation time 61273630994 ps
CPU time 2602.39 seconds
Started Aug 25 09:57:36 AM UTC 24
Finished Aug 25 10:41:33 AM UTC 24
Peak memory 1128724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369489134 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.369489134 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/19.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/2.kmac_alert_test.333245284
Short name T55
Test name
Test status
Simulation time 148924613 ps
CPU time 1.24 seconds
Started Aug 25 09:46:53 AM UTC 24
Finished Aug 25 09:46:56 AM UTC 24
Peak memory 214268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333245284 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.333245284 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/2.kmac_app.1411679934
Short name T93
Test name
Test status
Simulation time 5706451415 ps
CPU time 42.22 seconds
Started Aug 25 09:46:33 AM UTC 24
Finished Aug 25 09:47:17 AM UTC 24
Peak memory 251932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411679934 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.1411679934 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/2.kmac_app_with_partial_data.3800218217
Short name T196
Test name
Test status
Simulation time 19734350179 ps
CPU time 183.32 seconds
Started Aug 25 09:46:38 AM UTC 24
Finished Aug 25 09:49:44 AM UTC 24
Peak memory 284448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800218217 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.3800218217 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/2.kmac_burst_write.3949507354
Short name T351
Test name
Test status
Simulation time 18219144107 ps
CPU time 808.84 seconds
Started Aug 25 09:46:33 AM UTC 24
Finished Aug 25 10:00:14 AM UTC 24
Peak memory 255804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949507354 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.3949507354 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/2.kmac_edn_timeout_error.2503058012
Short name T72
Test name
Test status
Simulation time 1027007864 ps
CPU time 37 seconds
Started Aug 25 09:46:41 AM UTC 24
Finished Aug 25 09:47:20 AM UTC 24
Peak memory 230620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503058012 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.2503058012 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_mode_error.416505676
Short name T73
Test name
Test status
Simulation time 1900577467 ps
CPU time 42.83 seconds
Started Aug 25 09:46:41 AM UTC 24
Finished Aug 25 09:47:25 AM UTC 24
Peak memory 232424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416505676 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.416505676 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_ready_error.801831873
Short name T204
Test name
Test status
Simulation time 6584215674 ps
CPU time 89.9 seconds
Started Aug 25 09:46:45 AM UTC 24
Finished Aug 25 09:48:17 AM UTC 24
Peak memory 230768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801831873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.801831873 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_refresh.1306180629
Short name T243
Test name
Test status
Simulation time 25310379408 ps
CPU time 345.14 seconds
Started Aug 25 09:46:40 AM UTC 24
Finished Aug 25 09:52:30 AM UTC 24
Peak memory 329480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306180629 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.1306180629 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/2.kmac_error.1550835353
Short name T26
Test name
Test status
Simulation time 42759412798 ps
CPU time 450.38 seconds
Started Aug 25 09:46:41 AM UTC 24
Finished Aug 25 09:54:19 AM UTC 24
Peak memory 380708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550835353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.1550835353 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/2.kmac_key_error.2721405699
Short name T21
Test name
Test status
Simulation time 1448994727 ps
CPU time 4.84 seconds
Started Aug 25 09:46:41 AM UTC 24
Finished Aug 25 09:46:47 AM UTC 24
Peak memory 230456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721405699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.2721405699 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/2.kmac_long_msg_and_output.2350815860
Short name T275
Test name
Test status
Simulation time 17410094070 ps
CPU time 454.07 seconds
Started Aug 25 09:46:31 AM UTC 24
Finished Aug 25 09:54:15 AM UTC 24
Peak memory 468936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350815860 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and_output.2350815860 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/2.kmac_mubi.912892972
Short name T85
Test name
Test status
Simulation time 32813192259 ps
CPU time 254.14 seconds
Started Aug 25 09:46:41 AM UTC 24
Finished Aug 25 09:51:00 AM UTC 24
Peak memory 377188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912892972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.912892972 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/2.kmac_sec_cm.3712130018
Short name T11
Test name
Test status
Simulation time 9999843781 ps
CPU time 46.25 seconds
Started Aug 25 09:46:53 AM UTC 24
Finished Aug 25 09:47:41 AM UTC 24
Peak memory 271656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712130018 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.3712130018 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/2.kmac_sideload.734055941
Short name T31
Test name
Test status
Simulation time 9297555387 ps
CPU time 266.62 seconds
Started Aug 25 09:46:31 AM UTC 24
Finished Aug 25 09:51:05 AM UTC 24
Peak memory 425716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734055941 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.734055941 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/2.kmac_smoke.2374553014
Short name T79
Test name
Test status
Simulation time 1623241143 ps
CPU time 32.6 seconds
Started Aug 25 09:46:31 AM UTC 24
Finished Aug 25 09:47:08 AM UTC 24
Peak memory 230648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374553014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.2374553014 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/2.kmac_stress_all.3064492772
Short name T190
Test name
Test status
Simulation time 37379936462 ps
CPU time 396.57 seconds
Started Aug 25 09:46:51 AM UTC 24
Finished Aug 25 09:53:34 AM UTC 24
Peak memory 606272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064492772 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.3064492772 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac.1348964330
Short name T15
Test name
Test status
Simulation time 202025897 ps
CPU time 3 seconds
Started Aug 25 09:46:33 AM UTC 24
Finished Aug 25 09:46:38 AM UTC 24
Peak memory 230572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348964330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac.1348964330 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac_xof.1343868890
Short name T17
Test name
Test status
Simulation time 225932184 ps
CPU time 4.03 seconds
Started Aug 25 09:46:33 AM UTC 24
Finished Aug 25 09:46:39 AM UTC 24
Peak memory 230536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343868890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.1343868890 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_224.598616348
Short name T685
Test name
Test status
Simulation time 361105566019 ps
CPU time 3220.74 seconds
Started Aug 25 09:46:33 AM UTC 24
Finished Aug 25 10:40:56 AM UTC 24
Peak memory 3161396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598616348 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.598616348 +
enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_256.4028409753
Short name T77
Test name
Test status
Simulation time 11614397367 ps
CPU time 52.86 seconds
Started Aug 25 09:46:33 AM UTC 24
Finished Aug 25 09:47:28 AM UTC 24
Peak memory 253812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028409753 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.4028409753
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_384.524510191
Short name T609
Test name
Test status
Simulation time 164346822074 ps
CPU time 2167.59 seconds
Started Aug 25 09:46:33 AM UTC 24
Finished Aug 25 10:23:10 AM UTC 24
Peak memory 2352968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524510191 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.524510191 +
enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_512.3345186838
Short name T174
Test name
Test status
Simulation time 751957355 ps
CPU time 23.85 seconds
Started Aug 25 09:46:33 AM UTC 24
Finished Aug 25 09:46:59 AM UTC 24
Peak memory 230224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345186838 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.3345186838
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_128.739790972
Short name T228
Test name
Test status
Simulation time 20422984277 ps
CPU time 280.9 seconds
Started Aug 25 09:46:33 AM UTC 24
Finished Aug 25 09:51:19 AM UTC 24
Peak memory 439564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739790972 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.73979097
2 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_256.3082606151
Short name T161
Test name
Test status
Simulation time 9920473202 ps
CPU time 171.09 seconds
Started Aug 25 09:46:33 AM UTC 24
Finished Aug 25 09:49:28 AM UTC 24
Peak memory 360188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082606151 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.3082606
151 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/20.kmac_alert_test.427346022
Short name T336
Test name
Test status
Simulation time 23271035 ps
CPU time 1.18 seconds
Started Aug 25 09:58:36 AM UTC 24
Finished Aug 25 09:58:39 AM UTC 24
Peak memory 214268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427346022 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.427346022 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/20.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/20.kmac_app.617451342
Short name T381
Test name
Test status
Simulation time 11449402755 ps
CPU time 284.12 seconds
Started Aug 25 09:58:16 AM UTC 24
Finished Aug 25 10:03:05 AM UTC 24
Peak memory 438076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617451342 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.617451342 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/20.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/20.kmac_burst_write.3964098424
Short name T423
Test name
Test status
Simulation time 23353187709 ps
CPU time 457.01 seconds
Started Aug 25 09:58:08 AM UTC 24
Finished Aug 25 10:05:52 AM UTC 24
Peak memory 243476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964098424 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.3964098424 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/20.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/20.kmac_entropy_refresh.2865301499
Short name T345
Test name
Test status
Simulation time 24145298465 ps
CPU time 73.49 seconds
Started Aug 25 09:58:17 AM UTC 24
Finished Aug 25 09:59:32 AM UTC 24
Peak memory 272324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865301499 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.2865301499 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/20.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/20.kmac_error.595582413
Short name T370
Test name
Test status
Simulation time 143784184484 ps
CPU time 225.37 seconds
Started Aug 25 09:58:19 AM UTC 24
Finished Aug 25 10:02:08 AM UTC 24
Peak memory 395148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595582413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.595582413 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/20.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/20.kmac_key_error.1014609793
Short name T337
Test name
Test status
Simulation time 1240466137 ps
CPU time 13.14 seconds
Started Aug 25 09:58:26 AM UTC 24
Finished Aug 25 09:58:41 AM UTC 24
Peak memory 230496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014609793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.1014609793 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/20.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/20.kmac_lc_escalation.4225679857
Short name T340
Test name
Test status
Simulation time 4924952363 ps
CPU time 27.91 seconds
Started Aug 25 09:58:26 AM UTC 24
Finished Aug 25 09:58:56 AM UTC 24
Peak memory 251732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225679857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.4225679857 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/20.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/20.kmac_long_msg_and_output.2598923014
Short name T386
Test name
Test status
Simulation time 16476928973 ps
CPU time 325.6 seconds
Started Aug 25 09:57:50 AM UTC 24
Finished Aug 25 10:03:21 AM UTC 24
Peak memory 386904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598923014 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_and_output.2598923014 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/20.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/20.kmac_sideload.492624428
Short name T418
Test name
Test status
Simulation time 46012244292 ps
CPU time 435.11 seconds
Started Aug 25 09:58:04 AM UTC 24
Finished Aug 25 10:05:26 AM UTC 24
Peak memory 548756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492624428 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.492624428 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/20.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/20.kmac_smoke.1585624329
Short name T333
Test name
Test status
Simulation time 647796245 ps
CPU time 37.47 seconds
Started Aug 25 09:57:47 AM UTC 24
Finished Aug 25 09:58:26 AM UTC 24
Peak memory 230496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585624329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.1585624329 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/20.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/20.kmac_stress_all.2267384039
Short name T371
Test name
Test status
Simulation time 21728643984 ps
CPU time 208.36 seconds
Started Aug 25 09:58:36 AM UTC 24
Finished Aug 25 10:02:09 AM UTC 24
Peak memory 468888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267384039 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.2267384039 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/20.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/21.kmac_alert_test.2354254584
Short name T346
Test name
Test status
Simulation time 23817866 ps
CPU time 1.25 seconds
Started Aug 25 09:59:30 AM UTC 24
Finished Aug 25 09:59:32 AM UTC 24
Peak memory 216392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354254584 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.2354254584 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/21.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/21.kmac_app.779388509
Short name T353
Test name
Test status
Simulation time 34646764656 ps
CPU time 87.32 seconds
Started Aug 25 09:58:58 AM UTC 24
Finished Aug 25 10:00:27 AM UTC 24
Peak memory 280596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779388509 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.779388509 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/21.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/21.kmac_burst_write.1384633366
Short name T503
Test name
Test status
Simulation time 36124599270 ps
CPU time 772.64 seconds
Started Aug 25 09:58:54 AM UTC 24
Finished Aug 25 10:11:57 AM UTC 24
Peak memory 253780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384633366 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.1384633366 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/21.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/21.kmac_entropy_refresh.579179470
Short name T378
Test name
Test status
Simulation time 5190817494 ps
CPU time 216.83 seconds
Started Aug 25 09:59:04 AM UTC 24
Finished Aug 25 10:02:44 AM UTC 24
Peak memory 302936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579179470 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.579179470 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/21.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/21.kmac_error.4027949260
Short name T376
Test name
Test status
Simulation time 2059341116 ps
CPU time 206.06 seconds
Started Aug 25 09:59:08 AM UTC 24
Finished Aug 25 10:02:38 AM UTC 24
Peak memory 313056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027949260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.4027949260 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/21.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/21.kmac_key_error.69202928
Short name T343
Test name
Test status
Simulation time 1569131012 ps
CPU time 13.76 seconds
Started Aug 25 09:59:13 AM UTC 24
Finished Aug 25 09:59:28 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69202928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.69202928 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/21.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/21.kmac_lc_escalation.536420192
Short name T350
Test name
Test status
Simulation time 2666899174 ps
CPU time 37.36 seconds
Started Aug 25 09:59:20 AM UTC 24
Finished Aug 25 09:59:59 AM UTC 24
Peak memory 249684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536420192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.536420192 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/21.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/21.kmac_long_msg_and_output.80386797
Short name T614
Test name
Test status
Simulation time 12057933939 ps
CPU time 1493.7 seconds
Started Aug 25 09:58:42 AM UTC 24
Finished Aug 25 10:23:56 AM UTC 24
Peak memory 938012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80386797 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_and_output.80386797 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/21.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/21.kmac_sideload.3295151138
Short name T417
Test name
Test status
Simulation time 13774735456 ps
CPU time 378.94 seconds
Started Aug 25 09:58:52 AM UTC 24
Finished Aug 25 10:05:17 AM UTC 24
Peak memory 352156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295151138 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.3295151138 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/21.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/21.kmac_smoke.1793314959
Short name T342
Test name
Test status
Simulation time 3825874963 ps
CPU time 37.8 seconds
Started Aug 25 09:58:39 AM UTC 24
Finished Aug 25 09:59:19 AM UTC 24
Peak memory 230696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793314959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.1793314959 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/21.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/21.kmac_stress_all.3070980972
Short name T493
Test name
Test status
Simulation time 94572670750 ps
CPU time 713 seconds
Started Aug 25 09:59:29 AM UTC 24
Finished Aug 25 10:11:33 AM UTC 24
Peak memory 628900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070980972 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.3070980972 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/21.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/22.kmac_alert_test.195558477
Short name T355
Test name
Test status
Simulation time 18856083 ps
CPU time 1.26 seconds
Started Aug 25 10:00:32 AM UTC 24
Finished Aug 25 10:00:35 AM UTC 24
Peak memory 214268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195558477 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.195558477 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/22.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/22.kmac_app.3738945450
Short name T415
Test name
Test status
Simulation time 11341176562 ps
CPU time 308.29 seconds
Started Aug 25 09:59:56 AM UTC 24
Finished Aug 25 10:05:09 AM UTC 24
Peak memory 444244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738945450 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.3738945450 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/22.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/22.kmac_burst_write.1167498503
Short name T548
Test name
Test status
Simulation time 45754751171 ps
CPU time 1027.05 seconds
Started Aug 25 09:59:41 AM UTC 24
Finished Aug 25 10:17:03 AM UTC 24
Peak memory 253732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167498503 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.1167498503 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/22.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/22.kmac_entropy_refresh.3178426965
Short name T397
Test name
Test status
Simulation time 15784793685 ps
CPU time 234.94 seconds
Started Aug 25 10:00:00 AM UTC 24
Finished Aug 25 10:04:05 AM UTC 24
Peak memory 384908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178426965 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.3178426965 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/22.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/22.kmac_error.901084557
Short name T37
Test name
Test status
Simulation time 11229469580 ps
CPU time 306.07 seconds
Started Aug 25 10:00:15 AM UTC 24
Finished Aug 25 10:05:26 AM UTC 24
Peak memory 454564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901084557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.901084557 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/22.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/22.kmac_key_error.1991959490
Short name T356
Test name
Test status
Simulation time 1926295899 ps
CPU time 17.74 seconds
Started Aug 25 10:00:18 AM UTC 24
Finished Aug 25 10:00:37 AM UTC 24
Peak memory 230420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991959490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.1991959490 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/22.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/22.kmac_lc_escalation.3778746180
Short name T357
Test name
Test status
Simulation time 374657200 ps
CPU time 13.1 seconds
Started Aug 25 10:00:28 AM UTC 24
Finished Aug 25 10:00:43 AM UTC 24
Peak memory 245536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778746180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.3778746180 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/22.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/22.kmac_long_msg_and_output.2282537709
Short name T616
Test name
Test status
Simulation time 117404359496 ps
CPU time 1447.98 seconds
Started Aug 25 09:59:33 AM UTC 24
Finished Aug 25 10:24:01 AM UTC 24
Peak memory 1632104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282537709 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_and_output.2282537709 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/22.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/22.kmac_sideload.931138017
Short name T431
Test name
Test status
Simulation time 17926548747 ps
CPU time 455.59 seconds
Started Aug 25 09:59:33 AM UTC 24
Finished Aug 25 10:07:16 AM UTC 24
Peak memory 387036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931138017 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.931138017 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/22.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/22.kmac_smoke.1005262239
Short name T354
Test name
Test status
Simulation time 1907316609 ps
CPU time 52.86 seconds
Started Aug 25 09:59:33 AM UTC 24
Finished Aug 25 10:00:28 AM UTC 24
Peak memory 230576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005262239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.1005262239 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/22.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/22.kmac_stress_all.918243560
Short name T487
Test name
Test status
Simulation time 128326526546 ps
CPU time 638.49 seconds
Started Aug 25 10:00:29 AM UTC 24
Finished Aug 25 10:11:17 AM UTC 24
Peak memory 694124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918243560 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.918243560 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/22.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/23.kmac_alert_test.3837110161
Short name T364
Test name
Test status
Simulation time 11981643 ps
CPU time 1.13 seconds
Started Aug 25 10:01:22 AM UTC 24
Finished Aug 25 10:01:24 AM UTC 24
Peak memory 214264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837110161 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.3837110161 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/23.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/23.kmac_app.2982174049
Short name T448
Test name
Test status
Simulation time 66741257080 ps
CPU time 442.67 seconds
Started Aug 25 10:00:56 AM UTC 24
Finished Aug 25 10:08:25 AM UTC 24
Peak memory 524172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982174049 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.2982174049 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/23.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/23.kmac_burst_write.3218262620
Short name T428
Test name
Test status
Simulation time 3818075151 ps
CPU time 350.74 seconds
Started Aug 25 10:00:45 AM UTC 24
Finished Aug 25 10:06:41 AM UTC 24
Peak memory 239652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218262620 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.3218262620 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/23.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/23.kmac_entropy_refresh.1950486928
Short name T368
Test name
Test status
Simulation time 2993592162 ps
CPU time 52.42 seconds
Started Aug 25 10:00:57 AM UTC 24
Finished Aug 25 10:01:51 AM UTC 24
Peak memory 251748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950486928 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.1950486928 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/23.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/23.kmac_error.3565084726
Short name T407
Test name
Test status
Simulation time 28625461018 ps
CPU time 225.93 seconds
Started Aug 25 10:00:58 AM UTC 24
Finished Aug 25 10:04:48 AM UTC 24
Peak memory 380680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565084726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.3565084726 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/23.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/23.kmac_key_error.4021825830
Short name T362
Test name
Test status
Simulation time 354384924 ps
CPU time 2.19 seconds
Started Aug 25 10:01:04 AM UTC 24
Finished Aug 25 10:01:07 AM UTC 24
Peak memory 232404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021825830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.4021825830 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/23.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/23.kmac_long_msg_and_output.2314081589
Short name T695
Test name
Test status
Simulation time 192408664173 ps
CPU time 2733.93 seconds
Started Aug 25 10:00:35 AM UTC 24
Finished Aug 25 10:46:45 AM UTC 24
Peak memory 2643756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314081589 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_and_output.2314081589 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/23.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/23.kmac_sideload.3669851907
Short name T404
Test name
Test status
Simulation time 4761136579 ps
CPU time 234.1 seconds
Started Aug 25 10:00:38 AM UTC 24
Finished Aug 25 10:04:36 AM UTC 24
Peak memory 311128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669851907 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.3669851907 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/23.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/23.kmac_smoke.233200083
Short name T361
Test name
Test status
Simulation time 826205403 ps
CPU time 27.28 seconds
Started Aug 25 10:00:34 AM UTC 24
Finished Aug 25 10:01:03 AM UTC 24
Peak memory 230512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233200083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.233200083 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/23.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/23.kmac_stress_all.1725407647
Short name T563
Test name
Test status
Simulation time 26489866401 ps
CPU time 994.3 seconds
Started Aug 25 10:01:12 AM UTC 24
Finished Aug 25 10:18:01 AM UTC 24
Peak memory 415908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725407647 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.1725407647 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/23.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/24.kmac_alert_test.4155395855
Short name T375
Test name
Test status
Simulation time 16352224 ps
CPU time 1.08 seconds
Started Aug 25 10:02:29 AM UTC 24
Finished Aug 25 10:02:31 AM UTC 24
Peak memory 214264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155395855 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.4155395855 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/24.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/24.kmac_app.2913777633
Short name T377
Test name
Test status
Simulation time 1637226462 ps
CPU time 45.86 seconds
Started Aug 25 10:01:52 AM UTC 24
Finished Aug 25 10:02:39 AM UTC 24
Peak memory 253720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913777633 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.2913777633 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/24.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/24.kmac_burst_write.1525736452
Short name T553
Test name
Test status
Simulation time 42778524876 ps
CPU time 922.03 seconds
Started Aug 25 10:01:41 AM UTC 24
Finished Aug 25 10:17:15 AM UTC 24
Peak memory 251696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525736452 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.1525736452 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/24.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/24.kmac_entropy_refresh.603528627
Short name T429
Test name
Test status
Simulation time 12317873820 ps
CPU time 289.11 seconds
Started Aug 25 10:02:01 AM UTC 24
Finished Aug 25 10:06:55 AM UTC 24
Peak memory 388896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603528627 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.603528627 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/24.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/24.kmac_error.4146326521
Short name T450
Test name
Test status
Simulation time 9022273425 ps
CPU time 379.87 seconds
Started Aug 25 10:02:09 AM UTC 24
Finished Aug 25 10:08:34 AM UTC 24
Peak memory 380756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146326521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.4146326521 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/24.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/24.kmac_key_error.3280739836
Short name T374
Test name
Test status
Simulation time 1743442375 ps
CPU time 17.51 seconds
Started Aug 25 10:02:10 AM UTC 24
Finished Aug 25 10:02:29 AM UTC 24
Peak memory 230368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280739836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.3280739836 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/24.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/24.kmac_lc_escalation.648100132
Short name T373
Test name
Test status
Simulation time 48930700 ps
CPU time 2.25 seconds
Started Aug 25 10:02:21 AM UTC 24
Finished Aug 25 10:02:24 AM UTC 24
Peak memory 235140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648100132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.648100132 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/24.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/24.kmac_long_msg_and_output.1281595010
Short name T719
Test name
Test status
Simulation time 1658409945364 ps
CPU time 4731.18 seconds
Started Aug 25 10:01:34 AM UTC 24
Finished Aug 25 11:21:26 AM UTC 24
Peak memory 4093700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281595010 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_and_output.1281595010 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/24.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/24.kmac_sideload.2878610012
Short name T498
Test name
Test status
Simulation time 165397748133 ps
CPU time 598.46 seconds
Started Aug 25 10:01:39 AM UTC 24
Finished Aug 25 10:11:47 AM UTC 24
Peak memory 638744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878610012 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.2878610012 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/24.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/24.kmac_smoke.2774045159
Short name T366
Test name
Test status
Simulation time 396071333 ps
CPU time 12.42 seconds
Started Aug 25 10:01:25 AM UTC 24
Finished Aug 25 10:01:39 AM UTC 24
Peak memory 230512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774045159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.2774045159 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/24.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/24.kmac_stress_all.3728177788
Short name T408
Test name
Test status
Simulation time 5402915504 ps
CPU time 143.45 seconds
Started Aug 25 10:02:25 AM UTC 24
Finished Aug 25 10:04:51 AM UTC 24
Peak memory 307208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728177788 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.3728177788 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/24.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/25.kmac_alert_test.3052944957
Short name T385
Test name
Test status
Simulation time 36263256 ps
CPU time 1.03 seconds
Started Aug 25 10:03:14 AM UTC 24
Finished Aug 25 10:03:16 AM UTC 24
Peak memory 214264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052944957 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.3052944957 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/25.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/25.kmac_app.2280089177
Short name T416
Test name
Test status
Simulation time 4158956010 ps
CPU time 141.09 seconds
Started Aug 25 10:02:45 AM UTC 24
Finished Aug 25 10:05:09 AM UTC 24
Peak memory 319424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280089177 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.2280089177 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/25.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/25.kmac_burst_write.1225546059
Short name T480
Test name
Test status
Simulation time 3744914839 ps
CPU time 453.3 seconds
Started Aug 25 10:02:40 AM UTC 24
Finished Aug 25 10:10:21 AM UTC 24
Peak memory 241500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225546059 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.1225546059 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/25.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/25.kmac_entropy_refresh.2094686425
Short name T461
Test name
Test status
Simulation time 6958371108 ps
CPU time 364.7 seconds
Started Aug 25 10:02:56 AM UTC 24
Finished Aug 25 10:09:06 AM UTC 24
Peak memory 335636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094686425 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.2094686425 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/25.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/25.kmac_error.2463074564
Short name T497
Test name
Test status
Simulation time 50496021825 ps
CPU time 520.49 seconds
Started Aug 25 10:02:57 AM UTC 24
Finished Aug 25 10:11:45 AM UTC 24
Peak memory 591704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463074564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.2463074564 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/25.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/25.kmac_key_error.3024095459
Short name T388
Test name
Test status
Simulation time 5632522294 ps
CPU time 15.56 seconds
Started Aug 25 10:03:06 AM UTC 24
Finished Aug 25 10:03:23 AM UTC 24
Peak memory 230676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024095459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.3024095459 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/25.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/25.kmac_lc_escalation.1596590041
Short name T384
Test name
Test status
Simulation time 37022383 ps
CPU time 2.11 seconds
Started Aug 25 10:03:11 AM UTC 24
Finished Aug 25 10:03:14 AM UTC 24
Peak memory 230356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596590041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.1596590041 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/25.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/25.kmac_long_msg_and_output.3612423883
Short name T696
Test name
Test status
Simulation time 197767164304 ps
CPU time 2612.89 seconds
Started Aug 25 10:02:39 AM UTC 24
Finished Aug 25 10:46:46 AM UTC 24
Peak memory 2539472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612423883 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_and_output.3612423883 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/25.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/25.kmac_sideload.2439106740
Short name T442
Test name
Test status
Simulation time 39917942958 ps
CPU time 322.78 seconds
Started Aug 25 10:02:40 AM UTC 24
Finished Aug 25 10:08:08 AM UTC 24
Peak memory 460640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439106740 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.2439106740 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/25.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/25.kmac_smoke.261686812
Short name T395
Test name
Test status
Simulation time 3966965501 ps
CPU time 83.38 seconds
Started Aug 25 10:02:32 AM UTC 24
Finished Aug 25 10:03:58 AM UTC 24
Peak memory 234688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261686812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.261686812 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/25.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/25.kmac_stress_all.731068217
Short name T699
Test name
Test status
Simulation time 395055153447 ps
CPU time 2742.98 seconds
Started Aug 25 10:03:11 AM UTC 24
Finished Aug 25 10:49:29 AM UTC 24
Peak memory 1663140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731068217 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.731068217 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/25.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/26.kmac_alert_test.2178978142
Short name T394
Test name
Test status
Simulation time 13787865 ps
CPU time 1.18 seconds
Started Aug 25 10:03:50 AM UTC 24
Finished Aug 25 10:03:52 AM UTC 24
Peak memory 216392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178978142 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.2178978142 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/26.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/26.kmac_burst_write.2847912417
Short name T656
Test name
Test status
Simulation time 34086922464 ps
CPU time 1526.09 seconds
Started Aug 25 10:03:23 AM UTC 24
Finished Aug 25 10:29:11 AM UTC 24
Peak memory 270116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847912417 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.2847912417 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/26.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/26.kmac_entropy_refresh.1691156716
Short name T436
Test name
Test status
Simulation time 9841942658 ps
CPU time 248.5 seconds
Started Aug 25 10:03:26 AM UTC 24
Finished Aug 25 10:07:39 AM UTC 24
Peak memory 436112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691156716 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.1691156716 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/26.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/26.kmac_error.1915187813
Short name T457
Test name
Test status
Simulation time 31217811236 ps
CPU time 315.86 seconds
Started Aug 25 10:03:38 AM UTC 24
Finished Aug 25 10:08:59 AM UTC 24
Peak memory 335824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915187813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.1915187813 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/26.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/26.kmac_key_error.3927251625
Short name T392
Test name
Test status
Simulation time 2465988833 ps
CPU time 7.04 seconds
Started Aug 25 10:03:40 AM UTC 24
Finished Aug 25 10:03:48 AM UTC 24
Peak memory 230560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927251625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.3927251625 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/26.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/26.kmac_lc_escalation.3961780566
Short name T60
Test name
Test status
Simulation time 1720937373 ps
CPU time 54.62 seconds
Started Aug 25 10:03:47 AM UTC 24
Finished Aug 25 10:04:43 AM UTC 24
Peak memory 255884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961780566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.3961780566 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/26.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/26.kmac_long_msg_and_output.2390512043
Short name T714
Test name
Test status
Simulation time 214665115926 ps
CPU time 4142 seconds
Started Aug 25 10:03:17 AM UTC 24
Finished Aug 25 11:13:13 AM UTC 24
Peak memory 3731244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390512043 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_and_output.2390512043 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/26.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/26.kmac_sideload.2678142498
Short name T389
Test name
Test status
Simulation time 67157450 ps
CPU time 3.39 seconds
Started Aug 25 10:03:21 AM UTC 24
Finished Aug 25 10:03:26 AM UTC 24
Peak memory 230584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678142498 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.2678142498 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/26.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/26.kmac_smoke.3264129967
Short name T396
Test name
Test status
Simulation time 1175935813 ps
CPU time 41.72 seconds
Started Aug 25 10:03:15 AM UTC 24
Finished Aug 25 10:03:58 AM UTC 24
Peak memory 230632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264129967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.3264129967 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/26.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/26.kmac_stress_all.780646539
Short name T624
Test name
Test status
Simulation time 11526232917 ps
CPU time 1243.94 seconds
Started Aug 25 10:03:49 AM UTC 24
Finished Aug 25 10:24:50 AM UTC 24
Peak memory 643176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780646539 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.780646539 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/26.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/27.kmac_alert_test.2484648407
Short name T405
Test name
Test status
Simulation time 104671682 ps
CPU time 1.33 seconds
Started Aug 25 10:04:37 AM UTC 24
Finished Aug 25 10:04:39 AM UTC 24
Peak memory 214264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484648407 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.2484648407 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/27.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/27.kmac_app.642710334
Short name T400
Test name
Test status
Simulation time 303119070 ps
CPU time 2.9 seconds
Started Aug 25 10:04:07 AM UTC 24
Finished Aug 25 10:04:11 AM UTC 24
Peak memory 230516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642710334 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.642710334 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/27.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/27.kmac_burst_write.886618667
Short name T419
Test name
Test status
Simulation time 6981773472 ps
CPU time 87.85 seconds
Started Aug 25 10:04:06 AM UTC 24
Finished Aug 25 10:05:36 AM UTC 24
Peak memory 230640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886618667 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.886618667 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/27.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/27.kmac_entropy_refresh.99859935
Short name T475
Test name
Test status
Simulation time 15706117830 ps
CPU time 349.65 seconds
Started Aug 25 10:04:11 AM UTC 24
Finished Aug 25 10:10:07 AM UTC 24
Peak memory 341780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99859935 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.99859935 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/27.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/27.kmac_error.3768265268
Short name T420
Test name
Test status
Simulation time 8567281611 ps
CPU time 85.4 seconds
Started Aug 25 10:04:13 AM UTC 24
Finished Aug 25 10:05:40 AM UTC 24
Peak memory 268116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768265268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.3768265268 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/27.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/27.kmac_key_error.1065173551
Short name T403
Test name
Test status
Simulation time 25958339339 ps
CPU time 16.59 seconds
Started Aug 25 10:04:19 AM UTC 24
Finished Aug 25 10:04:36 AM UTC 24
Peak memory 230512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065173551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.1065173551 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/27.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/27.kmac_lc_escalation.2002829235
Short name T402
Test name
Test status
Simulation time 58866789 ps
CPU time 1.76 seconds
Started Aug 25 10:04:30 AM UTC 24
Finished Aug 25 10:04:33 AM UTC 24
Peak memory 229716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002829235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.2002829235 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/27.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/27.kmac_long_msg_and_output.3615702661
Short name T449
Test name
Test status
Simulation time 16057119875 ps
CPU time 270.93 seconds
Started Aug 25 10:03:58 AM UTC 24
Finished Aug 25 10:08:34 AM UTC 24
Peak memory 505612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615702661 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_and_output.3615702661 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/27.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/27.kmac_sideload.426502049
Short name T399
Test name
Test status
Simulation time 123137658 ps
CPU time 10.1 seconds
Started Aug 25 10:03:59 AM UTC 24
Finished Aug 25 10:04:11 AM UTC 24
Peak memory 232568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426502049 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.426502049 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/27.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/27.kmac_smoke.499110387
Short name T401
Test name
Test status
Simulation time 3487693765 ps
CPU time 23.63 seconds
Started Aug 25 10:03:53 AM UTC 24
Finished Aug 25 10:04:18 AM UTC 24
Peak memory 230576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499110387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.499110387 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/27.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/27.kmac_stress_all.3129115188
Short name T472
Test name
Test status
Simulation time 19113903457 ps
CPU time 309.18 seconds
Started Aug 25 10:04:34 AM UTC 24
Finished Aug 25 10:09:48 AM UTC 24
Peak memory 493336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129115188 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.3129115188 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/27.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/28.kmac_alert_test.2316533418
Short name T414
Test name
Test status
Simulation time 140026560 ps
CPU time 1.12 seconds
Started Aug 25 10:05:07 AM UTC 24
Finished Aug 25 10:05:09 AM UTC 24
Peak memory 214264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316533418 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.2316533418 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/28.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/28.kmac_app.3173709902
Short name T477
Test name
Test status
Simulation time 19814788600 ps
CPU time 321.19 seconds
Started Aug 25 10:04:48 AM UTC 24
Finished Aug 25 10:10:15 AM UTC 24
Peak memory 337760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173709902 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.3173709902 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/28.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/28.kmac_burst_write.4022034344
Short name T662
Test name
Test status
Simulation time 145433160914 ps
CPU time 1549.88 seconds
Started Aug 25 10:04:47 AM UTC 24
Finished Aug 25 10:30:59 AM UTC 24
Peak memory 272224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022034344 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.4022034344 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/28.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/28.kmac_entropy_refresh.1655817022
Short name T453
Test name
Test status
Simulation time 14128676426 ps
CPU time 230.84 seconds
Started Aug 25 10:04:52 AM UTC 24
Finished Aug 25 10:08:47 AM UTC 24
Peak memory 303008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655817022 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.1655817022 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/28.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/28.kmac_error.1300978665
Short name T439
Test name
Test status
Simulation time 40469189451 ps
CPU time 169.72 seconds
Started Aug 25 10:04:54 AM UTC 24
Finished Aug 25 10:07:48 AM UTC 24
Peak memory 354140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300978665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.1300978665 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/28.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/28.kmac_key_error.2581145110
Short name T413
Test name
Test status
Simulation time 1610828189 ps
CPU time 5.48 seconds
Started Aug 25 10:04:59 AM UTC 24
Finished Aug 25 10:05:06 AM UTC 24
Peak memory 230448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581145110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.2581145110 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/28.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/28.kmac_lc_escalation.3495795705
Short name T412
Test name
Test status
Simulation time 183102430 ps
CPU time 1.73 seconds
Started Aug 25 10:05:00 AM UTC 24
Finished Aug 25 10:05:02 AM UTC 24
Peak memory 229668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495795705 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.3495795705 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/28.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/28.kmac_long_msg_and_output.1730142080
Short name T421
Test name
Test status
Simulation time 2008038768 ps
CPU time 60.11 seconds
Started Aug 25 10:04:40 AM UTC 24
Finished Aug 25 10:05:42 AM UTC 24
Peak memory 253656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730142080 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_and_output.1730142080 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/28.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/28.kmac_sideload.2529263084
Short name T411
Test name
Test status
Simulation time 1530151897 ps
CPU time 13.31 seconds
Started Aug 25 10:04:44 AM UTC 24
Finished Aug 25 10:04:59 AM UTC 24
Peak memory 234680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529263084 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.2529263084 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/28.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/28.kmac_smoke.2120280047
Short name T410
Test name
Test status
Simulation time 761374188 ps
CPU time 19.94 seconds
Started Aug 25 10:04:37 AM UTC 24
Finished Aug 25 10:04:58 AM UTC 24
Peak memory 230580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120280047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.2120280047 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/28.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/28.kmac_stress_all.3736345748
Short name T430
Test name
Test status
Simulation time 1984050504 ps
CPU time 121.28 seconds
Started Aug 25 10:05:04 AM UTC 24
Finished Aug 25 10:07:08 AM UTC 24
Peak memory 245656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736345748 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.3736345748 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/28.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/29.kmac_alert_test.3136930056
Short name T424
Test name
Test status
Simulation time 37688903 ps
CPU time 1.17 seconds
Started Aug 25 10:05:53 AM UTC 24
Finished Aug 25 10:05:55 AM UTC 24
Peak memory 214264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136930056 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.3136930056 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/29.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/29.kmac_app.3644863785
Short name T452
Test name
Test status
Simulation time 6310514842 ps
CPU time 190.26 seconds
Started Aug 25 10:05:26 AM UTC 24
Finished Aug 25 10:08:40 AM UTC 24
Peak memory 366352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644863785 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.3644863785 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/29.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/29.kmac_burst_write.1645616576
Short name T467
Test name
Test status
Simulation time 4791840605 ps
CPU time 257.08 seconds
Started Aug 25 10:05:17 AM UTC 24
Finished Aug 25 10:09:39 AM UTC 24
Peak memory 237408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645616576 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.1645616576 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/29.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/29.kmac_entropy_refresh.3953923777
Short name T502
Test name
Test status
Simulation time 130411893940 ps
CPU time 383.9 seconds
Started Aug 25 10:05:27 AM UTC 24
Finished Aug 25 10:11:57 AM UTC 24
Peak memory 415820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953923777 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.3953923777 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/29.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/29.kmac_error.2447435418
Short name T38
Test name
Test status
Simulation time 16940685689 ps
CPU time 387.86 seconds
Started Aug 25 10:05:37 AM UTC 24
Finished Aug 25 10:12:11 AM UTC 24
Peak memory 366468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447435418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.2447435418 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/29.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/29.kmac_key_error.481184841
Short name T425
Test name
Test status
Simulation time 9545309688 ps
CPU time 18.41 seconds
Started Aug 25 10:05:41 AM UTC 24
Finished Aug 25 10:06:01 AM UTC 24
Peak memory 230496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481184841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.481184841 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/29.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/29.kmac_lc_escalation.2785718331
Short name T422
Test name
Test status
Simulation time 44552282 ps
CPU time 1.94 seconds
Started Aug 25 10:05:43 AM UTC 24
Finished Aug 25 10:05:45 AM UTC 24
Peak memory 234344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785718331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.2785718331 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/29.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/29.kmac_long_msg_and_output.516038743
Short name T599
Test name
Test status
Simulation time 10115083668 ps
CPU time 1021.24 seconds
Started Aug 25 10:05:10 AM UTC 24
Finished Aug 25 10:22:25 AM UTC 24
Peak memory 745288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516038743 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_and_output.516038743 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/29.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/29.kmac_sideload.3636256610
Short name T440
Test name
Test status
Simulation time 11375142942 ps
CPU time 163.41 seconds
Started Aug 25 10:05:11 AM UTC 24
Finished Aug 25 10:07:58 AM UTC 24
Peak memory 335764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636256610 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.3636256610 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/29.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/29.kmac_smoke.800805746
Short name T426
Test name
Test status
Simulation time 16894925500 ps
CPU time 74.76 seconds
Started Aug 25 10:05:10 AM UTC 24
Finished Aug 25 10:06:26 AM UTC 24
Peak memory 230572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800805746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.800805746 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/29.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/29.kmac_stress_all.3156171817
Short name T674
Test name
Test status
Simulation time 20085238154 ps
CPU time 1787.2 seconds
Started Aug 25 10:05:47 AM UTC 24
Finished Aug 25 10:35:58 AM UTC 24
Peak memory 754012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156171817 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.3156171817 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/29.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/3.kmac_alert_test.1592264652
Short name T201
Test name
Test status
Simulation time 130098923 ps
CPU time 1.27 seconds
Started Aug 25 09:47:30 AM UTC 24
Finished Aug 25 09:47:32 AM UTC 24
Peak memory 214268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592264652 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.1592264652 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/3.kmac_app.3706620930
Short name T210
Test name
Test status
Simulation time 2622427556 ps
CPU time 146.59 seconds
Started Aug 25 09:47:10 AM UTC 24
Finished Aug 25 09:49:40 AM UTC 24
Peak memory 278272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706620930 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.3706620930 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/3.kmac_app_with_partial_data.3452193280
Short name T250
Test name
Test status
Simulation time 12668176297 ps
CPU time 335.31 seconds
Started Aug 25 09:47:11 AM UTC 24
Finished Aug 25 09:52:52 AM UTC 24
Peak memory 440224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452193280 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.3452193280 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/3.kmac_burst_write.3216040253
Short name T175
Test name
Test status
Simulation time 7178506996 ps
CPU time 807.59 seconds
Started Aug 25 09:46:55 AM UTC 24
Finished Aug 25 10:00:33 AM UTC 24
Peak memory 249692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216040253 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.3216040253 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/3.kmac_edn_timeout_error.84597119
Short name T203
Test name
Test status
Simulation time 1702997757 ps
CPU time 42.23 seconds
Started Aug 25 09:47:19 AM UTC 24
Finished Aug 25 09:48:02 AM UTC 24
Peak memory 235140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84597119 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.84597119 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_mode_error.2788074404
Short name T200
Test name
Test status
Simulation time 611976436 ps
CPU time 10.38 seconds
Started Aug 25 09:47:21 AM UTC 24
Finished Aug 25 09:47:32 AM UTC 24
Peak memory 228356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788074404 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.2788074404 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_ready_error.2303681737
Short name T54
Test name
Test status
Simulation time 8413445430 ps
CPU time 34 seconds
Started Aug 25 09:47:27 AM UTC 24
Finished Aug 25 09:48:02 AM UTC 24
Peak memory 230620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303681737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.2303681737 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_refresh.3939005297
Short name T23
Test name
Test status
Simulation time 1596650427 ps
CPU time 84.47 seconds
Started Aug 25 09:47:12 AM UTC 24
Finished Aug 25 09:48:39 AM UTC 24
Peak memory 257816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939005297 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.3939005297 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/3.kmac_error.3124286374
Short name T49
Test name
Test status
Simulation time 44339144994 ps
CPU time 164.84 seconds
Started Aug 25 09:47:14 AM UTC 24
Finished Aug 25 09:50:03 AM UTC 24
Peak memory 352136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124286374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.3124286374 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/3.kmac_key_error.848981319
Short name T64
Test name
Test status
Simulation time 5028661821 ps
CPU time 12.33 seconds
Started Aug 25 09:47:19 AM UTC 24
Finished Aug 25 09:47:32 AM UTC 24
Peak memory 230576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848981319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.848981319 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/3.kmac_long_msg_and_output.2972209198
Short name T509
Test name
Test status
Simulation time 49032576049 ps
CPU time 1516.92 seconds
Started Aug 25 09:46:54 AM UTC 24
Finished Aug 25 10:12:32 AM UTC 24
Peak memory 960544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972209198 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_and_output.2972209198 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/3.kmac_sec_cm.204032446
Short name T52
Test name
Test status
Simulation time 12568538088 ps
CPU time 62.03 seconds
Started Aug 25 09:47:29 AM UTC 24
Finished Aug 25 09:48:33 AM UTC 24
Peak memory 277748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204032446 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.204032446 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/3.kmac_sideload.2833800649
Short name T129
Test name
Test status
Simulation time 24785329056 ps
CPU time 311.06 seconds
Started Aug 25 09:46:55 AM UTC 24
Finished Aug 25 09:52:11 AM UTC 24
Peak memory 335712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833800649 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.2833800649 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/3.kmac_smoke.4073642866
Short name T95
Test name
Test status
Simulation time 460880266 ps
CPU time 14.48 seconds
Started Aug 25 09:46:53 AM UTC 24
Finished Aug 25 09:47:09 AM UTC 24
Peak memory 232744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073642866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.4073642866 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/3.kmac_stress_all.3013020849
Short name T516
Test name
Test status
Simulation time 74261187992 ps
CPU time 1576.08 seconds
Started Aug 25 09:47:28 AM UTC 24
Finished Aug 25 10:14:05 AM UTC 24
Peak memory 1181856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013020849 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.3013020849 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac.797140929
Short name T198
Test name
Test status
Simulation time 49348183 ps
CPU time 3.41 seconds
Started Aug 25 09:47:09 AM UTC 24
Finished Aug 25 09:47:14 AM UTC 24
Peak memory 230488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797140929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_ve
ctors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac.797140929 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac_xof.2574292723
Short name T199
Test name
Test status
Simulation time 150746976 ps
CPU time 3.67 seconds
Started Aug 25 09:47:09 AM UTC 24
Finished Aug 25 09:47:14 AM UTC 24
Peak memory 230548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574292723 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.2574292723 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_224.208440233
Short name T610
Test name
Test status
Simulation time 17320802435 ps
CPU time 2155.46 seconds
Started Aug 25 09:46:57 AM UTC 24
Finished Aug 25 10:23:21 AM UTC 24
Peak memory 1140524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208440233 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.208440233 +
enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_256.3660834365
Short name T686
Test name
Test status
Simulation time 319803487544 ps
CPU time 3212.73 seconds
Started Aug 25 09:47:00 AM UTC 24
Finished Aug 25 10:41:15 AM UTC 24
Peak memory 2983724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660834365 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.3660834365
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_384.3131923856
Short name T145
Test name
Test status
Simulation time 4208647710 ps
CPU time 38.5 seconds
Started Aug 25 09:47:02 AM UTC 24
Finished Aug 25 09:47:42 AM UTC 24
Peak memory 239288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131923856 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.3131923856
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_512.3907969025
Short name T75
Test name
Test status
Simulation time 1083354154 ps
CPU time 19.36 seconds
Started Aug 25 09:47:06 AM UTC 24
Finished Aug 25 09:47:27 AM UTC 24
Peak memory 230620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907969025 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.3907969025
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_128.4234246112
Short name T693
Test name
Test status
Simulation time 78733138204 ps
CPU time 3496.59 seconds
Started Aug 25 09:47:08 AM UTC 24
Finished Aug 25 10:46:09 AM UTC 24
Peak memory 3622696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234246112 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.4234246
112 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_256.3091766341
Short name T208
Test name
Test status
Simulation time 6487652761 ps
CPU time 147.22 seconds
Started Aug 25 09:47:09 AM UTC 24
Finished Aug 25 09:49:39 AM UTC 24
Peak memory 263872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091766341 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.3091766
341 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/3.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/30.kmac_alert_test.39880356
Short name T434
Test name
Test status
Simulation time 223848204 ps
CPU time 1.25 seconds
Started Aug 25 10:07:21 AM UTC 24
Finished Aug 25 10:07:23 AM UTC 24
Peak memory 214268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39880356 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.39880356 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/30.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/30.kmac_app.91116554
Short name T479
Test name
Test status
Simulation time 11022341005 ps
CPU time 213.95 seconds
Started Aug 25 10:06:43 AM UTC 24
Finished Aug 25 10:10:20 AM UTC 24
Peak memory 315340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91116554 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.91116554 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/30.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/30.kmac_burst_write.269849884
Short name T462
Test name
Test status
Simulation time 13922615105 ps
CPU time 164.76 seconds
Started Aug 25 10:06:33 AM UTC 24
Finished Aug 25 10:09:22 AM UTC 24
Peak memory 247028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269849884 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.269849884 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/30.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/30.kmac_entropy_refresh.2873723797
Short name T447
Test name
Test status
Simulation time 6736079780 ps
CPU time 90.68 seconds
Started Aug 25 10:06:43 AM UTC 24
Finished Aug 25 10:08:15 AM UTC 24
Peak memory 282452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873723797 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.2873723797 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/30.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/30.kmac_error.2223136620
Short name T513
Test name
Test status
Simulation time 15496438020 ps
CPU time 398.95 seconds
Started Aug 25 10:06:56 AM UTC 24
Finished Aug 25 10:13:41 AM UTC 24
Peak memory 366484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223136620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.2223136620 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/30.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/30.kmac_key_error.1664132918
Short name T432
Test name
Test status
Simulation time 1718291154 ps
CPU time 8.66 seconds
Started Aug 25 10:07:09 AM UTC 24
Finished Aug 25 10:07:19 AM UTC 24
Peak memory 230376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664132918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.1664132918 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/30.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/30.kmac_lc_escalation.3913391104
Short name T433
Test name
Test status
Simulation time 43355549 ps
CPU time 1.94 seconds
Started Aug 25 10:07:17 AM UTC 24
Finished Aug 25 10:07:20 AM UTC 24
Peak memory 229836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913391104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.3913391104 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/30.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/30.kmac_long_msg_and_output.1783558415
Short name T657
Test name
Test status
Simulation time 10942532566 ps
CPU time 1384.16 seconds
Started Aug 25 10:06:02 AM UTC 24
Finished Aug 25 10:29:25 AM UTC 24
Peak memory 907160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783558415 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_and_output.1783558415 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/30.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/30.kmac_sideload.3923002879
Short name T507
Test name
Test status
Simulation time 8760662104 ps
CPU time 357.37 seconds
Started Aug 25 10:06:27 AM UTC 24
Finished Aug 25 10:12:30 AM UTC 24
Peak memory 472904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923002879 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.3923002879 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/30.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/30.kmac_smoke.2380000323
Short name T435
Test name
Test status
Simulation time 7601662561 ps
CPU time 90.17 seconds
Started Aug 25 10:05:56 AM UTC 24
Finished Aug 25 10:07:29 AM UTC 24
Peak memory 235408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380000323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.2380000323 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/30.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/30.kmac_stress_all.1934725537
Short name T654
Test name
Test status
Simulation time 13846313686 ps
CPU time 1270.26 seconds
Started Aug 25 10:07:20 AM UTC 24
Finished Aug 25 10:28:48 AM UTC 24
Peak memory 595816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934725537 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.1934725537 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/30.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/31.kmac_alert_test.4213544691
Short name T446
Test name
Test status
Simulation time 17642156 ps
CPU time 1.2 seconds
Started Aug 25 10:08:13 AM UTC 24
Finished Aug 25 10:08:15 AM UTC 24
Peak memory 214264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213544691 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.4213544691 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/31.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/31.kmac_app.4290965799
Short name T443
Test name
Test status
Simulation time 3016893579 ps
CPU time 19.17 seconds
Started Aug 25 10:07:48 AM UTC 24
Finished Aug 25 10:08:08 AM UTC 24
Peak memory 235412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290965799 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.4290965799 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/31.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/31.kmac_burst_write.1177369320
Short name T489
Test name
Test status
Simulation time 6129826241 ps
CPU time 208.94 seconds
Started Aug 25 10:07:45 AM UTC 24
Finished Aug 25 10:11:18 AM UTC 24
Peak memory 245532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177369320 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.1177369320 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/31.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/31.kmac_entropy_refresh.2207596631
Short name T485
Test name
Test status
Simulation time 50431147194 ps
CPU time 174.92 seconds
Started Aug 25 10:07:49 AM UTC 24
Finished Aug 25 10:10:47 AM UTC 24
Peak memory 313108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207596631 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.2207596631 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/31.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/31.kmac_error.1300999353
Short name T529
Test name
Test status
Simulation time 10940887465 ps
CPU time 422.84 seconds
Started Aug 25 10:07:59 AM UTC 24
Finished Aug 25 10:15:08 AM UTC 24
Peak memory 509796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300999353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.1300999353 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/31.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/31.kmac_key_error.2349895483
Short name T445
Test name
Test status
Simulation time 929115390 ps
CPU time 9.47 seconds
Started Aug 25 10:08:02 AM UTC 24
Finished Aug 25 10:08:12 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349895483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.2349895483 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/31.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/31.kmac_lc_escalation.1630703299
Short name T444
Test name
Test status
Simulation time 237304257 ps
CPU time 1.8 seconds
Started Aug 25 10:08:09 AM UTC 24
Finished Aug 25 10:08:12 AM UTC 24
Peak memory 231892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630703299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.1630703299 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/31.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/31.kmac_long_msg_and_output.3183456654
Short name T694
Test name
Test status
Simulation time 69339193168 ps
CPU time 2305.52 seconds
Started Aug 25 10:07:29 AM UTC 24
Finished Aug 25 10:46:26 AM UTC 24
Peak memory 1275736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183456654 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_and_output.3183456654 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/31.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/31.kmac_sideload.2576322032
Short name T470
Test name
Test status
Simulation time 4260131541 ps
CPU time 122.38 seconds
Started Aug 25 10:07:40 AM UTC 24
Finished Aug 25 10:09:45 AM UTC 24
Peak memory 325396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576322032 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.2576322032 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/31.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/31.kmac_smoke.2171485463
Short name T438
Test name
Test status
Simulation time 2721494779 ps
CPU time 20.79 seconds
Started Aug 25 10:07:24 AM UTC 24
Finished Aug 25 10:07:46 AM UTC 24
Peak memory 230656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171485463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.2171485463 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/31.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/31.kmac_stress_all.3586843492
Short name T700
Test name
Test status
Simulation time 47500126713 ps
CPU time 2541.33 seconds
Started Aug 25 10:08:09 AM UTC 24
Finished Aug 25 10:51:04 AM UTC 24
Peak memory 878688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586843492 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.3586843492 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/31.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/32.kmac_alert_test.3042538467
Short name T456
Test name
Test status
Simulation time 21186294 ps
CPU time 1.26 seconds
Started Aug 25 10:08:55 AM UTC 24
Finished Aug 25 10:08:57 AM UTC 24
Peak memory 214264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042538467 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.3042538467 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/32.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/32.kmac_app.2076245983
Short name T451
Test name
Test status
Simulation time 676957040 ps
CPU time 3.27 seconds
Started Aug 25 10:08:34 AM UTC 24
Finished Aug 25 10:08:39 AM UTC 24
Peak memory 230496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076245983 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.2076245983 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/32.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/32.kmac_burst_write.1788264390
Short name T633
Test name
Test status
Simulation time 86868620360 ps
CPU time 1021 seconds
Started Aug 25 10:08:26 AM UTC 24
Finished Aug 25 10:25:41 AM UTC 24
Peak memory 259876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788264390 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.1788264390 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/32.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/32.kmac_entropy_refresh.851495697
Short name T537
Test name
Test status
Simulation time 131666127970 ps
CPU time 440.16 seconds
Started Aug 25 10:08:35 AM UTC 24
Finished Aug 25 10:16:02 AM UTC 24
Peak memory 507856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851495697 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.851495697 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/32.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/32.kmac_error.3443782351
Short name T543
Test name
Test status
Simulation time 9109281738 ps
CPU time 451.99 seconds
Started Aug 25 10:08:40 AM UTC 24
Finished Aug 25 10:16:18 AM UTC 24
Peak memory 378700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443782351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.3443782351 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/32.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/32.kmac_key_error.1050082227
Short name T455
Test name
Test status
Simulation time 3964325565 ps
CPU time 12.8 seconds
Started Aug 25 10:08:41 AM UTC 24
Finished Aug 25 10:08:54 AM UTC 24
Peak memory 230692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050082227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.1050082227 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/32.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/32.kmac_lc_escalation.758744745
Short name T454
Test name
Test status
Simulation time 446382309 ps
CPU time 1.91 seconds
Started Aug 25 10:08:49 AM UTC 24
Finished Aug 25 10:08:52 AM UTC 24
Peak memory 231828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758744745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.758744745 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/32.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/32.kmac_long_msg_and_output.1015596855
Short name T712
Test name
Test status
Simulation time 109039938237 ps
CPU time 3598.38 seconds
Started Aug 25 10:08:16 AM UTC 24
Finished Aug 25 11:09:01 AM UTC 24
Peak memory 1970060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015596855 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_and_output.1015596855 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/32.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/32.kmac_sideload.980505583
Short name T505
Test name
Test status
Simulation time 4865200884 ps
CPU time 242.37 seconds
Started Aug 25 10:08:16 AM UTC 24
Finished Aug 25 10:12:23 AM UTC 24
Peak memory 313136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980505583 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.980505583 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/32.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/32.kmac_smoke.319041519
Short name T458
Test name
Test status
Simulation time 1603058851 ps
CPU time 47.43 seconds
Started Aug 25 10:08:13 AM UTC 24
Finished Aug 25 10:09:02 AM UTC 24
Peak memory 235348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319041519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.319041519 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/32.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/32.kmac_stress_all.25765754
Short name T526
Test name
Test status
Simulation time 3308553391 ps
CPU time 358.07 seconds
Started Aug 25 10:08:53 AM UTC 24
Finished Aug 25 10:14:56 AM UTC 24
Peak memory 350368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25765754 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.25765754 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/32.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/33.kmac_alert_test.3627815543
Short name T468
Test name
Test status
Simulation time 20516930 ps
CPU time 1.29 seconds
Started Aug 25 10:09:36 AM UTC 24
Finished Aug 25 10:09:39 AM UTC 24
Peak memory 216392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627815543 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.3627815543 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/33.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/33.kmac_app.2822820939
Short name T463
Test name
Test status
Simulation time 743862290 ps
CPU time 20.91 seconds
Started Aug 25 10:09:06 AM UTC 24
Finished Aug 25 10:09:28 AM UTC 24
Peak memory 235356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822820939 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.2822820939 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/33.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/33.kmac_burst_write.3141174734
Short name T558
Test name
Test status
Simulation time 66368248680 ps
CPU time 513.75 seconds
Started Aug 25 10:09:06 AM UTC 24
Finished Aug 25 10:17:47 AM UTC 24
Peak memory 243556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141174734 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.3141174734 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/33.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/33.kmac_entropy_refresh.3461175957
Short name T474
Test name
Test status
Simulation time 7790865473 ps
CPU time 55.14 seconds
Started Aug 25 10:09:07 AM UTC 24
Finished Aug 25 10:10:06 AM UTC 24
Peak memory 266028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461175957 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.3461175957 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/33.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/33.kmac_error.3644493593
Short name T464
Test name
Test status
Simulation time 666308587 ps
CPU time 7.08 seconds
Started Aug 25 10:09:22 AM UTC 24
Finished Aug 25 10:09:31 AM UTC 24
Peak memory 230628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644493593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.3644493593 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/33.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/33.kmac_key_error.394874724
Short name T465
Test name
Test status
Simulation time 462601267 ps
CPU time 3.14 seconds
Started Aug 25 10:09:30 AM UTC 24
Finished Aug 25 10:09:34 AM UTC 24
Peak memory 230436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394874724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.394874724 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/33.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/33.kmac_lc_escalation.3179459345
Short name T466
Test name
Test status
Simulation time 50704285 ps
CPU time 1.61 seconds
Started Aug 25 10:09:33 AM UTC 24
Finished Aug 25 10:09:35 AM UTC 24
Peak memory 229776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179459345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.3179459345 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/33.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/33.kmac_long_msg_and_output.3019905234
Short name T517
Test name
Test status
Simulation time 5166324188 ps
CPU time 303.59 seconds
Started Aug 25 10:09:00 AM UTC 24
Finished Aug 25 10:14:09 AM UTC 24
Peak memory 372692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019905234 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_and_output.3019905234 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/33.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/33.kmac_sideload.2669414871
Short name T469
Test name
Test status
Simulation time 4486149435 ps
CPU time 37.7 seconds
Started Aug 25 10:09:03 AM UTC 24
Finished Aug 25 10:09:42 AM UTC 24
Peak memory 239456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669414871 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.2669414871 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/33.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/33.kmac_smoke.2126102815
Short name T459
Test name
Test status
Simulation time 309136610 ps
CPU time 6.05 seconds
Started Aug 25 10:08:58 AM UTC 24
Finished Aug 25 10:09:05 AM UTC 24
Peak memory 230700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126102815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.2126102815 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/33.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/33.kmac_stress_all.2909401853
Short name T688
Test name
Test status
Simulation time 36676425413 ps
CPU time 1904.56 seconds
Started Aug 25 10:09:36 AM UTC 24
Finished Aug 25 10:41:46 AM UTC 24
Peak memory 794792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909401853 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.2909401853 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/33.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/34.kmac_alert_test.2441274452
Short name T478
Test name
Test status
Simulation time 12550099 ps
CPU time 1.17 seconds
Started Aug 25 10:10:16 AM UTC 24
Finished Aug 25 10:10:18 AM UTC 24
Peak memory 214264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441274452 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.2441274452 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/34.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/34.kmac_app.202022539
Short name T494
Test name
Test status
Simulation time 4071799415 ps
CPU time 105.44 seconds
Started Aug 25 10:09:48 AM UTC 24
Finished Aug 25 10:11:36 AM UTC 24
Peak memory 292636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202022539 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.202022539 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/34.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/34.kmac_burst_write.1316707501
Short name T547
Test name
Test status
Simulation time 9864773439 ps
CPU time 426.38 seconds
Started Aug 25 10:09:46 AM UTC 24
Finished Aug 25 10:16:59 AM UTC 24
Peak memory 243548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316707501 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.1316707501 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/34.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/34.kmac_entropy_refresh.2498410679
Short name T538
Test name
Test status
Simulation time 67863327158 ps
CPU time 369.53 seconds
Started Aug 25 10:09:49 AM UTC 24
Finished Aug 25 10:16:04 AM UTC 24
Peak memory 450384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498410679 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.2498410679 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/34.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/34.kmac_error.152537660
Short name T521
Test name
Test status
Simulation time 22905898663 ps
CPU time 260.39 seconds
Started Aug 25 10:09:55 AM UTC 24
Finished Aug 25 10:14:20 AM UTC 24
Peak memory 321292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152537660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.152537660 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/34.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/34.kmac_key_error.1071396349
Short name T483
Test name
Test status
Simulation time 1762983727 ps
CPU time 16.09 seconds
Started Aug 25 10:10:06 AM UTC 24
Finished Aug 25 10:10:24 AM UTC 24
Peak memory 230496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071396349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.1071396349 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/34.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/34.kmac_lc_escalation.2218366563
Short name T476
Test name
Test status
Simulation time 162956816 ps
CPU time 2.58 seconds
Started Aug 25 10:10:07 AM UTC 24
Finished Aug 25 10:10:11 AM UTC 24
Peak memory 235172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218366563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.2218366563 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/34.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/34.kmac_long_msg_and_output.4178168693
Short name T709
Test name
Test status
Simulation time 89609788273 ps
CPU time 3010.13 seconds
Started Aug 25 10:09:40 AM UTC 24
Finished Aug 25 11:00:29 AM UTC 24
Peak memory 1638380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178168693 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_and_output.4178168693 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/34.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/34.kmac_sideload.2264156295
Short name T486
Test name
Test status
Simulation time 2350083194 ps
CPU time 82.47 seconds
Started Aug 25 10:09:43 AM UTC 24
Finished Aug 25 10:11:08 AM UTC 24
Peak memory 286552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264156295 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.2264156295 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/34.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/34.kmac_smoke.777800567
Short name T471
Test name
Test status
Simulation time 93068729 ps
CPU time 6.68 seconds
Started Aug 25 10:09:40 AM UTC 24
Finished Aug 25 10:09:48 AM UTC 24
Peak memory 230616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777800567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.777800567 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/34.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/34.kmac_stress_all.2592904574
Short name T720
Test name
Test status
Simulation time 107405865228 ps
CPU time 4249.6 seconds
Started Aug 25 10:10:12 AM UTC 24
Finished Aug 25 11:21:58 AM UTC 24
Peak memory 1722532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592904574 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.2592904574 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/34.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/35.kmac_alert_test.1769869487
Short name T491
Test name
Test status
Simulation time 15880127 ps
CPU time 1.24 seconds
Started Aug 25 10:11:20 AM UTC 24
Finished Aug 25 10:11:22 AM UTC 24
Peak memory 214264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769869487 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.1769869487 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/35.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/35.kmac_app.2443740561
Short name T495
Test name
Test status
Simulation time 9089814196 ps
CPU time 73.18 seconds
Started Aug 25 10:10:24 AM UTC 24
Finished Aug 25 10:11:39 AM UTC 24
Peak memory 272144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443740561 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.2443740561 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/35.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/35.kmac_burst_write.3205274118
Short name T546
Test name
Test status
Simulation time 6258289352 ps
CPU time 387.7 seconds
Started Aug 25 10:10:24 AM UTC 24
Finished Aug 25 10:16:58 AM UTC 24
Peak memory 241444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205274118 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.3205274118 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/35.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/35.kmac_entropy_refresh.2034883562
Short name T554
Test name
Test status
Simulation time 24658451210 ps
CPU time 388.5 seconds
Started Aug 25 10:10:42 AM UTC 24
Finished Aug 25 10:17:17 AM UTC 24
Peak memory 458848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034883562 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.2034883562 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/35.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/35.kmac_error.1697462851
Short name T544
Test name
Test status
Simulation time 16657055668 ps
CPU time 338.59 seconds
Started Aug 25 10:10:48 AM UTC 24
Finished Aug 25 10:16:33 AM UTC 24
Peak memory 462804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697462851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.1697462851 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/35.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/35.kmac_key_error.2222891140
Short name T492
Test name
Test status
Simulation time 1595795848 ps
CPU time 14.27 seconds
Started Aug 25 10:11:08 AM UTC 24
Finished Aug 25 10:11:24 AM UTC 24
Peak memory 230496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222891140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.2222891140 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/35.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/35.kmac_lc_escalation.3325910227
Short name T490
Test name
Test status
Simulation time 144672880 ps
CPU time 2.18 seconds
Started Aug 25 10:11:19 AM UTC 24
Finished Aug 25 10:11:22 AM UTC 24
Peak memory 230612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325910227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.3325910227 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/35.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/35.kmac_long_msg_and_output.4183489406
Short name T711
Test name
Test status
Simulation time 82061850086 ps
CPU time 3354.95 seconds
Started Aug 25 10:10:21 AM UTC 24
Finished Aug 25 11:07:01 AM UTC 24
Peak memory 3174164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183489406 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_and_output.4183489406 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/35.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/35.kmac_sideload.2092529379
Short name T519
Test name
Test status
Simulation time 2288980887 ps
CPU time 227.8 seconds
Started Aug 25 10:10:22 AM UTC 24
Finished Aug 25 10:14:14 AM UTC 24
Peak memory 304916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092529379 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.2092529379 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/35.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/35.kmac_smoke.3112337782
Short name T484
Test name
Test status
Simulation time 13744980269 ps
CPU time 20.89 seconds
Started Aug 25 10:10:19 AM UTC 24
Finished Aug 25 10:10:41 AM UTC 24
Peak memory 230716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112337782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.3112337782 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/35.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/35.kmac_stress_all.1042001092
Short name T710
Test name
Test status
Simulation time 358693528910 ps
CPU time 2992.13 seconds
Started Aug 25 10:11:19 AM UTC 24
Finished Aug 25 11:01:51 AM UTC 24
Peak memory 796796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042001092 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.1042001092 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/35.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/36.kmac_alert_test.3458685995
Short name T501
Test name
Test status
Simulation time 39139466 ps
CPU time 1.17 seconds
Started Aug 25 10:11:53 AM UTC 24
Finished Aug 25 10:11:55 AM UTC 24
Peak memory 214264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458685995 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.3458685995 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/36.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/36.kmac_app.3149239678
Short name T560
Test name
Test status
Simulation time 10173408410 ps
CPU time 372.83 seconds
Started Aug 25 10:11:37 AM UTC 24
Finished Aug 25 10:17:56 AM UTC 24
Peak memory 472928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149239678 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.3149239678 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/36.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/36.kmac_burst_write.1025551765
Short name T567
Test name
Test status
Simulation time 21891561814 ps
CPU time 391.53 seconds
Started Aug 25 10:11:35 AM UTC 24
Finished Aug 25 10:18:13 AM UTC 24
Peak memory 241500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025551765 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.1025551765 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/36.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/36.kmac_entropy_refresh.1076654516
Short name T533
Test name
Test status
Simulation time 7835710242 ps
CPU time 219.58 seconds
Started Aug 25 10:11:40 AM UTC 24
Finished Aug 25 10:15:24 AM UTC 24
Peak memory 292628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076654516 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.1076654516 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/36.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/36.kmac_error.379929694
Short name T515
Test name
Test status
Simulation time 8532023319 ps
CPU time 127.21 seconds
Started Aug 25 10:11:43 AM UTC 24
Finished Aug 25 10:13:53 AM UTC 24
Peak memory 284508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379929694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.379929694 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/36.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/36.kmac_key_error.2569832177
Short name T499
Test name
Test status
Simulation time 436522473 ps
CPU time 3.77 seconds
Started Aug 25 10:11:46 AM UTC 24
Finished Aug 25 10:11:51 AM UTC 24
Peak memory 230496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569832177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.2569832177 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/36.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/36.kmac_lc_escalation.3776848008
Short name T500
Test name
Test status
Simulation time 258182104 ps
CPU time 1.98 seconds
Started Aug 25 10:11:48 AM UTC 24
Finished Aug 25 10:11:52 AM UTC 24
Peak memory 231712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776848008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.3776848008 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/36.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/36.kmac_long_msg_and_output.3066555718
Short name T676
Test name
Test status
Simulation time 235219334736 ps
CPU time 1512.62 seconds
Started Aug 25 10:11:23 AM UTC 24
Finished Aug 25 10:36:56 AM UTC 24
Peak memory 1695524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066555718 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_and_output.3066555718 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/36.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/36.kmac_sideload.2790930577
Short name T535
Test name
Test status
Simulation time 14273067053 ps
CPU time 245.75 seconds
Started Aug 25 10:11:25 AM UTC 24
Finished Aug 25 10:15:35 AM UTC 24
Peak memory 325400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790930577 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.2790930577 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/36.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/36.kmac_smoke.4215158599
Short name T506
Test name
Test status
Simulation time 11655104204 ps
CPU time 63.62 seconds
Started Aug 25 10:11:23 AM UTC 24
Finished Aug 25 10:12:28 AM UTC 24
Peak memory 235336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215158599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.4215158599 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/36.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/36.kmac_stress_all.1003982588
Short name T702
Test name
Test status
Simulation time 259151852243 ps
CPU time 2354.02 seconds
Started Aug 25 10:11:53 AM UTC 24
Finished Aug 25 10:51:38 AM UTC 24
Peak memory 940192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003982588 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.1003982588 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/36.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/37.kmac_alert_test.4030659397
Short name T511
Test name
Test status
Simulation time 39839444 ps
CPU time 1.15 seconds
Started Aug 25 10:12:40 AM UTC 24
Finished Aug 25 10:12:42 AM UTC 24
Peak memory 214264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030659397 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.4030659397 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/37.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/37.kmac_app.592628020
Short name T568
Test name
Test status
Simulation time 19855492659 ps
CPU time 356.52 seconds
Started Aug 25 10:12:12 AM UTC 24
Finished Aug 25 10:18:14 AM UTC 24
Peak memory 352072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592628020 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.592628020 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/37.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/37.kmac_burst_write.1734346350
Short name T650
Test name
Test status
Simulation time 21074661354 ps
CPU time 939.11 seconds
Started Aug 25 10:12:02 AM UTC 24
Finished Aug 25 10:27:54 AM UTC 24
Peak memory 251744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734346350 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.1734346350 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/37.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/37.kmac_error.799513936
Short name T557
Test name
Test status
Simulation time 30126926299 ps
CPU time 311.77 seconds
Started Aug 25 10:12:29 AM UTC 24
Finished Aug 25 10:17:46 AM UTC 24
Peak memory 440092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799513936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.799513936 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/37.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/37.kmac_key_error.373219825
Short name T482
Test name
Test status
Simulation time 689952582 ps
CPU time 6.33 seconds
Started Aug 25 10:12:31 AM UTC 24
Finished Aug 25 10:12:39 AM UTC 24
Peak memory 230644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373219825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.373219825 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/37.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/37.kmac_lc_escalation.3952796402
Short name T510
Test name
Test status
Simulation time 144592883 ps
CPU time 2.04 seconds
Started Aug 25 10:12:33 AM UTC 24
Finished Aug 25 10:12:37 AM UTC 24
Peak memory 230500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952796402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.3952796402 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/37.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/37.kmac_long_msg_and_output.3460179533
Short name T598
Test name
Test status
Simulation time 20783503555 ps
CPU time 609.51 seconds
Started Aug 25 10:11:58 AM UTC 24
Finished Aug 25 10:22:17 AM UTC 24
Peak memory 552916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460179533 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_and_output.3460179533 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/37.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/37.kmac_sideload.179570782
Short name T579
Test name
Test status
Simulation time 49602604712 ps
CPU time 462.07 seconds
Started Aug 25 10:11:58 AM UTC 24
Finished Aug 25 10:19:47 AM UTC 24
Peak memory 526180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179570782 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.179570782 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/37.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/37.kmac_smoke.3666363119
Short name T504
Test name
Test status
Simulation time 62861835 ps
CPU time 4.06 seconds
Started Aug 25 10:11:56 AM UTC 24
Finished Aug 25 10:12:01 AM UTC 24
Peak memory 230684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666363119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.3666363119 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/37.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/37.kmac_stress_all.4238888228
Short name T647
Test name
Test status
Simulation time 127476359519 ps
CPU time 877.26 seconds
Started Aug 25 10:12:37 AM UTC 24
Finished Aug 25 10:27:28 AM UTC 24
Peak memory 436328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238888228 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.4238888228 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/37.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/38.kmac_alert_test.4272358797
Short name T520
Test name
Test status
Simulation time 18319177 ps
CPU time 1.19 seconds
Started Aug 25 10:14:14 AM UTC 24
Finished Aug 25 10:14:16 AM UTC 24
Peak memory 214264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272358797 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.4272358797 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/38.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/38.kmac_app.3311623046
Short name T531
Test name
Test status
Simulation time 3154136454 ps
CPU time 89.61 seconds
Started Aug 25 10:13:45 AM UTC 24
Finished Aug 25 10:15:17 AM UTC 24
Peak memory 286612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311623046 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.3311623046 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/38.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/38.kmac_burst_write.2939165185
Short name T678
Test name
Test status
Simulation time 32071017906 ps
CPU time 1406.69 seconds
Started Aug 25 10:13:42 AM UTC 24
Finished Aug 25 10:37:30 AM UTC 24
Peak memory 274216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939165185 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.2939165185 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/38.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/38.kmac_entropy_refresh.223227493
Short name T555
Test name
Test status
Simulation time 14604014362 ps
CPU time 224.08 seconds
Started Aug 25 10:13:54 AM UTC 24
Finished Aug 25 10:17:42 AM UTC 24
Peak memory 368536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223227493 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.223227493 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/38.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/38.kmac_error.1369324690
Short name T620
Test name
Test status
Simulation time 59298882022 ps
CPU time 608.97 seconds
Started Aug 25 10:13:55 AM UTC 24
Finished Aug 25 10:24:12 AM UTC 24
Peak memory 634772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369324690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.1369324690 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/38.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/38.kmac_key_error.2105881902
Short name T518
Test name
Test status
Simulation time 1346550041 ps
CPU time 13.99 seconds
Started Aug 25 10:13:58 AM UTC 24
Finished Aug 25 10:14:13 AM UTC 24
Peak memory 230368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105881902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.2105881902 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/38.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/38.kmac_lc_escalation.4209913667
Short name T523
Test name
Test status
Simulation time 1386014951 ps
CPU time 17.92 seconds
Started Aug 25 10:14:06 AM UTC 24
Finished Aug 25 10:14:25 AM UTC 24
Peak memory 245536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209913667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.4209913667 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/38.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/38.kmac_long_msg_and_output.1505162878
Short name T713
Test name
Test status
Simulation time 68227129638 ps
CPU time 3502.69 seconds
Started Aug 25 10:12:45 AM UTC 24
Finished Aug 25 11:11:53 AM UTC 24
Peak memory 3268444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505162878 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_and_output.1505162878 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/38.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/38.kmac_sideload.2755785873
Short name T545
Test name
Test status
Simulation time 2091940864 ps
CPU time 216.72 seconds
Started Aug 25 10:13:12 AM UTC 24
Finished Aug 25 10:16:53 AM UTC 24
Peak memory 300904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755785873 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.2755785873 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/38.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/38.kmac_smoke.2655573743
Short name T512
Test name
Test status
Simulation time 1698997115 ps
CPU time 26.44 seconds
Started Aug 25 10:12:43 AM UTC 24
Finished Aug 25 10:13:11 AM UTC 24
Peak memory 230828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655573743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.2655573743 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/38.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/38.kmac_stress_all.132436795
Short name T522
Test name
Test status
Simulation time 656919717 ps
CPU time 10.99 seconds
Started Aug 25 10:14:10 AM UTC 24
Finished Aug 25 10:14:22 AM UTC 24
Peak memory 230576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132436795 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.132436795 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/38.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/39.kmac_alert_test.3955589096
Short name T530
Test name
Test status
Simulation time 80667968 ps
CPU time 1.21 seconds
Started Aug 25 10:15:09 AM UTC 24
Finished Aug 25 10:15:12 AM UTC 24
Peak memory 214264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955589096 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.3955589096 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/39.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/39.kmac_app.3269783973
Short name T574
Test name
Test status
Simulation time 3643726466 ps
CPU time 283.67 seconds
Started Aug 25 10:14:26 AM UTC 24
Finished Aug 25 10:19:14 AM UTC 24
Peak memory 331644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269783973 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.3269783973 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/39.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/39.kmac_burst_write.3083960305
Short name T566
Test name
Test status
Simulation time 20336114292 ps
CPU time 222.57 seconds
Started Aug 25 10:14:23 AM UTC 24
Finished Aug 25 10:18:10 AM UTC 24
Peak memory 247624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083960305 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.3083960305 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/39.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/39.kmac_entropy_refresh.3735740914
Short name T534
Test name
Test status
Simulation time 12814246699 ps
CPU time 61.53 seconds
Started Aug 25 10:14:29 AM UTC 24
Finished Aug 25 10:15:32 AM UTC 24
Peak memory 257856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735740914 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.3735740914 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/39.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/39.kmac_error.782132135
Short name T589
Test name
Test status
Simulation time 8512787267 ps
CPU time 426.19 seconds
Started Aug 25 10:14:44 AM UTC 24
Finished Aug 25 10:21:57 AM UTC 24
Peak memory 368624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782132135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.782132135 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/39.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/39.kmac_key_error.574696961
Short name T527
Test name
Test status
Simulation time 492049217 ps
CPU time 5.5 seconds
Started Aug 25 10:14:57 AM UTC 24
Finished Aug 25 10:15:03 AM UTC 24
Peak memory 230432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574696961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.574696961 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/39.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/39.kmac_lc_escalation.1531583726
Short name T528
Test name
Test status
Simulation time 242630074 ps
CPU time 2.07 seconds
Started Aug 25 10:15:04 AM UTC 24
Finished Aug 25 10:15:07 AM UTC 24
Peak memory 230376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531583726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.1531583726 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/39.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/39.kmac_long_msg_and_output.590585682
Short name T701
Test name
Test status
Simulation time 181207795917 ps
CPU time 2181.6 seconds
Started Aug 25 10:14:17 AM UTC 24
Finished Aug 25 10:51:08 AM UTC 24
Peak memory 2305880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590585682 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_and_output.590585682 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/39.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/39.kmac_sideload.4041627936
Short name T525
Test name
Test status
Simulation time 479896646 ps
CPU time 20.07 seconds
Started Aug 25 10:14:21 AM UTC 24
Finished Aug 25 10:14:43 AM UTC 24
Peak memory 235296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041627936 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.4041627936 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/39.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/39.kmac_smoke.896148930
Short name T524
Test name
Test status
Simulation time 311001246 ps
CPU time 11.22 seconds
Started Aug 25 10:14:15 AM UTC 24
Finished Aug 25 10:14:28 AM UTC 24
Peak memory 230592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896148930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.896148930 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/39.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/39.kmac_stress_all.862237951
Short name T613
Test name
Test status
Simulation time 12425986964 ps
CPU time 519.06 seconds
Started Aug 25 10:15:08 AM UTC 24
Finished Aug 25 10:23:55 AM UTC 24
Peak memory 330096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862237951 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.862237951 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/39.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/4.kmac_alert_test.933725113
Short name T205
Test name
Test status
Simulation time 27724189 ps
CPU time 1.21 seconds
Started Aug 25 09:48:42 AM UTC 24
Finished Aug 25 09:48:44 AM UTC 24
Peak memory 214268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933725113 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.933725113 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/4.kmac_app.3690057191
Short name T162
Test name
Test status
Simulation time 10428610643 ps
CPU time 184.69 seconds
Started Aug 25 09:47:54 AM UTC 24
Finished Aug 25 09:51:03 AM UTC 24
Peak memory 290724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690057191 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.3690057191 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/4.kmac_edn_timeout_error.3460809381
Short name T206
Test name
Test status
Simulation time 6178031831 ps
CPU time 35.57 seconds
Started Aug 25 09:48:27 AM UTC 24
Finished Aug 25 09:49:04 AM UTC 24
Peak memory 232552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460809381 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.3460809381 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_mode_error.2084394047
Short name T207
Test name
Test status
Simulation time 3178484420 ps
CPU time 41.8 seconds
Started Aug 25 09:48:32 AM UTC 24
Finished Aug 25 09:49:15 AM UTC 24
Peak memory 234540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084394047 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.2084394047 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_ready_error.3782392877
Short name T213
Test name
Test status
Simulation time 5373393682 ps
CPU time 74.14 seconds
Started Aug 25 09:48:34 AM UTC 24
Finished Aug 25 09:49:50 AM UTC 24
Peak memory 230560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782392877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.3782392877 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_refresh.1439694109
Short name T225
Test name
Test status
Simulation time 12497546097 ps
CPU time 186.98 seconds
Started Aug 25 09:47:59 AM UTC 24
Finished Aug 25 09:51:10 AM UTC 24
Peak memory 288616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439694109 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.1439694109 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/4.kmac_key_error.3857949061
Short name T65
Test name
Test status
Simulation time 8406681678 ps
CPU time 21.92 seconds
Started Aug 25 09:48:18 AM UTC 24
Finished Aug 25 09:48:42 AM UTC 24
Peak memory 230508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857949061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.3857949061 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/4.kmac_long_msg_and_output.1520995170
Short name T622
Test name
Test status
Simulation time 43703523616 ps
CPU time 2186.05 seconds
Started Aug 25 09:47:33 AM UTC 24
Finished Aug 25 10:24:28 AM UTC 24
Peak memory 2289420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520995170 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and_output.1520995170 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/4.kmac_mubi.2969296364
Short name T88
Test name
Test status
Simulation time 4450933360 ps
CPU time 319.05 seconds
Started Aug 25 09:48:03 AM UTC 24
Finished Aug 25 09:53:28 AM UTC 24
Peak memory 340060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969296364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.2969296364 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/4.kmac_sec_cm.3889137688
Short name T71
Test name
Test status
Simulation time 10016321055 ps
CPU time 38.05 seconds
Started Aug 25 09:48:41 AM UTC 24
Finished Aug 25 09:49:21 AM UTC 24
Peak memory 267616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889137688 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.3889137688 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/4.kmac_sideload.3770792668
Short name T146
Test name
Test status
Simulation time 130516610 ps
CPU time 12.95 seconds
Started Aug 25 09:47:33 AM UTC 24
Finished Aug 25 09:47:47 AM UTC 24
Peak memory 232564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770792668 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.3770792668 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/4.kmac_smoke.1563808364
Short name T193
Test name
Test status
Simulation time 10116078325 ps
CPU time 51.71 seconds
Started Aug 25 09:47:32 AM UTC 24
Finished Aug 25 09:48:26 AM UTC 24
Peak memory 230720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563808364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.1563808364 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/4.kmac_stress_all.350413707
Short name T294
Test name
Test status
Simulation time 6952898766 ps
CPU time 418.91 seconds
Started Aug 25 09:48:38 AM UTC 24
Finished Aug 25 09:55:43 AM UTC 24
Peak memory 352480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350413707 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.350413707 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac.423349020
Short name T148
Test name
Test status
Simulation time 181434311 ps
CPU time 2.38 seconds
Started Aug 25 09:47:50 AM UTC 24
Finished Aug 25 09:47:53 AM UTC 24
Peak memory 230712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423349020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_ve
ctors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac.423349020 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac_xof.1633185000
Short name T202
Test name
Test status
Simulation time 32603625 ps
CPU time 3.23 seconds
Started Aug 25 09:47:54 AM UTC 24
Finished Aug 25 09:47:58 AM UTC 24
Peak memory 230560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633185000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac_xof.1633185000 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_224.2628772717
Short name T679
Test name
Test status
Simulation time 127558906198 ps
CPU time 2957.03 seconds
Started Aug 25 09:47:36 AM UTC 24
Finished Aug 25 10:37:32 AM UTC 24
Peak memory 3159752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628772717 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.2628772717
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_256.3289428759
Short name T683
Test name
Test status
Simulation time 346041830564 ps
CPU time 3125.14 seconds
Started Aug 25 09:47:40 AM UTC 24
Finished Aug 25 10:40:26 AM UTC 24
Peak memory 2991820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289428759 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.3289428759
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_384.2766168885
Short name T514
Test name
Test status
Simulation time 70165675763 ps
CPU time 1539.12 seconds
Started Aug 25 09:47:43 AM UTC 24
Finished Aug 25 10:13:44 AM UTC 24
Peak memory 904892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766168885 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.2766168885
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_512.1345660878
Short name T406
Test name
Test status
Simulation time 125692998318 ps
CPU time 1009.21 seconds
Started Aug 25 09:47:43 AM UTC 24
Finished Aug 25 10:04:46 AM UTC 24
Peak memory 691908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345660878 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.1345660878
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_128.682258456
Short name T245
Test name
Test status
Simulation time 24577976457 ps
CPU time 289.45 seconds
Started Aug 25 09:47:49 AM UTC 24
Finished Aug 25 09:52:43 AM UTC 24
Peak memory 280312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682258456 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.68225845
6 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_256.4126808270
Short name T681
Test name
Test status
Simulation time 300660753872 ps
CPU time 3101.85 seconds
Started Aug 25 09:47:50 AM UTC 24
Finished Aug 25 10:40:12 AM UTC 24
Peak memory 2998088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126808270 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.4126808
270 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/4.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/40.kmac_alert_test.352775866
Short name T541
Test name
Test status
Simulation time 42010127 ps
CPU time 1.19 seconds
Started Aug 25 10:16:09 AM UTC 24
Finished Aug 25 10:16:11 AM UTC 24
Peak memory 214268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352775866 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.352775866 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/40.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/40.kmac_app.1482028283
Short name T575
Test name
Test status
Simulation time 31583459902 ps
CPU time 222.14 seconds
Started Aug 25 10:15:33 AM UTC 24
Finished Aug 25 10:19:19 AM UTC 24
Peak memory 378700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482028283 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.1482028283 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/40.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/40.kmac_burst_write.601858064
Short name T666
Test name
Test status
Simulation time 21584156528 ps
CPU time 1043.14 seconds
Started Aug 25 10:15:25 AM UTC 24
Finished Aug 25 10:33:03 AM UTC 24
Peak memory 251696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601858064 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.601858064 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/40.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/40.kmac_entropy_refresh.2032376000
Short name T542
Test name
Test status
Simulation time 2498648905 ps
CPU time 38.08 seconds
Started Aug 25 10:15:36 AM UTC 24
Finished Aug 25 10:16:16 AM UTC 24
Peak memory 251740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032376000 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.2032376000 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/40.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/40.kmac_error.1241413221
Short name T601
Test name
Test status
Simulation time 10445862712 ps
CPU time 382.36 seconds
Started Aug 25 10:16:01 AM UTC 24
Finished Aug 25 10:22:29 AM UTC 24
Peak memory 524056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241413221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.1241413221 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/40.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/40.kmac_key_error.2167152083
Short name T539
Test name
Test status
Simulation time 92630099 ps
CPU time 1.83 seconds
Started Aug 25 10:16:03 AM UTC 24
Finished Aug 25 10:16:06 AM UTC 24
Peak memory 229776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167152083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.2167152083 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/40.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/40.kmac_lc_escalation.822312957
Short name T540
Test name
Test status
Simulation time 111495717 ps
CPU time 2.34 seconds
Started Aug 25 10:16:05 AM UTC 24
Finished Aug 25 10:16:08 AM UTC 24
Peak memory 230380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822312957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.822312957 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/40.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/40.kmac_long_msg_and_output.2768314705
Short name T652
Test name
Test status
Simulation time 61594833366 ps
CPU time 765.59 seconds
Started Aug 25 10:15:17 AM UTC 24
Finished Aug 25 10:28:14 AM UTC 24
Peak memory 616280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768314705 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_and_output.2768314705 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/40.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/40.kmac_sideload.2386805820
Short name T556
Test name
Test status
Simulation time 6677469328 ps
CPU time 142.52 seconds
Started Aug 25 10:15:18 AM UTC 24
Finished Aug 25 10:17:44 AM UTC 24
Peak memory 278420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386805820 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.2386805820 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/40.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/40.kmac_smoke.3693405686
Short name T536
Test name
Test status
Simulation time 6212286633 ps
CPU time 45.83 seconds
Started Aug 25 10:15:12 AM UTC 24
Finished Aug 25 10:16:00 AM UTC 24
Peak memory 230652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693405686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.3693405686 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/40.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/40.kmac_stress_all.4154807792
Short name T677
Test name
Test status
Simulation time 163282016398 ps
CPU time 1247.01 seconds
Started Aug 25 10:16:06 AM UTC 24
Finished Aug 25 10:37:11 AM UTC 24
Peak memory 1367976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154807792 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.4154807792 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/40.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/41.kmac_alert_test.938066946
Short name T551
Test name
Test status
Simulation time 148301232 ps
CPU time 1.24 seconds
Started Aug 25 10:17:09 AM UTC 24
Finished Aug 25 10:17:11 AM UTC 24
Peak memory 214268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938066946 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.938066946 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/41.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/41.kmac_app.3718630649
Short name T608
Test name
Test status
Simulation time 21151818405 ps
CPU time 379.19 seconds
Started Aug 25 10:16:38 AM UTC 24
Finished Aug 25 10:23:03 AM UTC 24
Peak memory 460696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718630649 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.3718630649 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/41.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/41.kmac_burst_write.727222113
Short name T665
Test name
Test status
Simulation time 90200251947 ps
CPU time 951.12 seconds
Started Aug 25 10:16:34 AM UTC 24
Finished Aug 25 10:32:39 AM UTC 24
Peak memory 259940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727222113 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.727222113 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/41.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/41.kmac_entropy_refresh.168706990
Short name T590
Test name
Test status
Simulation time 18924216459 ps
CPU time 298.6 seconds
Started Aug 25 10:16:53 AM UTC 24
Finished Aug 25 10:21:57 AM UTC 24
Peak memory 327764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168706990 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.168706990 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/41.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/41.kmac_error.1179121012
Short name T562
Test name
Test status
Simulation time 1510291815 ps
CPU time 60.08 seconds
Started Aug 25 10:16:58 AM UTC 24
Finished Aug 25 10:18:00 AM UTC 24
Peak memory 268060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179121012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.1179121012 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/41.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/41.kmac_key_error.1690883472
Short name T549
Test name
Test status
Simulation time 2658773703 ps
CPU time 5.11 seconds
Started Aug 25 10:17:00 AM UTC 24
Finished Aug 25 10:17:06 AM UTC 24
Peak memory 230432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690883472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.1690883472 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/41.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/41.kmac_lc_escalation.415929149
Short name T550
Test name
Test status
Simulation time 191696650 ps
CPU time 1.75 seconds
Started Aug 25 10:17:04 AM UTC 24
Finished Aug 25 10:17:07 AM UTC 24
Peak memory 229908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415929149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.415929149 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/41.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/41.kmac_long_msg_and_output.496158626
Short name T689
Test name
Test status
Simulation time 48134599580 ps
CPU time 1510.91 seconds
Started Aug 25 10:16:16 AM UTC 24
Finished Aug 25 10:41:49 AM UTC 24
Peak memory 980776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496158626 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_and_output.496158626 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/41.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/41.kmac_sideload.558579122
Short name T595
Test name
Test status
Simulation time 35201687754 ps
CPU time 348.48 seconds
Started Aug 25 10:16:19 AM UTC 24
Finished Aug 25 10:22:14 AM UTC 24
Peak memory 472876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558579122 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.558579122 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/41.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/41.kmac_smoke.784275864
Short name T552
Test name
Test status
Simulation time 3540552100 ps
CPU time 57.76 seconds
Started Aug 25 10:16:12 AM UTC 24
Finished Aug 25 10:17:12 AM UTC 24
Peak memory 230704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784275864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.784275864 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/41.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/41.kmac_stress_all.274458483
Short name T715
Test name
Test status
Simulation time 160031505934 ps
CPU time 3409.69 seconds
Started Aug 25 10:17:08 AM UTC 24
Finished Aug 25 11:14:43 AM UTC 24
Peak memory 1544488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274458483 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.274458483 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/41.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/42.kmac_alert_test.2180945541
Short name T564
Test name
Test status
Simulation time 61476463 ps
CPU time 1.19 seconds
Started Aug 25 10:18:01 AM UTC 24
Finished Aug 25 10:18:03 AM UTC 24
Peak memory 214264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180945541 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.2180945541 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/42.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/42.kmac_app.81909509
Short name T643
Test name
Test status
Simulation time 36419188506 ps
CPU time 536.69 seconds
Started Aug 25 10:17:42 AM UTC 24
Finished Aug 25 10:26:47 AM UTC 24
Peak memory 591632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81909509 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.81909509 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/42.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/42.kmac_burst_write.1032216599
Short name T641
Test name
Test status
Simulation time 9751500365 ps
CPU time 539.13 seconds
Started Aug 25 10:17:18 AM UTC 24
Finished Aug 25 10:26:25 AM UTC 24
Peak memory 247644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032216599 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.1032216599 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/42.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/42.kmac_entropy_refresh.3027012103
Short name T644
Test name
Test status
Simulation time 83173689240 ps
CPU time 541.89 seconds
Started Aug 25 10:17:44 AM UTC 24
Finished Aug 25 10:26:54 AM UTC 24
Peak memory 556920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027012103 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.3027012103 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/42.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/42.kmac_error.1968077535
Short name T565
Test name
Test status
Simulation time 313003766 ps
CPU time 16.33 seconds
Started Aug 25 10:17:47 AM UTC 24
Finished Aug 25 10:18:05 AM UTC 24
Peak memory 249628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968077535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.1968077535 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/42.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/42.kmac_key_error.3939267248
Short name T561
Test name
Test status
Simulation time 1123844569 ps
CPU time 10.52 seconds
Started Aug 25 10:17:48 AM UTC 24
Finished Aug 25 10:18:00 AM UTC 24
Peak memory 230424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939267248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.3939267248 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/42.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/42.kmac_long_msg_and_output.3087780881
Short name T722
Test name
Test status
Simulation time 350766574941 ps
CPU time 3866.81 seconds
Started Aug 25 10:17:13 AM UTC 24
Finished Aug 25 11:22:29 AM UTC 24
Peak memory 3405832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087780881 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_and_output.3087780881 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/42.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/42.kmac_sideload.2254538915
Short name T592
Test name
Test status
Simulation time 28611510731 ps
CPU time 285.87 seconds
Started Aug 25 10:17:16 AM UTC 24
Finished Aug 25 10:22:06 AM UTC 24
Peak memory 331680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254538915 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.2254538915 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/42.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/42.kmac_smoke.40314485
Short name T559
Test name
Test status
Simulation time 5265140224 ps
CPU time 38.75 seconds
Started Aug 25 10:17:12 AM UTC 24
Finished Aug 25 10:17:52 AM UTC 24
Peak memory 230684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40314485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.40314485 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/42.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/42.kmac_stress_all.2214381919
Short name T724
Test name
Test status
Simulation time 216564358095 ps
CPU time 3981.07 seconds
Started Aug 25 10:17:57 AM UTC 24
Finished Aug 25 11:25:12 AM UTC 24
Peak memory 1284296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214381919 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.2214381919 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/42.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/43.kmac_alert_test.3681415998
Short name T573
Test name
Test status
Simulation time 19853414 ps
CPU time 1.18 seconds
Started Aug 25 10:18:53 AM UTC 24
Finished Aug 25 10:18:55 AM UTC 24
Peak memory 214264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681415998 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.3681415998 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/43.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/43.kmac_app.2714846239
Short name T585
Test name
Test status
Simulation time 2761429204 ps
CPU time 148.23 seconds
Started Aug 25 10:18:11 AM UTC 24
Finished Aug 25 10:20:42 AM UTC 24
Peak memory 288592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714846239 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.2714846239 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/43.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/43.kmac_burst_write.3930969835
Short name T639
Test name
Test status
Simulation time 9695436292 ps
CPU time 482.12 seconds
Started Aug 25 10:18:06 AM UTC 24
Finished Aug 25 10:26:15 AM UTC 24
Peak memory 247588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930969835 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.3930969835 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/43.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/43.kmac_entropy_refresh.1883838181
Short name T576
Test name
Test status
Simulation time 4144789260 ps
CPU time 64.21 seconds
Started Aug 25 10:18:14 AM UTC 24
Finished Aug 25 10:19:20 AM UTC 24
Peak memory 270088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883838181 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.1883838181 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/43.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/43.kmac_error.3120619304
Short name T584
Test name
Test status
Simulation time 1334300898 ps
CPU time 121.94 seconds
Started Aug 25 10:18:15 AM UTC 24
Finished Aug 25 10:20:20 AM UTC 24
Peak memory 282396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120619304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.3120619304 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/43.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/43.kmac_key_error.4126105127
Short name T571
Test name
Test status
Simulation time 537753486 ps
CPU time 6.46 seconds
Started Aug 25 10:18:41 AM UTC 24
Finished Aug 25 10:18:49 AM UTC 24
Peak memory 230388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126105127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.4126105127 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/43.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/43.kmac_lc_escalation.443419593
Short name T572
Test name
Test status
Simulation time 31575935 ps
CPU time 1.94 seconds
Started Aug 25 10:18:48 AM UTC 24
Finished Aug 25 10:18:52 AM UTC 24
Peak memory 229732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443419593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.443419593 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/43.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/43.kmac_long_msg_and_output.2962758702
Short name T723
Test name
Test status
Simulation time 89012838750 ps
CPU time 3893.1 seconds
Started Aug 25 10:18:02 AM UTC 24
Finished Aug 25 11:23:46 AM UTC 24
Peak memory 3665672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962758702 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_and_output.2962758702 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/43.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/43.kmac_sideload.1975956160
Short name T578
Test name
Test status
Simulation time 15872227831 ps
CPU time 84.06 seconds
Started Aug 25 10:18:04 AM UTC 24
Finished Aug 25 10:19:30 AM UTC 24
Peak memory 282712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975956160 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.1975956160 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/43.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/43.kmac_smoke.3004921128
Short name T569
Test name
Test status
Simulation time 2237229742 ps
CPU time 37.17 seconds
Started Aug 25 10:18:02 AM UTC 24
Finished Aug 25 10:18:41 AM UTC 24
Peak memory 230704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004921128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.3004921128 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/43.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/43.kmac_stress_all.4188683876
Short name T691
Test name
Test status
Simulation time 16414555780 ps
CPU time 1515.14 seconds
Started Aug 25 10:18:50 AM UTC 24
Finished Aug 25 10:44:25 AM UTC 24
Peak memory 634776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188683876 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.4188683876 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/43.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/44.kmac_alert_test.1302985270
Short name T583
Test name
Test status
Simulation time 33130241 ps
CPU time 1.16 seconds
Started Aug 25 10:20:07 AM UTC 24
Finished Aug 25 10:20:09 AM UTC 24
Peak memory 214264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302985270 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.1302985270 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/44.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/44.kmac_app.1544678732
Short name T621
Test name
Test status
Simulation time 4303687404 ps
CPU time 295.26 seconds
Started Aug 25 10:19:21 AM UTC 24
Finished Aug 25 10:24:21 AM UTC 24
Peak memory 337744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544678732 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.1544678732 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/44.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/44.kmac_burst_write.1718014954
Short name T671
Test name
Test status
Simulation time 175408981044 ps
CPU time 872.7 seconds
Started Aug 25 10:19:20 AM UTC 24
Finished Aug 25 10:34:06 AM UTC 24
Peak memory 255900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718014954 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.1718014954 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/44.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/44.kmac_entropy_refresh.1489703945
Short name T623
Test name
Test status
Simulation time 12191321737 ps
CPU time 314.07 seconds
Started Aug 25 10:19:28 AM UTC 24
Finished Aug 25 10:24:47 AM UTC 24
Peak memory 431888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489703945 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.1489703945 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/44.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/44.kmac_error.3922856889
Short name T580
Test name
Test status
Simulation time 245636234 ps
CPU time 18.69 seconds
Started Aug 25 10:19:31 AM UTC 24
Finished Aug 25 10:19:51 AM UTC 24
Peak memory 245544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922856889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.3922856889 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/44.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/44.kmac_key_error.43651146
Short name T582
Test name
Test status
Simulation time 2656872103 ps
CPU time 15.69 seconds
Started Aug 25 10:19:48 AM UTC 24
Finished Aug 25 10:20:05 AM UTC 24
Peak memory 230488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43651146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.43651146 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/44.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/44.kmac_lc_escalation.2116133692
Short name T581
Test name
Test status
Simulation time 53171851 ps
CPU time 1.89 seconds
Started Aug 25 10:19:53 AM UTC 24
Finished Aug 25 10:19:55 AM UTC 24
Peak memory 229780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116133692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.2116133692 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/44.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/44.kmac_long_msg_and_output.2629683067
Short name T705
Test name
Test status
Simulation time 77137235441 ps
CPU time 2247.45 seconds
Started Aug 25 10:18:56 AM UTC 24
Finished Aug 25 10:56:54 AM UTC 24
Peak memory 1337160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629683067 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_and_output.2629683067 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/44.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/44.kmac_sideload.2464692336
Short name T588
Test name
Test status
Simulation time 3749892258 ps
CPU time 139.08 seconds
Started Aug 25 10:19:15 AM UTC 24
Finished Aug 25 10:21:37 AM UTC 24
Peak memory 325460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464692336 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.2464692336 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/44.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/44.kmac_smoke.367234032
Short name T577
Test name
Test status
Simulation time 490702919 ps
CPU time 32.79 seconds
Started Aug 25 10:18:53 AM UTC 24
Finished Aug 25 10:19:27 AM UTC 24
Peak memory 230560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367234032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.367234032 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/44.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/44.kmac_stress_all.238867653
Short name T708
Test name
Test status
Simulation time 76284107698 ps
CPU time 2354.92 seconds
Started Aug 25 10:19:57 AM UTC 24
Finished Aug 25 10:59:44 AM UTC 24
Peak memory 723176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238867653 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.238867653 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/44.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/45.kmac_alert_test.1105243240
Short name T594
Test name
Test status
Simulation time 14237339 ps
CPU time 1.22 seconds
Started Aug 25 10:22:07 AM UTC 24
Finished Aug 25 10:22:10 AM UTC 24
Peak memory 214264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105243240 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.1105243240 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/45.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/45.kmac_app.4142932882
Short name T606
Test name
Test status
Simulation time 3344411250 ps
CPU time 89.23 seconds
Started Aug 25 10:21:19 AM UTC 24
Finished Aug 25 10:22:50 AM UTC 24
Peak memory 284512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142932882 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.4142932882 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/45.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/45.kmac_burst_write.4005142310
Short name T646
Test name
Test status
Simulation time 56465828113 ps
CPU time 393.8 seconds
Started Aug 25 10:20:42 AM UTC 24
Finished Aug 25 10:27:22 AM UTC 24
Peak memory 243592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005142310 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.4005142310 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/45.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/45.kmac_entropy_refresh.1244155268
Short name T596
Test name
Test status
Simulation time 667660637 ps
CPU time 34.11 seconds
Started Aug 25 10:21:38 AM UTC 24
Finished Aug 25 10:22:14 AM UTC 24
Peak memory 239368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244155268 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.1244155268 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/45.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/45.kmac_error.1378735999
Short name T661
Test name
Test status
Simulation time 13764214977 ps
CPU time 534.5 seconds
Started Aug 25 10:21:38 AM UTC 24
Finished Aug 25 10:30:41 AM UTC 24
Peak memory 610128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378735999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.1378735999 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/45.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/45.kmac_key_error.1813993763
Short name T593
Test name
Test status
Simulation time 937222378 ps
CPU time 9.19 seconds
Started Aug 25 10:21:57 AM UTC 24
Finished Aug 25 10:22:07 AM UTC 24
Peak memory 230428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813993763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.1813993763 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/45.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/45.kmac_lc_escalation.2403858683
Short name T591
Test name
Test status
Simulation time 38966604 ps
CPU time 1.92 seconds
Started Aug 25 10:21:58 AM UTC 24
Finished Aug 25 10:22:01 AM UTC 24
Peak memory 229716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403858683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.2403858683 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/45.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/45.kmac_long_msg_and_output.4210751933
Short name T717
Test name
Test status
Simulation time 27448432072 ps
CPU time 3458.73 seconds
Started Aug 25 10:20:09 AM UTC 24
Finished Aug 25 11:18:34 AM UTC 24
Peak memory 1900508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210751933 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_and_output.4210751933 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/45.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/45.kmac_sideload.2819356687
Short name T660
Test name
Test status
Simulation time 20097779414 ps
CPU time 590.64 seconds
Started Aug 25 10:20:21 AM UTC 24
Finished Aug 25 10:30:22 AM UTC 24
Peak memory 649056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819356687 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.2819356687 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/45.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/45.kmac_smoke.4174152670
Short name T587
Test name
Test status
Simulation time 7704475626 ps
CPU time 86.07 seconds
Started Aug 25 10:20:08 AM UTC 24
Finished Aug 25 10:21:37 AM UTC 24
Peak memory 235352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174152670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.4174152670 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/45.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/45.kmac_stress_all.3943416533
Short name T597
Test name
Test status
Simulation time 48212897867 ps
CPU time 1116.31 seconds
Started Aug 25 10:22:02 AM UTC 24
Finished Aug 25 10:40:54 AM UTC 24
Peak memory 700508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943416533 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.3943416533 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/45.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/46.kmac_alert_test.2704321322
Short name T605
Test name
Test status
Simulation time 81173614 ps
CPU time 1.3 seconds
Started Aug 25 10:22:41 AM UTC 24
Finished Aug 25 10:22:43 AM UTC 24
Peak memory 216392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704321322 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.2704321322 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/46.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/46.kmac_app.661823761
Short name T600
Test name
Test status
Simulation time 294465814 ps
CPU time 9.05 seconds
Started Aug 25 10:22:18 AM UTC 24
Finished Aug 25 10:22:28 AM UTC 24
Peak memory 230692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661823761 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.661823761 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/46.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/46.kmac_burst_write.3142620703
Short name T692
Test name
Test status
Simulation time 26593403850 ps
CPU time 1362 seconds
Started Aug 25 10:22:15 AM UTC 24
Finished Aug 25 10:45:16 AM UTC 24
Peak memory 270228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142620703 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.3142620703 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/46.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/46.kmac_entropy_refresh.544629354
Short name T649
Test name
Test status
Simulation time 16895238785 ps
CPU time 320.08 seconds
Started Aug 25 10:22:26 AM UTC 24
Finished Aug 25 10:27:52 AM UTC 24
Peak memory 472848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544629354 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.544629354 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/46.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/46.kmac_error.4121316939
Short name T667
Test name
Test status
Simulation time 86039429492 ps
CPU time 639.43 seconds
Started Aug 25 10:22:29 AM UTC 24
Finished Aug 25 10:33:18 AM UTC 24
Peak memory 659244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121316939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.4121316939 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/46.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/46.kmac_key_error.1923688086
Short name T604
Test name
Test status
Simulation time 760279749 ps
CPU time 8.39 seconds
Started Aug 25 10:22:30 AM UTC 24
Finished Aug 25 10:22:40 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923688086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.1923688086 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/46.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/46.kmac_lc_escalation.4156953894
Short name T603
Test name
Test status
Simulation time 34910200 ps
CPU time 2.08 seconds
Started Aug 25 10:22:30 AM UTC 24
Finished Aug 25 10:22:34 AM UTC 24
Peak memory 230504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156953894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.4156953894 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/46.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/46.kmac_long_msg_and_output.2432964979
Short name T698
Test name
Test status
Simulation time 128682367718 ps
CPU time 1578.91 seconds
Started Aug 25 10:22:11 AM UTC 24
Finished Aug 25 10:48:53 AM UTC 24
Peak memory 1726424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432964979 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_and_output.2432964979 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/46.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/46.kmac_sideload.209846245
Short name T651
Test name
Test status
Simulation time 11103551688 ps
CPU time 336.53 seconds
Started Aug 25 10:22:15 AM UTC 24
Finished Aug 25 10:27:57 AM UTC 24
Peak memory 470864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209846245 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.209846245 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/46.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/46.kmac_smoke.1571898104
Short name T602
Test name
Test status
Simulation time 1301826674 ps
CPU time 18.98 seconds
Started Aug 25 10:22:09 AM UTC 24
Finished Aug 25 10:22:29 AM UTC 24
Peak memory 230560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571898104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.1571898104 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/46.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/46.kmac_stress_all.172782637
Short name T707
Test name
Test status
Simulation time 113468776527 ps
CPU time 2093.72 seconds
Started Aug 25 10:22:34 AM UTC 24
Finished Aug 25 10:57:58 AM UTC 24
Peak memory 1134816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172782637 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.172782637 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/46.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/47.kmac_alert_test.796769882
Short name T617
Test name
Test status
Simulation time 25497342 ps
CPU time 1.2 seconds
Started Aug 25 10:24:00 AM UTC 24
Finished Aug 25 10:24:02 AM UTC 24
Peak memory 214268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796769882 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.796769882 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/47.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/47.kmac_app.3484411962
Short name T611
Test name
Test status
Simulation time 908442149 ps
CPU time 11.66 seconds
Started Aug 25 10:23:10 AM UTC 24
Finished Aug 25 10:23:23 AM UTC 24
Peak memory 230552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484411962 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.3484411962 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/47.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/47.kmac_burst_write.111504507
Short name T636
Test name
Test status
Simulation time 11958477413 ps
CPU time 175.17 seconds
Started Aug 25 10:23:04 AM UTC 24
Finished Aug 25 10:26:02 AM UTC 24
Peak memory 235004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111504507 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.111504507 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/47.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/47.kmac_entropy_refresh.1531939729
Short name T635
Test name
Test status
Simulation time 33775733476 ps
CPU time 156.55 seconds
Started Aug 25 10:23:22 AM UTC 24
Finished Aug 25 10:26:02 AM UTC 24
Peak memory 317196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531939729 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.1531939729 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/47.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/47.kmac_error.1105190701
Short name T612
Test name
Test status
Simulation time 2540297797 ps
CPU time 27.22 seconds
Started Aug 25 10:23:23 AM UTC 24
Finished Aug 25 10:23:52 AM UTC 24
Peak memory 262104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105190701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.1105190701 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/47.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/47.kmac_key_error.2112573492
Short name T618
Test name
Test status
Simulation time 2290798250 ps
CPU time 9.55 seconds
Started Aug 25 10:23:53 AM UTC 24
Finished Aug 25 10:24:03 AM UTC 24
Peak memory 230496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112573492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.2112573492 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/47.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/47.kmac_lc_escalation.2666352836
Short name T615
Test name
Test status
Simulation time 32499771 ps
CPU time 1.85 seconds
Started Aug 25 10:23:56 AM UTC 24
Finished Aug 25 10:23:59 AM UTC 24
Peak memory 229840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666352836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.2666352836 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/47.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/47.kmac_long_msg_and_output.1631162697
Short name T675
Test name
Test status
Simulation time 35605815556 ps
CPU time 822.91 seconds
Started Aug 25 10:22:52 AM UTC 24
Finished Aug 25 10:36:46 AM UTC 24
Peak memory 1042192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631162697 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_and_output.1631162697 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/47.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/47.kmac_sideload.3630692124
Short name T653
Test name
Test status
Simulation time 32729594716 ps
CPU time 318.4 seconds
Started Aug 25 10:23:03 AM UTC 24
Finished Aug 25 10:28:26 AM UTC 24
Peak memory 331620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630692124 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.3630692124 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/47.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/47.kmac_smoke.261087756
Short name T619
Test name
Test status
Simulation time 4364514102 ps
CPU time 79.22 seconds
Started Aug 25 10:22:44 AM UTC 24
Finished Aug 25 10:24:05 AM UTC 24
Peak memory 232688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261087756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.261087756 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/47.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/47.kmac_stress_all.3922281621
Short name T659
Test name
Test status
Simulation time 4117834200 ps
CPU time 350.13 seconds
Started Aug 25 10:23:57 AM UTC 24
Finished Aug 25 10:29:52 AM UTC 24
Peak memory 301276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922281621 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.3922281621 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/47.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/48.kmac_alert_test.1343032007
Short name T628
Test name
Test status
Simulation time 63375301 ps
CPU time 1.22 seconds
Started Aug 25 10:24:54 AM UTC 24
Finished Aug 25 10:24:56 AM UTC 24
Peak memory 216392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343032007 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.1343032007 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/48.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/48.kmac_app.490157838
Short name T625
Test name
Test status
Simulation time 1672628233 ps
CPU time 35.51 seconds
Started Aug 25 10:24:13 AM UTC 24
Finished Aug 25 10:24:50 AM UTC 24
Peak memory 251784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490157838 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.490157838 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/48.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/48.kmac_burst_write.1690856762
Short name T697
Test name
Test status
Simulation time 30858266065 ps
CPU time 1376.28 seconds
Started Aug 25 10:24:06 AM UTC 24
Finished Aug 25 10:47:24 AM UTC 24
Peak memory 268064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690856762 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.1690856762 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/48.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/48.kmac_entropy_refresh.2473510936
Short name T645
Test name
Test status
Simulation time 3839533957 ps
CPU time 168.63 seconds
Started Aug 25 10:24:22 AM UTC 24
Finished Aug 25 10:27:14 AM UTC 24
Peak memory 278488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473510936 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.2473510936 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/48.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/48.kmac_error.1834290107
Short name T655
Test name
Test status
Simulation time 6894048171 ps
CPU time 275.77 seconds
Started Aug 25 10:24:29 AM UTC 24
Finished Aug 25 10:29:09 AM UTC 24
Peak memory 321284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834290107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.1834290107 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/48.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/48.kmac_key_error.1454881912
Short name T626
Test name
Test status
Simulation time 275049728 ps
CPU time 3.37 seconds
Started Aug 25 10:24:49 AM UTC 24
Finished Aug 25 10:24:53 AM UTC 24
Peak memory 232476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454881912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.1454881912 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/48.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/48.kmac_lc_escalation.675578371
Short name T627
Test name
Test status
Simulation time 36809256 ps
CPU time 1.78 seconds
Started Aug 25 10:24:51 AM UTC 24
Finished Aug 25 10:24:54 AM UTC 24
Peak memory 231832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675578371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.675578371 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/48.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/48.kmac_long_msg_and_output.1153493469
Short name T664
Test name
Test status
Simulation time 8401312258 ps
CPU time 488.68 seconds
Started Aug 25 10:24:03 AM UTC 24
Finished Aug 25 10:32:19 AM UTC 24
Peak memory 483072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153493469 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_and_output.1153493469 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/48.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/48.kmac_sideload.3237448438
Short name T631
Test name
Test status
Simulation time 2437406389 ps
CPU time 68.65 seconds
Started Aug 25 10:24:04 AM UTC 24
Finished Aug 25 10:25:15 AM UTC 24
Peak memory 251864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237448438 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.3237448438 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/48.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/48.kmac_smoke.3365129889
Short name T629
Test name
Test status
Simulation time 5277851301 ps
CPU time 66.53 seconds
Started Aug 25 10:24:02 AM UTC 24
Finished Aug 25 10:25:10 AM UTC 24
Peak memory 235352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365129889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.3365129889 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/48.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/48.kmac_stress_all.248636
Short name T682
Test name
Test status
Simulation time 97848906609 ps
CPU time 920.37 seconds
Started Aug 25 10:24:52 AM UTC 24
Finished Aug 25 10:40:25 AM UTC 24
Peak memory 491616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248636 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.248636 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/48.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/49.kmac_alert_test.3420724405
Short name T637
Test name
Test status
Simulation time 18932523 ps
CPU time 1.27 seconds
Started Aug 25 10:26:07 AM UTC 24
Finished Aug 25 10:26:09 AM UTC 24
Peak memory 216392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420724405 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.3420724405 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/49.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/49.kmac_app.633419944
Short name T663
Test name
Test status
Simulation time 22853129545 ps
CPU time 383.02 seconds
Started Aug 25 10:25:15 AM UTC 24
Finished Aug 25 10:31:45 AM UTC 24
Peak memory 480760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633419944 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.633419944 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/49.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/49.kmac_burst_write.3744563637
Short name T640
Test name
Test status
Simulation time 5112997150 ps
CPU time 65.12 seconds
Started Aug 25 10:25:15 AM UTC 24
Finished Aug 25 10:26:22 AM UTC 24
Peak memory 234352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744563637 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.3744563637 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/49.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/49.kmac_entropy_refresh.764746044
Short name T668
Test name
Test status
Simulation time 18264639284 ps
CPU time 471.8 seconds
Started Aug 25 10:25:24 AM UTC 24
Finished Aug 25 10:33:23 AM UTC 24
Peak memory 534340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764746044 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.764746044 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/49.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/49.kmac_error.1451877521
Short name T658
Test name
Test status
Simulation time 9562776913 ps
CPU time 237.18 seconds
Started Aug 25 10:25:43 AM UTC 24
Finished Aug 25 10:29:44 AM UTC 24
Peak memory 317260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451877521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.1451877521 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/49.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/49.kmac_key_error.4135669625
Short name T638
Test name
Test status
Simulation time 1872901022 ps
CPU time 13.78 seconds
Started Aug 25 10:25:59 AM UTC 24
Finished Aug 25 10:26:14 AM UTC 24
Peak memory 230688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135669625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.4135669625 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/49.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/49.kmac_long_msg_and_output.130902662
Short name T716
Test name
Test status
Simulation time 79491195501 ps
CPU time 3150.56 seconds
Started Aug 25 10:24:57 AM UTC 24
Finished Aug 25 11:18:09 AM UTC 24
Peak memory 3043168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130902662 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_and_output.130902662 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/49.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/49.kmac_sideload.130130213
Short name T669
Test name
Test status
Simulation time 49746313416 ps
CPU time 491.78 seconds
Started Aug 25 10:25:11 AM UTC 24
Finished Aug 25 10:33:31 AM UTC 24
Peak memory 562972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130130213 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.130130213 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/49.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/49.kmac_smoke.3066311136
Short name T642
Test name
Test status
Simulation time 8511395882 ps
CPU time 96.88 seconds
Started Aug 25 10:24:55 AM UTC 24
Finished Aug 25 10:26:34 AM UTC 24
Peak memory 234728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066311136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.3066311136 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/49.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/49.kmac_stress_all.3459587659
Short name T648
Test name
Test status
Simulation time 6356251140 ps
CPU time 87.2 seconds
Started Aug 25 10:26:03 AM UTC 24
Finished Aug 25 10:27:33 AM UTC 24
Peak memory 264396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459587659 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.3459587659 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/49.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/5.kmac_alert_test.2810738683
Short name T211
Test name
Test status
Simulation time 16225100 ps
CPU time 1.25 seconds
Started Aug 25 09:49:46 AM UTC 24
Finished Aug 25 09:49:48 AM UTC 24
Peak memory 214268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810738683 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.2810738683 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/5.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/5.kmac_app.3231944666
Short name T226
Test name
Test status
Simulation time 2540975314 ps
CPU time 126.95 seconds
Started Aug 25 09:49:05 AM UTC 24
Finished Aug 25 09:51:14 AM UTC 24
Peak memory 268188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231944666 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.3231944666 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/5.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/5.kmac_app_with_partial_data.3599891167
Short name T267
Test name
Test status
Simulation time 7927720669 ps
CPU time 287.02 seconds
Started Aug 25 09:49:10 AM UTC 24
Finished Aug 25 09:54:02 AM UTC 24
Peak memory 425816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599891167 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.3599891167 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/5.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/5.kmac_burst_write.859874029
Short name T427
Test name
Test status
Simulation time 23542447637 ps
CPU time 1050.47 seconds
Started Aug 25 09:48:56 AM UTC 24
Finished Aug 25 10:06:41 AM UTC 24
Peak memory 262092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859874029 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.859874029 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/5.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/5.kmac_edn_timeout_error.2433456454
Short name T215
Test name
Test status
Simulation time 1138491855 ps
CPU time 40.72 seconds
Started Aug 25 09:49:28 AM UTC 24
Finished Aug 25 09:50:11 AM UTC 24
Peak memory 232696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433456454 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.2433456454 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/5.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_mode_error.1024846231
Short name T209
Test name
Test status
Simulation time 245040380 ps
CPU time 3.04 seconds
Started Aug 25 09:49:34 AM UTC 24
Finished Aug 25 09:49:40 AM UTC 24
Peak memory 228340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024846231 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.1024846231 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/5.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_ready_error.2370275379
Short name T165
Test name
Test status
Simulation time 59891941653 ps
CPU time 107.69 seconds
Started Aug 25 09:49:40 AM UTC 24
Finished Aug 25 09:51:31 AM UTC 24
Peak memory 230892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370275379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.2370275379 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/5.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_refresh.1897433838
Short name T348
Test name
Test status
Simulation time 182869629082 ps
CPU time 615.01 seconds
Started Aug 25 09:49:16 AM UTC 24
Finished Aug 25 09:59:40 AM UTC 24
Peak memory 557060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897433838 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.1897433838 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/5.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/5.kmac_error.2139280481
Short name T51
Test name
Test status
Simulation time 19955096978 ps
CPU time 142.23 seconds
Started Aug 25 09:49:21 AM UTC 24
Finished Aug 25 09:51:46 AM UTC 24
Peak memory 341800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139280481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.2139280481 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/5.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/5.kmac_key_error.2339034431
Short name T66
Test name
Test status
Simulation time 952624916 ps
CPU time 9.98 seconds
Started Aug 25 09:49:22 AM UTC 24
Finished Aug 25 09:49:33 AM UTC 24
Peak memory 230376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339034431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.2339034431 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/5.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/5.kmac_lc_escalation.2168479863
Short name T40
Test name
Test status
Simulation time 39569303 ps
CPU time 1.85 seconds
Started Aug 25 09:49:40 AM UTC 24
Finished Aug 25 09:49:43 AM UTC 24
Peak memory 229788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168479863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.2168479863 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/5.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/5.kmac_long_msg_and_output.789037050
Short name T349
Test name
Test status
Simulation time 57596463240 ps
CPU time 657.75 seconds
Started Aug 25 09:48:47 AM UTC 24
Finished Aug 25 09:59:54 AM UTC 24
Peak memory 900964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789037050 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and_output.789037050 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/5.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/5.kmac_mubi.549019127
Short name T84
Test name
Test status
Simulation time 11186920331 ps
CPU time 68.85 seconds
Started Aug 25 09:49:16 AM UTC 24
Finished Aug 25 09:50:27 AM UTC 24
Peak memory 274784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549019127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.549019127 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/5.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/5.kmac_sideload.2972274794
Short name T341
Test name
Test status
Simulation time 21273697423 ps
CPU time 608.68 seconds
Started Aug 25 09:48:49 AM UTC 24
Finished Aug 25 09:59:07 AM UTC 24
Peak memory 673572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972274794 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.2972274794 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/5.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/5.kmac_smoke.3373726724
Short name T195
Test name
Test status
Simulation time 1477149368 ps
CPU time 57.47 seconds
Started Aug 25 09:48:45 AM UTC 24
Finished Aug 25 09:49:44 AM UTC 24
Peak memory 234672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373726724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.3373726724 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/5.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/5.kmac_stress_all.3005121783
Short name T320
Test name
Test status
Simulation time 6246769230 ps
CPU time 449.13 seconds
Started Aug 25 09:49:40 AM UTC 24
Finished Aug 25 09:57:17 AM UTC 24
Peak memory 331880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005121783 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.3005121783 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/5.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/6.kmac_alert_test.3058151555
Short name T216
Test name
Test status
Simulation time 17187950 ps
CPU time 1.05 seconds
Started Aug 25 09:50:11 AM UTC 24
Finished Aug 25 09:50:13 AM UTC 24
Peak memory 214268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058151555 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.3058151555 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/6.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/6.kmac_app.2675573497
Short name T230
Test name
Test status
Simulation time 8622636581 ps
CPU time 98.82 seconds
Started Aug 25 09:49:53 AM UTC 24
Finished Aug 25 09:51:34 AM UTC 24
Peak memory 263960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675573497 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.2675573497 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/6.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/6.kmac_app_with_partial_data.1236429660
Short name T222
Test name
Test status
Simulation time 5462658080 ps
CPU time 58.05 seconds
Started Aug 25 09:49:55 AM UTC 24
Finished Aug 25 09:50:55 AM UTC 24
Peak memory 245720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236429660 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.1236429660 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/6.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/6.kmac_burst_write.3094235393
Short name T398
Test name
Test status
Simulation time 7230977402 ps
CPU time 840.41 seconds
Started Aug 25 09:49:53 AM UTC 24
Finished Aug 25 10:04:06 AM UTC 24
Peak memory 249688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094235393 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.3094235393 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/6.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/6.kmac_edn_timeout_error.3822835403
Short name T217
Test name
Test status
Simulation time 346229521 ps
CPU time 12.56 seconds
Started Aug 25 09:50:03 AM UTC 24
Finished Aug 25 09:50:17 AM UTC 24
Peak memory 232448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822835403 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.3822835403 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/6.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_mode_error.3155466759
Short name T214
Test name
Test status
Simulation time 452986348 ps
CPU time 4.43 seconds
Started Aug 25 09:50:03 AM UTC 24
Finished Aug 25 09:50:09 AM UTC 24
Peak memory 232496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155466759 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.3155466759 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/6.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_ready_error.2378366085
Short name T231
Test name
Test status
Simulation time 24935185674 ps
CPU time 95.71 seconds
Started Aug 25 09:50:05 AM UTC 24
Finished Aug 25 09:51:43 AM UTC 24
Peak memory 230700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378366085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.2378366085 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/6.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_refresh.2329760213
Short name T309
Test name
Test status
Simulation time 14846366401 ps
CPU time 384.66 seconds
Started Aug 25 09:50:02 AM UTC 24
Finished Aug 25 09:56:34 AM UTC 24
Peak memory 341916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329760213 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.2329760213 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/6.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/6.kmac_error.54685951
Short name T50
Test name
Test status
Simulation time 9127905733 ps
CPU time 97.62 seconds
Started Aug 25 09:50:02 AM UTC 24
Finished Aug 25 09:51:42 AM UTC 24
Peak memory 268128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54685951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.54685951 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/6.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/6.kmac_key_error.3297663895
Short name T67
Test name
Test status
Simulation time 1641136619 ps
CPU time 15.8 seconds
Started Aug 25 09:50:02 AM UTC 24
Finished Aug 25 09:50:19 AM UTC 24
Peak memory 230456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297663895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.3297663895 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/6.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/6.kmac_lc_escalation.2321273000
Short name T41
Test name
Test status
Simulation time 302492803 ps
CPU time 2.09 seconds
Started Aug 25 09:50:07 AM UTC 24
Finished Aug 25 09:50:10 AM UTC 24
Peak memory 230376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321273000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.2321273000 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/6.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/6.kmac_long_msg_and_output.4058037277
Short name T690
Test name
Test status
Simulation time 23037818589 ps
CPU time 3079.49 seconds
Started Aug 25 09:49:49 AM UTC 24
Finished Aug 25 10:41:49 AM UTC 24
Peak memory 1662752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058037277 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and_output.4058037277 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/6.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/6.kmac_mubi.4245301381
Short name T86
Test name
Test status
Simulation time 1747078984 ps
CPU time 128.34 seconds
Started Aug 25 09:50:02 AM UTC 24
Finished Aug 25 09:52:13 AM UTC 24
Peak memory 272480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245301381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.4245301381 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/6.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/6.kmac_sideload.1097799668
Short name T339
Test name
Test status
Simulation time 28447751029 ps
CPU time 534.89 seconds
Started Aug 25 09:49:51 AM UTC 24
Finished Aug 25 09:58:53 AM UTC 24
Peak memory 605976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097799668 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.1097799668 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/6.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/6.kmac_smoke.4284901986
Short name T194
Test name
Test status
Simulation time 3868484642 ps
CPU time 84.42 seconds
Started Aug 25 09:49:46 AM UTC 24
Finished Aug 25 09:51:13 AM UTC 24
Peak memory 234776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284901986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.4284901986 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/6.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/6.kmac_stress_all.2034366726
Short name T437
Test name
Test status
Simulation time 25399390760 ps
CPU time 1040.59 seconds
Started Aug 25 09:50:09 AM UTC 24
Finished Aug 25 10:07:44 AM UTC 24
Peak memory 461008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034366726 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.2034366726 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/6.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/7.kmac_alert_test.2839768201
Short name T221
Test name
Test status
Simulation time 253598949 ps
CPU time 1.21 seconds
Started Aug 25 09:50:46 AM UTC 24
Finished Aug 25 09:50:48 AM UTC 24
Peak memory 214268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839768201 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.2839768201 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/7.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/7.kmac_app.434840215
Short name T260
Test name
Test status
Simulation time 4402119633 ps
CPU time 272.78 seconds
Started Aug 25 09:50:20 AM UTC 24
Finished Aug 25 09:54:57 AM UTC 24
Peak memory 317348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434840215 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.434840215 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/7.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/7.kmac_app_with_partial_data.818716954
Short name T224
Test name
Test status
Simulation time 28020718658 ps
CPU time 199.06 seconds
Started Aug 25 09:50:21 AM UTC 24
Finished Aug 25 09:53:43 AM UTC 24
Peak memory 343964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818716954 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.818716954 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/7.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/7.kmac_burst_write.8809846
Short name T43
Test name
Test status
Simulation time 1133900262 ps
CPU time 117.55 seconds
Started Aug 25 09:50:20 AM UTC 24
Finished Aug 25 09:52:20 AM UTC 24
Peak memory 234872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8809846 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.8809846 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/7.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/7.kmac_edn_timeout_error.121536762
Short name T218
Test name
Test status
Simulation time 442727970 ps
CPU time 5.44 seconds
Started Aug 25 09:50:30 AM UTC 24
Finished Aug 25 09:50:36 AM UTC 24
Peak memory 228408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121536762 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.121536762 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/7.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_mode_error.1203867326
Short name T223
Test name
Test status
Simulation time 2235539217 ps
CPU time 29.8 seconds
Started Aug 25 09:50:37 AM UTC 24
Finished Aug 25 09:51:08 AM UTC 24
Peak memory 230448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203867326 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.1203867326 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/7.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_ready_error.670499762
Short name T237
Test name
Test status
Simulation time 23134516097 ps
CPU time 74.64 seconds
Started Aug 25 09:50:41 AM UTC 24
Finished Aug 25 09:51:57 AM UTC 24
Peak memory 230620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670499762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.670499762 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/7.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_refresh.23606237
Short name T112
Test name
Test status
Simulation time 1307658662 ps
CPU time 17.88 seconds
Started Aug 25 09:50:21 AM UTC 24
Finished Aug 25 09:50:40 AM UTC 24
Peak memory 235256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23606237 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.23606237 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/7.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/7.kmac_error.494480081
Short name T167
Test name
Test status
Simulation time 2890262876 ps
CPU time 268.77 seconds
Started Aug 25 09:50:27 AM UTC 24
Finished Aug 25 09:55:00 AM UTC 24
Peak memory 319468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494480081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.494480081 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/7.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/7.kmac_key_error.4214787424
Short name T68
Test name
Test status
Simulation time 22385509360 ps
CPU time 14.75 seconds
Started Aug 25 09:50:29 AM UTC 24
Finished Aug 25 09:50:45 AM UTC 24
Peak memory 230564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214787424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.4214787424 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/7.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/7.kmac_lc_escalation.151275303
Short name T83
Test name
Test status
Simulation time 35146813 ps
CPU time 1.99 seconds
Started Aug 25 09:50:42 AM UTC 24
Finished Aug 25 09:50:45 AM UTC 24
Peak memory 231828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151275303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.151275303 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/7.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/7.kmac_long_msg_and_output.3599983620
Short name T725
Test name
Test status
Simulation time 496876759672 ps
CPU time 6226.72 seconds
Started Aug 25 09:50:14 AM UTC 24
Finished Aug 25 11:35:24 AM UTC 24
Peak memory 4640172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599983620 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_and_output.3599983620 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/7.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/7.kmac_mubi.1993274320
Short name T281
Test name
Test status
Simulation time 35520494390 ps
CPU time 259.81 seconds
Started Aug 25 09:50:25 AM UTC 24
Finished Aug 25 09:54:50 AM UTC 24
Peak memory 385180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993274320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.1993274320 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/7.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/7.kmac_sideload.4221203672
Short name T219
Test name
Test status
Simulation time 2865905031 ps
CPU time 21.95 seconds
Started Aug 25 09:50:17 AM UTC 24
Finished Aug 25 09:50:41 AM UTC 24
Peak memory 239568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221203672 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.4221203672 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/7.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/7.kmac_smoke.3934817539
Short name T197
Test name
Test status
Simulation time 2495431463 ps
CPU time 14.86 seconds
Started Aug 25 09:50:12 AM UTC 24
Finished Aug 25 09:50:28 AM UTC 24
Peak memory 232748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934817539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.3934817539 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/7.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/7.kmac_stress_all.2392469419
Short name T634
Test name
Test status
Simulation time 212989539818 ps
CPU time 2085.88 seconds
Started Aug 25 09:50:45 AM UTC 24
Finished Aug 25 10:25:58 AM UTC 24
Peak memory 1089840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392469419 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.2392469419 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/7.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/8.kmac_alert_test.2071144289
Short name T229
Test name
Test status
Simulation time 16608538 ps
CPU time 1.06 seconds
Started Aug 25 09:51:19 AM UTC 24
Finished Aug 25 09:51:21 AM UTC 24
Peak memory 214268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071144289 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.2071144289 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/8.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/8.kmac_app.1897879958
Short name T321
Test name
Test status
Simulation time 26428689029 ps
CPU time 370.27 seconds
Started Aug 25 09:51:03 AM UTC 24
Finished Aug 25 09:57:19 AM UTC 24
Peak memory 475040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897879958 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.1897879958 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/8.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/8.kmac_app_with_partial_data.2540409169
Short name T131
Test name
Test status
Simulation time 4754221380 ps
CPU time 70.09 seconds
Started Aug 25 09:51:04 AM UTC 24
Finished Aug 25 09:52:16 AM UTC 24
Peak memory 264032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540409169 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.2540409169 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/8.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/8.kmac_burst_write.3769127465
Short name T47
Test name
Test status
Simulation time 18237063146 ps
CPU time 562.44 seconds
Started Aug 25 09:51:00 AM UTC 24
Finished Aug 25 10:00:31 AM UTC 24
Peak memory 246980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769127465 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.3769127465 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/8.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/8.kmac_edn_timeout_error.4038333915
Short name T132
Test name
Test status
Simulation time 4418964244 ps
CPU time 63.98 seconds
Started Aug 25 09:51:10 AM UTC 24
Finished Aug 25 09:52:16 AM UTC 24
Peak memory 234560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038333915 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.4038333915 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/8.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_mode_error.3546975078
Short name T233
Test name
Test status
Simulation time 2384626619 ps
CPU time 36.56 seconds
Started Aug 25 09:51:10 AM UTC 24
Finished Aug 25 09:51:49 AM UTC 24
Peak memory 235284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546975078 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.3546975078 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/8.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_ready_error.88680044
Short name T244
Test name
Test status
Simulation time 5031553911 ps
CPU time 79.93 seconds
Started Aug 25 09:51:13 AM UTC 24
Finished Aug 25 09:52:35 AM UTC 24
Peak memory 230624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88680044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.88680044 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/8.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_refresh.2894467274
Short name T163
Test name
Test status
Simulation time 3513669961 ps
CPU time 113.47 seconds
Started Aug 25 09:51:04 AM UTC 24
Finished Aug 25 09:53:00 AM UTC 24
Peak memory 270224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894467274 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.2894467274 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/8.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/8.kmac_error.3033343632
Short name T277
Test name
Test status
Simulation time 4234280281 ps
CPU time 200.67 seconds
Started Aug 25 09:51:06 AM UTC 24
Finished Aug 25 09:54:31 AM UTC 24
Peak memory 300896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033343632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.3033343632 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/8.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/8.kmac_key_error.1542892190
Short name T69
Test name
Test status
Simulation time 1179888224 ps
CPU time 8.27 seconds
Started Aug 25 09:51:08 AM UTC 24
Finished Aug 25 09:51:18 AM UTC 24
Peak memory 230424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542892190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.1542892190 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/8.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/8.kmac_lc_escalation.1192133656
Short name T227
Test name
Test status
Simulation time 416374685 ps
CPU time 1.8 seconds
Started Aug 25 09:51:14 AM UTC 24
Finished Aug 25 09:51:17 AM UTC 24
Peak memory 229736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192133656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.1192133656 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/8.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/8.kmac_long_msg_and_output.2367002891
Short name T721
Test name
Test status
Simulation time 244768307849 ps
CPU time 5397.84 seconds
Started Aug 25 09:50:56 AM UTC 24
Finished Aug 25 11:22:03 AM UTC 24
Peak memory 4685740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367002891 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_and_output.2367002891 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/8.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/8.kmac_mubi.2945341895
Short name T89
Test name
Test status
Simulation time 8568329625 ps
CPU time 149.46 seconds
Started Aug 25 09:51:04 AM UTC 24
Finished Aug 25 09:53:37 AM UTC 24
Peak memory 333980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945341895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.2945341895 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/8.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/8.kmac_sideload.358110159
Short name T254
Test name
Test status
Simulation time 3402872938 ps
CPU time 136.68 seconds
Started Aug 25 09:51:00 AM UTC 24
Finished Aug 25 09:53:20 AM UTC 24
Peak memory 278328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358110159 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.358110159 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/8.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/8.kmac_smoke.766977353
Short name T234
Test name
Test status
Simulation time 8774816122 ps
CPU time 60.25 seconds
Started Aug 25 09:50:49 AM UTC 24
Finished Aug 25 09:51:51 AM UTC 24
Peak memory 232756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766977353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.766977353 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/8.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/8.kmac_stress_all.2266208376
Short name T508
Test name
Test status
Simulation time 36028820029 ps
CPU time 1271.41 seconds
Started Aug 25 09:51:15 AM UTC 24
Finished Aug 25 10:12:44 AM UTC 24
Peak memory 1319072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266208376 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.2266208376 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/8.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/9.kmac_alert_test.667832069
Short name T238
Test name
Test status
Simulation time 29732434 ps
CPU time 1.24 seconds
Started Aug 25 09:51:58 AM UTC 24
Finished Aug 25 09:52:00 AM UTC 24
Peak memory 214268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667832069 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.667832069 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/9.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/9.kmac_app.2516268247
Short name T232
Test name
Test status
Simulation time 1351831600 ps
CPU time 10.33 seconds
Started Aug 25 09:51:36 AM UTC 24
Finished Aug 25 09:51:47 AM UTC 24
Peak memory 245640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516268247 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.2516268247 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/9.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/9.kmac_app_with_partial_data.4240928286
Short name T300
Test name
Test status
Simulation time 25271813941 ps
CPU time 261.09 seconds
Started Aug 25 09:51:39 AM UTC 24
Finished Aug 25 09:56:05 AM UTC 24
Peak memory 395232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240928286 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.4240928286 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/9.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/9.kmac_burst_write.2578909199
Short name T358
Test name
Test status
Simulation time 10398115556 ps
CPU time 551.64 seconds
Started Aug 25 09:51:35 AM UTC 24
Finished Aug 25 10:00:55 AM UTC 24
Peak memory 247636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578909199 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.2578909199 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/9.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/9.kmac_edn_timeout_error.2682638066
Short name T128
Test name
Test status
Simulation time 9121883239 ps
CPU time 19.24 seconds
Started Aug 25 09:51:49 AM UTC 24
Finished Aug 25 09:52:10 AM UTC 24
Peak memory 235156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682638066 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.2682638066 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/9.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_mode_error.3694034904
Short name T130
Test name
Test status
Simulation time 1784921631 ps
CPU time 23.43 seconds
Started Aug 25 09:51:49 AM UTC 24
Finished Aug 25 09:52:14 AM UTC 24
Peak memory 235364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694034904 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.3694034904 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/9.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_ready_error.2643558984
Short name T256
Test name
Test status
Simulation time 11120539087 ps
CPU time 90.66 seconds
Started Aug 25 09:51:52 AM UTC 24
Finished Aug 25 09:53:24 AM UTC 24
Peak memory 230620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643558984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.2643558984 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/9.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_refresh.809910564
Short name T164
Test name
Test status
Simulation time 25279472718 ps
CPU time 377.47 seconds
Started Aug 25 09:51:43 AM UTC 24
Finished Aug 25 09:58:06 AM UTC 24
Peak memory 501520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809910564 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.809910564 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/9.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/9.kmac_error.3987843926
Short name T235
Test name
Test status
Simulation time 47867749 ps
CPU time 4.47 seconds
Started Aug 25 09:51:47 AM UTC 24
Finished Aug 25 09:51:53 AM UTC 24
Peak memory 230560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987843926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.3987843926 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/9.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/9.kmac_key_error.3539478839
Short name T70
Test name
Test status
Simulation time 1222916751 ps
CPU time 10.67 seconds
Started Aug 25 09:51:48 AM UTC 24
Finished Aug 25 09:52:00 AM UTC 24
Peak memory 230516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539478839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.3539478839 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/9.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/9.kmac_lc_escalation.1922021617
Short name T236
Test name
Test status
Simulation time 126300895 ps
CPU time 1.96 seconds
Started Aug 25 09:51:53 AM UTC 24
Finished Aug 25 09:51:56 AM UTC 24
Peak memory 229728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922021617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.1922021617 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/9.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/9.kmac_long_msg_and_output.933656812
Short name T672
Test name
Test status
Simulation time 103819297531 ps
CPU time 2531.8 seconds
Started Aug 25 09:51:22 AM UTC 24
Finished Aug 25 10:34:07 AM UTC 24
Peak memory 2559836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933656812 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and_output.933656812 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/9.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/9.kmac_mubi.3228453387
Short name T87
Test name
Test status
Simulation time 1097011884 ps
CPU time 76.58 seconds
Started Aug 25 09:51:44 AM UTC 24
Finished Aug 25 09:53:03 AM UTC 24
Peak memory 254044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228453387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.3228453387 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/9.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/9.kmac_sideload.3845479249
Short name T271
Test name
Test status
Simulation time 1628899873 ps
CPU time 155.67 seconds
Started Aug 25 09:51:31 AM UTC 24
Finished Aug 25 09:54:11 AM UTC 24
Peak memory 284444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845479249 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.3845479249 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/9.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/9.kmac_smoke.1822091211
Short name T239
Test name
Test status
Simulation time 8758897873 ps
CPU time 40.32 seconds
Started Aug 25 09:51:20 AM UTC 24
Finished Aug 25 09:52:02 AM UTC 24
Peak memory 230624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822091211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.1822091211 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/9.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default/9.kmac_stress_all.499743249
Short name T369
Test name
Test status
Simulation time 61402723337 ps
CPU time 596.51 seconds
Started Aug 25 09:51:54 AM UTC 24
Finished Aug 25 10:01:59 AM UTC 24
Peak memory 766104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499743249 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.499743249 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/9.kmac_stress_all/latest
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