Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15251893	1			T1	90		T2	137		T12	133
all_values[1]	15251893	1			T1	90		T2	137		T12	133
all_values[2]	15251893	1			T1	90		T2	137		T12	133

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

504487

1

T1

14

T2

137

T12

266

auto[1]

45251192

1

T1

256

T2

274

T12

133

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45530085

1

T1

258

T2

393

T12

381

auto[1]

225594

1

T1

12

T2

18

T12

18

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	197072	1			T2	131		T12	127		T13	4
all_values[0]	auto[0]	auto[1]	1328	1			T2	6		T12	6		T13	2
all_values[0]	auto[1]	auto[0]	14979623	1			T1	86		T13	129		T14	873
all_values[0]	auto[1]	auto[1]	73870	1			T1	4		T13	3		T14	114
all_values[1]	auto[0]	auto[0]	164051	1			T1	6		T12	127		T13	58
all_values[1]	auto[0]	auto[1]	999	1			T1	1		T12	6		T13	3
all_values[1]	auto[1]	auto[0]	15012644	1			T1	80		T2	131		T13	75
all_values[1]	auto[1]	auto[1]	74199	1			T1	3		T2	6		T13	2
all_values[2]	auto[0]	auto[0]	140110	1			T1	6		T13	58		T14	2
all_values[2]	auto[0]	auto[1]	927	1			T1	1		T13	3		T14	1
all_values[2]	auto[1]	auto[0]	15036585	1			T1	80		T2	131		T12	127
all_values[2]	auto[1]	auto[1]	74271	1			T1	3		T2	6		T12	6