Unified Coverage Report :: Group :: kmac_env_pkg::config_unmasked_cg

Group : kmac_env_pkg::config_unmasked_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::config_unmasked_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	23	0	23	100.00
Crosses	4	0	4	100.00

Variables for Group kmac_env_pkg::config_unmasked_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
key_len	5	0	5	100.00	100	1	1	0
kmac_en	2	0	2	100.00	100	1	1	2
mode	3	0	3	100.00	100	1	1	0
msg_endian	2	0	2	100.00	100	1	1	2
sideload	2	0	2	100.00	100	1	1	2
state_endian	2	0	2	100.00	100	1	1	2
strength	5	0	5	100.00	100	1	1	0
xof_en	2	0	2	100.00	100	1	1	2

Crosses for Group kmac_env_pkg::config_unmasked_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
kmac_cross	1	0	1	100.00	100	1	1	0
cshake_cross	1	0	1	100.00	100	1	1	0
shake_cross	1	0	1	100.00	100	1	1	0
sha3_cross	1	0	1	100.00	100	1	1	0

Summary for Variable key_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for key_len

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[Key128]	8380	1			T14	9		T16	24		T18	11
auto[Key192]	8367	1			T14	18		T16	24		T18	9
auto[Key256]	22869	1			T1	3		T2	3		T12	3
auto[Key384]	8274	1			T14	18		T16	25		T18	25
auto[Key512]	8252	1			T14	14		T16	28		T18	15

---

Summary for Variable kmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24755

1

T14

73

T16

137

T18

73

auto[1]

31387

1

T1

3

T2

3

T12

3

---

Summary for Variable mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[Sha3]	3437	1			T14	73		T16	137		T18	73
auto[Shake]	17865	1			T40	10		T51	13		T121	25
auto[CShake]	34840	1			T1	3		T2	3		T12	3

---

Summary for Variable msg_endian

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msg_endian

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27929

1

T1

2

T2

1

T12

1

auto[1]

28213

1

T1

1

T2

2

T12

2

---

Summary for Variable sideload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sideload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45016

1

T1

3

T2

3

T12

3

auto[1]

11126

1

T21

26

T23

1

T24

26

---

Summary for Variable state_endian

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for state_endian

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28011

1

T1

1

T2

2

T12

2

auto[1]

28131

1

T1

2

T2

1

T12

1

---

Summary for Variable strength

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for strength

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[L128]	23875	1			T1	3		T40	14		T81	3
auto[L224]	875	1			T40	3		T79	145		T51	3
auto[L256]	29767	1			T2	3		T12	3		T13	3
auto[L384]	897	1			T95	105		T96	105		T51	5
auto[L512]	728	1			T14	73		T18	73		T40	1

---

Summary for Variable xof_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for xof_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38343

1

T1

3

T12

3

T14

73

auto[1]

17799

1

T2

3

T13

3

T40

19

---

Summary for Cross kmac_cross

Samples crossed: kmac_en xof_en strength key_len msg_endian state_endian

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for kmac_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid_mode	0	Excluded
invalid_strength	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valid

31387

1

T1

3

T2

3

T12

3

---

Summary for Cross cshake_cross

Samples crossed: mode strength msg_endian state_endian

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for cshake_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid_mode	0	Excluded
invalid_strength	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valid

34840

1

T1

3

T2

3

T12

3

---

Summary for Cross shake_cross

Samples crossed: mode strength msg_endian state_endian

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for shake_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid_mode	0	Excluded
invalid_strength	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valid

17865

1

T40

10

T51

13

T121

25

---

Summary for Cross sha3_cross

Samples crossed: mode strength msg_endian state_endian

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for sha3_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid_mode	0	Excluded
invalid_strength	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valid

3437

1

T14

73

T16

137

T18

73