Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
60486 |
1 |
|
|
T1 |
6 |
|
T2 |
6 |
|
T3 |
2 |
auto[1] |
54040 |
1 |
|
|
T12 |
4 |
|
T14 |
144 |
|
T18 |
144 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
28473 |
1 |
|
|
T2 |
2 |
|
T12 |
2 |
|
T13 |
2 |
lower_val |
28391 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
zero_val |
867 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
1 |
2 |
66.67 |
User Defined Bins for wait_timer_val
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
zero_val |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
57202 |
1 |
|
|
T1 |
4 |
|
T2 |
2 |
|
T3 |
2 |
lower_val |
57324 |
1 |
|
|
T1 |
2 |
|
T2 |
4 |
|
T12 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
6 |
12 |
66.67 |
6 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
* |
[zero_val] |
* |
-- |
-- |
6 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
7534 |
1 |
|
|
T2 |
1 |
|
T13 |
2 |
|
T16 |
33 |
higher_val |
higher_val |
auto[1] |
6873 |
1 |
|
|
T12 |
1 |
|
T14 |
17 |
|
T18 |
12 |
higher_val |
lower_val |
auto[0] |
7331 |
1 |
|
|
T2 |
1 |
|
T12 |
1 |
|
T16 |
31 |
higher_val |
lower_val |
auto[1] |
6735 |
1 |
|
|
T14 |
15 |
|
T18 |
14 |
|
T96 |
25 |
lower_val |
higher_val |
auto[0] |
7528 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
33 |
lower_val |
higher_val |
auto[1] |
6629 |
1 |
|
|
T14 |
21 |
|
T18 |
19 |
|
T96 |
33 |
lower_val |
lower_val |
auto[0] |
7475 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
lower_val |
lower_val |
auto[1] |
6759 |
1 |
|
|
T14 |
25 |
|
T18 |
22 |
|
T96 |
21 |
zero_val |
higher_val |
auto[0] |
336 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T13 |
1 |
zero_val |
higher_val |
auto[1] |
82 |
1 |
|
|
T167 |
2 |
|
T64 |
1 |
|
T153 |
2 |
zero_val |
lower_val |
auto[0] |
355 |
1 |
|
|
T2 |
1 |
|
T12 |
1 |
|
T14 |
1 |
zero_val |
lower_val |
auto[1] |
94 |
1 |
|
|
T168 |
2 |
|
T64 |
1 |
|
T169 |
2 |