Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}
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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 0 7 100.00
Crosses 12 0 12 100.00


Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr_pin 3 0 3 100.00 100 1 1 0
cp_intr_pin_value 4 0 4 100.00 100 1 1 0


Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_intr_pins_all_values 12 0 12 100.00 100 1 1 0


Summary for Variable cp_intr_pin

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr_pin

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] 15251893 1 T1 90 T2 137 T12 133
all_pins[1] 15251893 1 T1 90 T2 137 T12 133
all_pins[2] 15251893 1 T1 90 T2 137 T12 133



Summary for Variable cp_intr_pin_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_intr_pin_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 45350373 1 T1 266 T2 411 T12 399
values[0x1] 405306 1 T1 4 T13 3 T14 114
transitions[0x0=>0x1] 403337 1 T1 4 T13 3 T14 114
transitions[0x1=>0x0] 403358 1 T1 4 T13 3 T14 114



Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 12 0 12 100.00


Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins
cp_intr_pincp_intr_pin_valueCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] values[0x0] 15178023 1 T1 86 T2 137 T12 133
all_pins[0] values[0x1] 73870 1 T1 4 T13 3 T14 114
all_pins[0] transitions[0x0=>0x1] 73856 1 T1 4 T13 3 T14 114
all_pins[0] transitions[0x1=>0x0] 45 1 T57 3 T178 3 T179 4
all_pins[1] values[0x0] 15251834 1 T1 90 T2 137 T12 133
all_pins[1] values[0x1] 59 1 T57 3 T178 3 T179 4
all_pins[1] transitions[0x0=>0x1] 53 1 T57 3 T178 3 T179 4
all_pins[1] transitions[0x1=>0x0] 331371 1 T23 1006 T25 261 T41 4784
all_pins[2] values[0x0] 14920516 1 T1 90 T2 137 T12 133
all_pins[2] values[0x1] 331377 1 T23 1006 T25 261 T41 4784
all_pins[2] transitions[0x0=>0x1] 329428 1 T23 1000 T25 261 T41 4756
all_pins[2] transitions[0x1=>0x0] 71942 1 T1 4 T13 3 T14 114

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