Summary for Variable cp_intr_pin
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_intr_pin
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
15251893 |
1 |
|
|
T1 |
90 |
|
T2 |
137 |
|
T12 |
133 |
all_pins[1] |
15251893 |
1 |
|
|
T1 |
90 |
|
T2 |
137 |
|
T12 |
133 |
all_pins[2] |
15251893 |
1 |
|
|
T1 |
90 |
|
T2 |
137 |
|
T12 |
133 |
Summary for Variable cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for cp_intr_pin_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x0] |
45350373 |
1 |
|
|
T1 |
266 |
|
T2 |
411 |
|
T12 |
399 |
values[0x1] |
405306 |
1 |
|
|
T1 |
4 |
|
T13 |
3 |
|
T14 |
114 |
transitions[0x0=>0x1] |
403337 |
1 |
|
|
T1 |
4 |
|
T13 |
3 |
|
T14 |
114 |
transitions[0x1=>0x0] |
403358 |
1 |
|
|
T1 |
4 |
|
T13 |
3 |
|
T14 |
114 |
Summary for Cross cp_intr_pins_all_values
Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
12 |
0 |
12 |
100.00 |
|
Automatically Generated Cross Bins for cp_intr_pins_all_values
Bins
cp_intr_pin | cp_intr_pin_value | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
values[0x0] |
15178023 |
1 |
|
|
T1 |
86 |
|
T2 |
137 |
|
T12 |
133 |
all_pins[0] |
values[0x1] |
73870 |
1 |
|
|
T1 |
4 |
|
T13 |
3 |
|
T14 |
114 |
all_pins[0] |
transitions[0x0=>0x1] |
73856 |
1 |
|
|
T1 |
4 |
|
T13 |
3 |
|
T14 |
114 |
all_pins[0] |
transitions[0x1=>0x0] |
45 |
1 |
|
|
T57 |
3 |
|
T178 |
3 |
|
T179 |
4 |
all_pins[1] |
values[0x0] |
15251834 |
1 |
|
|
T1 |
90 |
|
T2 |
137 |
|
T12 |
133 |
all_pins[1] |
values[0x1] |
59 |
1 |
|
|
T57 |
3 |
|
T178 |
3 |
|
T179 |
4 |
all_pins[1] |
transitions[0x0=>0x1] |
53 |
1 |
|
|
T57 |
3 |
|
T178 |
3 |
|
T179 |
4 |
all_pins[1] |
transitions[0x1=>0x0] |
331371 |
1 |
|
|
T23 |
1006 |
|
T25 |
261 |
|
T41 |
4784 |
all_pins[2] |
values[0x0] |
14920516 |
1 |
|
|
T1 |
90 |
|
T2 |
137 |
|
T12 |
133 |
all_pins[2] |
values[0x1] |
331377 |
1 |
|
|
T23 |
1006 |
|
T25 |
261 |
|
T41 |
4784 |
all_pins[2] |
transitions[0x0=>0x1] |
329428 |
1 |
|
|
T23 |
1000 |
|
T25 |
261 |
|
T41 |
4756 |
all_pins[2] |
transitions[0x1=>0x0] |
71942 |
1 |
|
|
T1 |
4 |
|
T13 |
3 |
|
T14 |
114 |