Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	655	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5447	1			T26	6		T41	5		T143	4
len_601_800	12076	1			T23	3		T25	2		T26	15
len_401_600	8186	1			T23	1		T25	2		T26	8
len_201_400	4357	1			T23	1		T25	1		T26	3
len_65_200	8338	1			T40	16		T51	61		T121	101
len_min_for_xof_require_squeeze	88	1			T121	1		T143	1		T116	1
len_keccak_block_sizes[72]	92	1			T40	1		T51	1		T121	2
len_keccak_block_sizes[104]	92	1			T121	1		T194	1		T151	9
len_keccak_block_sizes[136]	82	1			T51	1		T121	3		T195	1
len_keccak_block_sizes[144]	48	1			T51	1		T121	1		T195	1
len_keccak_block_sizes[168]	47	1			T51	2		T196	5		T197	5
len_datapath_width	1019	1			T2	3		T12	3		T13	3
len_2_63	16013	1			T1	3		T16	137		T95	105
len_1	51	1			T51	2		T121	1		T195	2