Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.79	95.77	90.51	100.00	67.77	93.67	98.84	96.01

Total test records in report: 878

T765	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.2108763015	Aug 29 11:06:13 AM UTC 24	Aug 29 11:06:15 AM UTC 24	34537613 ps
T766	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.1687532234	Aug 29 11:06:13 AM UTC 24	Aug 29 11:06:15 AM UTC 24	62381524 ps
T767	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.3332671124	Aug 29 11:06:11 AM UTC 24	Aug 29 11:06:16 AM UTC 24	262955224 ps
T768	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.1782547576	Aug 29 11:06:12 AM UTC 24	Aug 29 11:06:16 AM UTC 24	103358090 ps
T769	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.1580368760	Aug 29 11:06:22 AM UTC 24	Aug 29 11:06:24 AM UTC 24	25732863 ps
T770	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.1442855306	Aug 29 11:06:06 AM UTC 24	Aug 29 11:06:16 AM UTC 24	1799537213 ps
T771	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.4117116473	Aug 29 11:06:14 AM UTC 24	Aug 29 11:06:16 AM UTC 24	20647628 ps
T772	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.1919385489	Aug 29 11:06:14 AM UTC 24	Aug 29 11:06:16 AM UTC 24	11158546 ps
T773	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.962832996	Aug 29 11:06:14 AM UTC 24	Aug 29 11:06:16 AM UTC 24	144836160 ps
T774	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2763007922	Aug 29 11:06:13 AM UTC 24	Aug 29 11:06:16 AM UTC 24	37474360 ps
T775	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.60080942	Aug 29 11:06:13 AM UTC 24	Aug 29 11:06:16 AM UTC 24	91651880 ps
T776	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.555684479	Aug 29 11:06:14 AM UTC 24	Aug 29 11:06:16 AM UTC 24	22175520 ps
T114	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.1802818152	Aug 29 11:06:14 AM UTC 24	Aug 29 11:06:16 AM UTC 24	29377377 ps
T777	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.333283253	Aug 29 11:05:57 AM UTC 24	Aug 29 11:06:17 AM UTC 24	1104502055 ps
T778	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.1356893656	Aug 29 11:06:14 AM UTC 24	Aug 29 11:06:17 AM UTC 24	70172133 ps
T779	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.414383443	Aug 29 11:06:14 AM UTC 24	Aug 29 11:06:17 AM UTC 24	129148743 ps
T780	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3599257852	Aug 29 11:06:14 AM UTC 24	Aug 29 11:06:18 AM UTC 24	128306212 ps
T139	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.64915771	Aug 29 11:06:14 AM UTC 24	Aug 29 11:06:18 AM UTC 24	180586297 ps
T781	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.3265828902	Aug 29 11:06:16 AM UTC 24	Aug 29 11:06:18 AM UTC 24	43900075 ps
T136	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.216984753	Aug 29 11:06:13 AM UTC 24	Aug 29 11:06:18 AM UTC 24	159447144 ps
T782	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.4048020076	Aug 29 11:06:16 AM UTC 24	Aug 29 11:06:18 AM UTC 24	32320843 ps
T783	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1927274728	Aug 29 11:06:15 AM UTC 24	Aug 29 11:06:18 AM UTC 24	89558741 ps
T784	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.4113371028	Aug 29 11:06:16 AM UTC 24	Aug 29 11:06:18 AM UTC 24	150900883 ps
T785	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.510028013	Aug 29 11:06:16 AM UTC 24	Aug 29 11:06:18 AM UTC 24	19218321 ps
T786	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.2092138866	Aug 29 11:06:16 AM UTC 24	Aug 29 11:06:18 AM UTC 24	118136998 ps
T787	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.4224238847	Aug 29 11:06:16 AM UTC 24	Aug 29 11:06:18 AM UTC 24	101260002 ps
T788	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.245867366	Aug 29 11:06:15 AM UTC 24	Aug 29 11:06:19 AM UTC 24	38853993 ps
T140	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.3957617385	Aug 29 11:06:16 AM UTC 24	Aug 29 11:06:19 AM UTC 24	32838928 ps
T789	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.2631559370	Aug 29 11:06:16 AM UTC 24	Aug 29 11:06:19 AM UTC 24	254186617 ps
T790	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.1166900285	Aug 29 11:06:22 AM UTC 24	Aug 29 11:06:24 AM UTC 24	90821099 ps
T180	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.4210280824	Aug 29 11:06:13 AM UTC 24	Aug 29 11:06:19 AM UTC 24	237467151 ps
T791	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.274850986	Aug 29 11:06:17 AM UTC 24	Aug 29 11:06:19 AM UTC 24	53114115 ps
T137	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.2908753795	Aug 29 11:06:14 AM UTC 24	Aug 29 11:06:19 AM UTC 24	279182656 ps
T189	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.3930616295	Aug 29 11:06:16 AM UTC 24	Aug 29 11:06:19 AM UTC 24	471287962 ps
T792	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.58641972	Aug 29 11:06:17 AM UTC 24	Aug 29 11:06:19 AM UTC 24	39051423 ps
T793	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.2296161075	Aug 29 11:06:17 AM UTC 24	Aug 29 11:06:19 AM UTC 24	35915754 ps
T109	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3693982010	Aug 29 11:06:17 AM UTC 24	Aug 29 11:06:19 AM UTC 24	70941435 ps
T186	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.1864124139	Aug 29 11:06:14 AM UTC 24	Aug 29 11:06:19 AM UTC 24	211227123 ps
T794	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.3399762360	Aug 29 11:06:17 AM UTC 24	Aug 29 11:06:19 AM UTC 24	53474173 ps
T795	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.2306295888	Aug 29 11:06:16 AM UTC 24	Aug 29 11:06:19 AM UTC 24	329778148 ps
T796	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3851186582	Aug 29 11:06:17 AM UTC 24	Aug 29 11:06:20 AM UTC 24	85112511 ps
T797	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2708902673	Aug 29 11:06:17 AM UTC 24	Aug 29 11:06:20 AM UTC 24	25763446 ps
T798	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.1647087136	Aug 29 11:06:14 AM UTC 24	Aug 29 11:06:20 AM UTC 24	471310930 ps
T799	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3572693009	Aug 29 11:06:17 AM UTC 24	Aug 29 11:06:20 AM UTC 24	210040552 ps
T800	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1158628247	Aug 29 11:06:17 AM UTC 24	Aug 29 11:06:20 AM UTC 24	90437192 ps
T801	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.811180201	Aug 29 11:06:17 AM UTC 24	Aug 29 11:06:21 AM UTC 24	78034312 ps
T802	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.677559998	Aug 29 11:06:17 AM UTC 24	Aug 29 11:06:21 AM UTC 24	339441273 ps
T803	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.3145989791	Aug 29 11:06:19 AM UTC 24	Aug 29 11:06:21 AM UTC 24	14104015 ps
T804	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.1776032161	Aug 29 11:06:19 AM UTC 24	Aug 29 11:06:21 AM UTC 24	59495929 ps
T113	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.3421213296	Aug 29 11:06:18 AM UTC 24	Aug 29 11:06:21 AM UTC 24	28129558 ps
T805	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.3888587029	Aug 29 11:06:17 AM UTC 24	Aug 29 11:06:21 AM UTC 24	110243640 ps
T806	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3535781702	Aug 29 11:06:18 AM UTC 24	Aug 29 11:06:21 AM UTC 24	124853910 ps
T807	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2568167343	Aug 29 11:06:19 AM UTC 24	Aug 29 11:06:21 AM UTC 24	44512351 ps
T808	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1462743843	Aug 29 11:06:19 AM UTC 24	Aug 29 11:06:22 AM UTC 24	96586387 ps
T809	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.4153473377	Aug 29 11:06:19 AM UTC 24	Aug 29 11:06:22 AM UTC 24	33120101 ps
T810	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.1232094974	Aug 29 11:06:20 AM UTC 24	Aug 29 11:06:25 AM UTC 24	55368655 ps
T811	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.3792712043	Aug 29 11:06:18 AM UTC 24	Aug 29 11:06:22 AM UTC 24	54767539 ps
T812	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.3721410765	Aug 29 11:06:17 AM UTC 24	Aug 29 11:06:22 AM UTC 24	235027705 ps
T813	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.3996715899	Aug 29 11:06:20 AM UTC 24	Aug 29 11:06:23 AM UTC 24	50795099 ps
T814	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.3852920825	Aug 29 11:06:20 AM UTC 24	Aug 29 11:06:23 AM UTC 24	17780557 ps
T815	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.2450016282	Aug 29 11:06:20 AM UTC 24	Aug 29 11:06:23 AM UTC 24	86834338 ps
T816	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2355111720	Aug 29 11:06:20 AM UTC 24	Aug 29 11:06:23 AM UTC 24	34413712 ps
T817	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.2602803002	Aug 29 11:06:20 AM UTC 24	Aug 29 11:06:23 AM UTC 24	43735753 ps
T818	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.3399876197	Aug 29 11:06:20 AM UTC 24	Aug 29 11:06:23 AM UTC 24	14992838 ps
T819	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.2000458637	Aug 29 11:06:19 AM UTC 24	Aug 29 11:06:23 AM UTC 24	586814442 ps
T820	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.792653624	Aug 29 11:06:22 AM UTC 24	Aug 29 11:06:24 AM UTC 24	15529929 ps
T821	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.3565392292	Aug 29 11:06:22 AM UTC 24	Aug 29 11:06:24 AM UTC 24	66601039 ps
T822	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.3813801979	Aug 29 11:06:20 AM UTC 24	Aug 29 11:06:24 AM UTC 24	158058069 ps
T823	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.3113032353	Aug 29 11:06:20 AM UTC 24	Aug 29 11:06:24 AM UTC 24	151387003 ps
T824	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.3211021769	Aug 29 11:06:23 AM UTC 24	Aug 29 11:06:25 AM UTC 24	103617921 ps
T825	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.3821181696	Aug 29 11:06:22 AM UTC 24	Aug 29 11:06:24 AM UTC 24	15190370 ps
T826	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1477719962	Aug 29 11:06:20 AM UTC 24	Aug 29 11:06:24 AM UTC 24	286753533 ps
T827	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.3128731027	Aug 29 11:06:20 AM UTC 24	Aug 29 11:06:24 AM UTC 24	239593044 ps
T183	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.944995233	Aug 29 11:06:19 AM UTC 24	Aug 29 11:06:24 AM UTC 24	121455847 ps
T828	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.4090854790	Aug 29 11:06:20 AM UTC 24	Aug 29 11:06:24 AM UTC 24	223028053 ps
T829	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.3216266633	Aug 29 11:06:22 AM UTC 24	Aug 29 11:06:24 AM UTC 24	19726850 ps
T830	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.3935155491	Aug 29 11:06:22 AM UTC 24	Aug 29 11:06:24 AM UTC 24	73897948 ps
T831	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.1944824882	Aug 29 11:06:23 AM UTC 24	Aug 29 11:06:25 AM UTC 24	14687651 ps
T832	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.4274423970	Aug 29 11:06:20 AM UTC 24	Aug 29 11:06:24 AM UTC 24	154498219 ps
T833	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.2223733058	Aug 29 11:06:04 AM UTC 24	Aug 29 11:06:24 AM UTC 24	13723913826 ps
T834	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.1143728648	Aug 29 11:06:20 AM UTC 24	Aug 29 11:06:25 AM UTC 24	295973234 ps
T835	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1692277322	Aug 29 11:06:22 AM UTC 24	Aug 29 11:06:25 AM UTC 24	272440881 ps
T836	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3965230083	Aug 29 11:06:22 AM UTC 24	Aug 29 11:06:25 AM UTC 24	219888000 ps
T837	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.886939700	Aug 29 11:06:20 AM UTC 24	Aug 29 11:06:25 AM UTC 24	423005016 ps
T838	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.2716478308	Aug 29 11:06:23 AM UTC 24	Aug 29 11:06:25 AM UTC 24	37212777 ps
T839	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.4046294099	Aug 29 11:06:23 AM UTC 24	Aug 29 11:06:25 AM UTC 24	31032003 ps
T840	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.3281777683	Aug 29 11:06:20 AM UTC 24	Aug 29 11:06:26 AM UTC 24	145324972 ps
T841	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.1894959452	Aug 29 11:06:20 AM UTC 24	Aug 29 11:06:26 AM UTC 24	101944234 ps
T842	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.470419054	Aug 29 11:06:23 AM UTC 24	Aug 29 11:06:26 AM UTC 24	78073260 ps
T843	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.3279350321	Aug 29 11:06:21 AM UTC 24	Aug 29 11:06:26 AM UTC 24	418534035 ps
T844	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.659345698	Aug 29 11:06:23 AM UTC 24	Aug 29 11:06:26 AM UTC 24	57443906 ps
T845	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.1291360159	Aug 29 11:06:23 AM UTC 24	Aug 29 11:06:26 AM UTC 24	32259939 ps
T846	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.3921289503	Aug 29 11:06:24 AM UTC 24	Aug 29 11:06:26 AM UTC 24	44462245 ps
T847	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.2130302287	Aug 29 11:06:24 AM UTC 24	Aug 29 11:06:27 AM UTC 24	15621036 ps
T848	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.1972152972	Aug 29 11:06:25 AM UTC 24	Aug 29 11:06:27 AM UTC 24	97114474 ps
T849	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.2622000420	Aug 29 11:06:24 AM UTC 24	Aug 29 11:06:27 AM UTC 24	12833778 ps
T850	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.2490527057	Aug 29 11:06:24 AM UTC 24	Aug 29 11:06:27 AM UTC 24	35507232 ps
T851	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.30336089	Aug 29 11:06:25 AM UTC 24	Aug 29 11:06:27 AM UTC 24	30204735 ps
T852	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.3524284237	Aug 29 11:06:25 AM UTC 24	Aug 29 11:06:27 AM UTC 24	12328709 ps
T853	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.4108468114	Aug 29 11:06:25 AM UTC 24	Aug 29 11:06:27 AM UTC 24	32291099 ps
T854	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.2573222791	Aug 29 11:06:25 AM UTC 24	Aug 29 11:06:27 AM UTC 24	29442415 ps
T855	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.3519273019	Aug 29 11:06:25 AM UTC 24	Aug 29 11:06:27 AM UTC 24	24850477 ps
T856	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.14091672	Aug 29 11:06:25 AM UTC 24	Aug 29 11:06:27 AM UTC 24	162675627 ps
T857	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.2061459441	Aug 29 11:06:25 AM UTC 24	Aug 29 11:06:27 AM UTC 24	36649871 ps
T187	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.1418064216	Aug 29 11:06:22 AM UTC 24	Aug 29 11:06:27 AM UTC 24	649276117 ps
T858	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.3253774709	Aug 29 11:06:25 AM UTC 24	Aug 29 11:06:27 AM UTC 24	42677825 ps
T859	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2282299225	Aug 29 11:06:24 AM UTC 24	Aug 29 11:06:28 AM UTC 24	155842330 ps
T860	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.3931662668	Aug 29 11:06:26 AM UTC 24	Aug 29 11:06:28 AM UTC 24	109351968 ps
T861	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.3967210008	Aug 29 11:06:24 AM UTC 24	Aug 29 11:06:28 AM UTC 24	97498367 ps
T862	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.164316255	Aug 29 11:06:26 AM UTC 24	Aug 29 11:06:28 AM UTC 24	34967109 ps
T863	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.301299434	Aug 29 11:06:26 AM UTC 24	Aug 29 11:06:28 AM UTC 24	39184579 ps
T188	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.441216527	Aug 29 11:06:22 AM UTC 24	Aug 29 11:06:28 AM UTC 24	1114256640 ps
T864	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.2101626930	Aug 29 11:06:26 AM UTC 24	Aug 29 11:06:28 AM UTC 24	28805984 ps
T865	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.1626438336	Aug 29 11:06:26 AM UTC 24	Aug 29 11:06:28 AM UTC 24	13146279 ps
T866	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.44500504	Aug 29 11:06:26 AM UTC 24	Aug 29 11:06:28 AM UTC 24	24929244 ps
T867	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.1207044737	Aug 29 11:06:26 AM UTC 24	Aug 29 11:06:28 AM UTC 24	17118326 ps
T868	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.4292127074	Aug 29 11:06:26 AM UTC 24	Aug 29 11:06:28 AM UTC 24	18405787 ps
T869	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.583720195	Aug 29 11:06:07 AM UTC 24	Aug 29 11:06:28 AM UTC 24	3000484822 ps
T870	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.4162198542	Aug 29 11:06:26 AM UTC 24	Aug 29 11:06:29 AM UTC 24	23055367 ps
T871	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.2047269744	Aug 29 11:06:26 AM UTC 24	Aug 29 11:06:29 AM UTC 24	26439654 ps
T872	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.3729718989	Aug 29 11:06:26 AM UTC 24	Aug 29 11:06:29 AM UTC 24	44783206 ps
T873	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.3280737986	Aug 29 11:06:26 AM UTC 24	Aug 29 11:06:29 AM UTC 24	35922023 ps
T874	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.1914517689	Aug 29 11:06:26 AM UTC 24	Aug 29 11:06:29 AM UTC 24	31106471 ps
T875	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.3467692715	Aug 29 11:06:26 AM UTC 24	Aug 29 11:06:29 AM UTC 24	34070022 ps
T876	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.3995270488	Aug 29 11:06:26 AM UTC 24	Aug 29 11:06:29 AM UTC 24	25620054 ps
T877	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.3598005720	Aug 29 11:06:26 AM UTC 24	Aug 29 11:06:29 AM UTC 24	34600325 ps
T878	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.1651465505	Aug 29 11:06:26 AM UTC 24	Aug 29 11:06:29 AM UTC 24	40080251 ps
T181	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.4019670590	Aug 29 11:06:23 AM UTC 24	Aug 29 11:06:29 AM UTC 24	595817669 ps

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac.141444525
Short name	T1
Test name
Test status
Simulation time	482078003 ps
CPU time	2.8 seconds
Started	Aug 29 11:43:52 AM UTC 24
Finished	Aug 29 11:43:56 AM UTC 24
Peak memory	230700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141444525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_ve ctors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac.141444525 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_test_vectors_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_ready_error.2812731665
Short name	T21
Test name
Test status
Simulation time	23485761107 ps
CPU time	48.95 seconds
Started	Aug 29 11:43:54 AM UTC 24
Finished	Aug 29 11:44:45 AM UTC 24
Peak memory	230768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812731665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.2812731665 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_entropy_ready_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.3195543326
Short name	T104
Test name
Test status
Simulation time	130879599 ps
CPU time	1.95 seconds
Started	Aug 29 11:05:53 AM UTC 24
Finished	Aug 29 11:05:56 AM UTC 24
Peak memory	228588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195543326 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors_with_csr_rw. 3195543326 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/0.kmac_sec_cm.3479119060
Short name	T6
Test name
Test status
Simulation time	1552803926 ps
CPU time	36.87 seconds
Started	Aug 29 11:43:56 AM UTC 24
Finished	Aug 29 11:44:34 AM UTC 24
Peak memory	275576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479119060 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.3479119060 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_refresh.2102701697
Short name	T26
Test name
Test status
Simulation time	8956586400 ps
CPU time	87.98 seconds
Started	Aug 29 11:44:03 AM UTC 24
Finished	Aug 29 11:45:33 AM UTC 24
Peak memory	286816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102701697 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.2102701697 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.3565805434
Short name	T124
Test name
Test status
Simulation time	73405794 ps
CPU time	2.54 seconds
Started	Aug 29 11:06:11 AM UTC 24
Finished	Aug 29 11:06:15 AM UTC 24
Peak memory	229632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565805434 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.3565805434 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/7.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/1.kmac_key_error.553867537
Short name	T17
Test name
Test status
Simulation time	5487160080 ps
CPU time	5.38 seconds
Started	Aug 29 11:44:08 AM UTC 24
Finished	Aug 29 11:44:15 AM UTC 24
Peak memory	230436 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553867537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.553867537 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/2.kmac_lc_escalation.1625184
Short name	T9
Test name
Test status
Simulation time	39081379 ps
CPU time	2.06 seconds
Started	Aug 29 11:44:51 AM UTC 24
Finished	Aug 29 11:44:55 AM UTC 24
Peak memory	230436 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.1625184 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/0.kmac_smoke.4177438582
Short name	T51
Test name
Test status
Simulation time	8829951914 ps
CPU time	50.78 seconds
Started	Aug 29 11:43:51 AM UTC 24
Finished	Aug 29 11:44:43 AM UTC 24
Peak memory	230896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177438582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.4177438582 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/4.kmac_error.1577491029
Short name	T30
Test name
Test status
Simulation time	12810237748 ps
CPU time	416 seconds
Started	Aug 29 11:46:40 AM UTC 24
Finished	Aug 29 11:53:42 AM UTC 24
Peak memory	579420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577491029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.1577491029 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/1.kmac_lc_escalation.2505275502
Short name	T5
Test name
Test status
Simulation time	38749697 ps
CPU time	1.85 seconds
Started	Aug 29 11:44:11 AM UTC 24
Finished	Aug 29 11:44:14 AM UTC 24
Peak memory	229724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505275502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.2505275502 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/14.kmac_lc_escalation.371741173
Short name	T66
Test name
Test status
Simulation time	319197949 ps
CPU time	18.18 seconds
Started	Aug 29 11:53:57 AM UTC 24
Finished	Aug 29 11:54:17 AM UTC 24
Peak memory	244968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371741173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.371741173 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/14.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.3528860770
Short name	T175
Test name
Test status
Simulation time	22817954 ps
CPU time	1.18 seconds
Started	Aug 29 11:06:09 AM UTC 24
Finished	Aug 29 11:06:11 AM UTC 24
Peak memory	218920 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528860770 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.3528860770 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/5.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_intg_err.650297684
Short name	T127
Test name
Test status
Simulation time	960233092 ps
CPU time	5.32 seconds
Started	Aug 29 11:06:02 AM UTC 24
Finished	Aug 29 11:06:08 AM UTC 24
Peak memory	219264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650297684 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.650297684 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/0.kmac_mubi.2038837883
Short name	T37
Test name
Test status
Simulation time	31695952635 ps
CPU time	251.36 seconds
Started	Aug 29 11:43:53 AM UTC 24
Finished	Aug 29 11:48:08 AM UTC 24
Peak memory	438424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038837883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.2038837883 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/7.kmac_burst_write.1753195208
Short name	T54
Test name
Test status
Simulation time	2726138851 ps
CPU time	122.85 seconds
Started	Aug 29 11:48:36 AM UTC 24
Finished	Aug 29 11:50:42 AM UTC 24
Peak memory	235364 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753195208 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.1753195208 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/7.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/45.kmac_lc_escalation.3689361367
Short name	T69
Test name
Test status
Simulation time	287431668 ps
CPU time	2.03 seconds
Started	Aug 29 12:24:12 PM UTC 24
Finished	Aug 29 12:24:15 PM UTC 24
Peak memory	232420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689361367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.3689361367 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/45.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_224.1626745992
Short name	T79
Test name
Test status
Simulation time	618039624 ps
CPU time	40.36 seconds
Started	Aug 29 11:43:57 AM UTC 24
Finished	Aug 29 11:44:39 AM UTC 24
Peak memory	232600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626745992 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.1626745992 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_224/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors.2277100249
Short name	T111
Test name
Test status
Simulation time	240352993 ps
CPU time	1.69 seconds
Started	Aug 29 11:06:06 AM UTC 24
Finished	Aug 29 11:06:08 AM UTC 24
Peak memory	228840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277100249 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors.2277100249 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/0.kmac_alert_test.2863635560
Short name	T19
Test name
Test status
Simulation time	12594879 ps
CPU time	1.14 seconds
Started	Aug 29 11:43:56 AM UTC 24
Finished	Aug 29 11:43:58 AM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863635560 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.2863635560 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_partial_access.3291119021
Short name	T145
Test name
Test status
Simulation time	20155435 ps
CPU time	1.56 seconds
Started	Aug 29 11:05:54 AM UTC 24
Finished	Aug 29 11:05:57 AM UTC 24
Peak memory	228860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291119021 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial_access.3291119021 +enable_mas king=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/21.kmac_lc_escalation.938204886
Short name	T7
Test name
Test status
Simulation time	89420732 ps
CPU time	1.73 seconds
Started	Aug 29 12:00:38 PM UTC 24
Finished	Aug 29 12:00:40 PM UTC 24
Peak memory	229780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938204886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.938204886 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/21.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.1919385489
Short name	T772
Test name
Test status
Simulation time	11158546 ps
CPU time	0.85 seconds
Started	Aug 29 11:06:14 AM UTC 24
Finished	Aug 29 11:06:16 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919385489 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.1919385489 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/10.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.4019670590
Short name	T181
Test name
Test status
Simulation time	595817669 ps
CPU time	4.78 seconds
Started	Aug 29 11:06:23 AM UTC 24
Finished	Aug 29 11:06:29 AM UTC 24
Peak memory	219336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019670590 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.4019670590 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/19.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_errors.530842105
Short name	T129
Test name
Test status
Simulation time	123686527 ps
CPU time	3.4 seconds
Started	Aug 29 11:05:59 AM UTC 24
Finished	Aug 29 11:06:04 AM UTC 24
Peak memory	229640 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530842105 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.530842105 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2568167343
Short name	T807
Test name
Test status
Simulation time	44512351 ps
CPU time	1.13 seconds
Started	Aug 29 11:06:19 AM UTC 24
Finished	Aug 29 11:06:21 AM UTC 24
Peak memory	228852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568167343 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors.2568167343 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/15.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/1.kmac_smoke.2245728289
Short name	T121
Test name
Test status
Simulation time	5233600575 ps
CPU time	55.49 seconds
Started	Aug 29 11:43:56 AM UTC 24
Finished	Aug 29 11:44:53 AM UTC 24
Peak memory	234712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245728289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.2245728289 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_intg_err.2041611195
Short name	T123
Test name
Test status
Simulation time	199169761 ps
CPU time	2.74 seconds
Started	Aug 29 11:05:59 AM UTC 24
Finished	Aug 29 11:06:03 AM UTC 24
Peak memory	229504 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041611195 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.2041611195 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_ready_error.2937637877
Short name	T24
Test name
Test status
Simulation time	3864614220 ps
CPU time	53.73 seconds
Started	Aug 29 11:44:11 AM UTC 24
Finished	Aug 29 11:45:06 AM UTC 24
Peak memory	230652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937637877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.2937637877 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_entropy_ready_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/19.kmac_stress_all.3127029559
Short name	T372
Test name
Test status
Simulation time	1919199675 ps
CPU time	138.88 seconds
Started	Aug 29 11:58:31 AM UTC 24
Finished	Aug 29 12:00:52 PM UTC 24
Peak memory	299156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127029559 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.3127029559 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/19.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.2908753795
Short name	T137
Test name
Test status
Simulation time	279182656 ps
CPU time	3.77 seconds
Started	Aug 29 11:06:14 AM UTC 24
Finished	Aug 29 11:06:19 AM UTC 24
Peak memory	229756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908753795 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.2908753795 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/10.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_hw_reset.2267189866
Short name	T105
Test name
Test status
Simulation time	43174483 ps
CPU time	1.04 seconds
Started	Aug 29 11:05:57 AM UTC 24
Finished	Aug 29 11:05:59 AM UTC 24
Peak memory	218920 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267189866 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.2267189866 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_errors.1707741539
Short name	T62
Test name
Test status
Simulation time	153421848 ps
CPU time	2.59 seconds
Started	Aug 29 11:05:56 AM UTC 24
Finished	Aug 29 11:05:59 AM UTC 24
Peak memory	229672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707741539 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.1707741539 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/0.kmac_edn_timeout_error.2853106219
Short name	T22
Test name
Test status
Simulation time	5913425553 ps
CPU time	55.27 seconds
Started	Aug 29 11:43:54 AM UTC 24
Finished	Aug 29 11:44:51 AM UTC 24
Peak memory	234740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853106219 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.2853106219 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/13.kmac_burst_write.2143177771
Short name	T56
Test name
Test status
Simulation time	1509952426 ps
CPU time	141.12 seconds
Started	Aug 29 11:52:27 AM UTC 24
Finished	Aug 29 11:54:50 AM UTC 24
Peak memory	235220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143177771 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.2143177771 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/13.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/0.kmac_app.2167927128
Short name	T35
Test name
Test status
Simulation time	22944268820 ps
CPU time	222.77 seconds
Started	Aug 29 11:43:53 AM UTC 24
Finished	Aug 29 11:47:39 AM UTC 24
Peak memory	444316 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167927128 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.2167927128 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_aliasing.3952337647
Short name	T736
Test name
Test status
Simulation time	136724372 ps
CPU time	7.56 seconds
Started	Aug 29 11:05:57 AM UTC 24
Finished	Aug 29 11:06:05 AM UTC 24
Peak memory	229568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952337647 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.3952337647 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.333283253
Short name	T777
Test name
Test status
Simulation time	1104502055 ps
CPU time	18.73 seconds
Started	Aug 29 11:05:57 AM UTC 24
Finished	Aug 29 11:06:17 AM UTC 24
Peak memory	219264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333283253 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.333283253 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.729680009
Short name	T63
Test name
Test status
Simulation time	39553889 ps
CPU time	2.39 seconds
Started	Aug 29 11:05:58 AM UTC 24
Finished	Aug 29 11:06:01 AM UTC 24
Peak memory	231620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=729680009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_m em_rw_with_rand_reset.729680009 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_rw.2352741568
Short name	T190
Test name
Test status
Simulation time	25492712 ps
CPU time	1.11 seconds
Started	Aug 29 11:05:57 AM UTC 24
Finished	Aug 29 11:05:59 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352741568 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.2352741568 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_intr_test.4168328272
Short name	T128
Test name
Test status
Simulation time	25174431 ps
CPU time	0.9 seconds
Started	Aug 29 11:05:56 AM UTC 24
Finished	Aug 29 11:05:58 AM UTC 24
Peak memory	218920 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168328272 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.4168328272 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_walk.2382338862
Short name	T729
Test name
Test status
Simulation time	28302262 ps
CPU time	0.8 seconds
Started	Aug 29 11:05:53 AM UTC 24
Finished	Aug 29 11:05:55 AM UTC 24
Peak memory	218584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382338862 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.2382338862 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_same_csr_outstanding.1230752336
Short name	T160
Test name
Test status
Simulation time	62723301 ps
CPU time	1.97 seconds
Started	Aug 29 11:05:57 AM UTC 24
Finished	Aug 29 11:06:00 AM UTC 24
Peak memory	228856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230752336 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_outstanding.1230752336 +enable _masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors.753796031
Short name	T103
Test name
Test status
Simulation time	53261607 ps
CPU time	1.67 seconds
Started	Aug 29 11:05:53 AM UTC 24
Finished	Aug 29 11:05:56 AM UTC 24
Peak memory	228792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753796031 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors.753796031 +enable_masking =0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_intg_err.2897234840
Short name	T61
Test name
Test status
Simulation time	120455121 ps
CPU time	2.52 seconds
Started	Aug 29 11:05:56 AM UTC 24
Finished	Aug 29 11:05:59 AM UTC 24
Peak memory	229564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897234840 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.2897234840 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_aliasing.4042180947
Short name	T748
Test name
Test status
Simulation time	381541346 ps
CPU time	8.79 seconds
Started	Aug 29 11:06:00 AM UTC 24
Finished	Aug 29 11:06:10 AM UTC 24
Peak memory	229508 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042180947 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.4042180947 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.2245780384
Short name	T750
Test name
Test status
Simulation time	149083128 ps
CPU time	9.15 seconds
Started	Aug 29 11:06:00 AM UTC 24
Finished	Aug 29 11:06:11 AM UTC 24
Peak memory	219348 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245780384 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.2245780384 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_hw_reset.2356986966
Short name	T733
Test name
Test status
Simulation time	112082909 ps
CPU time	1.24 seconds
Started	Aug 29 11:06:00 AM UTC 24
Finished	Aug 29 11:06:03 AM UTC 24
Peak memory	218880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356986966 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.2356986966 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.2359388547
Short name	T141
Test name
Test status
Simulation time	218315403 ps
CPU time	1.81 seconds
Started	Aug 29 11:06:01 AM UTC 24
Finished	Aug 29 11:06:03 AM UTC 24
Peak memory	228856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2359388547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_ mem_rw_with_rand_reset.2359388547 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_rw.4118458735
Short name	T161
Test name
Test status
Simulation time	53027670 ps
CPU time	1.33 seconds
Started	Aug 29 11:06:00 AM UTC 24
Finished	Aug 29 11:06:03 AM UTC 24
Peak memory	228852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118458735 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.4118458735 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_intr_test.695291137
Short name	T132
Test name
Test status
Simulation time	15956043 ps
CPU time	0.85 seconds
Started	Aug 29 11:05:59 AM UTC 24
Finished	Aug 29 11:06:01 AM UTC 24
Peak memory	218924 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695291137 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.695291137 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_partial_access.961124458
Short name	T731
Test name
Test status
Simulation time	128817353 ps
CPU time	1.63 seconds
Started	Aug 29 11:05:59 AM UTC 24
Finished	Aug 29 11:06:02 AM UTC 24
Peak memory	228856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961124458 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial_access.961124458 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_walk.1773064345
Short name	T730
Test name
Test status
Simulation time	30039513 ps
CPU time	0.82 seconds
Started	Aug 29 11:05:58 AM UTC 24
Finished	Aug 29 11:06:00 AM UTC 24
Peak memory	218972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773064345 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.1773064345 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_same_csr_outstanding.1622730669
Short name	T734
Test name
Test status
Simulation time	126936245 ps
CPU time	2.09 seconds
Started	Aug 29 11:06:01 AM UTC 24
Finished	Aug 29 11:06:04 AM UTC 24
Peak memory	229568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622730669 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_outstanding.1622730669 +enable _masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors.4027353767
Short name	T106
Test name
Test status
Simulation time	186443753 ps
CPU time	1.28 seconds
Started	Aug 29 11:05:58 AM UTC 24
Finished	Aug 29 11:06:00 AM UTC 24
Peak memory	228596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027353767 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors.4027353767 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.3679959236
Short name	T110
Test name
Test status
Simulation time	454309533 ps
CPU time	2.86 seconds
Started	Aug 29 11:05:58 AM UTC 24
Finished	Aug 29 11:06:02 AM UTC 24
Peak memory	229972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679959236 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors_with_csr_rw. 3679959236 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1927274728
Short name	T783
Test name
Test status
Simulation time	89558741 ps
CPU time	1.59 seconds
Started	Aug 29 11:06:15 AM UTC 24
Finished	Aug 29 11:06:18 AM UTC 24
Peak memory	228860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1927274728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr _mem_rw_with_rand_reset.1927274728 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.555684479
Short name	T776
Test name
Test status
Simulation time	22175520 ps
CPU time	0.97 seconds
Started	Aug 29 11:06:14 AM UTC 24
Finished	Aug 29 11:06:16 AM UTC 24
Peak memory	218924 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555684479 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.555684479 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/10.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.245867366
Short name	T788
Test name
Test status
Simulation time	38853993 ps
CPU time	2.3 seconds
Started	Aug 29 11:06:15 AM UTC 24
Finished	Aug 29 11:06:19 AM UTC 24
Peak memory	229552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245867366 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr_outstanding.245867366 +enable_ masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/10.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.1802818152
Short name	T114
Test name
Test status
Simulation time	29377377 ps
CPU time	1.29 seconds
Started	Aug 29 11:06:14 AM UTC 24
Finished	Aug 29 11:06:16 AM UTC 24
Peak memory	228788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802818152 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors.1802818152 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.1356893656
Short name	T778
Test name
Test status
Simulation time	70172133 ps
CPU time	1.63 seconds
Started	Aug 29 11:06:14 AM UTC 24
Finished	Aug 29 11:06:17 AM UTC 24
Peak memory	228848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356893656 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors_with_csr_rw .1356893656 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.1864124139
Short name	T186
Test name
Test status
Simulation time	211227123 ps
CPU time	4.08 seconds
Started	Aug 29 11:06:14 AM UTC 24
Finished	Aug 29 11:06:19 AM UTC 24
Peak memory	229700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864124139 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.1864124139 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/10.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.2092138866
Short name	T786
Test name
Test status
Simulation time	118136998 ps
CPU time	1.55 seconds
Started	Aug 29 11:06:16 AM UTC 24
Finished	Aug 29 11:06:18 AM UTC 24
Peak memory	234860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2092138866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr _mem_rw_with_rand_reset.2092138866 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.4048020076
Short name	T782
Test name
Test status
Simulation time	32320843 ps
CPU time	1.22 seconds
Started	Aug 29 11:06:16 AM UTC 24
Finished	Aug 29 11:06:18 AM UTC 24
Peak memory	218876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048020076 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.4048020076 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/11.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.3265828902
Short name	T781
Test name
Test status
Simulation time	43900075 ps
CPU time	0.94 seconds
Started	Aug 29 11:06:16 AM UTC 24
Finished	Aug 29 11:06:18 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265828902 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.3265828902 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/11.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.2306295888
Short name	T795
Test name
Test status
Simulation time	329778148 ps
CPU time	2.64 seconds
Started	Aug 29 11:06:16 AM UTC 24
Finished	Aug 29 11:06:19 AM UTC 24
Peak memory	229512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306295888 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr_outstanding.2306295888 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/11.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.4113371028
Short name	T784
Test name
Test status
Simulation time	150900883 ps
CPU time	1.52 seconds
Started	Aug 29 11:06:16 AM UTC 24
Finished	Aug 29 11:06:18 AM UTC 24
Peak memory	228792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113371028 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors.4113371028 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/11.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.4224238847
Short name	T787
Test name
Test status
Simulation time	101260002 ps
CPU time	1.78 seconds
Started	Aug 29 11:06:16 AM UTC 24
Finished	Aug 29 11:06:18 AM UTC 24
Peak memory	228792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224238847 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors_with_csr_rw .4224238847 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.3957617385
Short name	T140
Test name
Test status
Simulation time	32838928 ps
CPU time	2.08 seconds
Started	Aug 29 11:06:16 AM UTC 24
Finished	Aug 29 11:06:19 AM UTC 24
Peak memory	229688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957617385 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.3957617385 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/11.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.3930616295
Short name	T189
Test name
Test status
Simulation time	471287962 ps
CPU time	2.55 seconds
Started	Aug 29 11:06:16 AM UTC 24
Finished	Aug 29 11:06:19 AM UTC 24
Peak memory	219400 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930616295 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.3930616295 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/11.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1158628247
Short name	T800
Test name
Test status
Simulation time	90437192 ps
CPU time	1.97 seconds
Started	Aug 29 11:06:17 AM UTC 24
Finished	Aug 29 11:06:20 AM UTC 24
Peak memory	228856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1158628247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr _mem_rw_with_rand_reset.1158628247 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.2296161075
Short name	T793
Test name
Test status
Simulation time	35915754 ps
CPU time	1.29 seconds
Started	Aug 29 11:06:17 AM UTC 24
Finished	Aug 29 11:06:19 AM UTC 24
Peak memory	228856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296161075 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.2296161075 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/12.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.274850986
Short name	T791
Test name
Test status
Simulation time	53114115 ps
CPU time	0.96 seconds
Started	Aug 29 11:06:17 AM UTC 24
Finished	Aug 29 11:06:19 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274850986 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.274850986 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/12.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3572693009
Short name	T799
Test name
Test status
Simulation time	210040552 ps
CPU time	2.02 seconds
Started	Aug 29 11:06:17 AM UTC 24
Finished	Aug 29 11:06:20 AM UTC 24
Peak memory	229640 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572693009 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr_outstanding.3572693009 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/12.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.510028013
Short name	T785
Test name
Test status
Simulation time	19218321 ps
CPU time	1.43 seconds
Started	Aug 29 11:06:16 AM UTC 24
Finished	Aug 29 11:06:18 AM UTC 24
Peak memory	228852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510028013 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors.510028013 +enable_maskin g=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/12.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.2631559370
Short name	T789
Test name
Test status
Simulation time	254186617 ps
CPU time	1.86 seconds
Started	Aug 29 11:06:16 AM UTC 24
Finished	Aug 29 11:06:19 AM UTC 24
Peak memory	228792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631559370 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors_with_csr_rw .2631559370 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.3721410765
Short name	T812
Test name
Test status
Simulation time	235027705 ps
CPU time	4.16 seconds
Started	Aug 29 11:06:17 AM UTC 24
Finished	Aug 29 11:06:22 AM UTC 24
Peak memory	229632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721410765 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.3721410765 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/12.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.677559998
Short name	T802
Test name
Test status
Simulation time	339441273 ps
CPU time	2.71 seconds
Started	Aug 29 11:06:17 AM UTC 24
Finished	Aug 29 11:06:21 AM UTC 24
Peak memory	229560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677559998 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.677559998 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/12.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3535781702
Short name	T806
Test name
Test status
Simulation time	124853910 ps
CPU time	1.45 seconds
Started	Aug 29 11:06:18 AM UTC 24
Finished	Aug 29 11:06:21 AM UTC 24
Peak memory	228860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3535781702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr _mem_rw_with_rand_reset.3535781702 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.3399762360
Short name	T794
Test name
Test status
Simulation time	53474173 ps
CPU time	1.07 seconds
Started	Aug 29 11:06:17 AM UTC 24
Finished	Aug 29 11:06:19 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399762360 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.3399762360 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/13.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.58641972
Short name	T792
Test name
Test status
Simulation time	39051423 ps
CPU time	0.93 seconds
Started	Aug 29 11:06:17 AM UTC 24
Finished	Aug 29 11:06:19 AM UTC 24
Peak memory	218976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58641972 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.58641972 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/13.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3851186582
Short name	T796
Test name
Test status
Simulation time	85112511 ps
CPU time	1.42 seconds
Started	Aug 29 11:06:17 AM UTC 24
Finished	Aug 29 11:06:20 AM UTC 24
Peak memory	228800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851186582 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr_outstanding.3851186582 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/13.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3693982010
Short name	T109
Test name
Test status
Simulation time	70941435 ps
CPU time	1.21 seconds
Started	Aug 29 11:06:17 AM UTC 24
Finished	Aug 29 11:06:19 AM UTC 24
Peak memory	228596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693982010 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors.3693982010 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/13.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2708902673
Short name	T797
Test name
Test status
Simulation time	25763446 ps
CPU time	1.66 seconds
Started	Aug 29 11:06:17 AM UTC 24
Finished	Aug 29 11:06:20 AM UTC 24
Peak memory	228788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708902673 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors_with_csr_rw .2708902673 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.811180201
Short name	T801
Test name
Test status
Simulation time	78034312 ps
CPU time	2.28 seconds
Started	Aug 29 11:06:17 AM UTC 24
Finished	Aug 29 11:06:21 AM UTC 24
Peak memory	229696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811180201 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.811180201 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/13.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.3888587029
Short name	T805
Test name
Test status
Simulation time	110243640 ps
CPU time	2.59 seconds
Started	Aug 29 11:06:17 AM UTC 24
Finished	Aug 29 11:06:21 AM UTC 24
Peak memory	219248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888587029 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.3888587029 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/13.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.4153473377
Short name	T809
Test name
Test status
Simulation time	33120101 ps
CPU time	2.1 seconds
Started	Aug 29 11:06:19 AM UTC 24
Finished	Aug 29 11:06:22 AM UTC 24
Peak memory	231620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4153473377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr _mem_rw_with_rand_reset.4153473377 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.1776032161
Short name	T804
Test name
Test status
Simulation time	59495929 ps
CPU time	0.96 seconds
Started	Aug 29 11:06:19 AM UTC 24
Finished	Aug 29 11:06:21 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776032161 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.1776032161 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/14.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.3145989791
Short name	T803
Test name
Test status
Simulation time	14104015 ps
CPU time	0.95 seconds
Started	Aug 29 11:06:19 AM UTC 24
Finished	Aug 29 11:06:21 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145989791 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.3145989791 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/14.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1462743843
Short name	T808
Test name
Test status
Simulation time	96586387 ps
CPU time	1.66 seconds
Started	Aug 29 11:06:19 AM UTC 24
Finished	Aug 29 11:06:22 AM UTC 24
Peak memory	228800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462743843 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr_outstanding.1462743843 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/14.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.3421213296
Short name	T113
Test name
Test status
Simulation time	28129558 ps
CPU time	1.21 seconds
Started	Aug 29 11:06:18 AM UTC 24
Finished	Aug 29 11:06:21 AM UTC 24
Peak memory	228728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421213296 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors.3421213296 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/14.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.3792712043
Short name	T811
Test name
Test status
Simulation time	54767539 ps
CPU time	2.49 seconds
Started	Aug 29 11:06:18 AM UTC 24
Finished	Aug 29 11:06:22 AM UTC 24
Peak memory	229976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792712043 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors_with_csr_rw .3792712043 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.2000458637
Short name	T819
Test name
Test status
Simulation time	586814442 ps
CPU time	3.66 seconds
Started	Aug 29 11:06:19 AM UTC 24
Finished	Aug 29 11:06:23 AM UTC 24
Peak memory	229632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000458637 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.2000458637 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/14.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.944995233
Short name	T183
Test name
Test status
Simulation time	121455847 ps
CPU time	4.07 seconds
Started	Aug 29 11:06:19 AM UTC 24
Finished	Aug 29 11:06:24 AM UTC 24
Peak memory	231608 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944995233 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.944995233 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/14.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.4274423970
Short name	T832
Test name
Test status
Simulation time	154498219 ps
CPU time	2.48 seconds
Started	Aug 29 11:06:20 AM UTC 24
Finished	Aug 29 11:06:24 AM UTC 24
Peak memory	231684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4274423970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr _mem_rw_with_rand_reset.4274423970 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.3852920825
Short name	T814
Test name
Test status
Simulation time	17780557 ps
CPU time	0.98 seconds
Started	Aug 29 11:06:20 AM UTC 24
Finished	Aug 29 11:06:23 AM UTC 24
Peak memory	218868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852920825 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.3852920825 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/15.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.3996715899
Short name	T813
Test name
Test status
Simulation time	50795099 ps
CPU time	0.83 seconds
Started	Aug 29 11:06:20 AM UTC 24
Finished	Aug 29 11:06:23 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996715899 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.3996715899 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/15.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.3813801979
Short name	T822
Test name
Test status
Simulation time	158058069 ps
CPU time	2.47 seconds
Started	Aug 29 11:06:20 AM UTC 24
Finished	Aug 29 11:06:24 AM UTC 24
Peak memory	229488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813801979 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr_outstanding.3813801979 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/15.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.3128731027
Short name	T827
Test name
Test status
Simulation time	239593044 ps
CPU time	2.11 seconds
Started	Aug 29 11:06:20 AM UTC 24
Finished	Aug 29 11:06:24 AM UTC 24
Peak memory	230040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128731027 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors_with_csr_rw .3128731027 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.3113032353
Short name	T823
Test name
Test status
Simulation time	151387003 ps
CPU time	1.88 seconds
Started	Aug 29 11:06:20 AM UTC 24
Finished	Aug 29 11:06:24 AM UTC 24
Peak memory	228856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113032353 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.3113032353 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/15.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.3281777683
Short name	T840
Test name
Test status
Simulation time	145324972 ps
CPU time	3.91 seconds
Started	Aug 29 11:06:20 AM UTC 24
Finished	Aug 29 11:06:26 AM UTC 24
Peak memory	219480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281777683 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.3281777683 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/15.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.1143728648
Short name	T834
Test name
Test status
Simulation time	295973234 ps
CPU time	2.5 seconds
Started	Aug 29 11:06:20 AM UTC 24
Finished	Aug 29 11:06:25 AM UTC 24
Peak memory	231684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1143728648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr _mem_rw_with_rand_reset.1143728648 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.2450016282
Short name	T815
Test name
Test status
Simulation time	86834338 ps
CPU time	1.04 seconds
Started	Aug 29 11:06:20 AM UTC 24
Finished	Aug 29 11:06:23 AM UTC 24
Peak memory	218872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450016282 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.2450016282 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/16.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.3399876197
Short name	T818
Test name
Test status
Simulation time	14992838 ps
CPU time	1.17 seconds
Started	Aug 29 11:06:20 AM UTC 24
Finished	Aug 29 11:06:23 AM UTC 24
Peak memory	218976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399876197 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.3399876197 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/16.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.4090854790
Short name	T828
Test name
Test status
Simulation time	223028053 ps
CPU time	1.7 seconds
Started	Aug 29 11:06:20 AM UTC 24
Finished	Aug 29 11:06:24 AM UTC 24
Peak memory	228800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090854790 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr_outstanding.4090854790 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/16.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.2602803002
Short name	T817
Test name
Test status
Simulation time	43735753 ps
CPU time	1.21 seconds
Started	Aug 29 11:06:20 AM UTC 24
Finished	Aug 29 11:06:23 AM UTC 24
Peak memory	228748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602803002 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors.2602803002 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/16.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1477719962
Short name	T826
Test name
Test status
Simulation time	286753533 ps
CPU time	1.75 seconds
Started	Aug 29 11:06:20 AM UTC 24
Finished	Aug 29 11:06:24 AM UTC 24
Peak memory	228788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477719962 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors_with_csr_rw .1477719962 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.1232094974
Short name	T810
Test name
Test status
Simulation time	55368655 ps
CPU time	3.15 seconds
Started	Aug 29 11:06:20 AM UTC 24
Finished	Aug 29 11:06:25 AM UTC 24
Peak memory	229460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232094974 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.1232094974 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/16.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.1894959452
Short name	T841
Test name
Test status
Simulation time	101944234 ps
CPU time	3.75 seconds
Started	Aug 29 11:06:20 AM UTC 24
Finished	Aug 29 11:06:26 AM UTC 24
Peak memory	231748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894959452 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.1894959452 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/16.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1692277322
Short name	T835
Test name
Test status
Simulation time	272440881 ps
CPU time	2.11 seconds
Started	Aug 29 11:06:22 AM UTC 24
Finished	Aug 29 11:06:25 AM UTC 24
Peak memory	229636 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1692277322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr _mem_rw_with_rand_reset.1692277322 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.3216266633
Short name	T829
Test name
Test status
Simulation time	19726850 ps
CPU time	1.22 seconds
Started	Aug 29 11:06:22 AM UTC 24
Finished	Aug 29 11:06:24 AM UTC 24
Peak memory	218856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216266633 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.3216266633 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/17.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.3821181696
Short name	T825
Test name
Test status
Simulation time	15190370 ps
CPU time	0.83 seconds
Started	Aug 29 11:06:22 AM UTC 24
Finished	Aug 29 11:06:24 AM UTC 24
Peak memory	218868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821181696 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.3821181696 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/17.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.1166900285
Short name	T790
Test name
Test status
Simulation time	90821099 ps
CPU time	1.56 seconds
Started	Aug 29 11:06:22 AM UTC 24
Finished	Aug 29 11:06:24 AM UTC 24
Peak memory	228800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166900285 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr_outstanding.1166900285 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/17.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2355111720
Short name	T816
Test name
Test status
Simulation time	34413712 ps
CPU time	0.91 seconds
Started	Aug 29 11:06:20 AM UTC 24
Finished	Aug 29 11:06:23 AM UTC 24
Peak memory	218676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355111720 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors.2355111720 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/17.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.886939700
Short name	T837
Test name
Test status
Simulation time	423005016 ps
CPU time	2.79 seconds
Started	Aug 29 11:06:20 AM UTC 24
Finished	Aug 29 11:06:25 AM UTC 24
Peak memory	229980 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886939700 -asse rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors_with_csr_rw. 886939700 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.3279350321
Short name	T843
Test name
Test status
Simulation time	418534035 ps
CPU time	3.08 seconds
Started	Aug 29 11:06:21 AM UTC 24
Finished	Aug 29 11:06:26 AM UTC 24
Peak memory	229692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279350321 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.3279350321 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/17.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.1418064216
Short name	T187
Test name
Test status
Simulation time	649276117 ps
CPU time	4.43 seconds
Started	Aug 29 11:06:22 AM UTC 24
Finished	Aug 29 11:06:27 AM UTC 24
Peak memory	229512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418064216 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.1418064216 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/17.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.470419054
Short name	T842
Test name
Test status
Simulation time	78073260 ps
CPU time	1.73 seconds
Started	Aug 29 11:06:23 AM UTC 24
Finished	Aug 29 11:06:26 AM UTC 24
Peak memory	228796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=470419054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_ mem_rw_with_rand_reset.470419054 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.3565392292
Short name	T821
Test name
Test status
Simulation time	66601039 ps
CPU time	1.05 seconds
Started	Aug 29 11:06:22 AM UTC 24
Finished	Aug 29 11:06:24 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565392292 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.3565392292 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/18.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.792653624
Short name	T820
Test name
Test status
Simulation time	15529929 ps
CPU time	0.87 seconds
Started	Aug 29 11:06:22 AM UTC 24
Finished	Aug 29 11:06:24 AM UTC 24
Peak memory	218856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792653624 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.792653624 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/18.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.659345698
Short name	T844
Test name
Test status
Simulation time	57443906 ps
CPU time	1.84 seconds
Started	Aug 29 11:06:23 AM UTC 24
Finished	Aug 29 11:06:26 AM UTC 24
Peak memory	228864 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659345698 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr_outstanding.659345698 +enable_ masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/18.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.3935155491
Short name	T830
Test name
Test status
Simulation time	73897948 ps
CPU time	1.17 seconds
Started	Aug 29 11:06:22 AM UTC 24
Finished	Aug 29 11:06:24 AM UTC 24
Peak memory	218636 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935155491 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors.3935155491 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/18.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3965230083
Short name	T836
Test name
Test status
Simulation time	219888000 ps
CPU time	1.97 seconds
Started	Aug 29 11:06:22 AM UTC 24
Finished	Aug 29 11:06:25 AM UTC 24
Peak memory	228788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965230083 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors_with_csr_rw .3965230083 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.1580368760
Short name	T769
Test name
Test status
Simulation time	25732863 ps
CPU time	1.5 seconds
Started	Aug 29 11:06:22 AM UTC 24
Finished	Aug 29 11:06:24 AM UTC 24
Peak memory	228648 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580368760 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.1580368760 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/18.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.441216527
Short name	T188
Test name
Test status
Simulation time	1114256640 ps
CPU time	5.13 seconds
Started	Aug 29 11:06:22 AM UTC 24
Finished	Aug 29 11:06:28 AM UTC 24
Peak memory	219320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441216527 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.441216527 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/18.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2282299225
Short name	T859
Test name
Test status
Simulation time	155842330 ps
CPU time	1.91 seconds
Started	Aug 29 11:06:24 AM UTC 24
Finished	Aug 29 11:06:28 AM UTC 24
Peak memory	230844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2282299225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr _mem_rw_with_rand_reset.2282299225 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.3211021769
Short name	T824
Test name
Test status
Simulation time	103617921 ps
CPU time	1.14 seconds
Started	Aug 29 11:06:23 AM UTC 24
Finished	Aug 29 11:06:25 AM UTC 24
Peak memory	218872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211021769 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.3211021769 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/19.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.1944824882
Short name	T831
Test name
Test status
Simulation time	14687651 ps
CPU time	0.93 seconds
Started	Aug 29 11:06:23 AM UTC 24
Finished	Aug 29 11:06:25 AM UTC 24
Peak memory	218976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944824882 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.1944824882 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/19.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.3967210008
Short name	T861
Test name
Test status
Simulation time	97498367 ps
CPU time	2.5 seconds
Started	Aug 29 11:06:24 AM UTC 24
Finished	Aug 29 11:06:28 AM UTC 24
Peak memory	229572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967210008 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr_outstanding.3967210008 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/19.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.2716478308
Short name	T838
Test name
Test status
Simulation time	37212777 ps
CPU time	1.4 seconds
Started	Aug 29 11:06:23 AM UTC 24
Finished	Aug 29 11:06:25 AM UTC 24
Peak memory	228792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716478308 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors.2716478308 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/19.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.4046294099
Short name	T839
Test name
Test status
Simulation time	31032003 ps
CPU time	1.39 seconds
Started	Aug 29 11:06:23 AM UTC 24
Finished	Aug 29 11:06:25 AM UTC 24
Peak memory	228792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046294099 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors_with_csr_rw .4046294099 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.1291360159
Short name	T845
Test name
Test status
Simulation time	32259939 ps
CPU time	1.82 seconds
Started	Aug 29 11:06:23 AM UTC 24
Finished	Aug 29 11:06:26 AM UTC 24
Peak memory	230904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291360159 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.1291360159 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/19.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.1295396731
Short name	T165
Test name
Test status
Simulation time	456289892 ps
CPU time	9.61 seconds
Started	Aug 29 11:06:03 AM UTC 24
Finished	Aug 29 11:06:14 AM UTC 24
Peak memory	219188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295396731 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.1295396731 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.1833419106
Short name	T753
Test name
Test status
Simulation time	153567989 ps
CPU time	7.6 seconds
Started	Aug 29 11:06:03 AM UTC 24
Finished	Aug 29 11:06:12 AM UTC 24
Peak memory	218636 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833419106 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.1833419106 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_hw_reset.1884800600
Short name	T162
Test name
Test status
Simulation time	108347412 ps
CPU time	1.13 seconds
Started	Aug 29 11:06:02 AM UTC 24
Finished	Aug 29 11:06:04 AM UTC 24
Peak memory	218880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884800600 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.1884800600 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.919444245
Short name	T135
Test name
Test status
Simulation time	111526573 ps
CPU time	2.29 seconds
Started	Aug 29 11:06:03 AM UTC 24
Finished	Aug 29 11:06:06 AM UTC 24
Peak memory	231684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=919444245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_m em_rw_with_rand_reset.919444245 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_rw.248157588
Short name	T735
Test name
Test status
Simulation time	21196542 ps
CPU time	0.96 seconds
Started	Aug 29 11:06:03 AM UTC 24
Finished	Aug 29 11:06:05 AM UTC 24
Peak memory	218208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248157588 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.248157588 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_intr_test.541773656
Short name	T173
Test name
Test status
Simulation time	46545635 ps
CPU time	0.87 seconds
Started	Aug 29 11:06:02 AM UTC 24
Finished	Aug 29 11:06:04 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541773656 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.541773656 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_partial_access.254170088
Short name	T146
Test name
Test status
Simulation time	22568033 ps
CPU time	1.65 seconds
Started	Aug 29 11:06:01 AM UTC 24
Finished	Aug 29 11:06:03 AM UTC 24
Peak memory	228860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254170088 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial_access.254170088 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_walk.2652837418
Short name	T732
Test name
Test status
Simulation time	32547844 ps
CPU time	0.77 seconds
Started	Aug 29 11:06:01 AM UTC 24
Finished	Aug 29 11:06:02 AM UTC 24
Peak memory	218972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652837418 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.2652837418 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_same_csr_outstanding.108810488
Short name	T737
Test name
Test status
Simulation time	350678570 ps
CPU time	1.86 seconds
Started	Aug 29 11:06:03 AM UTC 24
Finished	Aug 29 11:06:06 AM UTC 24
Peak memory	228856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108810488 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_outstanding.108810488 +enable_m asking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors.2850930723
Short name	T115
Test name
Test status
Simulation time	39134031 ps
CPU time	1.04 seconds
Started	Aug 29 11:06:01 AM UTC 24
Finished	Aug 29 11:06:03 AM UTC 24
Peak memory	218672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850930723 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors.2850930723 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.4192048137
Short name	T107
Test name
Test status
Simulation time	64680590 ps
CPU time	2.18 seconds
Started	Aug 29 11:06:01 AM UTC 24
Finished	Aug 29 11:06:04 AM UTC 24
Peak memory	230036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192048137 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors_with_csr_rw. 4192048137 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_errors.2599067018
Short name	T134
Test name
Test status
Simulation time	339177858 ps
CPU time	2.45 seconds
Started	Aug 29 11:06:02 AM UTC 24
Finished	Aug 29 11:06:05 AM UTC 24
Peak memory	229632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599067018 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.2599067018 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.2490527057
Short name	T850
Test name
Test status
Simulation time	35507232 ps
CPU time	0.95 seconds
Started	Aug 29 11:06:24 AM UTC 24
Finished	Aug 29 11:06:27 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490527057 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.2490527057 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/20.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.3921289503
Short name	T846
Test name
Test status
Simulation time	44462245 ps
CPU time	0.87 seconds
Started	Aug 29 11:06:24 AM UTC 24
Finished	Aug 29 11:06:26 AM UTC 24
Peak memory	218976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921289503 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.3921289503 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/21.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.2622000420
Short name	T849
Test name
Test status
Simulation time	12833778 ps
CPU time	0.87 seconds
Started	Aug 29 11:06:24 AM UTC 24
Finished	Aug 29 11:06:27 AM UTC 24
Peak memory	218976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622000420 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.2622000420 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/22.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.2130302287
Short name	T847
Test name
Test status
Simulation time	15621036 ps
CPU time	0.83 seconds
Started	Aug 29 11:06:24 AM UTC 24
Finished	Aug 29 11:06:27 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130302287 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.2130302287 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/23.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.1972152972
Short name	T848
Test name
Test status
Simulation time	97114474 ps
CPU time	0.8 seconds
Started	Aug 29 11:06:25 AM UTC 24
Finished	Aug 29 11:06:27 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972152972 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.1972152972 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/24.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.30336089
Short name	T851
Test name
Test status
Simulation time	30204735 ps
CPU time	0.81 seconds
Started	Aug 29 11:06:25 AM UTC 24
Finished	Aug 29 11:06:27 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30336089 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.30336089 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/25.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.4108468114
Short name	T853
Test name
Test status
Simulation time	32291099 ps
CPU time	0.76 seconds
Started	Aug 29 11:06:25 AM UTC 24
Finished	Aug 29 11:06:27 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108468114 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.4108468114 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/26.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.14091672
Short name	T856
Test name
Test status
Simulation time	162675627 ps
CPU time	0.97 seconds
Started	Aug 29 11:06:25 AM UTC 24
Finished	Aug 29 11:06:27 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14091672 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.14091672 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/27.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.3524284237
Short name	T852
Test name
Test status
Simulation time	12328709 ps
CPU time	0.73 seconds
Started	Aug 29 11:06:25 AM UTC 24
Finished	Aug 29 11:06:27 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524284237 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.3524284237 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/28.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.3519273019
Short name	T855
Test name
Test status
Simulation time	24850477 ps
CPU time	0.86 seconds
Started	Aug 29 11:06:25 AM UTC 24
Finished	Aug 29 11:06:27 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519273019 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.3519273019 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/29.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.1442855306
Short name	T770
Test name
Test status
Simulation time	1799537213 ps
CPU time	9.3 seconds
Started	Aug 29 11:06:06 AM UTC 24
Finished	Aug 29 11:06:16 AM UTC 24
Peak memory	219268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442855306 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.1442855306 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.2223733058
Short name	T833
Test name
Test status
Simulation time	13723913826 ps
CPU time	18.69 seconds
Started	Aug 29 11:06:04 AM UTC 24
Finished	Aug 29 11:06:24 AM UTC 24
Peak memory	219396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223733058 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.2223733058 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_hw_reset.2886320642
Short name	T740
Test name
Test status
Simulation time	88664715 ps
CPU time	1.19 seconds
Started	Aug 29 11:06:04 AM UTC 24
Finished	Aug 29 11:06:07 AM UTC 24
Peak memory	218880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886320642 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.2886320642 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.2652095787
Short name	T142
Test name
Test status
Simulation time	165181821 ps
CPU time	2.49 seconds
Started	Aug 29 11:06:06 AM UTC 24
Finished	Aug 29 11:06:09 AM UTC 24
Peak memory	231612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2652095787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_ mem_rw_with_rand_reset.2652095787 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_rw.242684534
Short name	T739
Test name
Test status
Simulation time	23179239 ps
CPU time	0.98 seconds
Started	Aug 29 11:06:04 AM UTC 24
Finished	Aug 29 11:06:06 AM UTC 24
Peak memory	218924 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242684534 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.242684534 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_intr_test.1120590530
Short name	T164
Test name
Test status
Simulation time	16421762 ps
CPU time	0.95 seconds
Started	Aug 29 11:06:04 AM UTC 24
Finished	Aug 29 11:06:06 AM UTC 24
Peak memory	218920 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120590530 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.1120590530 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_partial_access.2188922909
Short name	T147
Test name
Test status
Simulation time	59101475 ps
CPU time	1.38 seconds
Started	Aug 29 11:06:04 AM UTC 24
Finished	Aug 29 11:06:07 AM UTC 24
Peak memory	228860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188922909 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial_access.2188922909 +enable_mas king=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_walk.3458422101
Short name	T738
Test name
Test status
Simulation time	17085955 ps
CPU time	1.04 seconds
Started	Aug 29 11:06:04 AM UTC 24
Finished	Aug 29 11:06:06 AM UTC 24
Peak memory	218912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458422101 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.3458422101 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_same_csr_outstanding.249155853
Short name	T743
Test name
Test status
Simulation time	85112086 ps
CPU time	2.7 seconds
Started	Aug 29 11:06:06 AM UTC 24
Finished	Aug 29 11:06:09 AM UTC 24
Peak memory	229504 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249155853 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_outstanding.249155853 +enable_m asking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors.2589711259
Short name	T108
Test name
Test status
Simulation time	32880432 ps
CPU time	1.22 seconds
Started	Aug 29 11:06:04 AM UTC 24
Finished	Aug 29 11:06:06 AM UTC 24
Peak memory	228852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589711259 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors.2589711259 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.2534282241
Short name	T125
Test name
Test status
Simulation time	554906613 ps
CPU time	3.51 seconds
Started	Aug 29 11:06:04 AM UTC 24
Finished	Aug 29 11:06:09 AM UTC 24
Peak memory	229888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534282241 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors_with_csr_rw. 2534282241 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_errors.1286586259
Short name	T131
Test name
Test status
Simulation time	194094135 ps
CPU time	3.18 seconds
Started	Aug 29 11:06:04 AM UTC 24
Finished	Aug 29 11:06:09 AM UTC 24
Peak memory	229672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286586259 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.1286586259 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_intg_err.1914634182
Short name	T184
Test name
Test status
Simulation time	394271878 ps
CPU time	5.06 seconds
Started	Aug 29 11:06:04 AM UTC 24
Finished	Aug 29 11:06:10 AM UTC 24
Peak memory	219264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914634182 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.1914634182 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.2573222791
Short name	T854
Test name
Test status
Simulation time	29442415 ps
CPU time	0.74 seconds
Started	Aug 29 11:06:25 AM UTC 24
Finished	Aug 29 11:06:27 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573222791 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.2573222791 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/30.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.3253774709
Short name	T858
Test name
Test status
Simulation time	42677825 ps
CPU time	0.95 seconds
Started	Aug 29 11:06:25 AM UTC 24
Finished	Aug 29 11:06:27 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253774709 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.3253774709 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/31.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.2061459441
Short name	T857
Test name
Test status
Simulation time	36649871 ps
CPU time	0.76 seconds
Started	Aug 29 11:06:25 AM UTC 24
Finished	Aug 29 11:06:27 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061459441 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.2061459441 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/32.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.164316255
Short name	T862
Test name
Test status
Simulation time	34967109 ps
CPU time	0.7 seconds
Started	Aug 29 11:06:26 AM UTC 24
Finished	Aug 29 11:06:28 AM UTC 24
Peak memory	218856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164316255 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.164316255 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/33.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.1207044737
Short name	T867
Test name
Test status
Simulation time	17118326 ps
CPU time	0.84 seconds
Started	Aug 29 11:06:26 AM UTC 24
Finished	Aug 29 11:06:28 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207044737 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.1207044737 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/34.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.4292127074
Short name	T868
Test name
Test status
Simulation time	18405787 ps
CPU time	0.89 seconds
Started	Aug 29 11:06:26 AM UTC 24
Finished	Aug 29 11:06:28 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292127074 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.4292127074 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/35.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.301299434
Short name	T863
Test name
Test status
Simulation time	39184579 ps
CPU time	0.77 seconds
Started	Aug 29 11:06:26 AM UTC 24
Finished	Aug 29 11:06:28 AM UTC 24
Peak memory	218856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301299434 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.301299434 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/36.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.3931662668
Short name	T860
Test name
Test status
Simulation time	109351968 ps
CPU time	0.74 seconds
Started	Aug 29 11:06:26 AM UTC 24
Finished	Aug 29 11:06:28 AM UTC 24
Peak memory	218976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931662668 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.3931662668 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/37.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.44500504
Short name	T866
Test name
Test status
Simulation time	24929244 ps
CPU time	0.81 seconds
Started	Aug 29 11:06:26 AM UTC 24
Finished	Aug 29 11:06:28 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44500504 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.44500504 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/38.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.2101626930
Short name	T864
Test name
Test status
Simulation time	28805984 ps
CPU time	0.74 seconds
Started	Aug 29 11:06:26 AM UTC 24
Finished	Aug 29 11:06:28 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101626930 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.2101626930 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/39.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.1058784270
Short name	T756
Test name
Test status
Simulation time	209428546 ps
CPU time	4.86 seconds
Started	Aug 29 11:06:07 AM UTC 24
Finished	Aug 29 11:06:13 AM UTC 24
Peak memory	219268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058784270 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.1058784270 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.583720195
Short name	T869
Test name
Test status
Simulation time	3000484822 ps
CPU time	20.01 seconds
Started	Aug 29 11:06:07 AM UTC 24
Finished	Aug 29 11:06:28 AM UTC 24
Peak memory	219392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583720195 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.583720195 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_hw_reset.984846663
Short name	T745
Test name
Test status
Simulation time	62606940 ps
CPU time	1.39 seconds
Started	Aug 29 11:06:07 AM UTC 24
Finished	Aug 29 11:06:10 AM UTC 24
Peak memory	228852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984846663 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.984846663 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2547587416
Short name	T751
Test name
Test status
Simulation time	37970838 ps
CPU time	2.49 seconds
Started	Aug 29 11:06:07 AM UTC 24
Finished	Aug 29 11:06:11 AM UTC 24
Peak memory	231676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2547587416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_ mem_rw_with_rand_reset.2547587416 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.850415355
Short name	T744
Test name
Test status
Simulation time	347237211 ps
CPU time	1.4 seconds
Started	Aug 29 11:06:07 AM UTC 24
Finished	Aug 29 11:06:09 AM UTC 24
Peak memory	218884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850415355 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.850415355 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_intr_test.824845089
Short name	T174
Test name
Test status
Simulation time	26213006 ps
CPU time	0.96 seconds
Started	Aug 29 11:06:07 AM UTC 24
Finished	Aug 29 11:06:09 AM UTC 24
Peak memory	218984 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824845089 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.824845089 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_partial_access.2164601912
Short name	T148
Test name
Test status
Simulation time	50598652 ps
CPU time	1.15 seconds
Started	Aug 29 11:06:06 AM UTC 24
Finished	Aug 29 11:06:08 AM UTC 24
Peak memory	228856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164601912 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial_access.2164601912 +enable_mas king=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_walk.1908016557
Short name	T741
Test name
Test status
Simulation time	37656040 ps
CPU time	0.99 seconds
Started	Aug 29 11:06:06 AM UTC 24
Finished	Aug 29 11:06:08 AM UTC 24
Peak memory	218972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908016557 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.1908016557 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.3668745015
Short name	T747
Test name
Test status
Simulation time	28258208 ps
CPU time	1.75 seconds
Started	Aug 29 11:06:07 AM UTC 24
Finished	Aug 29 11:06:10 AM UTC 24
Peak memory	228860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668745015 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_outstanding.3668745015 +enable _masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.3723867709
Short name	T742
Test name
Test status
Simulation time	988346565 ps
CPU time	1.86 seconds
Started	Aug 29 11:06:06 AM UTC 24
Finished	Aug 29 11:06:09 AM UTC 24
Peak memory	228908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723867709 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors_with_csr_rw. 3723867709 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.2191364036
Short name	T130
Test name
Test status
Simulation time	1339449749 ps
CPU time	3.99 seconds
Started	Aug 29 11:06:06 AM UTC 24
Finished	Aug 29 11:06:11 AM UTC 24
Peak memory	229764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191364036 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.2191364036 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.537437154
Short name	T182
Test name
Test status
Simulation time	64136586 ps
CPU time	2.63 seconds
Started	Aug 29 11:06:07 AM UTC 24
Finished	Aug 29 11:06:11 AM UTC 24
Peak memory	229480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537437154 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.537437154 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.4162198542
Short name	T870
Test name
Test status
Simulation time	23055367 ps
CPU time	0.76 seconds
Started	Aug 29 11:06:26 AM UTC 24
Finished	Aug 29 11:06:29 AM UTC 24
Peak memory	218976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162198542 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.4162198542 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/40.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.1626438336
Short name	T865
Test name
Test status
Simulation time	13146279 ps
CPU time	0.76 seconds
Started	Aug 29 11:06:26 AM UTC 24
Finished	Aug 29 11:06:28 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626438336 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.1626438336 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/41.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.3467692715
Short name	T875
Test name
Test status
Simulation time	34070022 ps
CPU time	0.85 seconds
Started	Aug 29 11:06:26 AM UTC 24
Finished	Aug 29 11:06:29 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467692715 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.3467692715 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/42.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.1914517689
Short name	T874
Test name
Test status
Simulation time	31106471 ps
CPU time	0.78 seconds
Started	Aug 29 11:06:26 AM UTC 24
Finished	Aug 29 11:06:29 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914517689 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.1914517689 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/43.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.2047269744
Short name	T871
Test name
Test status
Simulation time	26439654 ps
CPU time	0.76 seconds
Started	Aug 29 11:06:26 AM UTC 24
Finished	Aug 29 11:06:29 AM UTC 24
Peak memory	218832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047269744 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.2047269744 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/44.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.1651465505
Short name	T878
Test name
Test status
Simulation time	40080251 ps
CPU time	0.89 seconds
Started	Aug 29 11:06:26 AM UTC 24
Finished	Aug 29 11:06:29 AM UTC 24
Peak memory	218976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651465505 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.1651465505 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/45.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.3729718989
Short name	T872
Test name
Test status
Simulation time	44783206 ps
CPU time	0.77 seconds
Started	Aug 29 11:06:26 AM UTC 24
Finished	Aug 29 11:06:29 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729718989 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.3729718989 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/46.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.3995270488
Short name	T876
Test name
Test status
Simulation time	25620054 ps
CPU time	0.75 seconds
Started	Aug 29 11:06:26 AM UTC 24
Finished	Aug 29 11:06:29 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995270488 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.3995270488 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/47.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.3280737986
Short name	T873
Test name
Test status
Simulation time	35922023 ps
CPU time	0.71 seconds
Started	Aug 29 11:06:26 AM UTC 24
Finished	Aug 29 11:06:29 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280737986 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.3280737986 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/48.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.3598005720
Short name	T877
Test name
Test status
Simulation time	34600325 ps
CPU time	0.7 seconds
Started	Aug 29 11:06:26 AM UTC 24
Finished	Aug 29 11:06:29 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598005720 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.3598005720 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/49.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.4148792989
Short name	T163
Test name
Test status
Simulation time	79723336 ps
CPU time	2.58 seconds
Started	Aug 29 11:06:10 AM UTC 24
Finished	Aug 29 11:06:13 AM UTC 24
Peak memory	231620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4148792989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_ mem_rw_with_rand_reset.4148792989 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_rw.2763695530
Short name	T752
Test name
Test status
Simulation time	43481268 ps
CPU time	1.31 seconds
Started	Aug 29 11:06:09 AM UTC 24
Finished	Aug 29 11:06:11 AM UTC 24
Peak memory	228856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763695530 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.2763695530 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/5.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3904724520
Short name	T755
Test name
Test status
Simulation time	133055020 ps
CPU time	2.16 seconds
Started	Aug 29 11:06:10 AM UTC 24
Finished	Aug 29 11:06:13 AM UTC 24
Peak memory	229608 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904724520 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_outstanding.3904724520 +enable _masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/5.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.706708046
Short name	T746
Test name
Test status
Simulation time	21605016 ps
CPU time	1.52 seconds
Started	Aug 29 11:06:07 AM UTC 24
Finished	Aug 29 11:06:10 AM UTC 24
Peak memory	228132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706708046 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors.706708046 +enable_masking =0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1860751948
Short name	T749
Test name
Test status
Simulation time	189985962 ps
CPU time	2.02 seconds
Started	Aug 29 11:06:07 AM UTC 24
Finished	Aug 29 11:06:10 AM UTC 24
Peak memory	229976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860751948 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors_with_csr_rw. 1860751948 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.128441909
Short name	T133
Test name
Test status
Simulation time	539566485 ps
CPU time	3.74 seconds
Started	Aug 29 11:06:07 AM UTC 24
Finished	Aug 29 11:06:12 AM UTC 24
Peak memory	229328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128441909 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.128441909 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/5.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.1583975850
Short name	T192
Test name
Test status
Simulation time	402089512 ps
CPU time	2.73 seconds
Started	Aug 29 11:06:08 AM UTC 24
Finished	Aug 29 11:06:12 AM UTC 24
Peak memory	229504 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583975850 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.1583975850 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/5.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3869616719
Short name	T762
Test name
Test status
Simulation time	132308973 ps
CPU time	2.56 seconds
Started	Aug 29 11:06:11 AM UTC 24
Finished	Aug 29 11:06:15 AM UTC 24
Peak memory	231748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3869616719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_ mem_rw_with_rand_reset.3869616719 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_rw.4136544310
Short name	T754
Test name
Test status
Simulation time	25926005 ps
CPU time	1.24 seconds
Started	Aug 29 11:06:10 AM UTC 24
Finished	Aug 29 11:06:12 AM UTC 24
Peak memory	218876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136544310 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.4136544310 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/6.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_intr_test.2966175475
Short name	T176
Test name
Test status
Simulation time	97235559 ps
CPU time	0.86 seconds
Started	Aug 29 11:06:10 AM UTC 24
Finished	Aug 29 11:06:12 AM UTC 24
Peak memory	218920 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966175475 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.2966175475 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/6.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.3725267014
Short name	T761
Test name
Test status
Simulation time	1466368498 ps
CPU time	2.71 seconds
Started	Aug 29 11:06:11 AM UTC 24
Finished	Aug 29 11:06:15 AM UTC 24
Peak memory	229544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725267014 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_outstanding.3725267014 +enable _masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/6.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.1433889161
Short name	T191
Test name
Test status
Simulation time	55050323 ps
CPU time	1.4 seconds
Started	Aug 29 11:06:10 AM UTC 24
Finished	Aug 29 11:06:12 AM UTC 24
Peak memory	228852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433889161 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors.1433889161 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3016349380
Short name	T126
Test name
Test status
Simulation time	35164469 ps
CPU time	2.08 seconds
Started	Aug 29 11:06:10 AM UTC 24
Finished	Aug 29 11:06:13 AM UTC 24
Peak memory	230040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016349380 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors_with_csr_rw. 3016349380 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.3247995448
Short name	T138
Test name
Test status
Simulation time	857015940 ps
CPU time	2.5 seconds
Started	Aug 29 11:06:10 AM UTC 24
Finished	Aug 29 11:06:13 AM UTC 24
Peak memory	229632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247995448 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.3247995448 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/6.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.4021429268
Short name	T185
Test name
Test status
Simulation time	254446207 ps
CPU time	3.26 seconds
Started	Aug 29 11:06:10 AM UTC 24
Finished	Aug 29 11:06:14 AM UTC 24
Peak memory	229508 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021429268 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.4021429268 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/6.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.863235020
Short name	T758
Test name
Test status
Simulation time	42726278 ps
CPU time	1.74 seconds
Started	Aug 29 11:06:11 AM UTC 24
Finished	Aug 29 11:06:14 AM UTC 24
Peak memory	228312 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=863235020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_m em_rw_with_rand_reset.863235020 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.2389533469
Short name	T757
Test name
Test status
Simulation time	28267219 ps
CPU time	1.14 seconds
Started	Aug 29 11:06:11 AM UTC 24
Finished	Aug 29 11:06:13 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389533469 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.2389533469 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/7.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.1648856207
Short name	T177
Test name
Test status
Simulation time	24469233 ps
CPU time	1.12 seconds
Started	Aug 29 11:06:11 AM UTC 24
Finished	Aug 29 11:06:13 AM UTC 24
Peak memory	218980 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648856207 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.1648856207 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/7.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.1513643632
Short name	T764
Test name
Test status
Simulation time	308961039 ps
CPU time	2.71 seconds
Started	Aug 29 11:06:11 AM UTC 24
Finished	Aug 29 11:06:15 AM UTC 24
Peak memory	228968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513643632 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_outstanding.1513643632 +enable _masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/7.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors.1250194721
Short name	T112
Test name
Test status
Simulation time	51816458 ps
CPU time	1.36 seconds
Started	Aug 29 11:06:11 AM UTC 24
Finished	Aug 29 11:06:14 AM UTC 24
Peak memory	228852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250194721 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors.1250194721 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3940998001
Short name	T759
Test name
Test status
Simulation time	530620458 ps
CPU time	1.98 seconds
Started	Aug 29 11:06:11 AM UTC 24
Finished	Aug 29 11:06:14 AM UTC 24
Peak memory	228868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940998001 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors_with_csr_rw. 3940998001 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.3332671124
Short name	T767
Test name
Test status
Simulation time	262955224 ps
CPU time	3.19 seconds
Started	Aug 29 11:06:11 AM UTC 24
Finished	Aug 29 11:06:16 AM UTC 24
Peak memory	229508 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332671124 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.3332671124 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/7.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2763007922
Short name	T774
Test name
Test status
Simulation time	37474360 ps
CPU time	2.4 seconds
Started	Aug 29 11:06:13 AM UTC 24
Finished	Aug 29 11:06:16 AM UTC 24
Peak memory	231628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2763007922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_ mem_rw_with_rand_reset.2763007922 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.2108763015
Short name	T765
Test name
Test status
Simulation time	34537613 ps
CPU time	1.55 seconds
Started	Aug 29 11:06:13 AM UTC 24
Finished	Aug 29 11:06:15 AM UTC 24
Peak memory	218872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108763015 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.2108763015 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/8.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.362946557
Short name	T760
Test name
Test status
Simulation time	23467662 ps
CPU time	0.89 seconds
Started	Aug 29 11:06:13 AM UTC 24
Finished	Aug 29 11:06:15 AM UTC 24
Peak memory	218924 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362946557 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.362946557 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/8.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.1687532234
Short name	T766
Test name
Test status
Simulation time	62381524 ps
CPU time	1.61 seconds
Started	Aug 29 11:06:13 AM UTC 24
Finished	Aug 29 11:06:15 AM UTC 24
Peak memory	228860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687532234 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_outstanding.1687532234 +enable _masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/8.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2053609048
Short name	T166
Test name
Test status
Simulation time	59892582 ps
CPU time	1.66 seconds
Started	Aug 29 11:06:11 AM UTC 24
Finished	Aug 29 11:06:14 AM UTC 24
Peak memory	228596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053609048 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors.2053609048 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.1782547576
Short name	T768
Test name
Test status
Simulation time	103358090 ps
CPU time	2.06 seconds
Started	Aug 29 11:06:12 AM UTC 24
Finished	Aug 29 11:06:16 AM UTC 24
Peak memory	229912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782547576 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors_with_csr_rw. 1782547576 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.216984753
Short name	T136
Test name
Test status
Simulation time	159447144 ps
CPU time	3.9 seconds
Started	Aug 29 11:06:13 AM UTC 24
Finished	Aug 29 11:06:18 AM UTC 24
Peak memory	229616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216984753 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.216984753 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/8.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.4210280824
Short name	T180
Test name
Test status
Simulation time	237467151 ps
CPU time	5.14 seconds
Started	Aug 29 11:06:13 AM UTC 24
Finished	Aug 29 11:06:19 AM UTC 24
Peak memory	219224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210280824 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.4210280824 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/8.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3599257852
Short name	T780
Test name
Test status
Simulation time	128306212 ps
CPU time	2.43 seconds
Started	Aug 29 11:06:14 AM UTC 24
Finished	Aug 29 11:06:18 AM UTC 24
Peak memory	231612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3599257852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_ mem_rw_with_rand_reset.3599257852 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.962832996
Short name	T773
Test name
Test status
Simulation time	144836160 ps
CPU time	1.14 seconds
Started	Aug 29 11:06:14 AM UTC 24
Finished	Aug 29 11:06:16 AM UTC 24
Peak memory	218900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962832996 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.962832996 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/9.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.4117116473
Short name	T771
Test name
Test status
Simulation time	20647628 ps
CPU time	1.02 seconds
Started	Aug 29 11:06:14 AM UTC 24
Finished	Aug 29 11:06:16 AM UTC 24
Peak memory	218916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117116473 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.4117116473 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/9.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.414383443
Short name	T779
Test name
Test status
Simulation time	129148743 ps
CPU time	2.05 seconds
Started	Aug 29 11:06:14 AM UTC 24
Finished	Aug 29 11:06:17 AM UTC 24
Peak memory	229480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414383443 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_outstanding.414383443 +enable_m asking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/9.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.3857633245
Short name	T763
Test name
Test status
Simulation time	137782870 ps
CPU time	1.11 seconds
Started	Aug 29 11:06:13 AM UTC 24
Finished	Aug 29 11:06:15 AM UTC 24
Peak memory	218676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857633245 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors.3857633245 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.60080942
Short name	T775
Test name
Test status
Simulation time	91651880 ps
CPU time	2.39 seconds
Started	Aug 29 11:06:13 AM UTC 24
Finished	Aug 29 11:06:16 AM UTC 24
Peak memory	236768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60080942 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors_with_csr_rw.60 080942 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.64915771
Short name	T139
Test name
Test status
Simulation time	180586297 ps
CPU time	2.66 seconds
Started	Aug 29 11:06:14 AM UTC 24
Finished	Aug 29 11:06:18 AM UTC 24
Peak memory	229700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64915771 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.64915771 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/9.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.1647087136
Short name	T798
Test name
Test status
Simulation time	471310930 ps
CPU time	4.99 seconds
Started	Aug 29 11:06:14 AM UTC 24
Finished	Aug 29 11:06:20 AM UTC 24
Peak memory	229504 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647087136 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.1647087136 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/9.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/0.kmac_app_with_partial_data.1689925917
Short name	T152
Test name
Test status
Simulation time	5788240839 ps
CPU time	191.98 seconds
Started	Aug 29 11:43:53 AM UTC 24
Finished	Aug 29 11:47:08 AM UTC 24
Peak memory	315264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689925917 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.1689925917 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_app_with_partial_data/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/0.kmac_burst_write.339576543
Short name	T149
Test name
Test status
Simulation time	9830737408 ps
CPU time	172.51 seconds
Started	Aug 29 11:43:51 AM UTC 24
Finished	Aug 29 11:46:46 AM UTC 24
Peak memory	241640 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339576543 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.339576543 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_mode_error.1944044181
Short name	T31
Test name
Test status
Simulation time	391024016 ps
CPU time	33.86 seconds
Started	Aug 29 11:43:54 AM UTC 24
Finished	Aug 29 11:44:30 AM UTC 24
Peak memory	232500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944044181 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.1944044181 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_refresh.2138845020
Short name	T116
Test name
Test status
Simulation time	25668451355 ps
CPU time	165.27 seconds
Started	Aug 29 11:43:53 AM UTC 24
Finished	Aug 29 11:46:41 AM UTC 24
Peak memory	294852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138845020 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.2138845020 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/0.kmac_error.4286146402
Short name	T44
Test name
Test status
Simulation time	6292507167 ps
CPU time	353.35 seconds
Started	Aug 29 11:43:54 AM UTC 24
Finished	Aug 29 11:49:52 AM UTC 24
Peak memory	388948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286146402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.4286146402 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/0.kmac_key_error.2737290082
Short name	T4
Test name
Test status
Simulation time	1227688695 ps
CPU time	4.11 seconds
Started	Aug 29 11:43:54 AM UTC 24
Finished	Aug 29 11:43:59 AM UTC 24
Peak memory	230508 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737290082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.2737290082 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/0.kmac_lc_escalation.3753051724
Short name	T3
Test name
Test status
Simulation time	36510238 ps
CPU time	1.76 seconds
Started	Aug 29 11:43:54 AM UTC 24
Finished	Aug 29 11:43:57 AM UTC 24
Peak memory	229784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753051724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.3753051724 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/0.kmac_long_msg_and_output.1033315730
Short name	T395
Test name
Test status
Simulation time	120665500630 ps
CPU time	1168.6 seconds
Started	Aug 29 11:43:51 AM UTC 24
Finished	Aug 29 12:03:33 PM UTC 24
Peak memory	1662368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033315730 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_and_output.1033315730 +enable_mas king=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/0.kmac_sideload.4026432840
Short name	T34
Test name
Test status
Simulation time	11508427604 ps
CPU time	253.53 seconds
Started	Aug 29 11:43:51 AM UTC 24
Finished	Aug 29 11:48:08 AM UTC 24
Peak memory	335716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026432840 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.4026432840 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/0.kmac_stress_all.2045999424
Short name	T311
Test name
Test status
Simulation time	22864278850 ps
CPU time	683.31 seconds
Started	Aug 29 11:43:56 AM UTC 24
Finished	Aug 29 11:55:27 AM UTC 24
Peak memory	968532 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045999424 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.2045999424 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac_xof.2688760354
Short name	T2
Test name
Test status
Simulation time	165696217 ps
CPU time	3.12 seconds
Started	Aug 29 11:43:52 AM UTC 24
Finished	Aug 29 11:43:57 AM UTC 24
Peak memory	230564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688760354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.2688760354 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_test_vectors_kmac_xof/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_224.324575515
Short name	T633
Test name
Test status
Simulation time	234761369198 ps
CPU time	2462.19 seconds
Started	Aug 29 11:43:51 AM UTC 24
Finished	Aug 29 12:25:21 PM UTC 24
Peak memory	3153180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324575515 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.324575515 + enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_224/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_256.2979545407
Short name	T82
Test name
Test status
Simulation time	10232942050 ps
CPU time	55.97 seconds
Started	Aug 29 11:43:51 AM UTC 24
Finished	Aug 29 11:44:48 AM UTC 24
Peak memory	253700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979545407 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.2979545407 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_256/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_384.2012866956
Short name	T95
Test name
Test status
Simulation time	3188870168 ps
CPU time	27.79 seconds
Started	Aug 29 11:43:52 AM UTC 24
Finished	Aug 29 11:44:21 AM UTC 24
Peak memory	230688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012866956 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.2012866956 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_384/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_512.3309250825
Short name	T14
Test name
Test status
Simulation time	745828576 ps
CPU time	16.27 seconds
Started	Aug 29 11:43:52 AM UTC 24
Finished	Aug 29 11:44:10 AM UTC 24
Peak memory	228660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309250825 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.3309250825 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_512/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_128.144967681
Short name	T151
Test name
Test status
Simulation time	10050521138 ps
CPU time	191.78 seconds
Started	Aug 29 11:43:52 AM UTC 24
Finished	Aug 29 11:47:07 AM UTC 24
Peak memory	280276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144967681 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.14496768 1 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_128/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_256.4242731573
Short name	T167
Test name
Test status
Simulation time	9706644100 ps
CPU time	143.38 seconds
Started	Aug 29 11:43:52 AM UTC 24
Finished	Aug 29 11:46:18 AM UTC 24
Peak memory	358088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242731573 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.4242731 573 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_256/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/1.kmac_alert_test.3488176876
Short name	T49
Test name
Test status
Simulation time	35502937 ps
CPU time	1.31 seconds
Started	Aug 29 11:44:15 AM UTC 24
Finished	Aug 29 11:44:18 AM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488176876 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.3488176876 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/1.kmac_app.2710994295
Short name	T170
Test name
Test status
Simulation time	8965274610 ps
CPU time	245.75 seconds
Started	Aug 29 11:44:00 AM UTC 24
Finished	Aug 29 11:48:10 AM UTC 24
Peak memory	403416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710994295 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.2710994295 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/1.kmac_app_with_partial_data.2474618296
Short name	T205
Test name
Test status
Simulation time	27226912872 ps
CPU time	229.16 seconds
Started	Aug 29 11:44:00 AM UTC 24
Finished	Aug 29 11:47:53 AM UTC 24
Peak memory	448324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474618296 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.2474618296 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_app_with_partial_data/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/1.kmac_burst_write.2732070999
Short name	T53
Test name
Test status
Simulation time	12701481987 ps
CPU time	267.43 seconds
Started	Aug 29 11:43:56 AM UTC 24
Finished	Aug 29 11:48:28 AM UTC 24
Peak memory	241504 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732070999 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.2732070999 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/1.kmac_edn_timeout_error.2105614118
Short name	T15
Test name
Test status
Simulation time	457155500 ps
CPU time	2.7 seconds
Started	Aug 29 11:44:08 AM UTC 24
Finished	Aug 29 11:44:12 AM UTC 24
Peak memory	228376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105614118 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.2105614118 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_mode_error.4041168686
Short name	T32
Test name
Test status
Simulation time	1234520032 ps
CPU time	33.62 seconds
Started	Aug 29 11:44:11 AM UTC 24
Finished	Aug 29 11:44:46 AM UTC 24
Peak memory	234468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041168686 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.4041168686 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/1.kmac_error.3402761563
Short name	T36
Test name
Test status
Simulation time	10881486801 ps
CPU time	246.69 seconds
Started	Aug 29 11:44:06 AM UTC 24
Finished	Aug 29 11:48:17 AM UTC 24
Peak memory	319384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402761563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.3402761563 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/1.kmac_long_msg_and_output.7412762
Short name	T427
Test name
Test status
Simulation time	14477359701 ps
CPU time	1363.82 seconds
Started	Aug 29 11:43:56 AM UTC 24
Finished	Aug 29 12:06:56 PM UTC 24
Peak memory	1072996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7412762 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_and_output.7412762 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/1.kmac_mubi.3687113645
Short name	T41
Test name
Test status
Simulation time	3670580715 ps
CPU time	102.61 seconds
Started	Aug 29 11:44:04 AM UTC 24
Finished	Aug 29 11:45:49 AM UTC 24
Peak memory	303256 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687113645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.3687113645 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/1.kmac_sec_cm.2319087497
Short name	T10
Test name
Test status
Simulation time	4926418671 ps
CPU time	70.25 seconds
Started	Aug 29 11:44:15 AM UTC 24
Finished	Aug 29 11:45:27 AM UTC 24
Peak memory	292140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319087497 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.2319087497 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/1.kmac_sideload.1846076294
Short name	T212
Test name
Test status
Simulation time	134911563655 ps
CPU time	290.25 seconds
Started	Aug 29 11:43:56 AM UTC 24
Finished	Aug 29 11:48:51 AM UTC 24
Peak memory	476820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846076294 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.1846076294 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/1.kmac_stress_all.4196509979
Short name	T693
Test name
Test status
Simulation time	162525671327 ps
CPU time	2994.76 seconds
Started	Aug 29 11:44:13 AM UTC 24
Finished	Aug 29 12:34:45 PM UTC 24
Peak memory	1511688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196509979 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.4196509979 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac.398180298
Short name	T12
Test name
Test status
Simulation time	302629052 ps
CPU time	3.6 seconds
Started	Aug 29 11:43:58 AM UTC 24
Finished	Aug 29 11:44:02 AM UTC 24
Peak memory	230496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398180298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_ve ctors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac.398180298 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_test_vectors_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac_xof.3073322155
Short name	T13
Test name
Test status
Simulation time	35649645 ps
CPU time	3.17 seconds
Started	Aug 29 11:43:59 AM UTC 24
Finished	Aug 29 11:44:03 AM UTC 24
Peak memory	230564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073322155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.3073322155 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_test_vectors_kmac_xof/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_256.1456449967
Short name	T668
Test name
Test status
Simulation time	77007969848 ps
CPU time	2631.89 seconds
Started	Aug 29 11:43:57 AM UTC 24
Finished	Aug 29 12:28:21 PM UTC 24
Peak memory	2955052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456449967 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.1456449967 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_256/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_384.2914476955
Short name	T96
Test name
Test status
Simulation time	1192645556 ps
CPU time	23.77 seconds
Started	Aug 29 11:43:57 AM UTC 24
Finished	Aug 29 11:44:22 AM UTC 24
Peak memory	237192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914476955 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.2914476955 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_384/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_512.1636943574
Short name	T18
Test name
Test status
Simulation time	3725546283 ps
CPU time	20.73 seconds
Started	Aug 29 11:43:57 AM UTC 24
Finished	Aug 29 11:44:19 AM UTC 24
Peak memory	230556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636943574 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.1636943574 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_512/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_128.2947149225
Short name	T221
Test name
Test status
Simulation time	14297044828 ps
CPU time	319.93 seconds
Started	Aug 29 11:43:57 AM UTC 24
Finished	Aug 29 11:49:22 AM UTC 24
Peak memory	279224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947149225 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.2947149 225 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_128/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_256.790135732
Short name	T93
Test name
Test status
Simulation time	13023638678 ps
CPU time	107.99 seconds
Started	Aug 29 11:43:57 AM UTC 24
Finished	Aug 29 11:45:48 AM UTC 24
Peak memory	263928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790135732 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.79013573 2 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_256/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/10.kmac_alert_test.349068091
Short name	T250
Test name
Test status
Simulation time	46243347 ps
CPU time	1.18 seconds
Started	Aug 29 11:51:18 AM UTC 24
Finished	Aug 29 11:51:21 AM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349068091 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.349068091 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/10.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/10.kmac_app.4150273147
Short name	T341
Test name
Test status
Simulation time	14479878356 ps
CPU time	423.96 seconds
Started	Aug 29 11:51:05 AM UTC 24
Finished	Aug 29 11:58:15 AM UTC 24
Peak memory	538460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150273147 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.4150273147 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/10.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/10.kmac_burst_write.1210713639
Short name	T287
Test name
Test status
Simulation time	16175752390 ps
CPU time	172.84 seconds
Started	Aug 29 11:51:00 AM UTC 24
Finished	Aug 29 11:53:56 AM UTC 24
Peak memory	235360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210713639 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.1210713639 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/10.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/10.kmac_edn_timeout_error.1905829338
Short name	T252
Test name
Test status
Simulation time	232561030 ps
CPU time	15.13 seconds
Started	Aug 29 11:51:09 AM UTC 24
Finished	Aug 29 11:51:25 AM UTC 24
Peak memory	235176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905829338 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.1905829338 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/10.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/10.kmac_entropy_mode_error.2484722476
Short name	T213
Test name
Test status
Simulation time	502857849 ps
CPU time	42.88 seconds
Started	Aug 29 11:51:11 AM UTC 24
Finished	Aug 29 11:51:56 AM UTC 24
Peak memory	232420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484722476 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.2484722476 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/10.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/10.kmac_entropy_refresh.3448251314
Short name	T274
Test name
Test status
Simulation time	22208717856 ps
CPU time	88.93 seconds
Started	Aug 29 11:51:08 AM UTC 24
Finished	Aug 29 11:52:39 AM UTC 24
Peak memory	292832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448251314 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.3448251314 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/10.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/10.kmac_error.3966220223
Short name	T353
Test name
Test status
Simulation time	32294919172 ps
CPU time	465.46 seconds
Started	Aug 29 11:51:08 AM UTC 24
Finished	Aug 29 11:59:00 AM UTC 24
Peak memory	603944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966220223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.3966220223 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/10.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/10.kmac_key_error.2525863627
Short name	T253
Test name
Test status
Simulation time	3137067236 ps
CPU time	15.25 seconds
Started	Aug 29 11:51:09 AM UTC 24
Finished	Aug 29 11:51:25 AM UTC 24
Peak memory	230500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525863627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.2525863627 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/10.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/10.kmac_lc_escalation.134765754
Short name	T246
Test name
Test status
Simulation time	129065317 ps
CPU time	1.87 seconds
Started	Aug 29 11:51:14 AM UTC 24
Finished	Aug 29 11:51:17 AM UTC 24
Peak memory	229736 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134765754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.134765754 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/10.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/10.kmac_long_msg_and_output.139960335
Short name	T267
Test name
Test status
Simulation time	6108203834 ps
CPU time	75.2 seconds
Started	Aug 29 11:51:00 AM UTC 24
Finished	Aug 29 11:52:17 AM UTC 24
Peak memory	339784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139960335 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_and_output.139960335 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/10.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/10.kmac_sideload.3431147808
Short name	T304
Test name
Test status
Simulation time	107199124365 ps
CPU time	234.49 seconds
Started	Aug 29 11:51:00 AM UTC 24
Finished	Aug 29 11:54:58 AM UTC 24
Peak memory	446228 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431147808 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.3431147808 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/10.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/10.kmac_smoke.1663129502
Short name	T255
Test name
Test status
Simulation time	1279301942 ps
CPU time	40.48 seconds
Started	Aug 29 11:50:57 AM UTC 24
Finished	Aug 29 11:51:39 AM UTC 24
Peak memory	230624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663129502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.1663129502 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/10.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/10.kmac_stress_all.1779495348
Short name	T315
Test name
Test status
Simulation time	30368125545 ps
CPU time	254.87 seconds
Started	Aug 29 11:51:15 AM UTC 24
Finished	Aug 29 11:55:34 AM UTC 24
Peak memory	329868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779495348 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.1779495348 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/10.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/11.kmac_alert_test.826955024
Short name	T259
Test name
Test status
Simulation time	82616541 ps
CPU time	1.12 seconds
Started	Aug 29 11:51:44 AM UTC 24
Finished	Aug 29 11:51:46 AM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826955024 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.826955024 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/11.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/11.kmac_app.1726977594
Short name	T307
Test name
Test status
Simulation time	8658015893 ps
CPU time	223.18 seconds
Started	Aug 29 11:51:22 AM UTC 24
Finished	Aug 29 11:55:08 AM UTC 24
Peak memory	319448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726977594 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.1726977594 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/11.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/11.kmac_burst_write.370189100
Short name	T318
Test name
Test status
Simulation time	14951985519 ps
CPU time	272.96 seconds
Started	Aug 29 11:51:22 AM UTC 24
Finished	Aug 29 11:55:59 AM UTC 24
Peak memory	239380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370189100 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.370189100 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/11.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/11.kmac_edn_timeout_error.512984256
Short name	T264
Test name
Test status
Simulation time	353484981 ps
CPU time	33.04 seconds
Started	Aug 29 11:51:38 AM UTC 24
Finished	Aug 29 11:52:12 AM UTC 24
Peak memory	235288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512984256 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.512984256 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/11.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/11.kmac_entropy_mode_error.2239674564
Short name	T263
Test name
Test status
Simulation time	786055234 ps
CPU time	23.55 seconds
Started	Aug 29 11:51:40 AM UTC 24
Finished	Aug 29 11:52:05 AM UTC 24
Peak memory	232468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239674564 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.2239674564 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/11.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/11.kmac_entropy_refresh.3362288408
Short name	T270
Test name
Test status
Simulation time	1911238493 ps
CPU time	54.68 seconds
Started	Aug 29 11:51:26 AM UTC 24
Finished	Aug 29 11:52:22 AM UTC 24
Peak memory	265956 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362288408 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.3362288408 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/11.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/11.kmac_error.3660886530
Short name	T45
Test name
Test status
Simulation time	7538400627 ps
CPU time	257.17 seconds
Started	Aug 29 11:51:26 AM UTC 24
Finished	Aug 29 11:55:47 AM UTC 24
Peak memory	364392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660886530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.3660886530 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/11.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/11.kmac_key_error.606630131
Short name	T260
Test name
Test status
Simulation time	1227004900 ps
CPU time	12.76 seconds
Started	Aug 29 11:51:36 AM UTC 24
Finished	Aug 29 11:51:50 AM UTC 24
Peak memory	230444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606630131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.606630131 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/11.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/11.kmac_lc_escalation.3219648663
Short name	T258
Test name
Test status
Simulation time	55939813 ps
CPU time	1.82 seconds
Started	Aug 29 11:51:40 AM UTC 24
Finished	Aug 29 11:51:43 AM UTC 24
Peak memory	229664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219648663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.3219648663 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/11.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/11.kmac_long_msg_and_output.4164054793
Short name	T273
Test name
Test status
Simulation time	13539775560 ps
CPU time	71.15 seconds
Started	Aug 29 11:51:19 AM UTC 24
Finished	Aug 29 11:52:31 AM UTC 24
Peak memory	268112 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164054793 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_and_output.4164054793 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/11.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/11.kmac_sideload.1265381028
Short name	T298
Test name
Test status
Simulation time	23203963357 ps
CPU time	202.29 seconds
Started	Aug 29 11:51:20 AM UTC 24
Finished	Aug 29 11:54:45 AM UTC 24
Peak memory	419660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265381028 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.1265381028 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/11.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/11.kmac_smoke.62074373
Short name	T262
Test name
Test status
Simulation time	1614902197 ps
CPU time	39.41 seconds
Started	Aug 29 11:51:18 AM UTC 24
Finished	Aug 29 11:51:59 AM UTC 24
Peak memory	234692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62074373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.62074373 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/11.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/11.kmac_stress_all.3362403505
Short name	T702
Test name
Test status
Simulation time	382351491106 ps
CPU time	2856.53 seconds
Started	Aug 29 11:51:41 AM UTC 24
Finished	Aug 29 12:39:50 PM UTC 24
Peak memory	2742368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362403505 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.3362403505 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/11.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/12.kmac_alert_test.2797432891
Short name	T271
Test name
Test status
Simulation time	47063868 ps
CPU time	1.25 seconds
Started	Aug 29 11:52:20 AM UTC 24
Finished	Aug 29 11:52:23 AM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797432891 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.2797432891 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/12.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/12.kmac_app.2526664570
Short name	T285
Test name
Test status
Simulation time	36097619597 ps
CPU time	114.22 seconds
Started	Aug 29 11:51:57 AM UTC 24
Finished	Aug 29 11:53:53 AM UTC 24
Peak memory	323552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526664570 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.2526664570 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/12.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/12.kmac_burst_write.934558206
Short name	T326
Test name
Test status
Simulation time	24994439558 ps
CPU time	269.77 seconds
Started	Aug 29 11:51:54 AM UTC 24
Finished	Aug 29 11:56:28 AM UTC 24
Peak memory	251676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934558206 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.934558206 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/12.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/12.kmac_edn_timeout_error.6529951
Short name	T278
Test name
Test status
Simulation time	3276577142 ps
CPU time	56.73 seconds
Started	Aug 29 11:52:13 AM UTC 24
Finished	Aug 29 11:53:11 AM UTC 24
Peak memory	235180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6529951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.6529951 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/12.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/12.kmac_entropy_mode_error.3107028232
Short name	T276
Test name
Test status
Simulation time	9324833519 ps
CPU time	42.59 seconds
Started	Aug 29 11:52:14 AM UTC 24
Finished	Aug 29 11:52:58 AM UTC 24
Peak memory	235244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107028232 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.3107028232 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/12.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/12.kmac_entropy_refresh.3757503635
Short name	T343
Test name
Test status
Simulation time	13029845771 ps
CPU time	373.75 seconds
Started	Aug 29 11:52:00 AM UTC 24
Finished	Aug 29 11:58:19 AM UTC 24
Peak memory	475016 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757503635 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.3757503635 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/12.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/12.kmac_error.2114102939
Short name	T266
Test name
Test status
Simulation time	270158291 ps
CPU time	11.91 seconds
Started	Aug 29 11:52:02 AM UTC 24
Finished	Aug 29 11:52:15 AM UTC 24
Peak memory	235296 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114102939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.2114102939 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/12.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/12.kmac_key_error.3560968555
Short name	T265
Test name
Test status
Simulation time	2974846021 ps
CPU time	6.44 seconds
Started	Aug 29 11:52:06 AM UTC 24
Finished	Aug 29 11:52:13 AM UTC 24
Peak memory	230444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560968555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.3560968555 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/12.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/12.kmac_lc_escalation.4267169036
Short name	T269
Test name
Test status
Simulation time	48579654 ps
CPU time	2.22 seconds
Started	Aug 29 11:52:16 AM UTC 24
Finished	Aug 29 11:52:19 AM UTC 24
Peak memory	230440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267169036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.4267169036 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/12.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/12.kmac_long_msg_and_output.852447605
Short name	T293
Test name
Test status
Simulation time	12677628756 ps
CPU time	140.48 seconds
Started	Aug 29 11:51:50 AM UTC 24
Finished	Aug 29 11:54:14 AM UTC 24
Peak memory	298856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852447605 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_and_output.852447605 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/12.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/12.kmac_sideload.328401780
Short name	T368
Test name
Test status
Simulation time	18881087016 ps
CPU time	527.05 seconds
Started	Aug 29 11:51:53 AM UTC 24
Finished	Aug 29 12:00:47 PM UTC 24
Peak memory	639000 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328401780 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.328401780 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/12.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/12.kmac_smoke.1136669750
Short name	T279
Test name
Test status
Simulation time	14168597491 ps
CPU time	87.26 seconds
Started	Aug 29 11:51:47 AM UTC 24
Finished	Aug 29 11:53:17 AM UTC 24
Peak memory	235268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136669750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.1136669750 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/12.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/12.kmac_stress_all.1682329272
Short name	T483
Test name
Test status
Simulation time	32089976461 ps
CPU time	1202.94 seconds
Started	Aug 29 11:52:17 AM UTC 24
Finished	Aug 29 12:12:35 PM UTC 24
Peak memory	807080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682329272 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.1682329272 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/12.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/13.kmac_alert_test.329664823
Short name	T281
Test name
Test status
Simulation time	17652120 ps
CPU time	1.22 seconds
Started	Aug 29 11:53:24 AM UTC 24
Finished	Aug 29 11:53:27 AM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329664823 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.329664823 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/13.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/13.kmac_app.2051018065
Short name	T282
Test name
Test status
Simulation time	2808582684 ps
CPU time	55.2 seconds
Started	Aug 29 11:52:33 AM UTC 24
Finished	Aug 29 11:53:30 AM UTC 24
Peak memory	249672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051018065 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.2051018065 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/13.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/13.kmac_edn_timeout_error.4180170215
Short name	T284
Test name
Test status
Simulation time	480569269 ps
CPU time	36.61 seconds
Started	Aug 29 11:53:05 AM UTC 24
Finished	Aug 29 11:53:43 AM UTC 24
Peak memory	235084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180170215 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.4180170215 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/13.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/13.kmac_entropy_mode_error.314858032
Short name	T283
Test name
Test status
Simulation time	1208398736 ps
CPU time	27.79 seconds
Started	Aug 29 11:53:12 AM UTC 24
Finished	Aug 29 11:53:41 AM UTC 24
Peak memory	235164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314858032 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.314858032 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/13.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/13.kmac_entropy_refresh.1322257932
Short name	T352
Test name
Test status
Simulation time	96307005861 ps
CPU time	369.25 seconds
Started	Aug 29 11:52:40 AM UTC 24
Finished	Aug 29 11:58:54 AM UTC 24
Peak memory	468892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322257932 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.1322257932 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/13.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/13.kmac_error.1595011507
Short name	T172
Test name
Test status
Simulation time	18053350076 ps
CPU time	337.59 seconds
Started	Aug 29 11:52:42 AM UTC 24
Finished	Aug 29 11:58:24 AM UTC 24
Peak memory	378792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595011507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.1595011507 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/13.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/13.kmac_key_error.712796920
Short name	T277
Test name
Test status
Simulation time	1114934770 ps
CPU time	3.8 seconds
Started	Aug 29 11:52:59 AM UTC 24
Finished	Aug 29 11:53:04 AM UTC 24
Peak memory	230572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712796920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.712796920 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/13.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/13.kmac_lc_escalation.11792956
Short name	T280
Test name
Test status
Simulation time	33416386 ps
CPU time	1.76 seconds
Started	Aug 29 11:53:17 AM UTC 24
Finished	Aug 29 11:53:20 AM UTC 24
Peak memory	229852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11792956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.11792956 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/13.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/13.kmac_long_msg_and_output.976913337
Short name	T434
Test name
Test status
Simulation time	25022101028 ps
CPU time	895.07 seconds
Started	Aug 29 11:52:23 AM UTC 24
Finished	Aug 29 12:07:31 PM UTC 24
Peak memory	1339272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976913337 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_and_output.976913337 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/13.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/13.kmac_sideload.3250245985
Short name	T313
Test name
Test status
Simulation time	29317437019 ps
CPU time	182.23 seconds
Started	Aug 29 11:52:25 AM UTC 24
Finished	Aug 29 11:55:31 AM UTC 24
Peak memory	413588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250245985 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.3250245985 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/13.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/13.kmac_smoke.970932897
Short name	T275
Test name
Test status
Simulation time	905699601 ps
CPU time	19.21 seconds
Started	Aug 29 11:52:20 AM UTC 24
Finished	Aug 29 11:52:41 AM UTC 24
Peak memory	234660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970932897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.970932897 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/13.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/13.kmac_stress_all.3674913699
Short name	T559
Test name
Test status
Simulation time	80112661315 ps
CPU time	1528.11 seconds
Started	Aug 29 11:53:20 AM UTC 24
Finished	Aug 29 12:19:07 PM UTC 24
Peak memory	645224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674913699 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.3674913699 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/13.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/14.kmac_alert_test.3584696751
Short name	T292
Test name
Test status
Simulation time	19800522 ps
CPU time	1.29 seconds
Started	Aug 29 11:54:03 AM UTC 24
Finished	Aug 29 11:54:06 AM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584696751 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.3584696751 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/14.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/14.kmac_app.873927248
Short name	T286
Test name
Test status
Simulation time	591754342 ps
CPU time	10.47 seconds
Started	Aug 29 11:53:43 AM UTC 24
Finished	Aug 29 11:53:55 AM UTC 24
Peak memory	230588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873927248 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.873927248 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/14.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/14.kmac_burst_write.2050066690
Short name	T342
Test name
Test status
Simulation time	6749063136 ps
CPU time	270.06 seconds
Started	Aug 29 11:53:42 AM UTC 24
Finished	Aug 29 11:58:16 AM UTC 24
Peak memory	241440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050066690 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.2050066690 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/14.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/14.kmac_edn_timeout_error.72456491
Short name	T300
Test name
Test status
Simulation time	6716571494 ps
CPU time	50.66 seconds
Started	Aug 29 11:53:56 AM UTC 24
Finished	Aug 29 11:54:49 AM UTC 24
Peak memory	235284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72456491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.72456491 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/14.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/14.kmac_entropy_mode_error.2524049402
Short name	T290
Test name
Test status
Simulation time	177513521 ps
CPU time	4.47 seconds
Started	Aug 29 11:53:56 AM UTC 24
Finished	Aug 29 11:54:02 AM UTC 24
Peak memory	232480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524049402 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.2524049402 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/14.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/14.kmac_entropy_refresh.2680968851
Short name	T305
Test name
Test status
Simulation time	4106325301 ps
CPU time	73.14 seconds
Started	Aug 29 11:53:44 AM UTC 24
Finished	Aug 29 11:54:59 AM UTC 24
Peak memory	253860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680968851 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.2680968851 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/14.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/14.kmac_error.1324644581
Short name	T384
Test name
Test status
Simulation time	16949942121 ps
CPU time	465.32 seconds
Started	Aug 29 11:53:54 AM UTC 24
Finished	Aug 29 12:01:46 PM UTC 24
Peak memory	632652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324644581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.1324644581 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/14.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/14.kmac_key_error.664626468
Short name	T291
Test name
Test status
Simulation time	864116519 ps
CPU time	8.47 seconds
Started	Aug 29 11:53:55 AM UTC 24
Finished	Aug 29 11:54:05 AM UTC 24
Peak memory	230440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664626468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.664626468 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/14.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/14.kmac_long_msg_and_output.3505316864
Short name	T719
Test name
Test status
Simulation time	125461958264 ps
CPU time	4396.98 seconds
Started	Aug 29 11:53:31 AM UTC 24
Finished	Aug 29 01:07:35 PM UTC 24
Peak memory	4616064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505316864 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_and_output.3505316864 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/14.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/14.kmac_sideload.1974185485
Short name	T356
Test name
Test status
Simulation time	38834438571 ps
CPU time	358.62 seconds
Started	Aug 29 11:53:37 AM UTC 24
Finished	Aug 29 11:59:41 AM UTC 24
Peak memory	505880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974185485 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.1974185485 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/14.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/14.kmac_smoke.2465699464
Short name	T295
Test name
Test status
Simulation time	15744681155 ps
CPU time	61.1 seconds
Started	Aug 29 11:53:28 AM UTC 24
Finished	Aug 29 11:54:30 AM UTC 24
Peak memory	230764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465699464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.2465699464 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/14.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/14.kmac_stress_all.2337668802
Short name	T518
Test name
Test status
Simulation time	17441917926 ps
CPU time	1270.51 seconds
Started	Aug 29 11:53:58 AM UTC 24
Finished	Aug 29 12:15:24 PM UTC 24
Peak memory	673752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337668802 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.2337668802 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/14.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/15.kmac_alert_test.2813008678
Short name	T302
Test name
Test status
Simulation time	51633789 ps
CPU time	1.2 seconds
Started	Aug 29 11:54:52 AM UTC 24
Finished	Aug 29 11:54:54 AM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813008678 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.2813008678 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/15.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/15.kmac_app.2589452874
Short name	T351
Test name
Test status
Simulation time	8106664272 ps
CPU time	271.72 seconds
Started	Aug 29 11:54:18 AM UTC 24
Finished	Aug 29 11:58:54 AM UTC 24
Peak memory	421828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589452874 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.2589452874 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/15.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/15.kmac_burst_write.1744603255
Short name	T418
Test name
Test status
Simulation time	23654047004 ps
CPU time	697.22 seconds
Started	Aug 29 11:54:16 AM UTC 24
Finished	Aug 29 12:06:02 PM UTC 24
Peak memory	257840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744603255 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.1744603255 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/15.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/15.kmac_edn_timeout_error.535038570
Short name	T310
Test name
Test status
Simulation time	10179377567 ps
CPU time	39.34 seconds
Started	Aug 29 11:54:45 AM UTC 24
Finished	Aug 29 11:55:26 AM UTC 24
Peak memory	235288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535038570 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.535038570 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/15.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/15.kmac_entropy_mode_error.1869277592
Short name	T303
Test name
Test status
Simulation time	1902472244 ps
CPU time	9.04 seconds
Started	Aug 29 11:54:46 AM UTC 24
Finished	Aug 29 11:54:56 AM UTC 24
Peak memory	232480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869277592 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.1869277592 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/15.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/15.kmac_entropy_refresh.2932621894
Short name	T330
Test name
Test status
Simulation time	12500829828 ps
CPU time	150.62 seconds
Started	Aug 29 11:54:27 AM UTC 24
Finished	Aug 29 11:57:00 AM UTC 24
Peak memory	341980 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932621894 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.2932621894 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/15.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/15.kmac_error.364072552
Short name	T385
Test name
Test status
Simulation time	74421589756 ps
CPU time	432.58 seconds
Started	Aug 29 11:54:31 AM UTC 24
Finished	Aug 29 12:01:50 PM UTC 24
Peak memory	626528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364072552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.364072552 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/15.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/15.kmac_key_error.4127728567
Short name	T297
Test name
Test status
Simulation time	1555639911 ps
CPU time	7.98 seconds
Started	Aug 29 11:54:35 AM UTC 24
Finished	Aug 29 11:54:44 AM UTC 24
Peak memory	230368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127728567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.4127728567 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/15.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/15.kmac_lc_escalation.1948819747
Short name	T301
Test name
Test status
Simulation time	162063063 ps
CPU time	2.4 seconds
Started	Aug 29 11:54:48 AM UTC 24
Finished	Aug 29 11:54:52 AM UTC 24
Peak memory	230440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948819747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.1948819747 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/15.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/15.kmac_long_msg_and_output.511878882
Short name	T488
Test name
Test status
Simulation time	44790935014 ps
CPU time	1132.93 seconds
Started	Aug 29 11:54:07 AM UTC 24
Finished	Aug 29 12:13:13 PM UTC 24
Peak memory	974816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511878882 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_and_output.511878882 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/15.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/15.kmac_sideload.726420203
Short name	T306
Test name
Test status
Simulation time	419130926 ps
CPU time	42.89 seconds
Started	Aug 29 11:54:15 AM UTC 24
Finished	Aug 29 11:54:59 AM UTC 24
Peak memory	239504 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726420203 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.726420203 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/15.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/15.kmac_smoke.644574057
Short name	T299
Test name
Test status
Simulation time	2749212689 ps
CPU time	39.7 seconds
Started	Aug 29 11:54:07 AM UTC 24
Finished	Aug 29 11:54:48 AM UTC 24
Peak memory	230820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644574057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.644574057 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/15.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/15.kmac_stress_all.546904539
Short name	T411
Test name
Test status
Simulation time	21508766825 ps
CPU time	633.29 seconds
Started	Aug 29 11:54:50 AM UTC 24
Finished	Aug 29 12:05:31 PM UTC 24
Peak memory	354656 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546904539 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.546904539 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/15.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/16.kmac_alert_test.2185185021
Short name	T314
Test name
Test status
Simulation time	38882509 ps
CPU time	0.99 seconds
Started	Aug 29 11:55:31 AM UTC 24
Finished	Aug 29 11:55:33 AM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185185021 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.2185185021 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/16.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/16.kmac_app.377172965
Short name	T320
Test name
Test status
Simulation time	11563019761 ps
CPU time	66.05 seconds
Started	Aug 29 11:55:00 AM UTC 24
Finished	Aug 29 11:56:08 AM UTC 24
Peak memory	272216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377172965 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.377172965 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/16.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/16.kmac_burst_write.3159541692
Short name	T489
Test name
Test status
Simulation time	27664259797 ps
CPU time	1081.3 seconds
Started	Aug 29 11:54:59 AM UTC 24
Finished	Aug 29 12:13:13 PM UTC 24
Peak memory	266028 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159541692 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.3159541692 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/16.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/16.kmac_edn_timeout_error.1830301113
Short name	T324
Test name
Test status
Simulation time	4158552437 ps
CPU time	52.24 seconds
Started	Aug 29 11:55:22 AM UTC 24
Finished	Aug 29 11:56:16 AM UTC 24
Peak memory	235376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830301113 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.1830301113 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/16.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/16.kmac_entropy_mode_error.3815664484
Short name	T319
Test name
Test status
Simulation time	1457270631 ps
CPU time	36.57 seconds
Started	Aug 29 11:55:24 AM UTC 24
Finished	Aug 29 11:56:03 AM UTC 24
Peak memory	235084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815664484 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.3815664484 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/16.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/16.kmac_entropy_refresh.3196032868
Short name	T335
Test name
Test status
Simulation time	11557134608 ps
CPU time	145.99 seconds
Started	Aug 29 11:55:00 AM UTC 24
Finished	Aug 29 11:57:29 AM UTC 24
Peak memory	350112 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196032868 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.3196032868 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/16.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/16.kmac_error.1470460831
Short name	T374
Test name
Test status
Simulation time	49564289539 ps
CPU time	341.21 seconds
Started	Aug 29 11:55:09 AM UTC 24
Finished	Aug 29 12:00:55 PM UTC 24
Peak memory	466972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470460831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.1470460831 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/16.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/16.kmac_key_error.604199215
Short name	T316
Test name
Test status
Simulation time	3558639702 ps
CPU time	16.16 seconds
Started	Aug 29 11:55:20 AM UTC 24
Finished	Aug 29 11:55:37 AM UTC 24
Peak memory	230508 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604199215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.604199215 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/16.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/16.kmac_lc_escalation.2706452344
Short name	T312
Test name
Test status
Simulation time	41088552 ps
CPU time	1.86 seconds
Started	Aug 29 11:55:26 AM UTC 24
Finished	Aug 29 11:55:29 AM UTC 24
Peak memory	229912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706452344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.2706452344 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/16.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/16.kmac_long_msg_and_output.4202566540
Short name	T645
Test name
Test status
Simulation time	290988038514 ps
CPU time	1869.81 seconds
Started	Aug 29 11:54:55 AM UTC 24
Finished	Aug 29 12:26:26 PM UTC 24
Peak memory	2281572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202566540 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_and_output.4202566540 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/16.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/16.kmac_sideload.4265783058
Short name	T394
Test name
Test status
Simulation time	13823293521 ps
CPU time	493.81 seconds
Started	Aug 29 11:54:58 AM UTC 24
Finished	Aug 29 12:03:19 PM UTC 24
Peak memory	593744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265783058 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.4265783058 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/16.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/16.kmac_smoke.1978472681
Short name	T321
Test name
Test status
Simulation time	11195705853 ps
CPU time	75.55 seconds
Started	Aug 29 11:54:53 AM UTC 24
Finished	Aug 29 11:56:10 AM UTC 24
Peak memory	234672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978472681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.1978472681 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/16.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/16.kmac_stress_all.780645717
Short name	T495
Test name
Test status
Simulation time	102658649917 ps
CPU time	1082.53 seconds
Started	Aug 29 11:55:29 AM UTC 24
Finished	Aug 29 12:13:45 PM UTC 24
Peak memory	737600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780645717 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.780645717 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/16.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/17.kmac_alert_test.3239235444
Short name	T325
Test name
Test status
Simulation time	15759203 ps
CPU time	1.2 seconds
Started	Aug 29 11:56:15 AM UTC 24
Finished	Aug 29 11:56:17 AM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239235444 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.3239235444 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/17.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/17.kmac_burst_write.3143962431
Short name	T527
Test name
Test status
Simulation time	369154133631 ps
CPU time	1247.01 seconds
Started	Aug 29 11:55:38 AM UTC 24
Finished	Aug 29 12:16:40 PM UTC 24
Peak memory	274268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143962431 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.3143962431 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/17.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/17.kmac_edn_timeout_error.1151777997
Short name	T327
Test name
Test status
Simulation time	267539876 ps
CPU time	26.11 seconds
Started	Aug 29 11:56:03 AM UTC 24
Finished	Aug 29 11:56:31 AM UTC 24
Peak memory	235288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151777997 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.1151777997 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/17.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/17.kmac_entropy_mode_error.763284812
Short name	T329
Test name
Test status
Simulation time	6793470755 ps
CPU time	44.23 seconds
Started	Aug 29 11:56:08 AM UTC 24
Finished	Aug 29 11:56:54 AM UTC 24
Peak memory	234660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763284812 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.763284812 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/17.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/17.kmac_entropy_refresh.3124669099
Short name	T337
Test name
Test status
Simulation time	4589192047 ps
CPU time	100.26 seconds
Started	Aug 29 11:55:52 AM UTC 24
Finished	Aug 29 11:57:35 AM UTC 24
Peak memory	259868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124669099 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.3124669099 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/17.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/17.kmac_error.1466742091
Short name	T363
Test name
Test status
Simulation time	25856017958 ps
CPU time	252.62 seconds
Started	Aug 29 11:55:56 AM UTC 24
Finished	Aug 29 12:00:13 PM UTC 24
Peak memory	415516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466742091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.1466742091 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/17.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/17.kmac_key_error.3005659564
Short name	T322
Test name
Test status
Simulation time	5267871195 ps
CPU time	11.35 seconds
Started	Aug 29 11:55:59 AM UTC 24
Finished	Aug 29 11:56:12 AM UTC 24
Peak memory	230444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005659564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.3005659564 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/17.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/17.kmac_lc_escalation.787140909
Short name	T323
Test name
Test status
Simulation time	79790032 ps
CPU time	2.02 seconds
Started	Aug 29 11:56:11 AM UTC 24
Finished	Aug 29 11:56:14 AM UTC 24
Peak memory	230372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787140909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.787140909 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/17.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/17.kmac_long_msg_and_output.3482599538
Short name	T528
Test name
Test status
Simulation time	146458947420 ps
CPU time	1251.75 seconds
Started	Aug 29 11:55:34 AM UTC 24
Finished	Aug 29 12:16:41 PM UTC 24
Peak memory	1714016 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482599538 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_and_output.3482599538 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/17.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/17.kmac_sideload.3695248889
Short name	T349
Test name
Test status
Simulation time	5870359887 ps
CPU time	181.29 seconds
Started	Aug 29 11:55:35 AM UTC 24
Finished	Aug 29 11:58:40 AM UTC 24
Peak memory	380772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695248889 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.3695248889 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/17.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/17.kmac_smoke.2157466065
Short name	T317
Test name
Test status
Simulation time	1037418364 ps
CPU time	18.27 seconds
Started	Aug 29 11:55:32 AM UTC 24
Finished	Aug 29 11:55:52 AM UTC 24
Peak memory	230584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157466065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.2157466065 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/17.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/17.kmac_stress_all.3331298375
Short name	T714
Test name
Test status
Simulation time	231510542859 ps
CPU time	3374.81 seconds
Started	Aug 29 11:56:13 AM UTC 24
Finished	Aug 29 12:53:06 PM UTC 24
Peak memory	1677416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331298375 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.3331298375 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/17.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/18.kmac_alert_test.3975925817
Short name	T336
Test name
Test status
Simulation time	15259450 ps
CPU time	1.21 seconds
Started	Aug 29 11:57:30 AM UTC 24
Finished	Aug 29 11:57:32 AM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975925817 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.3975925817 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/18.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/18.kmac_app.2052642160
Short name	T383
Test name
Test status
Simulation time	17070607416 ps
CPU time	300.48 seconds
Started	Aug 29 11:56:39 AM UTC 24
Finished	Aug 29 12:01:44 PM UTC 24
Peak memory	493404 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052642160 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.2052642160 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/18.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/18.kmac_burst_write.3463792891
Short name	T357
Test name
Test status
Simulation time	19228465178 ps
CPU time	188.91 seconds
Started	Aug 29 11:56:32 AM UTC 24
Finished	Aug 29 11:59:44 AM UTC 24
Peak memory	237408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463792891 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.3463792891 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/18.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/18.kmac_edn_timeout_error.2897938716
Short name	T339
Test name
Test status
Simulation time	1824898310 ps
CPU time	34.5 seconds
Started	Aug 29 11:57:13 AM UTC 24
Finished	Aug 29 11:57:50 AM UTC 24
Peak memory	232468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897938716 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.2897938716 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/18.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/18.kmac_entropy_mode_error.1024393383
Short name	T338
Test name
Test status
Simulation time	607849116 ps
CPU time	22.24 seconds
Started	Aug 29 11:57:18 AM UTC 24
Finished	Aug 29 11:57:41 AM UTC 24
Peak memory	232420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024393383 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.1024393383 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/18.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/18.kmac_entropy_refresh.1105095686
Short name	T333
Test name
Test status
Simulation time	4995676571 ps
CPU time	26.1 seconds
Started	Aug 29 11:56:55 AM UTC 24
Finished	Aug 29 11:57:23 AM UTC 24
Peak memory	239700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105095686 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.1105095686 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/18.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/18.kmac_error.961650419
Short name	T389
Test name
Test status
Simulation time	16499071558 ps
CPU time	311.88 seconds
Started	Aug 29 11:57:01 AM UTC 24
Finished	Aug 29 12:02:17 PM UTC 24
Peak memory	376864 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961650419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.961650419 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/18.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/18.kmac_key_error.239477149
Short name	T332
Test name
Test status
Simulation time	835211894 ps
CPU time	4.87 seconds
Started	Aug 29 11:57:10 AM UTC 24
Finished	Aug 29 11:57:17 AM UTC 24
Peak memory	230620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239477149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.239477149 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/18.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/18.kmac_lc_escalation.469788809
Short name	T334
Test name
Test status
Simulation time	141306669 ps
CPU time	1.83 seconds
Started	Aug 29 11:57:24 AM UTC 24
Finished	Aug 29 11:57:26 AM UTC 24
Peak memory	234584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469788809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.469788809 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/18.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/18.kmac_long_msg_and_output.3553930820
Short name	T616
Test name
Test status
Simulation time	144733461383 ps
CPU time	1645.86 seconds
Started	Aug 29 11:56:18 AM UTC 24
Finished	Aug 29 12:24:03 PM UTC 24
Peak memory	2101152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553930820 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_and_output.3553930820 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/18.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/18.kmac_sideload.609997910
Short name	T391
Test name
Test status
Simulation time	12231159041 ps
CPU time	379.41 seconds
Started	Aug 29 11:56:28 AM UTC 24
Finished	Aug 29 12:02:53 PM UTC 24
Peak memory	497488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609997910 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.609997910 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/18.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/18.kmac_smoke.380224242
Short name	T328
Test name
Test status
Simulation time	816480333 ps
CPU time	19.93 seconds
Started	Aug 29 11:56:17 AM UTC 24
Finished	Aug 29 11:56:38 AM UTC 24
Peak memory	230688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380224242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.380224242 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/18.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/18.kmac_stress_all.2577187319
Short name	T380
Test name
Test status
Simulation time	11198692888 ps
CPU time	240.64 seconds
Started	Aug 29 11:57:28 AM UTC 24
Finished	Aug 29 12:01:32 PM UTC 24
Peak memory	401564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577187319 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.2577187319 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/18.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/19.kmac_alert_test.4195525829
Short name	T348
Test name
Test status
Simulation time	10531791 ps
CPU time	1.12 seconds
Started	Aug 29 11:58:33 AM UTC 24
Finished	Aug 29 11:58:35 AM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195525829 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.4195525829 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/19.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/19.kmac_app.3344251940
Short name	T365
Test name
Test status
Simulation time	11870123931 ps
CPU time	150.75 seconds
Started	Aug 29 11:57:57 AM UTC 24
Finished	Aug 29 12:00:31 PM UTC 24
Peak memory	321500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344251940 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.3344251940 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/19.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/19.kmac_burst_write.179897453
Short name	T469
Test name
Test status
Simulation time	84614681161 ps
CPU time	845.28 seconds
Started	Aug 29 11:57:50 AM UTC 24
Finished	Aug 29 12:12:06 PM UTC 24
Peak memory	257844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179897453 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.179897453 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/19.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/19.kmac_edn_timeout_error.172073771
Short name	T350
Test name
Test status
Simulation time	1832547991 ps
CPU time	16.24 seconds
Started	Aug 29 11:58:26 AM UTC 24
Finished	Aug 29 11:58:43 AM UTC 24
Peak memory	232468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172073771 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.172073771 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/19.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/19.kmac_entropy_mode_error.3236995875
Short name	T347
Test name
Test status
Simulation time	288849472 ps
CPU time	5.4 seconds
Started	Aug 29 11:58:26 AM UTC 24
Finished	Aug 29 11:58:32 AM UTC 24
Peak memory	230392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236995875 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.3236995875 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/19.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/19.kmac_entropy_refresh.727807137
Short name	T392
Test name
Test status
Simulation time	8296500145 ps
CPU time	287.51 seconds
Started	Aug 29 11:58:16 AM UTC 24
Finished	Aug 29 12:03:08 PM UTC 24
Peak memory	329560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727807137 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.727807137 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/19.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/19.kmac_error.2378435735
Short name	T344
Test name
Test status
Simulation time	65488130 ps
CPU time	7.42 seconds
Started	Aug 29 11:58:16 AM UTC 24
Finished	Aug 29 11:58:25 AM UTC 24
Peak memory	235424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378435735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.2378435735 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/19.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/19.kmac_key_error.2278960527
Short name	T345
Test name
Test status
Simulation time	955061121 ps
CPU time	3.28 seconds
Started	Aug 29 11:58:20 AM UTC 24
Finished	Aug 29 11:58:25 AM UTC 24
Peak memory	230380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278960527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.2278960527 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/19.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/19.kmac_lc_escalation.53692704
Short name	T346
Test name
Test status
Simulation time	44400865 ps
CPU time	1.95 seconds
Started	Aug 29 11:58:27 AM UTC 24
Finished	Aug 29 11:58:30 AM UTC 24
Peak memory	229848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53692704 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.53692704 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/19.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/19.kmac_long_msg_and_output.3414213244
Short name	T721
Test name
Test status
Simulation time	454355709783 ps
CPU time	4381.88 seconds
Started	Aug 29 11:57:36 AM UTC 24
Finished	Aug 29 01:11:26 PM UTC 24
Peak memory	4351944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414213244 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_and_output.3414213244 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/19.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/19.kmac_sideload.1616479534
Short name	T402
Test name
Test status
Simulation time	17904084027 ps
CPU time	382.79 seconds
Started	Aug 29 11:57:42 AM UTC 24
Finished	Aug 29 12:04:10 PM UTC 24
Peak memory	378896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616479534 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.1616479534 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/19.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/19.kmac_smoke.992801051
Short name	T340
Test name
Test status
Simulation time	460390160 ps
CPU time	22.01 seconds
Started	Aug 29 11:57:33 AM UTC 24
Finished	Aug 29 11:57:56 AM UTC 24
Peak memory	230688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992801051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.992801051 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/19.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/2.kmac_alert_test.3986151373
Short name	T198
Test name
Test status
Simulation time	23144821 ps
CPU time	1.16 seconds
Started	Aug 29 11:44:58 AM UTC 24
Finished	Aug 29 11:45:00 AM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986151373 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.3986151373 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/2.kmac_app.1636741580
Short name	T33
Test name
Test status
Simulation time	17395574116 ps
CPU time	116.61 seconds
Started	Aug 29 11:44:40 AM UTC 24
Finished	Aug 29 11:46:39 AM UTC 24
Peak memory	317264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636741580 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.1636741580 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/2.kmac_app_with_partial_data.3061960533
Short name	T27
Test name
Test status
Simulation time	2135042967 ps
CPU time	90.44 seconds
Started	Aug 29 11:44:41 AM UTC 24
Finished	Aug 29 11:46:13 AM UTC 24
Peak memory	257964 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061960533 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.3061960533 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_app_with_partial_data/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/2.kmac_burst_write.3529694196
Short name	T156
Test name
Test status
Simulation time	5917240811 ps
CPU time	228.22 seconds
Started	Aug 29 11:44:20 AM UTC 24
Finished	Aug 29 11:48:12 AM UTC 24
Peak memory	239372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529694196 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.3529694196 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/2.kmac_edn_timeout_error.1077847913
Short name	T94
Test name
Test status
Simulation time	60378985 ps
CPU time	4.69 seconds
Started	Aug 29 11:44:49 AM UTC 24
Finished	Aug 29 11:44:55 AM UTC 24
Peak memory	230484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077847913 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.1077847913 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_mode_error.2277896659
Short name	T52
Test name
Test status
Simulation time	1184573371 ps
CPU time	6.3 seconds
Started	Aug 29 11:44:49 AM UTC 24
Finished	Aug 29 11:44:57 AM UTC 24
Peak memory	228372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277896659 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.2277896659 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_ready_error.2023118172
Short name	T59
Test name
Test status
Simulation time	34023166909 ps
CPU time	102.45 seconds
Started	Aug 29 11:44:50 AM UTC 24
Finished	Aug 29 11:46:35 AM UTC 24
Peak memory	230832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023118172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.2023118172 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_entropy_ready_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_refresh.1500268737
Short name	T117
Test name
Test status
Simulation time	8378064260 ps
CPU time	229.34 seconds
Started	Aug 29 11:44:42 AM UTC 24
Finished	Aug 29 11:48:35 AM UTC 24
Peak memory	442204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500268737 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.1500268737 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/2.kmac_error.62839481
Short name	T25
Test name
Test status
Simulation time	2998104241 ps
CPU time	23.32 seconds
Started	Aug 29 11:44:45 AM UTC 24
Finished	Aug 29 11:45:10 AM UTC 24
Peak memory	251740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62839481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.62839481 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/2.kmac_key_error.1628751649
Short name	T20
Test name
Test status
Simulation time	1068769318 ps
CPU time	8.37 seconds
Started	Aug 29 11:44:47 AM UTC 24
Finished	Aug 29 11:44:57 AM UTC 24
Peak memory	230376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628751649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.1628751649 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/2.kmac_long_msg_and_output.1731250205
Short name	T226
Test name
Test status
Simulation time	10049624253 ps
CPU time	317.58 seconds
Started	Aug 29 11:44:19 AM UTC 24
Finished	Aug 29 11:49:41 AM UTC 24
Peak memory	630556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731250205 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and_output.1731250205 +enable_mas king=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/2.kmac_mubi.394544566
Short name	T23
Test name
Test status
Simulation time	5817130003 ps
CPU time	19.25 seconds
Started	Aug 29 11:44:44 AM UTC 24
Finished	Aug 29 11:45:04 AM UTC 24
Peak memory	243996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394544566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.394544566 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/2.kmac_sec_cm.3181279419
Short name	T11
Test name
Test status
Simulation time	1542950962 ps
CPU time	32.49 seconds
Started	Aug 29 11:44:56 AM UTC 24
Finished	Aug 29 11:45:29 AM UTC 24
Peak memory	264836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181279419 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.3181279419 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/2.kmac_sideload.1680904339
Short name	T217
Test name
Test status
Simulation time	8206608815 ps
CPU time	289.55 seconds
Started	Aug 29 11:44:20 AM UTC 24
Finished	Aug 29 11:49:13 AM UTC 24
Peak memory	352056 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680904339 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.1680904339 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/2.kmac_smoke.2486775171
Short name	T40
Test name
Test status
Simulation time	216339652 ps
CPU time	14.13 seconds
Started	Aug 29 11:44:16 AM UTC 24
Finished	Aug 29 11:44:31 AM UTC 24
Peak memory	230696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486775171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.2486775171 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/2.kmac_stress_all.125696630
Short name	T157
Test name
Test status
Simulation time	6081515277 ps
CPU time	270.38 seconds
Started	Aug 29 11:44:53 AM UTC 24
Finished	Aug 29 11:49:28 AM UTC 24
Peak memory	311116 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125696630 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.125696630 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac.2796768748
Short name	T80
Test name
Test status
Simulation time	62991598 ps
CPU time	3.11 seconds
Started	Aug 29 11:44:35 AM UTC 24
Finished	Aug 29 11:44:40 AM UTC 24
Peak memory	230568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796768748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac.2796768748 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_test_vectors_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac_xof.4167442983
Short name	T81
Test name
Test status
Simulation time	91289786 ps
CPU time	2.44 seconds
Started	Aug 29 11:44:38 AM UTC 24
Finished	Aug 29 11:44:41 AM UTC 24
Peak memory	230648 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167442983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.4167442983 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_test_vectors_kmac_xof/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_224.2541547661
Short name	T515
Test name
Test status
Simulation time	21910282772 ps
CPU time	1833.43 seconds
Started	Aug 29 11:44:21 AM UTC 24
Finished	Aug 29 12:15:17 PM UTC 24
Peak memory	1191616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541547661 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.2541547661 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_224/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_256.3879758095
Short name	T676
Test name
Test status
Simulation time	354379951555 ps
CPU time	2718.69 seconds
Started	Aug 29 11:44:22 AM UTC 24
Finished	Aug 29 12:30:11 PM UTC 24
Peak memory	3057340 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879758095 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.3879758095 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_256/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_384.3044109477
Short name	T473
Test name
Test status
Simulation time	60189541949 ps
CPU time	1649.66 seconds
Started	Aug 29 11:44:23 AM UTC 24
Finished	Aug 29 12:12:11 PM UTC 24
Peak memory	2354880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044109477 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.3044109477 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_384/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_512.943432512
Short name	T83
Test name
Test status
Simulation time	273824521 ps
CPU time	17.98 seconds
Started	Aug 29 11:44:30 AM UTC 24
Finished	Aug 29 11:44:49 AM UTC 24
Peak memory	230636 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943432512 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.943432512 + enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_512/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_128.2905543015
Short name	T122
Test name
Test status
Simulation time	2191057979 ps
CPU time	144.31 seconds
Started	Aug 29 11:44:31 AM UTC 24
Finished	Aug 29 11:46:58 AM UTC 24
Peak memory	286476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905543015 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.2905543 015 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_128/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_256.33726577
Short name	T197
Test name
Test status
Simulation time	19610276369 ps
CPU time	377.96 seconds
Started	Aug 29 11:44:33 AM UTC 24
Finished	Aug 29 11:50:57 AM UTC 24
Peak memory	360128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33726577 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.33726577 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_256/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/20.kmac_alert_test.44040543
Short name	T359
Test name
Test status
Simulation time	13520762 ps
CPU time	1.17 seconds
Started	Aug 29 11:59:46 AM UTC 24
Finished	Aug 29 11:59:48 AM UTC 24
Peak memory	216392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44040543 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.44040543 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/20.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/20.kmac_app.2669217829
Short name	T401
Test name
Test status
Simulation time	46042841032 ps
CPU time	294.92 seconds
Started	Aug 29 11:58:55 AM UTC 24
Finished	Aug 29 12:03:54 PM UTC 24
Peak memory	487188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669217829 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.2669217829 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/20.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/20.kmac_burst_write.1060959805
Short name	T437
Test name
Test status
Simulation time	53618535450 ps
CPU time	530.9 seconds
Started	Aug 29 11:58:55 AM UTC 24
Finished	Aug 29 12:07:53 PM UTC 24
Peak memory	247712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060959805 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.1060959805 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/20.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/20.kmac_entropy_refresh.2713273742
Short name	T378
Test name
Test status
Simulation time	10198444526 ps
CPU time	138.98 seconds
Started	Aug 29 11:59:00 AM UTC 24
Finished	Aug 29 12:01:22 PM UTC 24
Peak memory	327516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713273742 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.2713273742 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/20.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/20.kmac_error.2822854458
Short name	T393
Test name
Test status
Simulation time	53618556629 ps
CPU time	238.93 seconds
Started	Aug 29 11:59:13 AM UTC 24
Finished	Aug 29 12:03:16 PM UTC 24
Peak memory	321380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822854458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.2822854458 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/20.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/20.kmac_key_error.1333482536
Short name	T360
Test name
Test status
Simulation time	989380689 ps
CPU time	5.5 seconds
Started	Aug 29 11:59:42 AM UTC 24
Finished	Aug 29 11:59:48 AM UTC 24
Peak memory	230456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333482536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.1333482536 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/20.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/20.kmac_lc_escalation.2912802878
Short name	T358
Test name
Test status
Simulation time	90053738 ps
CPU time	2.04 seconds
Started	Aug 29 11:59:42 AM UTC 24
Finished	Aug 29 11:59:45 AM UTC 24
Peak memory	235268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912802878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.2912802878 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/20.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/20.kmac_long_msg_and_output.2996223129
Short name	T679
Test name
Test status
Simulation time	48466762096 ps
CPU time	1920.44 seconds
Started	Aug 29 11:58:41 AM UTC 24
Finished	Aug 29 12:31:03 PM UTC 24
Peak memory	2426920 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996223129 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_and_output.2996223129 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/20.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/20.kmac_sideload.2678501935
Short name	T409
Test name
Test status
Simulation time	25043204372 ps
CPU time	389.86 seconds
Started	Aug 29 11:58:44 AM UTC 24
Finished	Aug 29 12:05:19 PM UTC 24
Peak memory	563028 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678501935 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.2678501935 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/20.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/20.kmac_smoke.1316361179
Short name	T355
Test name
Test status
Simulation time	31288779464 ps
CPU time	62.78 seconds
Started	Aug 29 11:58:36 AM UTC 24
Finished	Aug 29 11:59:41 AM UTC 24
Peak memory	235356 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316361179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.1316361179 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/20.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/20.kmac_stress_all.3240758271
Short name	T404
Test name
Test status
Simulation time	11315975996 ps
CPU time	283.64 seconds
Started	Aug 29 11:59:45 AM UTC 24
Finished	Aug 29 12:04:33 PM UTC 24
Peak memory	417936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240758271 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.3240758271 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/20.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/21.kmac_alert_test.3692749400
Short name	T371
Test name
Test status
Simulation time	15234324 ps
CPU time	1.2 seconds
Started	Aug 29 12:00:48 PM UTC 24
Finished	Aug 29 12:00:50 PM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692749400 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.3692749400 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/21.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/21.kmac_app.2581426418
Short name	T412
Test name
Test status
Simulation time	10101339918 ps
CPU time	319.69 seconds
Started	Aug 29 12:00:13 PM UTC 24
Finished	Aug 29 12:05:38 PM UTC 24
Peak memory	442264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581426418 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.2581426418 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/21.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/21.kmac_burst_write.1789481992
Short name	T193
Test name
Test status
Simulation time	6754640725 ps
CPU time	276.78 seconds
Started	Aug 29 12:00:06 PM UTC 24
Finished	Aug 29 12:04:47 PM UTC 24
Peak memory	241500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789481992 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.1789481992 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/21.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/21.kmac_entropy_refresh.3732820360
Short name	T367
Test name
Test status
Simulation time	780996258 ps
CPU time	20.99 seconds
Started	Aug 29 12:00:14 PM UTC 24
Finished	Aug 29 12:00:37 PM UTC 24
Peak memory	247580 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732820360 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.3732820360 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/21.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/21.kmac_error.119365493
Short name	T397
Test name
Test status
Simulation time	8626901527 ps
CPU time	184.64 seconds
Started	Aug 29 12:00:31 PM UTC 24
Finished	Aug 29 12:03:39 PM UTC 24
Peak memory	421640 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119365493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.119365493 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/21.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/21.kmac_key_error.370987807
Short name	T369
Test name
Test status
Simulation time	3704610739 ps
CPU time	11.56 seconds
Started	Aug 29 12:00:35 PM UTC 24
Finished	Aug 29 12:00:47 PM UTC 24
Peak memory	230560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370987807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.370987807 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/21.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/21.kmac_long_msg_and_output.3183759087
Short name	T366
Test name
Test status
Simulation time	899228547 ps
CPU time	42.89 seconds
Started	Aug 29 11:59:49 AM UTC 24
Finished	Aug 29 12:00:33 PM UTC 24
Peak memory	251812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183759087 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_and_output.3183759087 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/21.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/21.kmac_sideload.3387528399
Short name	T373
Test name
Test status
Simulation time	3681515623 ps
CPU time	59.52 seconds
Started	Aug 29 11:59:53 AM UTC 24
Finished	Aug 29 12:00:54 PM UTC 24
Peak memory	253920 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387528399 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.3387528399 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/21.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/21.kmac_smoke.2497078513
Short name	T370
Test name
Test status
Simulation time	2052121962 ps
CPU time	57.62 seconds
Started	Aug 29 11:59:49 AM UTC 24
Finished	Aug 29 12:00:48 PM UTC 24
Peak memory	230584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497078513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.2497078513 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/21.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/21.kmac_stress_all.1729676610
Short name	T447
Test name
Test status
Simulation time	13122908908 ps
CPU time	514.68 seconds
Started	Aug 29 12:00:42 PM UTC 24
Finished	Aug 29 12:09:23 PM UTC 24
Peak memory	364692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729676610 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.1729676610 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/21.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/22.kmac_alert_test.3595744489
Short name	T379
Test name
Test status
Simulation time	78599212 ps
CPU time	1.25 seconds
Started	Aug 29 12:01:21 PM UTC 24
Finished	Aug 29 12:01:24 PM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595744489 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.3595744489 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/22.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/22.kmac_app.2911747058
Short name	T375
Test name
Test status
Simulation time	383809593 ps
CPU time	15.64 seconds
Started	Aug 29 12:00:53 PM UTC 24
Finished	Aug 29 12:01:10 PM UTC 24
Peak memory	234596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911747058 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.2911747058 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/22.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/22.kmac_burst_write.3285537561
Short name	T546
Test name
Test status
Simulation time	220782279293 ps
CPU time	1017.74 seconds
Started	Aug 29 12:00:52 PM UTC 24
Finished	Aug 29 12:18:01 PM UTC 24
Peak memory	272220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285537561 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.3285537561 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/22.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/22.kmac_entropy_refresh.1120011164
Short name	T376
Test name
Test status
Simulation time	964685670 ps
CPU time	14.8 seconds
Started	Aug 29 12:00:55 PM UTC 24
Finished	Aug 29 12:01:11 PM UTC 24
Peak memory	232692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120011164 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.1120011164 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/22.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/22.kmac_error.3769639259
Short name	T386
Test name
Test status
Simulation time	707523227 ps
CPU time	63.71 seconds
Started	Aug 29 12:00:56 PM UTC 24
Finished	Aug 29 12:02:01 PM UTC 24
Peak memory	261840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769639259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.3769639259 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/22.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/22.kmac_key_error.3403859656
Short name	T377
Test name
Test status
Simulation time	2764947900 ps
CPU time	9.1 seconds
Started	Aug 29 12:01:10 PM UTC 24
Finished	Aug 29 12:01:21 PM UTC 24
Peak memory	230488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403859656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.3403859656 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/22.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/22.kmac_lc_escalation.3772244984
Short name	T8
Test name
Test status
Simulation time	73763587 ps
CPU time	1.72 seconds
Started	Aug 29 12:01:12 PM UTC 24
Finished	Aug 29 12:01:15 PM UTC 24
Peak memory	231844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772244984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.3772244984 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/22.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/22.kmac_long_msg_and_output.2709112156
Short name	T701
Test name
Test status
Simulation time	20466679570 ps
CPU time	2278 seconds
Started	Aug 29 12:00:49 PM UTC 24
Finished	Aug 29 12:39:15 PM UTC 24
Peak memory	1439584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709112156 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_and_output.2709112156 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/22.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/22.kmac_sideload.3129516221
Short name	T433
Test name
Test status
Simulation time	3838826801 ps
CPU time	393.78 seconds
Started	Aug 29 12:00:51 PM UTC 24
Finished	Aug 29 12:07:30 PM UTC 24
Peak memory	354064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129516221 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.3129516221 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/22.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/22.kmac_smoke.1126321537
Short name	T382
Test name
Test status
Simulation time	952352672 ps
CPU time	49.47 seconds
Started	Aug 29 12:00:48 PM UTC 24
Finished	Aug 29 12:01:39 PM UTC 24
Peak memory	230516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126321537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.1126321537 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/22.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/22.kmac_stress_all.4225914149
Short name	T485
Test name
Test status
Simulation time	42591975222 ps
CPU time	684.25 seconds
Started	Aug 29 12:01:16 PM UTC 24
Finished	Aug 29 12:12:50 PM UTC 24
Peak memory	917600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225914149 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.4225914149 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/22.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/23.kmac_alert_test.820962754
Short name	T388
Test name
Test status
Simulation time	58541802 ps
CPU time	1.16 seconds
Started	Aug 29 12:02:06 PM UTC 24
Finished	Aug 29 12:02:08 PM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820962754 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.820962754 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/23.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/23.kmac_app.2633958713
Short name	T422
Test name
Test status
Simulation time	49150148027 ps
CPU time	275.54 seconds
Started	Aug 29 12:01:40 PM UTC 24
Finished	Aug 29 12:06:20 PM UTC 24
Peak memory	438096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633958713 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.2633958713 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/23.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/23.kmac_burst_write.3469972319
Short name	T403
Test name
Test status
Simulation time	1276862002 ps
CPU time	152.55 seconds
Started	Aug 29 12:01:35 PM UTC 24
Finished	Aug 29 12:04:10 PM UTC 24
Peak memory	235424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469972319 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.3469972319 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/23.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/23.kmac_entropy_refresh.3881332511
Short name	T441
Test name
Test status
Simulation time	52124354313 ps
CPU time	370.59 seconds
Started	Aug 29 12:01:45 PM UTC 24
Finished	Aug 29 12:08:01 PM UTC 24
Peak memory	483160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881332511 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.3881332511 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/23.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/23.kmac_error.2665288000
Short name	T429
Test name
Test status
Simulation time	33898654955 ps
CPU time	319.12 seconds
Started	Aug 29 12:01:47 PM UTC 24
Finished	Aug 29 12:07:12 PM UTC 24
Peak memory	485216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665288000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.2665288000 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/23.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/23.kmac_key_error.1727163156
Short name	T387
Test name
Test status
Simulation time	1678989467 ps
CPU time	8.82 seconds
Started	Aug 29 12:01:51 PM UTC 24
Finished	Aug 29 12:02:02 PM UTC 24
Peak memory	230676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727163156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.1727163156 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/23.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/23.kmac_lc_escalation.639495050
Short name	T97
Test name
Test status
Simulation time	81761568 ps
CPU time	1.7 seconds
Started	Aug 29 12:02:02 PM UTC 24
Finished	Aug 29 12:02:05 PM UTC 24
Peak memory	229732 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639495050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.639495050 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/23.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/23.kmac_long_msg_and_output.2582063839
Short name	T718
Test name
Test status
Simulation time	535272875125 ps
CPU time	3804.7 seconds
Started	Aug 29 12:01:24 PM UTC 24
Finished	Aug 29 01:05:32 PM UTC 24
Peak memory	3843916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582063839 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_and_output.2582063839 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/23.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/23.kmac_sideload.170678060
Short name	T396
Test name
Test status
Simulation time	3392338891 ps
CPU time	122.38 seconds
Started	Aug 29 12:01:32 PM UTC 24
Finished	Aug 29 12:03:37 PM UTC 24
Peak memory	315216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170678060 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.170678060 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/23.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/23.kmac_smoke.4050975546
Short name	T381
Test name
Test status
Simulation time	234920466 ps
CPU time	8.73 seconds
Started	Aug 29 12:01:23 PM UTC 24
Finished	Aug 29 12:01:34 PM UTC 24
Peak memory	230688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050975546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.4050975546 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/23.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/23.kmac_stress_all.2158162366
Short name	T666
Test name
Test status
Simulation time	16401048845 ps
CPU time	1538.25 seconds
Started	Aug 29 12:02:03 PM UTC 24
Finished	Aug 29 12:28:00 PM UTC 24
Peak memory	661664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158162366 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.2158162366 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/23.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/24.kmac_alert_test.2278060183
Short name	T400
Test name
Test status
Simulation time	24376247 ps
CPU time	1.17 seconds
Started	Aug 29 12:03:42 PM UTC 24
Finished	Aug 29 12:03:45 PM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278060183 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.2278060183 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/24.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/24.kmac_app.3217285148
Short name	T431
Test name
Test status
Simulation time	5160995389 ps
CPU time	248.19 seconds
Started	Aug 29 12:03:09 PM UTC 24
Finished	Aug 29 12:07:21 PM UTC 24
Peak memory	333660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217285148 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.3217285148 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/24.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/24.kmac_burst_write.1514284582
Short name	T442
Test name
Test status
Simulation time	2785664421 ps
CPU time	308.37 seconds
Started	Aug 29 12:02:54 PM UTC 24
Finished	Aug 29 12:08:07 PM UTC 24
Peak memory	239456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514284582 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.1514284582 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/24.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/24.kmac_entropy_refresh.1002801571
Short name	T443
Test name
Test status
Simulation time	12815526040 ps
CPU time	325.12 seconds
Started	Aug 29 12:03:17 PM UTC 24
Finished	Aug 29 12:08:47 PM UTC 24
Peak memory	450532 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002801571 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.1002801571 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/24.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/24.kmac_error.3421291126
Short name	T446
Test name
Test status
Simulation time	12007448923 ps
CPU time	352.55 seconds
Started	Aug 29 12:03:20 PM UTC 24
Finished	Aug 29 12:09:17 PM UTC 24
Peak memory	540632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421291126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.3421291126 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/24.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/24.kmac_key_error.1025650097
Short name	T399
Test name
Test status
Simulation time	13840377490 ps
CPU time	7.97 seconds
Started	Aug 29 12:03:34 PM UTC 24
Finished	Aug 29 12:03:43 PM UTC 24
Peak memory	230440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025650097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.1025650097 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/24.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/24.kmac_lc_escalation.3621489961
Short name	T398
Test name
Test status
Simulation time	377793298 ps
CPU time	2.1 seconds
Started	Aug 29 12:03:38 PM UTC 24
Finished	Aug 29 12:03:41 PM UTC 24
Peak memory	235080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621489961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.3621489961 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/24.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/24.kmac_long_msg_and_output.2553804071
Short name	T716
Test name
Test status
Simulation time	57073832866 ps
CPU time	3160.56 seconds
Started	Aug 29 12:02:18 PM UTC 24
Finished	Aug 29 12:55:36 PM UTC 24
Peak memory	1931108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553804071 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_and_output.2553804071 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/24.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/24.kmac_sideload.1785370674
Short name	T413
Test name
Test status
Simulation time	3019994399 ps
CPU time	199.4 seconds
Started	Aug 29 12:02:23 PM UTC 24
Finished	Aug 29 12:05:46 PM UTC 24
Peak memory	331716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785370674 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.1785370674 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/24.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/24.kmac_smoke.1107129108
Short name	T390
Test name
Test status
Simulation time	1632962501 ps
CPU time	11.91 seconds
Started	Aug 29 12:02:09 PM UTC 24
Finished	Aug 29 12:02:23 PM UTC 24
Peak memory	230704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107129108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.1107129108 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/24.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/24.kmac_stress_all.1896472892
Short name	T420
Test name
Test status
Simulation time	5536127660 ps
CPU time	142.19 seconds
Started	Aug 29 12:03:40 PM UTC 24
Finished	Aug 29 12:06:05 PM UTC 24
Peak memory	334164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896472892 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.1896472892 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/24.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/25.kmac_alert_test.485603132
Short name	T408
Test name
Test status
Simulation time	54227127 ps
CPU time	1.18 seconds
Started	Aug 29 12:04:49 PM UTC 24
Finished	Aug 29 12:04:52 PM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485603132 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.485603132 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/25.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/25.kmac_app.2445016837
Short name	T453
Test name
Test status
Simulation time	11247392182 ps
CPU time	324.88 seconds
Started	Aug 29 12:04:11 PM UTC 24
Finished	Aug 29 12:09:41 PM UTC 24
Peak memory	497476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445016837 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.2445016837 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/25.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/25.kmac_burst_write.387789878
Short name	T603
Test name
Test status
Simulation time	30594624386 ps
CPU time	1119.84 seconds
Started	Aug 29 12:04:11 PM UTC 24
Finished	Aug 29 12:23:04 PM UTC 24
Peak memory	268124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387789878 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.387789878 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/25.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/25.kmac_entropy_refresh.3427995420
Short name	T444
Test name
Test status
Simulation time	12085243362 ps
CPU time	258.98 seconds
Started	Aug 29 12:04:35 PM UTC 24
Finished	Aug 29 12:08:58 PM UTC 24
Peak memory	335628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427995420 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.3427995420 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/25.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/25.kmac_error.1303541669
Short name	T480
Test name
Test status
Simulation time	12204055170 ps
CPU time	465.18 seconds
Started	Aug 29 12:04:39 PM UTC 24
Finished	Aug 29 12:12:31 PM UTC 24
Peak memory	571312 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303541669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.1303541669 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/25.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/25.kmac_key_error.2193609757
Short name	T407
Test name
Test status
Simulation time	6420862759 ps
CPU time	11.37 seconds
Started	Aug 29 12:04:39 PM UTC 24
Finished	Aug 29 12:04:52 PM UTC 24
Peak memory	230576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193609757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.2193609757 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/25.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/25.kmac_lc_escalation.2303231613
Short name	T406
Test name
Test status
Simulation time	104346516 ps
CPU time	1.76 seconds
Started	Aug 29 12:04:45 PM UTC 24
Finished	Aug 29 12:04:48 PM UTC 24
Peak memory	231840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303231613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.2303231613 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/25.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/25.kmac_long_msg_and_output.3075278320
Short name	T709
Test name
Test status
Simulation time	25139712548 ps
CPU time	2582.71 seconds
Started	Aug 29 12:03:45 PM UTC 24
Finished	Aug 29 12:47:17 PM UTC 24
Peak memory	1711952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075278320 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_and_output.3075278320 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/25.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/25.kmac_sideload.3679180821
Short name	T465
Test name
Test status
Simulation time	136962917816 ps
CPU time	455.17 seconds
Started	Aug 29 12:03:55 PM UTC 24
Finished	Aug 29 12:11:36 PM UTC 24
Peak memory	593760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679180821 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.3679180821 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/25.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/25.kmac_smoke.1283859096
Short name	T405
Test name
Test status
Simulation time	1571400568 ps
CPU time	52.36 seconds
Started	Aug 29 12:03:44 PM UTC 24
Finished	Aug 29 12:04:38 PM UTC 24
Peak memory	230704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283859096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.1283859096 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/25.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/25.kmac_stress_all.1952821109
Short name	T627
Test name
Test status
Simulation time	14433919726 ps
CPU time	1193.1 seconds
Started	Aug 29 12:04:49 PM UTC 24
Finished	Aug 29 12:24:57 PM UTC 24
Peak memory	514172 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952821109 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.1952821109 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/25.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/26.kmac_alert_test.986895847
Short name	T421
Test name
Test status
Simulation time	24254249 ps
CPU time	1.33 seconds
Started	Aug 29 12:06:04 PM UTC 24
Finished	Aug 29 12:06:06 PM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986895847 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.986895847 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/26.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/26.kmac_app.2863431497
Short name	T416
Test name
Test status
Simulation time	2053964842 ps
CPU time	25.28 seconds
Started	Aug 29 12:05:32 PM UTC 24
Finished	Aug 29 12:05:59 PM UTC 24
Peak memory	237632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863431497 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.2863431497 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/26.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/26.kmac_burst_write.1769388702
Short name	T498
Test name
Test status
Simulation time	15574001106 ps
CPU time	522.8 seconds
Started	Aug 29 12:05:28 PM UTC 24
Finished	Aug 29 12:14:18 PM UTC 24
Peak memory	249696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769388702 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.1769388702 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/26.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/26.kmac_entropy_refresh.1686561170
Short name	T454
Test name
Test status
Simulation time	14178968356 ps
CPU time	250.28 seconds
Started	Aug 29 12:05:40 PM UTC 24
Finished	Aug 29 12:09:54 PM UTC 24
Peak memory	311236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686561170 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.1686561170 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/26.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/26.kmac_error.1567952239
Short name	T414
Test name
Test status
Simulation time	260120040 ps
CPU time	4.45 seconds
Started	Aug 29 12:05:48 PM UTC 24
Finished	Aug 29 12:05:54 PM UTC 24
Peak memory	232632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567952239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.1567952239 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/26.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/26.kmac_key_error.1068018302
Short name	T417
Test name
Test status
Simulation time	1519074250 ps
CPU time	6.04 seconds
Started	Aug 29 12:05:54 PM UTC 24
Finished	Aug 29 12:06:02 PM UTC 24
Peak memory	230396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068018302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.1068018302 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/26.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/26.kmac_lc_escalation.922302446
Short name	T419
Test name
Test status
Simulation time	225194294 ps
CPU time	2.64 seconds
Started	Aug 29 12:06:00 PM UTC 24
Finished	Aug 29 12:06:04 PM UTC 24
Peak memory	230440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922302446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.922302446 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/26.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/26.kmac_long_msg_and_output.2570394164
Short name	T581
Test name
Test status
Simulation time	121883598612 ps
CPU time	970.6 seconds
Started	Aug 29 12:04:54 PM UTC 24
Finished	Aug 29 12:21:16 PM UTC 24
Peak memory	1351516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570394164 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_and_output.2570394164 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/26.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/26.kmac_sideload.4173417033
Short name	T455
Test name
Test status
Simulation time	10375873207 ps
CPU time	271.48 seconds
Started	Aug 29 12:05:22 PM UTC 24
Finished	Aug 29 12:09:57 PM UTC 24
Peak memory	511892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173417033 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.4173417033 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/26.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/26.kmac_smoke.3369885730
Short name	T415
Test name
Test status
Simulation time	993331767 ps
CPU time	62.57 seconds
Started	Aug 29 12:04:54 PM UTC 24
Finished	Aug 29 12:05:58 PM UTC 24
Peak memory	230768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369885730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.3369885730 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/26.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/26.kmac_stress_all.1385971405
Short name	T476
Test name
Test status
Simulation time	4083071420 ps
CPU time	369.87 seconds
Started	Aug 29 12:06:00 PM UTC 24
Finished	Aug 29 12:12:16 PM UTC 24
Peak memory	333596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385971405 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.1385971405 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/26.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/27.kmac_alert_test.3589617716
Short name	T428
Test name
Test status
Simulation time	27000872 ps
CPU time	0.93 seconds
Started	Aug 29 12:06:57 PM UTC 24
Finished	Aug 29 12:06:59 PM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589617716 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.3589617716 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/27.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/27.kmac_app.2442115433
Short name	T435
Test name
Test status
Simulation time	1513767515 ps
CPU time	85.03 seconds
Started	Aug 29 12:06:09 PM UTC 24
Finished	Aug 29 12:07:36 PM UTC 24
Peak memory	264016 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442115433 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.2442115433 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/27.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/27.kmac_burst_write.878008088
Short name	T511
Test name
Test status
Simulation time	47550419141 ps
CPU time	532.52 seconds
Started	Aug 29 12:06:08 PM UTC 24
Finished	Aug 29 12:15:08 PM UTC 24
Peak memory	251876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878008088 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.878008088 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/27.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/27.kmac_entropy_refresh.2046270068
Short name	T423
Test name
Test status
Simulation time	277352712 ps
CPU time	5.21 seconds
Started	Aug 29 12:06:21 PM UTC 24
Finished	Aug 29 12:06:27 PM UTC 24
Peak memory	232692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046270068 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.2046270068 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/27.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/27.kmac_error.769299804
Short name	T486
Test name
Test status
Simulation time	18535707202 ps
CPU time	377.11 seconds
Started	Aug 29 12:06:28 PM UTC 24
Finished	Aug 29 12:12:50 PM UTC 24
Peak memory	384932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769299804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.769299804 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/27.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/27.kmac_key_error.111244027
Short name	T425
Test name
Test status
Simulation time	1973356319 ps
CPU time	17.35 seconds
Started	Aug 29 12:06:33 PM UTC 24
Finished	Aug 29 12:06:52 PM UTC 24
Peak memory	230428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111244027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.111244027 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/27.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/27.kmac_lc_escalation.584232557
Short name	T426
Test name
Test status
Simulation time	64460768 ps
CPU time	2 seconds
Started	Aug 29 12:06:52 PM UTC 24
Finished	Aug 29 12:06:55 PM UTC 24
Peak memory	229736 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584232557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.584232557 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/27.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/27.kmac_long_msg_and_output.1358566479
Short name	T710
Test name
Test status
Simulation time	25091215153 ps
CPU time	2523.74 seconds
Started	Aug 29 12:06:06 PM UTC 24
Finished	Aug 29 12:48:39 PM UTC 24
Peak memory	1652556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358566479 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_and_output.1358566479 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/27.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/27.kmac_sideload.962186987
Short name	T451
Test name
Test status
Simulation time	22231252533 ps
CPU time	209.46 seconds
Started	Aug 29 12:06:06 PM UTC 24
Finished	Aug 29 12:09:39 PM UTC 24
Peak memory	370456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962186987 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.962186987 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/27.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/27.kmac_smoke.2899296090
Short name	T430
Test name
Test status
Simulation time	1041008473 ps
CPU time	69.68 seconds
Started	Aug 29 12:06:04 PM UTC 24
Finished	Aug 29 12:07:15 PM UTC 24
Peak memory	230512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899296090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.2899296090 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/27.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/27.kmac_stress_all.2663127006
Short name	T448
Test name
Test status
Simulation time	7926563763 ps
CPU time	145.63 seconds
Started	Aug 29 12:06:56 PM UTC 24
Finished	Aug 29 12:09:24 PM UTC 24
Peak memory	315556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663127006 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.2663127006 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/27.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/28.kmac_alert_test.3610470923
Short name	T440
Test name
Test status
Simulation time	71852734 ps
CPU time	1.14 seconds
Started	Aug 29 12:07:57 PM UTC 24
Finished	Aug 29 12:08:00 PM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610470923 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.3610470923 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/28.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/28.kmac_app.1889094973
Short name	T475
Test name
Test status
Simulation time	65412515472 ps
CPU time	281.56 seconds
Started	Aug 29 12:07:26 PM UTC 24
Finished	Aug 29 12:12:12 PM UTC 24
Peak memory	454548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889094973 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.1889094973 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/28.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/28.kmac_burst_write.3436409491
Short name	T466
Test name
Test status
Simulation time	3076021820 ps
CPU time	262.32 seconds
Started	Aug 29 12:07:22 PM UTC 24
Finished	Aug 29 12:11:48 PM UTC 24
Peak memory	239516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436409491 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.3436409491 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/28.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/28.kmac_entropy_refresh.1470342713
Short name	T484
Test name
Test status
Simulation time	33938194224 ps
CPU time	312.09 seconds
Started	Aug 29 12:07:31 PM UTC 24
Finished	Aug 29 12:12:48 PM UTC 24
Peak memory	331936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470342713 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.1470342713 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/28.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/28.kmac_error.1215518670
Short name	T504
Test name
Test status
Simulation time	16060069674 ps
CPU time	419.22 seconds
Started	Aug 29 12:07:32 PM UTC 24
Finished	Aug 29 12:14:38 PM UTC 24
Peak memory	366424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215518670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.1215518670 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/28.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/28.kmac_key_error.1325957529
Short name	T436
Test name
Test status
Simulation time	3882176431 ps
CPU time	12.78 seconds
Started	Aug 29 12:07:37 PM UTC 24
Finished	Aug 29 12:07:52 PM UTC 24
Peak memory	230708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325957529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.1325957529 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/28.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/28.kmac_lc_escalation.1384806817
Short name	T438
Test name
Test status
Simulation time	59273774 ps
CPU time	2.57 seconds
Started	Aug 29 12:07:52 PM UTC 24
Finished	Aug 29 12:07:56 PM UTC 24
Peak memory	230380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384806817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.1384806817 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/28.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/28.kmac_long_msg_and_output.142855320
Short name	T725
Test name
Test status
Simulation time	447578544942 ps
CPU time	4635.08 seconds
Started	Aug 29 12:07:13 PM UTC 24
Finished	Aug 29 01:25:20 PM UTC 24
Peak memory	4368388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142855320 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_and_output.142855320 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/28.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/28.kmac_sideload.2406778576
Short name	T474
Test name
Test status
Simulation time	11950530782 ps
CPU time	290.89 seconds
Started	Aug 29 12:07:16 PM UTC 24
Finished	Aug 29 12:12:11 PM UTC 24
Peak memory	335652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406778576 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.2406778576 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/28.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/28.kmac_smoke.788974350
Short name	T439
Test name
Test status
Simulation time	6148106818 ps
CPU time	56 seconds
Started	Aug 29 12:07:01 PM UTC 24
Finished	Aug 29 12:07:58 PM UTC 24
Peak memory	230708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788974350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.788974350 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/28.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/28.kmac_stress_all.2097257820
Short name	T496
Test name
Test status
Simulation time	121199557272 ps
CPU time	353.95 seconds
Started	Aug 29 12:07:54 PM UTC 24
Finished	Aug 29 12:13:53 PM UTC 24
Peak memory	399188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097257820 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.2097257820 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/28.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/29.kmac_alert_test.1847258299
Short name	T450
Test name
Test status
Simulation time	18308794 ps
CPU time	1.26 seconds
Started	Aug 29 12:09:26 PM UTC 24
Finished	Aug 29 12:09:28 PM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847258299 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.1847258299 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/29.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/29.kmac_app.4291224435
Short name	T479
Test name
Test status
Simulation time	16879772524 ps
CPU time	217.67 seconds
Started	Aug 29 12:08:48 PM UTC 24
Finished	Aug 29 12:12:29 PM UTC 24
Peak memory	325592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291224435 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.4291224435 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/29.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/29.kmac_burst_write.2632217053
Short name	T577
Test name
Test status
Simulation time	38058355873 ps
CPU time	748.63 seconds
Started	Aug 29 12:08:08 PM UTC 24
Finished	Aug 29 12:20:47 PM UTC 24
Peak memory	253788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632217053 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.2632217053 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/29.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/29.kmac_entropy_refresh.3301953112
Short name	T463
Test name
Test status
Simulation time	7496765078 ps
CPU time	134.06 seconds
Started	Aug 29 12:08:59 PM UTC 24
Finished	Aug 29 12:11:16 PM UTC 24
Peak memory	329496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301953112 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.3301953112 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/29.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/29.kmac_error.22368185
Short name	T541
Test name
Test status
Simulation time	70288517541 ps
CPU time	514.88 seconds
Started	Aug 29 12:09:06 PM UTC 24
Finished	Aug 29 12:17:48 PM UTC 24
Peak memory	628628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22368185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.22368185 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/29.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/29.kmac_key_error.815063203
Short name	T449
Test name
Test status
Simulation time	394136995 ps
CPU time	4.61 seconds
Started	Aug 29 12:09:18 PM UTC 24
Finished	Aug 29 12:09:25 PM UTC 24
Peak memory	230432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815063203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.815063203 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/29.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/29.kmac_lc_escalation.1185112518
Short name	T99
Test name
Test status
Simulation time	89228043 ps
CPU time	1.73 seconds
Started	Aug 29 12:09:24 PM UTC 24
Finished	Aug 29 12:09:27 PM UTC 24
Peak memory	231792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185112518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.1185112518 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/29.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/29.kmac_long_msg_and_output.833348388
Short name	T596
Test name
Test status
Simulation time	37221816943 ps
CPU time	855.82 seconds
Started	Aug 29 12:08:01 PM UTC 24
Finished	Aug 29 12:22:26 PM UTC 24
Peak memory	780264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833348388 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_and_output.833348388 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/29.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/29.kmac_sideload.423942150
Short name	T506
Test name
Test status
Simulation time	4768917232 ps
CPU time	397.82 seconds
Started	Aug 29 12:08:02 PM UTC 24
Finished	Aug 29 12:14:45 PM UTC 24
Peak memory	391064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423942150 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.423942150 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/29.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/29.kmac_smoke.1767924305
Short name	T445
Test name
Test status
Simulation time	12371517391 ps
CPU time	63.74 seconds
Started	Aug 29 12:07:59 PM UTC 24
Finished	Aug 29 12:09:05 PM UTC 24
Peak memory	235600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767924305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.1767924305 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/29.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/29.kmac_stress_all.2525127112
Short name	T452
Test name
Test status
Simulation time	774421561 ps
CPU time	14.18 seconds
Started	Aug 29 12:09:26 PM UTC 24
Finished	Aug 29 12:09:41 PM UTC 24
Peak memory	245596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525127112 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.2525127112 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/29.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/3.kmac_alert_test.4158251529
Short name	T199
Test name
Test status
Simulation time	15839573 ps
CPU time	1.17 seconds
Started	Aug 29 11:46:05 AM UTC 24
Finished	Aug 29 11:46:07 AM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158251529 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.4158251529 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/3.kmac_app.2438995587
Short name	T43
Test name
Test status
Simulation time	3587564110 ps
CPU time	60.25 seconds
Started	Aug 29 11:45:31 AM UTC 24
Finished	Aug 29 11:46:33 AM UTC 24
Peak memory	284628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438995587 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.2438995587 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/3.kmac_app_with_partial_data.932383481
Short name	T232
Test name
Test status
Simulation time	11896439522 ps
CPU time	267.54 seconds
Started	Aug 29 11:45:31 AM UTC 24
Finished	Aug 29 11:50:02 AM UTC 24
Peak memory	444256 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932383481 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.932383481 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_app_with_partial_data/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/3.kmac_burst_write.1560427097
Short name	T159
Test name
Test status
Simulation time	8682349851 ps
CPU time	363.58 seconds
Started	Aug 29 11:45:05 AM UTC 24
Finished	Aug 29 11:51:14 AM UTC 24
Peak memory	245540 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560427097 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.1560427097 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/3.kmac_edn_timeout_error.2289243426
Short name	T144
Test name
Test status
Simulation time	473156212 ps
CPU time	13.66 seconds
Started	Aug 29 11:45:50 AM UTC 24
Finished	Aug 29 11:46:05 AM UTC 24
Peak memory	230504 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289243426 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.2289243426 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_mode_error.4210181473
Short name	T118
Test name
Test status
Simulation time	84232208 ps
CPU time	7.95 seconds
Started	Aug 29 11:45:50 AM UTC 24
Finished	Aug 29 11:45:59 AM UTC 24
Peak memory	230580 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210181473 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.4210181473 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_ready_error.1714583073
Short name	T119
Test name
Test status
Simulation time	3270012715 ps
CPU time	46.31 seconds
Started	Aug 29 11:45:50 AM UTC 24
Finished	Aug 29 11:46:38 AM UTC 24
Peak memory	230716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714583073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.1714583073 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_entropy_ready_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_refresh.3050257288
Short name	T64
Test name
Test status
Simulation time	2418501591 ps
CPU time	48.85 seconds
Started	Aug 29 11:45:33 AM UTC 24
Finished	Aug 29 11:46:23 AM UTC 24
Peak memory	247648 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050257288 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.3050257288 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/3.kmac_error.697224211
Short name	T28
Test name
Test status
Simulation time	9352068032 ps
CPU time	198.73 seconds
Started	Aug 29 11:45:35 AM UTC 24
Finished	Aug 29 11:48:57 AM UTC 24
Peak memory	327632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697224211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.697224211 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/3.kmac_key_error.1708556600
Short name	T50
Test name
Test status
Simulation time	1856015829 ps
CPU time	10.26 seconds
Started	Aug 29 11:45:37 AM UTC 24
Finished	Aug 29 11:45:48 AM UTC 24
Peak memory	230380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708556600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.1708556600 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/3.kmac_lc_escalation.4262302656
Short name	T47
Test name
Test status
Simulation time	120955290 ps
CPU time	1.81 seconds
Started	Aug 29 11:46:00 AM UTC 24
Finished	Aug 29 11:46:03 AM UTC 24
Peak memory	229780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262302656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.4262302656 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/3.kmac_long_msg_and_output.817593438
Short name	T713
Test name
Test status
Simulation time	447145402191 ps
CPU time	3976.52 seconds
Started	Aug 29 11:44:58 AM UTC 24
Finished	Aug 29 12:51:57 PM UTC 24
Peak memory	4083652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817593438 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_and_output.817593438 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/3.kmac_mubi.1164808398
Short name	T42
Test name
Test status
Simulation time	860119912 ps
CPU time	29.37 seconds
Started	Aug 29 11:45:33 AM UTC 24
Finished	Aug 29 11:46:04 AM UTC 24
Peak memory	243792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164808398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.1164808398 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/3.kmac_sec_cm.1278736195
Short name	T77
Test name
Test status
Simulation time	6836943267 ps
CPU time	45.98 seconds
Started	Aug 29 11:46:04 AM UTC 24
Finished	Aug 29 11:46:52 AM UTC 24
Peak memory	271560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278736195 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.1278736195 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/3.kmac_sideload.861130082
Short name	T143
Test name
Test status
Simulation time	11187087224 ps
CPU time	59.18 seconds
Started	Aug 29 11:45:01 AM UTC 24
Finished	Aug 29 11:46:02 AM UTC 24
Peak memory	294688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861130082 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.861130082 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/3.kmac_smoke.2785390201
Short name	T195
Test name
Test status
Simulation time	13949748074 ps
CPU time	80.87 seconds
Started	Aug 29 11:44:58 AM UTC 24
Finished	Aug 29 11:46:21 AM UTC 24
Peak memory	232764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785390201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.2785390201 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/3.kmac_stress_all.960835633
Short name	T544
Test name
Test status
Simulation time	55901719998 ps
CPU time	1895.16 seconds
Started	Aug 29 11:46:02 AM UTC 24
Finished	Aug 29 12:18:00 PM UTC 24
Peak memory	962664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960835633 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.960835633 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac.2204682981
Short name	T90
Test name
Test status
Simulation time	28004174 ps
CPU time	2.48 seconds
Started	Aug 29 11:45:28 AM UTC 24
Finished	Aug 29 11:45:32 AM UTC 24
Peak memory	230724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204682981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac.2204682981 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_test_vectors_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac_xof.1799733458
Short name	T91
Test name
Test status
Simulation time	91905732 ps
CPU time	2.51 seconds
Started	Aug 29 11:45:28 AM UTC 24
Finished	Aug 29 11:45:32 AM UTC 24
Peak memory	230600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799733458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.1799733458 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_test_vectors_kmac_xof/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_224.1304785292
Short name	T487
Test name
Test status
Simulation time	33241602402 ps
CPU time	1648.71 seconds
Started	Aug 29 11:45:06 AM UTC 24
Finished	Aug 29 12:12:54 PM UTC 24
Peak memory	1181412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304785292 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.1304785292 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_224/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_256.3679583389
Short name	T168
Test name
Test status
Simulation time	1733131775 ps
CPU time	51.81 seconds
Started	Aug 29 11:45:07 AM UTC 24
Finished	Aug 29 11:46:00 AM UTC 24
Peak memory	253656 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679583389 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.3679583389 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_256/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_384.767844156
Short name	T92
Test name
Test status
Simulation time	402308757 ps
CPU time	22.19 seconds
Started	Aug 29 11:45:11 AM UTC 24
Finished	Aug 29 11:45:35 AM UTC 24
Peak memory	230576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767844156 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.767844156 + enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_384/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_512.3126607654
Short name	T424
Test name
Test status
Simulation time	48881238538 ps
CPU time	1258.19 seconds
Started	Aug 29 11:45:20 AM UTC 24
Finished	Aug 29 12:06:33 PM UTC 24
Peak memory	1709752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126607654 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.3126607654 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_512/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_128.1541368857
Short name	T601
Test name
Test status
Simulation time	36248014985 ps
CPU time	2211.94 seconds
Started	Aug 29 11:45:22 AM UTC 24
Finished	Aug 29 12:22:41 PM UTC 24
Peak memory	1306316 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541368857 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.1541368 857 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_test_vectors_shake_128/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_256.3642727360
Short name	T196
Test name
Test status
Simulation time	5420803780 ps
CPU time	307.57 seconds
Started	Aug 29 11:45:26 AM UTC 24
Finished	Aug 29 11:50:38 AM UTC 24
Peak memory	263884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642727360 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.3642727 360 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/3.kmac_test_vectors_shake_256/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/30.kmac_alert_test.1733762102
Short name	T460
Test name
Test status
Simulation time	52028986 ps
CPU time	1.22 seconds
Started	Aug 29 12:10:13 PM UTC 24
Finished	Aug 29 12:10:16 PM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733762102 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.1733762102 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/30.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/30.kmac_app.4009289187
Short name	T461
Test name
Test status
Simulation time	2293055132 ps
CPU time	57.78 seconds
Started	Aug 29 12:09:42 PM UTC 24
Finished	Aug 29 12:10:42 PM UTC 24
Peak memory	274272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009289187 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.4009289187 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/30.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/30.kmac_burst_write.3749514634
Short name	T588
Test name
Test status
Simulation time	24262170376 ps
CPU time	722.01 seconds
Started	Aug 29 12:09:42 PM UTC 24
Finished	Aug 29 12:21:53 PM UTC 24
Peak memory	257828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749514634 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.3749514634 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/30.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/30.kmac_entropy_refresh.3837589871
Short name	T522
Test name
Test status
Simulation time	15336739822 ps
CPU time	365.73 seconds
Started	Aug 29 12:09:55 PM UTC 24
Finished	Aug 29 12:16:06 PM UTC 24
Peak memory	538532 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837589871 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.3837589871 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/30.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/30.kmac_error.598354818
Short name	T464
Test name
Test status
Simulation time	1963742668 ps
CPU time	83.94 seconds
Started	Aug 29 12:09:58 PM UTC 24
Finished	Aug 29 12:11:24 PM UTC 24
Peak memory	278600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598354818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.598354818 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/30.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/30.kmac_key_error.906611334
Short name	T458
Test name
Test status
Simulation time	12341217387 ps
CPU time	8.42 seconds
Started	Aug 29 12:10:03 PM UTC 24
Finished	Aug 29 12:10:13 PM UTC 24
Peak memory	230568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906611334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.906611334 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/30.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/30.kmac_lc_escalation.1494225299
Short name	T68
Test name
Test status
Simulation time	91900300 ps
CPU time	2.37 seconds
Started	Aug 29 12:10:06 PM UTC 24
Finished	Aug 29 12:10:10 PM UTC 24
Peak memory	230364 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494225299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.1494225299 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/30.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/30.kmac_long_msg_and_output.4284095340
Short name	T576
Test name
Test status
Simulation time	41482123225 ps
CPU time	662.33 seconds
Started	Aug 29 12:09:29 PM UTC 24
Finished	Aug 29 12:20:39 PM UTC 24
Peak memory	1126244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284095340 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_and_output.4284095340 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/30.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/30.kmac_sideload.136481738
Short name	T529
Test name
Test status
Simulation time	8791315007 ps
CPU time	423.02 seconds
Started	Aug 29 12:09:40 PM UTC 24
Finished	Aug 29 12:16:49 PM UTC 24
Peak memory	382868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136481738 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.136481738 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/30.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/30.kmac_smoke.2158472895
Short name	T456
Test name
Test status
Simulation time	1206872132 ps
CPU time	32.03 seconds
Started	Aug 29 12:09:29 PM UTC 24
Finished	Aug 29 12:10:02 PM UTC 24
Peak memory	230564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158472895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.2158472895 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/30.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/30.kmac_stress_all.2256146132
Short name	T459
Test name
Test status
Simulation time	219561355 ps
CPU time	3.01 seconds
Started	Aug 29 12:10:10 PM UTC 24
Finished	Aug 29 12:10:15 PM UTC 24
Peak memory	230584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256146132 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.2256146132 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/30.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/31.kmac_alert_test.1386454296
Short name	T472
Test name
Test status
Simulation time	14394701 ps
CPU time	1.17 seconds
Started	Aug 29 12:12:07 PM UTC 24
Finished	Aug 29 12:12:09 PM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386454296 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.1386454296 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/31.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/31.kmac_app.368790501
Short name	T471
Test name
Test status
Simulation time	2150742846 ps
CPU time	48.65 seconds
Started	Aug 29 12:11:17 PM UTC 24
Finished	Aug 29 12:12:07 PM UTC 24
Peak memory	276324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368790501 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.368790501 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/31.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/31.kmac_burst_write.2513434132
Short name	T585
Test name
Test status
Simulation time	153049912451 ps
CPU time	620.31 seconds
Started	Aug 29 12:11:08 PM UTC 24
Finished	Aug 29 12:21:36 PM UTC 24
Peak memory	251744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513434132 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.2513434132 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/31.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/31.kmac_entropy_refresh.3992076237
Short name	T542
Test name
Test status
Simulation time	57478238717 ps
CPU time	385.88 seconds
Started	Aug 29 12:11:25 PM UTC 24
Finished	Aug 29 12:17:56 PM UTC 24
Peak memory	489300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992076237 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.3992076237 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/31.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/31.kmac_error.3834895531
Short name	T547
Test name
Test status
Simulation time	44027024335 ps
CPU time	380.64 seconds
Started	Aug 29 12:11:37 PM UTC 24
Finished	Aug 29 12:18:03 PM UTC 24
Peak memory	542544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834895531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.3834895531 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/31.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/31.kmac_key_error.3677316790
Short name	T470
Test name
Test status
Simulation time	11391303006 ps
CPU time	15.81 seconds
Started	Aug 29 12:11:49 PM UTC 24
Finished	Aug 29 12:12:06 PM UTC 24
Peak memory	230688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677316790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.3677316790 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/31.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/31.kmac_lc_escalation.2576990427
Short name	T468
Test name
Test status
Simulation time	78727022 ps
CPU time	1.79 seconds
Started	Aug 29 12:12:02 PM UTC 24
Finished	Aug 29 12:12:05 PM UTC 24
Peak memory	229852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576990427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.2576990427 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/31.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/31.kmac_long_msg_and_output.2459694997
Short name	T708
Test name
Test status
Simulation time	388597555805 ps
CPU time	2088.54 seconds
Started	Aug 29 12:10:17 PM UTC 24
Finished	Aug 29 12:45:30 PM UTC 24
Peak memory	1443752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459694997 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_and_output.2459694997 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/31.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/31.kmac_sideload.3139642521
Short name	T467
Test name
Test status
Simulation time	2620917096 ps
CPU time	76.35 seconds
Started	Aug 29 12:10:43 PM UTC 24
Finished	Aug 29 12:12:02 PM UTC 24
Peak memory	284496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139642521 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.3139642521 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/31.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/31.kmac_smoke.2429829018
Short name	T462
Test name
Test status
Simulation time	792988173 ps
CPU time	50.1 seconds
Started	Aug 29 12:10:16 PM UTC 24
Finished	Aug 29 12:11:07 PM UTC 24
Peak memory	230512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429829018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.2429829018 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/31.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/31.kmac_stress_all.2833111192
Short name	T536
Test name
Test status
Simulation time	171980278967 ps
CPU time	298.92 seconds
Started	Aug 29 12:12:07 PM UTC 24
Finished	Aug 29 12:17:10 PM UTC 24
Peak memory	448580 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833111192 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.2833111192 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/31.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/32.kmac_alert_test.561686961
Short name	T482
Test name
Test status
Simulation time	21496281 ps
CPU time	1.17 seconds
Started	Aug 29 12:12:31 PM UTC 24
Finished	Aug 29 12:12:34 PM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561686961 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.561686961 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/32.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/32.kmac_app.249897776
Short name	T510
Test name
Test status
Simulation time	18982945221 ps
CPU time	170.37 seconds
Started	Aug 29 12:12:12 PM UTC 24
Finished	Aug 29 12:15:06 PM UTC 24
Peak memory	288604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249897776 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.249897776 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/32.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/32.kmac_burst_write.3729134434
Short name	T625
Test name
Test status
Simulation time	79701071221 ps
CPU time	742.26 seconds
Started	Aug 29 12:12:12 PM UTC 24
Finished	Aug 29 12:24:44 PM UTC 24
Peak memory	257880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729134434 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.3729134434 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/32.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/32.kmac_entropy_refresh.4126450109
Short name	T507
Test name
Test status
Simulation time	6474321874 ps
CPU time	153.36 seconds
Started	Aug 29 12:12:13 PM UTC 24
Finished	Aug 29 12:14:49 PM UTC 24
Peak memory	327496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126450109 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.4126450109 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/32.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/32.kmac_error.62747825
Short name	T509
Test name
Test status
Simulation time	26139008109 ps
CPU time	162.29 seconds
Started	Aug 29 12:12:17 PM UTC 24
Finished	Aug 29 12:15:03 PM UTC 24
Peak memory	401272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62747825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.62747825 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/32.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/32.kmac_key_error.561929799
Short name	T478
Test name
Test status
Simulation time	1307135921 ps
CPU time	7.23 seconds
Started	Aug 29 12:12:19 PM UTC 24
Finished	Aug 29 12:12:28 PM UTC 24
Peak memory	230432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561929799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.561929799 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/32.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/32.kmac_lc_escalation.4276152097
Short name	T481
Test name
Test status
Simulation time	43592744 ps
CPU time	1.95 seconds
Started	Aug 29 12:12:29 PM UTC 24
Finished	Aug 29 12:12:32 PM UTC 24
Peak memory	229916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276152097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.4276152097 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/32.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/32.kmac_long_msg_and_output.4200984443
Short name	T517
Test name
Test status
Simulation time	2065776186 ps
CPU time	189.72 seconds
Started	Aug 29 12:12:08 PM UTC 24
Finished	Aug 29 12:15:21 PM UTC 24
Peak memory	315204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200984443 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_and_output.4200984443 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/32.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/32.kmac_sideload.2830848032
Short name	T508
Test name
Test status
Simulation time	1874088425 ps
CPU time	159.41 seconds
Started	Aug 29 12:12:10 PM UTC 24
Finished	Aug 29 12:14:52 PM UTC 24
Peak memory	296664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830848032 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.2830848032 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/32.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/32.kmac_smoke.1687525848
Short name	T477
Test name
Test status
Simulation time	1147707001 ps
CPU time	9.27 seconds
Started	Aug 29 12:12:08 PM UTC 24
Finished	Aug 29 12:12:18 PM UTC 24
Peak memory	230504 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687525848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.1687525848 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/32.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/32.kmac_stress_all.3639848416
Short name	T539
Test name
Test status
Simulation time	6163023107 ps
CPU time	297.62 seconds
Started	Aug 29 12:12:29 PM UTC 24
Finished	Aug 29 12:17:31 PM UTC 24
Peak memory	328112 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639848416 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.3639848416 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/32.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/33.kmac_alert_test.69949078
Short name	T492
Test name
Test status
Simulation time	19716272 ps
CPU time	1.24 seconds
Started	Aug 29 12:13:21 PM UTC 24
Finished	Aug 29 12:13:24 PM UTC 24
Peak memory	216392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69949078 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.69949078 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/33.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/33.kmac_app.2034872723
Short name	T550
Test name
Test status
Simulation time	12260271865 ps
CPU time	314.22 seconds
Started	Aug 29 12:12:51 PM UTC 24
Finished	Aug 29 12:18:10 PM UTC 24
Peak memory	497564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034872723 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.2034872723 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/33.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/33.kmac_burst_write.619143315
Short name	T575
Test name
Test status
Simulation time	14238866069 ps
CPU time	463.81 seconds
Started	Aug 29 12:12:49 PM UTC 24
Finished	Aug 29 12:20:39 PM UTC 24
Peak memory	247844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619143315 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.619143315 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/33.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/33.kmac_entropy_refresh.3703444906
Short name	T549
Test name
Test status
Simulation time	13644893053 ps
CPU time	312.27 seconds
Started	Aug 29 12:12:51 PM UTC 24
Finished	Aug 29 12:18:08 PM UTC 24
Peak memory	491408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703444906 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.3703444906 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/33.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/33.kmac_error.350293444
Short name	T503
Test name
Test status
Simulation time	12026021130 ps
CPU time	98.65 seconds
Started	Aug 29 12:12:55 PM UTC 24
Finished	Aug 29 12:14:36 PM UTC 24
Peak memory	278360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350293444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.350293444 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/33.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/33.kmac_key_error.3428021722
Short name	T491
Test name
Test status
Simulation time	499074337 ps
CPU time	5.86 seconds
Started	Aug 29 12:13:13 PM UTC 24
Finished	Aug 29 12:13:20 PM UTC 24
Peak memory	230436 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428021722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.3428021722 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/33.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/33.kmac_lc_escalation.3499339789
Short name	T490
Test name
Test status
Simulation time	103448656 ps
CPU time	1.88 seconds
Started	Aug 29 12:13:14 PM UTC 24
Finished	Aug 29 12:13:17 PM UTC 24
Peak memory	229804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499339789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.3499339789 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/33.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/33.kmac_long_msg_and_output.3206975176
Short name	T580
Test name
Test status
Simulation time	5086817707 ps
CPU time	490.3 seconds
Started	Aug 29 12:12:35 PM UTC 24
Finished	Aug 29 12:20:52 PM UTC 24
Peak memory	548692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206975176 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_and_output.3206975176 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/33.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/33.kmac_sideload.1665307194
Short name	T525
Test name
Test status
Simulation time	2728425340 ps
CPU time	232.51 seconds
Started	Aug 29 12:12:37 PM UTC 24
Finished	Aug 29 12:16:33 PM UTC 24
Peak memory	323328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665307194 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.1665307194 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/33.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/33.kmac_smoke.2008557650
Short name	T494
Test name
Test status
Simulation time	6147944511 ps
CPU time	68.69 seconds
Started	Aug 29 12:12:34 PM UTC 24
Finished	Aug 29 12:13:45 PM UTC 24
Peak memory	232676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008557650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.2008557650 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/33.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/33.kmac_stress_all.4060203326
Short name	T656
Test name
Test status
Simulation time	139777362233 ps
CPU time	823.16 seconds
Started	Aug 29 12:13:18 PM UTC 24
Finished	Aug 29 12:27:12 PM UTC 24
Peak memory	422060 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060203326 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.4060203326 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/33.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/34.kmac_alert_test.2416689630
Short name	T502
Test name
Test status
Simulation time	12060607 ps
CPU time	1.15 seconds
Started	Aug 29 12:14:26 PM UTC 24
Finished	Aug 29 12:14:29 PM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416689630 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.2416689630 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/34.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/34.kmac_app.1066245490
Short name	T530
Test name
Test status
Simulation time	9793943976 ps
CPU time	174.04 seconds
Started	Aug 29 12:13:54 PM UTC 24
Finished	Aug 29 12:16:51 PM UTC 24
Peak memory	292820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066245490 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.1066245490 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/34.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/34.kmac_burst_write.648460183
Short name	T499
Test name
Test status
Simulation time	1916204926 ps
CPU time	29.87 seconds
Started	Aug 29 12:13:47 PM UTC 24
Finished	Aug 29 12:14:18 PM UTC 24
Peak memory	235408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648460183 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.648460183 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/34.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/34.kmac_entropy_refresh.1227137015
Short name	T564
Test name
Test status
Simulation time	63162628633 ps
CPU time	332.92 seconds
Started	Aug 29 12:14:04 PM UTC 24
Finished	Aug 29 12:19:41 PM UTC 24
Peak memory	513880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227137015 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.1227137015 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/34.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/34.kmac_error.846353820
Short name	T538
Test name
Test status
Simulation time	2055860361 ps
CPU time	190 seconds
Started	Aug 29 12:14:05 PM UTC 24
Finished	Aug 29 12:17:18 PM UTC 24
Peak memory	300820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846353820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.846353820 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/34.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/34.kmac_key_error.976219318
Short name	T501
Test name
Test status
Simulation time	1626897377 ps
CPU time	5.42 seconds
Started	Aug 29 12:14:19 PM UTC 24
Finished	Aug 29 12:14:25 PM UTC 24
Peak memory	230564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976219318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.976219318 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/34.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/34.kmac_lc_escalation.258139451
Short name	T500
Test name
Test status
Simulation time	46214339 ps
CPU time	2.02 seconds
Started	Aug 29 12:14:19 PM UTC 24
Finished	Aug 29 12:14:22 PM UTC 24
Peak memory	230552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258139451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.258139451 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/34.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/34.kmac_long_msg_and_output.4215448959
Short name	T687
Test name
Test status
Simulation time	116379817033 ps
CPU time	1164.9 seconds
Started	Aug 29 12:13:40 PM UTC 24
Finished	Aug 29 12:33:19 PM UTC 24
Peak memory	1556376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215448959 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_and_output.4215448959 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/34.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/34.kmac_sideload.100181029
Short name	T555
Test name
Test status
Simulation time	52826470406 ps
CPU time	303.31 seconds
Started	Aug 29 12:13:46 PM UTC 24
Finished	Aug 29 12:18:53 PM UTC 24
Peak memory	491476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100181029 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.100181029 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/34.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/34.kmac_smoke.610781506
Short name	T493
Test name
Test status
Simulation time	980719853 ps
CPU time	12.65 seconds
Started	Aug 29 12:13:25 PM UTC 24
Finished	Aug 29 12:13:38 PM UTC 24
Peak memory	230908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610781506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.610781506 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/34.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/34.kmac_stress_all.3406676900
Short name	T520
Test name
Test status
Simulation time	17063042668 ps
CPU time	82.6 seconds
Started	Aug 29 12:14:23 PM UTC 24
Finished	Aug 29 12:15:48 PM UTC 24
Peak memory	290712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406676900 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.3406676900 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/34.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/35.kmac_alert_test.2834884571
Short name	T514
Test name
Test status
Simulation time	20137085 ps
CPU time	1.27 seconds
Started	Aug 29 12:15:11 PM UTC 24
Finished	Aug 29 12:15:13 PM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834884571 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.2834884571 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/35.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/35.kmac_app.3036974305
Short name	T532
Test name
Test status
Simulation time	1454728546 ps
CPU time	122.93 seconds
Started	Aug 29 12:14:46 PM UTC 24
Finished	Aug 29 12:16:52 PM UTC 24
Peak memory	276304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036974305 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.3036974305 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/35.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/35.kmac_burst_write.1416337356
Short name	T594
Test name
Test status
Simulation time	50433415549 ps
CPU time	445.33 seconds
Started	Aug 29 12:14:44 PM UTC 24
Finished	Aug 29 12:22:15 PM UTC 24
Peak memory	249628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416337356 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.1416337356 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/35.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/35.kmac_entropy_refresh.4221743589
Short name	T516
Test name
Test status
Simulation time	1437736135 ps
CPU time	29.15 seconds
Started	Aug 29 12:14:51 PM UTC 24
Finished	Aug 29 12:15:21 PM UTC 24
Peak memory	241604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221743589 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.4221743589 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/35.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/35.kmac_error.2185188864
Short name	T537
Test name
Test status
Simulation time	17356688307 ps
CPU time	137.43 seconds
Started	Aug 29 12:14:53 PM UTC 24
Finished	Aug 29 12:17:13 PM UTC 24
Peak memory	333680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185188864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.2185188864 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/35.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/35.kmac_key_error.906496185
Short name	T513
Test name
Test status
Simulation time	594343301 ps
CPU time	6.23 seconds
Started	Aug 29 12:15:04 PM UTC 24
Finished	Aug 29 12:15:11 PM UTC 24
Peak memory	230384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906496185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.906496185 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/35.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/35.kmac_lc_escalation.3722520741
Short name	T512
Test name
Test status
Simulation time	241521281 ps
CPU time	1.94 seconds
Started	Aug 29 12:15:07 PM UTC 24
Finished	Aug 29 12:15:10 PM UTC 24
Peak memory	234532 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722520741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.3722520741 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/35.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/35.kmac_long_msg_and_output.221300235
Short name	T715
Test name
Test status
Simulation time	103549247407 ps
CPU time	2294.12 seconds
Started	Aug 29 12:14:37 PM UTC 24
Finished	Aug 29 12:53:18 PM UTC 24
Peak memory	2662240 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221300235 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_and_output.221300235 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/35.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/35.kmac_sideload.2112574997
Short name	T551
Test name
Test status
Simulation time	10035994291 ps
CPU time	226.32 seconds
Started	Aug 29 12:14:38 PM UTC 24
Finished	Aug 29 12:18:28 PM UTC 24
Peak memory	315152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112574997 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.2112574997 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/35.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/35.kmac_smoke.3062109444
Short name	T505
Test name
Test status
Simulation time	455538249 ps
CPU time	13.43 seconds
Started	Aug 29 12:14:29 PM UTC 24
Finished	Aug 29 12:14:44 PM UTC 24
Peak memory	232608 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062109444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.3062109444 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/35.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/35.kmac_stress_all.2772051804
Short name	T704
Test name
Test status
Simulation time	42108546424 ps
CPU time	1511.86 seconds
Started	Aug 29 12:15:09 PM UTC 24
Finished	Aug 29 12:40:39 PM UTC 24
Peak memory	692392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772051804 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.2772051804 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/35.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/36.kmac_alert_test.958925012
Short name	T523
Test name
Test status
Simulation time	13957947 ps
CPU time	1.2 seconds
Started	Aug 29 12:16:07 PM UTC 24
Finished	Aug 29 12:16:09 PM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958925012 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.958925012 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/36.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/36.kmac_app.3241615180
Short name	T589
Test name
Test status
Simulation time	26084223903 ps
CPU time	385.46 seconds
Started	Aug 29 12:15:22 PM UTC 24
Finished	Aug 29 12:21:53 PM UTC 24
Peak memory	466776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241615180 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.3241615180 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/36.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/36.kmac_burst_write.1276802010
Short name	T526
Test name
Test status
Simulation time	877215841 ps
CPU time	75.72 seconds
Started	Aug 29 12:15:22 PM UTC 24
Finished	Aug 29 12:16:40 PM UTC 24
Peak memory	232628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276802010 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.1276802010 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/36.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/36.kmac_entropy_refresh.2406942134
Short name	T568
Test name
Test status
Simulation time	12591228103 ps
CPU time	273.06 seconds
Started	Aug 29 12:15:25 PM UTC 24
Finished	Aug 29 12:20:02 PM UTC 24
Peak memory	468836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406942134 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.2406942134 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/36.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/36.kmac_error.2598097349
Short name	T561
Test name
Test status
Simulation time	3956320340 ps
CPU time	215.92 seconds
Started	Aug 29 12:15:47 PM UTC 24
Finished	Aug 29 12:19:26 PM UTC 24
Peak memory	309092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598097349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.2598097349 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/36.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/36.kmac_key_error.2836399884
Short name	T521
Test name
Test status
Simulation time	898007019 ps
CPU time	5.1 seconds
Started	Aug 29 12:15:49 PM UTC 24
Finished	Aug 29 12:15:55 PM UTC 24
Peak memory	230380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836399884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.2836399884 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/36.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/36.kmac_lc_escalation.2226702415
Short name	T98
Test name
Test status
Simulation time	60612975 ps
CPU time	2.08 seconds
Started	Aug 29 12:15:56 PM UTC 24
Finished	Aug 29 12:15:59 PM UTC 24
Peak memory	232408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226702415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.2226702415 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/36.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/36.kmac_long_msg_and_output.1917768336
Short name	T726
Test name
Test status
Simulation time	124811580752 ps
CPU time	4547.11 seconds
Started	Aug 29 12:15:14 PM UTC 24
Finished	Aug 29 01:31:53 PM UTC 24
Peak memory	4538244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917768336 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_and_output.1917768336 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/36.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/36.kmac_sideload.3706208044
Short name	T635
Test name
Test status
Simulation time	267995712834 ps
CPU time	601.22 seconds
Started	Aug 29 12:15:17 PM UTC 24
Finished	Aug 29 12:25:26 PM UTC 24
Peak memory	610196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706208044 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.3706208044 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/36.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/36.kmac_smoke.3744562678
Short name	T519
Test name
Test status
Simulation time	1842769741 ps
CPU time	31.85 seconds
Started	Aug 29 12:15:12 PM UTC 24
Finished	Aug 29 12:15:45 PM UTC 24
Peak memory	230704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744562678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.3744562678 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/36.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/36.kmac_stress_all.2260021554
Short name	T595
Test name
Test status
Simulation time	21952649032 ps
CPU time	373.18 seconds
Started	Aug 29 12:16:00 PM UTC 24
Finished	Aug 29 12:22:18 PM UTC 24
Peak memory	428192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260021554 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.2260021554 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/36.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/37.kmac_alert_test.290448337
Short name	T534
Test name
Test status
Simulation time	15737445 ps
CPU time	1.23 seconds
Started	Aug 29 12:16:57 PM UTC 24
Finished	Aug 29 12:16:59 PM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290448337 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.290448337 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/37.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/37.kmac_app.1140154582
Short name	T563
Test name
Test status
Simulation time	3743519223 ps
CPU time	174.24 seconds
Started	Aug 29 12:16:40 PM UTC 24
Finished	Aug 29 12:19:38 PM UTC 24
Peak memory	290648 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140154582 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.1140154582 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/37.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/37.kmac_burst_write.1540821415
Short name	T655
Test name
Test status
Simulation time	44944479984 ps
CPU time	619.41 seconds
Started	Aug 29 12:16:40 PM UTC 24
Finished	Aug 29 12:27:08 PM UTC 24
Peak memory	247776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540821415 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.1540821415 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/37.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/37.kmac_entropy_refresh.3686540464
Short name	T558
Test name
Test status
Simulation time	40362021143 ps
CPU time	133.74 seconds
Started	Aug 29 12:16:41 PM UTC 24
Finished	Aug 29 12:18:58 PM UTC 24
Peak memory	282664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686540464 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.3686540464 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/37.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/37.kmac_error.3423567353
Short name	T618
Test name
Test status
Simulation time	64516291662 ps
CPU time	434.14 seconds
Started	Aug 29 12:16:51 PM UTC 24
Finished	Aug 29 12:24:11 PM UTC 24
Peak memory	567244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423567353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.3423567353 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/37.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/37.kmac_key_error.2984865040
Short name	T535
Test name
Test status
Simulation time	3619697076 ps
CPU time	8.42 seconds
Started	Aug 29 12:16:52 PM UTC 24
Finished	Aug 29 12:17:01 PM UTC 24
Peak memory	230444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984865040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.2984865040 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/37.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/37.kmac_lc_escalation.3644939550
Short name	T533
Test name
Test status
Simulation time	366019619 ps
CPU time	2.07 seconds
Started	Aug 29 12:16:53 PM UTC 24
Finished	Aug 29 12:16:56 PM UTC 24
Peak memory	230688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644939550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.3644939550 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/37.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/37.kmac_long_msg_and_output.135625818
Short name	T723
Test name
Test status
Simulation time	161516180501 ps
CPU time	3666.55 seconds
Started	Aug 29 12:16:33 PM UTC 24
Finished	Aug 29 01:18:22 PM UTC 24
Peak memory	3927900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135625818 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_and_output.135625818 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/37.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/37.kmac_sideload.91396330
Short name	T610
Test name
Test status
Simulation time	11789741241 ps
CPU time	403.08 seconds
Started	Aug 29 12:16:34 PM UTC 24
Finished	Aug 29 12:23:23 PM UTC 24
Peak memory	538460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91396330 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.91396330 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/37.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/37.kmac_smoke.2639440398
Short name	T531
Test name
Test status
Simulation time	2860475253 ps
CPU time	40.2 seconds
Started	Aug 29 12:16:10 PM UTC 24
Finished	Aug 29 12:16:52 PM UTC 24
Peak memory	230660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639440398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.2639440398 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/37.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/37.kmac_stress_all.4282712949
Short name	T707
Test name
Test status
Simulation time	60602502170 ps
CPU time	1657.66 seconds
Started	Aug 29 12:16:53 PM UTC 24
Finished	Aug 29 12:44:51 PM UTC 24
Peak memory	1273624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282712949 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.4282712949 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/37.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/38.kmac_alert_test.1309160173
Short name	T548
Test name
Test status
Simulation time	52552170 ps
CPU time	1.14 seconds
Started	Aug 29 12:18:02 PM UTC 24
Finished	Aug 29 12:18:05 PM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309160173 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.1309160173 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/38.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/38.kmac_app.1209174493
Short name	T574
Test name
Test status
Simulation time	7654840246 ps
CPU time	192.78 seconds
Started	Aug 29 12:17:19 PM UTC 24
Finished	Aug 29 12:20:35 PM UTC 24
Peak memory	393052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209174493 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.1209174493 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/38.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/38.kmac_burst_write.4108504333
Short name	T683
Test name
Test status
Simulation time	22159559554 ps
CPU time	886.61 seconds
Started	Aug 29 12:17:13 PM UTC 24
Finished	Aug 29 12:32:11 PM UTC 24
Peak memory	261896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108504333 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.4108504333 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/38.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/38.kmac_entropy_refresh.1318471885
Short name	T572
Test name
Test status
Simulation time	13753148466 ps
CPU time	169.63 seconds
Started	Aug 29 12:17:32 PM UTC 24
Finished	Aug 29 12:20:25 PM UTC 24
Peak memory	300960 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318471885 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.1318471885 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/38.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/38.kmac_error.2474570774
Short name	T570
Test name
Test status
Simulation time	12477183970 ps
CPU time	155.31 seconds
Started	Aug 29 12:17:34 PM UTC 24
Finished	Aug 29 12:20:12 PM UTC 24
Peak memory	366548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474570774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.2474570774 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/38.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/38.kmac_key_error.1585937351
Short name	T543
Test name
Test status
Simulation time	2894223383 ps
CPU time	9.45 seconds
Started	Aug 29 12:17:49 PM UTC 24
Finished	Aug 29 12:17:59 PM UTC 24
Peak memory	232620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585937351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.1585937351 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/38.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/38.kmac_lc_escalation.1591510080
Short name	T545
Test name
Test status
Simulation time	112049686 ps
CPU time	2.1 seconds
Started	Aug 29 12:17:58 PM UTC 24
Finished	Aug 29 12:18:01 PM UTC 24
Peak memory	235152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591510080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.1591510080 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/38.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/38.kmac_long_msg_and_output.2410198754
Short name	T582
Test name
Test status
Simulation time	8730405984 ps
CPU time	252.37 seconds
Started	Aug 29 12:17:02 PM UTC 24
Finished	Aug 29 12:21:18 PM UTC 24
Peak memory	343908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410198754 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_and_output.2410198754 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/38.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/38.kmac_sideload.4198476009
Short name	T553
Test name
Test status
Simulation time	5005876457 ps
CPU time	94.89 seconds
Started	Aug 29 12:17:11 PM UTC 24
Finished	Aug 29 12:18:48 PM UTC 24
Peak memory	292688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198476009 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.4198476009 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/38.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/38.kmac_smoke.3981499987
Short name	T540
Test name
Test status
Simulation time	4255585608 ps
CPU time	31.55 seconds
Started	Aug 29 12:17:00 PM UTC 24
Finished	Aug 29 12:17:33 PM UTC 24
Peak memory	230692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981499987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.3981499987 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/38.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/38.kmac_stress_all.3760643748
Short name	T586
Test name
Test status
Simulation time	28567477900 ps
CPU time	219 seconds
Started	Aug 29 12:18:00 PM UTC 24
Finished	Aug 29 12:21:43 PM UTC 24
Peak memory	311520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760643748 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.3760643748 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/38.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/39.kmac_alert_test.1870841065
Short name	T557
Test name
Test status
Simulation time	22326004 ps
CPU time	1.12 seconds
Started	Aug 29 12:18:54 PM UTC 24
Finished	Aug 29 12:18:56 PM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870841065 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.1870841065 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/39.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/39.kmac_app.1912545499
Short name	T609
Test name
Test status
Simulation time	4204307460 ps
CPU time	307.73 seconds
Started	Aug 29 12:18:08 PM UTC 24
Finished	Aug 29 12:23:21 PM UTC 24
Peak memory	337756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912545499 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.1912545499 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/39.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/39.kmac_burst_write.2313016238
Short name	T622
Test name
Test status
Simulation time	45725134903 ps
CPU time	379.4 seconds
Started	Aug 29 12:18:05 PM UTC 24
Finished	Aug 29 12:24:30 PM UTC 24
Peak memory	243696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313016238 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.2313016238 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/39.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/39.kmac_entropy_refresh.560057962
Short name	T571
Test name
Test status
Simulation time	16583735758 ps
CPU time	127.08 seconds
Started	Aug 29 12:18:11 PM UTC 24
Finished	Aug 29 12:20:21 PM UTC 24
Peak memory	270172 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560057962 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.560057962 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/39.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/39.kmac_error.1926313809
Short name	T562
Test name
Test status
Simulation time	617591932 ps
CPU time	60.89 seconds
Started	Aug 29 12:18:30 PM UTC 24
Finished	Aug 29 12:19:32 PM UTC 24
Peak memory	261924 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926313809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.1926313809 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/39.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/39.kmac_key_error.2833263890
Short name	T556
Test name
Test status
Simulation time	10982883592 ps
CPU time	10.01 seconds
Started	Aug 29 12:18:43 PM UTC 24
Finished	Aug 29 12:18:54 PM UTC 24
Peak memory	232700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833263890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.2833263890 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/39.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/39.kmac_lc_escalation.2881436932
Short name	T554
Test name
Test status
Simulation time	36706303 ps
CPU time	1.78 seconds
Started	Aug 29 12:18:49 PM UTC 24
Finished	Aug 29 12:18:52 PM UTC 24
Peak memory	231952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881436932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.2881436932 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/39.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/39.kmac_long_msg_and_output.3636495439
Short name	T698
Test name
Test status
Simulation time	23378427469 ps
CPU time	1172.49 seconds
Started	Aug 29 12:18:02 PM UTC 24
Finished	Aug 29 12:37:49 PM UTC 24
Peak memory	923420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636495439 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_and_output.3636495439 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/39.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/39.kmac_sideload.1571243456
Short name	T552
Test name
Test status
Simulation time	1932786966 ps
CPU time	35.87 seconds
Started	Aug 29 12:18:04 PM UTC 24
Finished	Aug 29 12:18:42 PM UTC 24
Peak memory	249752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571243456 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.1571243456 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/39.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/39.kmac_smoke.1568901356
Short name	T560
Test name
Test status
Simulation time	4038173830 ps
CPU time	63.8 seconds
Started	Aug 29 12:18:02 PM UTC 24
Finished	Aug 29 12:19:08 PM UTC 24
Peak memory	230568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568901356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.1568901356 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/39.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/39.kmac_stress_all.95805223
Short name	T686
Test name
Test status
Simulation time	104968281762 ps
CPU time	832.38 seconds
Started	Aug 29 12:18:53 PM UTC 24
Finished	Aug 29 12:32:56 PM UTC 24
Peak memory	549168 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95805223 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.95805223 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/39.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/4.kmac_alert_test.3721180086
Short name	T60
Test name
Test status
Simulation time	32505994 ps
CPU time	1.26 seconds
Started	Aug 29 11:46:59 AM UTC 24
Finished	Aug 29 11:47:01 AM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721180086 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.3721180086 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/4.kmac_app_with_partial_data.4217686633
Short name	T214
Test name
Test status
Simulation time	6643506834 ps
CPU time	133.27 seconds
Started	Aug 29 11:46:38 AM UTC 24
Finished	Aug 29 11:48:54 AM UTC 24
Peak memory	319300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217686633 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.4217686633 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_app_with_partial_data/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/4.kmac_burst_write.3965914384
Short name	T309
Test name
Test status
Simulation time	59980106160 ps
CPU time	540.01 seconds
Started	Aug 29 11:46:17 AM UTC 24
Finished	Aug 29 11:55:24 AM UTC 24
Peak memory	255908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965914384 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.3965914384 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/4.kmac_edn_timeout_error.3297916840
Short name	T154
Test name
Test status
Simulation time	994973794 ps
CPU time	41.05 seconds
Started	Aug 29 11:46:43 AM UTC 24
Finished	Aug 29 11:47:26 AM UTC 24
Peak memory	232476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297916840 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.3297916840 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_mode_error.3115124005
Short name	T155
Test name
Test status
Simulation time	4096089999 ps
CPU time	50.79 seconds
Started	Aug 29 11:46:43 AM UTC 24
Finished	Aug 29 11:47:36 AM UTC 24
Peak memory	235400 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115124005 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.3115124005 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_ready_error.2844699907
Short name	T202
Test name
Test status
Simulation time	35195498037 ps
CPU time	48.02 seconds
Started	Aug 29 11:46:47 AM UTC 24
Finished	Aug 29 11:47:36 AM UTC 24
Peak memory	230632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844699907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.2844699907 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_entropy_ready_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_refresh.3281782032
Short name	T120
Test name
Test status
Simulation time	887508827 ps
CPU time	21.77 seconds
Started	Aug 29 11:46:40 AM UTC 24
Finished	Aug 29 11:47:03 AM UTC 24
Peak memory	253788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281782032 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.3281782032 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/4.kmac_key_error.1852552239
Short name	T71
Test name
Test status
Simulation time	153432260 ps
CPU time	2.62 seconds
Started	Aug 29 11:46:42 AM UTC 24
Finished	Aug 29 11:46:46 AM UTC 24
Peak memory	230584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852552239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.1852552239 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/4.kmac_lc_escalation.3965672899
Short name	T48
Test name
Test status
Simulation time	846000981 ps
CPU time	8.22 seconds
Started	Aug 29 11:46:47 AM UTC 24
Finished	Aug 29 11:46:56 AM UTC 24
Peak memory	244976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965672899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.3965672899 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/4.kmac_long_msg_and_output.3217600942
Short name	T242
Test name
Test status
Simulation time	9242073607 ps
CPU time	293.01 seconds
Started	Aug 29 11:46:09 AM UTC 24
Finished	Aug 29 11:51:07 AM UTC 24
Peak memory	593964 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217600942 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and_output.3217600942 +enable_mas king=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/4.kmac_mubi.2483782464
Short name	T85
Test name
Test status
Simulation time	7442398263 ps
CPU time	185.56 seconds
Started	Aug 29 11:46:40 AM UTC 24
Finished	Aug 29 11:49:49 AM UTC 24
Peak memory	321620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483782464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.2483782464 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/4.kmac_sec_cm.3372592298
Short name	T78
Test name
Test status
Simulation time	6604333664 ps
CPU time	66.37 seconds
Started	Aug 29 11:46:59 AM UTC 24
Finished	Aug 29 11:48:07 AM UTC 24
Peak memory	265384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372592298 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.3372592298 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/4.kmac_sideload.1978673789
Short name	T228
Test name
Test status
Simulation time	31935546300 ps
CPU time	211.1 seconds
Started	Aug 29 11:46:15 AM UTC 24
Finished	Aug 29 11:49:50 AM UTC 24
Peak memory	307052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978673789 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.1978673789 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/4.kmac_smoke.3298600839
Short name	T194
Test name
Test status
Simulation time	2710663566 ps
CPU time	19.49 seconds
Started	Aug 29 11:46:07 AM UTC 24
Finished	Aug 29 11:46:27 AM UTC 24
Peak memory	230616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298600839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.3298600839 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/4.kmac_stress_all.3170812323
Short name	T58
Test name
Test status
Simulation time	224572152510 ps
CPU time	1052.05 seconds
Started	Aug 29 11:46:53 AM UTC 24
Finished	Aug 29 12:04:37 PM UTC 24
Peak memory	528528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170812323 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.3170812323 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac.3330141138
Short name	T200
Test name
Test status
Simulation time	229229169 ps
CPU time	2.21 seconds
Started	Aug 29 11:46:34 AM UTC 24
Finished	Aug 29 11:46:37 AM UTC 24
Peak memory	230520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330141138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac.3330141138 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_test_vectors_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac_xof.1362410530
Short name	T201
Test name
Test status
Simulation time	28226190 ps
CPU time	2.72 seconds
Started	Aug 29 11:46:36 AM UTC 24
Finished	Aug 29 11:46:39 AM UTC 24
Peak memory	230520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362410530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac_xof.1362410530 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_test_vectors_kmac_xof/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_224.2245488515
Short name	T677
Test name
Test status
Simulation time	60819459535 ps
CPU time	2622.17 seconds
Started	Aug 29 11:46:19 AM UTC 24
Finished	Aug 29 12:30:33 PM UTC 24
Peak memory	3141504 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245488515 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.2245488515 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_224/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_256.3429289146
Short name	T16
Test name
Test status
Simulation time	1126461935 ps
CPU time	35.23 seconds
Started	Aug 29 11:46:21 AM UTC 24
Finished	Aug 29 11:46:58 AM UTC 24
Peak memory	230688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429289146 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.3429289146 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_256/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_384.3388557748
Short name	T150
Test name
Test status
Simulation time	1679144014 ps
CPU time	41.41 seconds
Started	Aug 29 11:46:23 AM UTC 24
Finished	Aug 29 11:47:06 AM UTC 24
Peak memory	239292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388557748 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.3388557748 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_384/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_512.1430685423
Short name	T410
Test name
Test status
Simulation time	63654586141 ps
CPU time	1127.34 seconds
Started	Aug 29 11:46:25 AM UTC 24
Finished	Aug 29 12:05:27 PM UTC 24
Peak memory	1720036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430685423 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.1430685423 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_512/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_128.1377148844
Short name	T692
Test name
Test status
Simulation time	427950251316 ps
CPU time	2851.74 seconds
Started	Aug 29 11:46:29 AM UTC 24
Finished	Aug 29 12:34:31 PM UTC 24
Peak memory	3509964 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377148844 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.1377148 844 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_test_vectors_shake_128/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_256.1810501807
Short name	T216
Test name
Test status
Simulation time	6318559279 ps
CPU time	156.01 seconds
Started	Aug 29 11:46:34 AM UTC 24
Finished	Aug 29 11:49:13 AM UTC 24
Peak memory	360196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810501807 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.1810501 807 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/4.kmac_test_vectors_shake_256/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/40.kmac_alert_test.238502013
Short name	T567
Test name
Test status
Simulation time	25167475 ps
CPU time	1.18 seconds
Started	Aug 29 12:19:47 PM UTC 24
Finished	Aug 29 12:19:49 PM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238502013 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.238502013 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/40.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/40.kmac_app.1886944532
Short name	T606
Test name
Test status
Simulation time	15276919173 ps
CPU time	238.68 seconds
Started	Aug 29 12:19:09 PM UTC 24
Finished	Aug 29 12:23:12 PM UTC 24
Peak memory	397140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886944532 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.1886944532 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/40.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/40.kmac_burst_write.3266548871
Short name	T651
Test name
Test status
Simulation time	16067318427 ps
CPU time	468.74 seconds
Started	Aug 29 12:19:07 PM UTC 24
Finished	Aug 29 12:27:03 PM UTC 24
Peak memory	247648 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266548871 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.3266548871 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/40.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/40.kmac_entropy_refresh.423371052
Short name	T614
Test name
Test status
Simulation time	81879304846 ps
CPU time	268.07 seconds
Started	Aug 29 12:19:27 PM UTC 24
Finished	Aug 29 12:23:59 PM UTC 24
Peak memory	307036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423371052 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.423371052 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/40.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/40.kmac_error.3044896035
Short name	T615
Test name
Test status
Simulation time	2918655969 ps
CPU time	262.29 seconds
Started	Aug 29 12:19:33 PM UTC 24
Finished	Aug 29 12:24:00 PM UTC 24
Peak memory	335708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044896035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.3044896035 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/40.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/40.kmac_key_error.3063022057
Short name	T566
Test name
Test status
Simulation time	2750660711 ps
CPU time	6.15 seconds
Started	Aug 29 12:19:39 PM UTC 24
Finished	Aug 29 12:19:46 PM UTC 24
Peak memory	230568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063022057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.3063022057 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/40.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/40.kmac_lc_escalation.1804524775
Short name	T565
Test name
Test status
Simulation time	101231817 ps
CPU time	1.7 seconds
Started	Aug 29 12:19:42 PM UTC 24
Finished	Aug 29 12:19:45 PM UTC 24
Peak memory	229844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804524775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.1804524775 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/40.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/40.kmac_long_msg_and_output.1065786329
Short name	T717
Test name
Test status
Simulation time	44550906918 ps
CPU time	2571.79 seconds
Started	Aug 29 12:18:57 PM UTC 24
Finished	Aug 29 01:02:20 PM UTC 24
Peak memory	1652748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065786329 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_and_output.1065786329 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/40.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/40.kmac_sideload.756825668
Short name	T605
Test name
Test status
Simulation time	22821569911 ps
CPU time	246.96 seconds
Started	Aug 29 12:18:58 PM UTC 24
Finished	Aug 29 12:23:09 PM UTC 24
Peak memory	491460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756825668 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.756825668 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/40.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/40.kmac_smoke.768587115
Short name	T573
Test name
Test status
Simulation time	16455510162 ps
CPU time	98.03 seconds
Started	Aug 29 12:18:55 PM UTC 24
Finished	Aug 29 12:20:35 PM UTC 24
Peak memory	234852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768587115 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.768587115 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/40.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/40.kmac_stress_all.4057402467
Short name	T694
Test name
Test status
Simulation time	40799048278 ps
CPU time	921.91 seconds
Started	Aug 29 12:19:46 PM UTC 24
Finished	Aug 29 12:35:20 PM UTC 24
Peak memory	579760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057402467 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.4057402467 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/40.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/41.kmac_alert_test.2006963952
Short name	T579
Test name
Test status
Simulation time	105297561 ps
CPU time	1.22 seconds
Started	Aug 29 12:20:48 PM UTC 24
Finished	Aug 29 12:20:50 PM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006963952 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.2006963952 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/41.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/41.kmac_app.3917697665
Short name	T584
Test name
Test status
Simulation time	4300884444 ps
CPU time	60.21 seconds
Started	Aug 29 12:20:21 PM UTC 24
Finished	Aug 29 12:21:23 PM UTC 24
Peak memory	276316 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917697665 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.3917697665 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/41.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/41.kmac_burst_write.3603002450
Short name	T663
Test name
Test status
Simulation time	29291235567 ps
CPU time	434.73 seconds
Started	Aug 29 12:20:13 PM UTC 24
Finished	Aug 29 12:27:34 PM UTC 24
Peak memory	243476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603002450 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.3603002450 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/41.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/41.kmac_entropy_refresh.2120221575
Short name	T587
Test name
Test status
Simulation time	4145793750 ps
CPU time	85.03 seconds
Started	Aug 29 12:20:26 PM UTC 24
Finished	Aug 29 12:21:53 PM UTC 24
Peak memory	282452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120221575 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.2120221575 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/41.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/41.kmac_error.424378139
Short name	T650
Test name
Test status
Simulation time	28370811169 ps
CPU time	364.76 seconds
Started	Aug 29 12:20:36 PM UTC 24
Finished	Aug 29 12:26:45 PM UTC 24
Peak memory	608092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424378139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.424378139 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/41.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/41.kmac_key_error.2495904217
Short name	T578
Test name
Test status
Simulation time	1032643640 ps
CPU time	10.22 seconds
Started	Aug 29 12:20:37 PM UTC 24
Finished	Aug 29 12:20:48 PM UTC 24
Peak memory	230428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495904217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.2495904217 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/41.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/41.kmac_lc_escalation.1734536136
Short name	T67
Test name
Test status
Simulation time	3428070374 ps
CPU time	72.67 seconds
Started	Aug 29 12:20:40 PM UTC 24
Finished	Aug 29 12:21:54 PM UTC 24
Peak memory	264092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734536136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.1734536136 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/41.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/41.kmac_long_msg_and_output.385743200
Short name	T695
Test name
Test status
Simulation time	35169709555 ps
CPU time	915.1 seconds
Started	Aug 29 12:20:03 PM UTC 24
Finished	Aug 29 12:35:30 PM UTC 24
Peak memory	763800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385743200 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_and_output.385743200 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/41.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/41.kmac_sideload.2179288631
Short name	T604
Test name
Test status
Simulation time	7052395827 ps
CPU time	176.11 seconds
Started	Aug 29 12:20:07 PM UTC 24
Finished	Aug 29 12:23:06 PM UTC 24
Peak memory	386960 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179288631 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.2179288631 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/41.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/41.kmac_smoke.904875800
Short name	T569
Test name
Test status
Simulation time	1999182033 ps
CPU time	15.42 seconds
Started	Aug 29 12:19:50 PM UTC 24
Finished	Aug 29 12:20:07 PM UTC 24
Peak memory	232604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904875800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.904875800 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/41.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/41.kmac_stress_all.3539617256
Short name	T705
Test name
Test status
Simulation time	174051165638 ps
CPU time	1294.91 seconds
Started	Aug 29 12:20:40 PM UTC 24
Finished	Aug 29 12:42:31 PM UTC 24
Peak memory	606312 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539617256 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.3539617256 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/41.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/42.kmac_alert_test.2283051914
Short name	T592
Test name
Test status
Simulation time	30754858 ps
CPU time	1.19 seconds
Started	Aug 29 12:21:54 PM UTC 24
Finished	Aug 29 12:21:56 PM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283051914 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.2283051914 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/42.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/42.kmac_app.427675708
Short name	T600
Test name
Test status
Simulation time	4276368872 ps
CPU time	78.94 seconds
Started	Aug 29 12:21:20 PM UTC 24
Finished	Aug 29 12:22:41 PM UTC 24
Peak memory	292760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427675708 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.427675708 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/42.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/42.kmac_burst_write.883685691
Short name	T642
Test name
Test status
Simulation time	6870311362 ps
CPU time	295.42 seconds
Started	Aug 29 12:21:17 PM UTC 24
Finished	Aug 29 12:26:18 PM UTC 24
Peak memory	243480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883685691 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.883685691 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/42.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/42.kmac_entropy_refresh.1416946114
Short name	T659
Test name
Test status
Simulation time	113037802394 ps
CPU time	354.07 seconds
Started	Aug 29 12:21:24 PM UTC 24
Finished	Aug 29 12:27:23 PM UTC 24
Peak memory	479060 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416946114 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.1416946114 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/42.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/42.kmac_error.2149792128
Short name	T670
Test name
Test status
Simulation time	18182139003 ps
CPU time	450.95 seconds
Started	Aug 29 12:21:25 PM UTC 24
Finished	Aug 29 12:29:02 PM UTC 24
Peak memory	603996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149792128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.2149792128 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/42.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/42.kmac_key_error.1453134497
Short name	T590
Test name
Test status
Simulation time	6857909933 ps
CPU time	14.66 seconds
Started	Aug 29 12:21:38 PM UTC 24
Finished	Aug 29 12:21:54 PM UTC 24
Peak memory	230624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453134497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.1453134497 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/42.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/42.kmac_lc_escalation.4090174235
Short name	T591
Test name
Test status
Simulation time	544142945 ps
CPU time	9.04 seconds
Started	Aug 29 12:21:44 PM UTC 24
Finished	Aug 29 12:21:54 PM UTC 24
Peak memory	235288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090174235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.4090174235 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/42.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/42.kmac_long_msg_and_output.3932220815
Short name	T712
Test name
Test status
Simulation time	18921450418 ps
CPU time	1827.71 seconds
Started	Aug 29 12:20:51 PM UTC 24
Finished	Aug 29 12:51:40 PM UTC 24
Peak memory	1310512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932220815 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_and_output.3932220815 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/42.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/42.kmac_sideload.4051466240
Short name	T632
Test name
Test status
Simulation time	12781024260 ps
CPU time	259.83 seconds
Started	Aug 29 12:20:53 PM UTC 24
Finished	Aug 29 12:25:17 PM UTC 24
Peak memory	339732 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051466240 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.4051466240 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/42.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/42.kmac_smoke.958807528
Short name	T583
Test name
Test status
Simulation time	5532392036 ps
CPU time	32.63 seconds
Started	Aug 29 12:20:49 PM UTC 24
Finished	Aug 29 12:21:23 PM UTC 24
Peak memory	230648 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958807528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.958807528 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/42.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/42.kmac_stress_all.3917720743
Short name	T593
Test name
Test status
Simulation time	2996129829 ps
CPU time	10.22 seconds
Started	Aug 29 12:21:54 PM UTC 24
Finished	Aug 29 12:22:05 PM UTC 24
Peak memory	234724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917720743 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.3917720743 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/42.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/43.kmac_alert_test.3224299791
Short name	T599
Test name
Test status
Simulation time	29777267 ps
CPU time	1.16 seconds
Started	Aug 29 12:22:32 PM UTC 24
Finished	Aug 29 12:22:34 PM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224299791 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.3224299791 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/43.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/43.kmac_app.4027856799
Short name	T629
Test name
Test status
Simulation time	69140898710 ps
CPU time	182.4 seconds
Started	Aug 29 12:21:57 PM UTC 24
Finished	Aug 29 12:25:03 PM UTC 24
Peak memory	331732 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027856799 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.4027856799 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/43.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/43.kmac_burst_write.3837303133
Short name	T706
Test name
Test status
Simulation time	143536430518 ps
CPU time	1265.42 seconds
Started	Aug 29 12:21:55 PM UTC 24
Finished	Aug 29 12:43:16 PM UTC 24
Peak memory	272472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837303133 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.3837303133 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/43.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/43.kmac_entropy_refresh.258603250
Short name	T613
Test name
Test status
Simulation time	13317775404 ps
CPU time	84.66 seconds
Started	Aug 29 12:22:06 PM UTC 24
Finished	Aug 29 12:23:33 PM UTC 24
Peak memory	288596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258603250 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.258603250 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/43.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/43.kmac_error.3937734514
Short name	T634
Test name
Test status
Simulation time	18989743613 ps
CPU time	181.54 seconds
Started	Aug 29 12:22:17 PM UTC 24
Finished	Aug 29 12:25:21 PM UTC 24
Peak memory	372636 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937734514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.3937734514 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/43.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/43.kmac_key_error.1331036743
Short name	T597
Test name
Test status
Simulation time	4199364753 ps
CPU time	10.03 seconds
Started	Aug 29 12:22:19 PM UTC 24
Finished	Aug 29 12:22:30 PM UTC 24
Peak memory	232748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331036743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.1331036743 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/43.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/43.kmac_lc_escalation.3539830386
Short name	T598
Test name
Test status
Simulation time	68105185 ps
CPU time	2.5 seconds
Started	Aug 29 12:22:28 PM UTC 24
Finished	Aug 29 12:22:31 PM UTC 24
Peak memory	230388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539830386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.3539830386 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/43.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/43.kmac_long_msg_and_output.4005710740
Short name	T720
Test name
Test status
Simulation time	105539235948 ps
CPU time	2874.04 seconds
Started	Aug 29 12:21:54 PM UTC 24
Finished	Aug 29 01:10:21 PM UTC 24
Peak memory	1836816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005710740 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_and_output.4005710740 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/43.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/43.kmac_sideload.1074493579
Short name	T682
Test name
Test status
Simulation time	127784412528 ps
CPU time	604.94 seconds
Started	Aug 29 12:21:55 PM UTC 24
Finished	Aug 29 12:32:09 PM UTC 24
Peak memory	612252 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074493579 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.1074493579 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/43.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/43.kmac_smoke.3132425217
Short name	T607
Test name
Test status
Simulation time	26071831256 ps
CPU time	76.73 seconds
Started	Aug 29 12:21:54 PM UTC 24
Finished	Aug 29 12:23:13 PM UTC 24
Peak memory	232696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132425217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.3132425217 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/43.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/43.kmac_stress_all.3142628276
Short name	T657
Test name
Test status
Simulation time	12903214682 ps
CPU time	278.58 seconds
Started	Aug 29 12:22:31 PM UTC 24
Finished	Aug 29 12:27:14 PM UTC 24
Peak memory	395432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142628276 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.3142628276 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/43.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/44.kmac_alert_test.3489996207
Short name	T611
Test name
Test status
Simulation time	103285774 ps
CPU time	1.27 seconds
Started	Aug 29 12:23:22 PM UTC 24
Finished	Aug 29 12:23:24 PM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489996207 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.3489996207 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/44.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/44.kmac_app.1156831023
Short name	T671
Test name
Test status
Simulation time	34794611370 ps
CPU time	351.44 seconds
Started	Aug 29 12:23:05 PM UTC 24
Finished	Aug 29 12:29:02 PM UTC 24
Peak memory	544528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156831023 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.1156831023 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/44.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/44.kmac_burst_write.1497820674
Short name	T624
Test name
Test status
Simulation time	1150188903 ps
CPU time	107.18 seconds
Started	Aug 29 12:22:45 PM UTC 24
Finished	Aug 29 12:24:35 PM UTC 24
Peak memory	234656 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497820674 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.1497820674 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/44.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/44.kmac_entropy_refresh.3628121382
Short name	T621
Test name
Test status
Simulation time	2895472272 ps
CPU time	70.59 seconds
Started	Aug 29 12:23:07 PM UTC 24
Finished	Aug 29 12:24:20 PM UTC 24
Peak memory	274264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628121382 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.3628121382 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/44.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/44.kmac_error.2568102004
Short name	T637
Test name
Test status
Simulation time	4349486717 ps
CPU time	164.23 seconds
Started	Aug 29 12:23:09 PM UTC 24
Finished	Aug 29 12:25:57 PM UTC 24
Peak memory	346156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568102004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.2568102004 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/44.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/44.kmac_key_error.1715831201
Short name	T612
Test name
Test status
Simulation time	2285493483 ps
CPU time	10.98 seconds
Started	Aug 29 12:23:13 PM UTC 24
Finished	Aug 29 12:23:25 PM UTC 24
Peak memory	230572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715831201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.1715831201 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/44.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/44.kmac_lc_escalation.2999688516
Short name	T608
Test name
Test status
Simulation time	109095752 ps
CPU time	1.87 seconds
Started	Aug 29 12:23:14 PM UTC 24
Finished	Aug 29 12:23:17 PM UTC 24
Peak memory	234604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999688516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.2999688516 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/44.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/44.kmac_long_msg_and_output.708800997
Short name	T727
Test name
Test status
Simulation time	115002670033 ps
CPU time	4112.49 seconds
Started	Aug 29 12:22:41 PM UTC 24
Finished	Aug 29 01:32:01 PM UTC 24
Peak memory	4269972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708800997 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_and_output.708800997 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/44.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/44.kmac_sideload.1281992243
Short name	T684
Test name
Test status
Simulation time	21721703507 ps
CPU time	600.47 seconds
Started	Aug 29 12:22:42 PM UTC 24
Finished	Aug 29 12:32:51 PM UTC 24
Peak memory	665364 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281992243 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.1281992243 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/44.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/44.kmac_smoke.2983807154
Short name	T602
Test name
Test status
Simulation time	867577629 ps
CPU time	7.85 seconds
Started	Aug 29 12:22:35 PM UTC 24
Finished	Aug 29 12:22:44 PM UTC 24
Peak memory	230644 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983807154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.2983807154 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/44.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/44.kmac_stress_all.4011887981
Short name	T179
Test name
Test status
Simulation time	11279127291 ps
CPU time	854.05 seconds
Started	Aug 29 12:23:18 PM UTC 24
Finished	Aug 29 12:37:43 PM UTC 24
Peak memory	497884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011887981 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.4011887981 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/44.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/45.kmac_alert_test.1039075356
Short name	T620
Test name
Test status
Simulation time	34183937 ps
CPU time	1.14 seconds
Started	Aug 29 12:24:16 PM UTC 24
Finished	Aug 29 12:24:18 PM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039075356 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.1039075356 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/45.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/45.kmac_app.3737766197
Short name	T641
Test name
Test status
Simulation time	11898665780 ps
CPU time	133.94 seconds
Started	Aug 29 12:24:00 PM UTC 24
Finished	Aug 29 12:26:17 PM UTC 24
Peak memory	335704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737766197 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.3737766197 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/45.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/45.kmac_burst_write.3251451291
Short name	T703
Test name
Test status
Simulation time	40815187406 ps
CPU time	993.76 seconds
Started	Aug 29 12:23:34 PM UTC 24
Finished	Aug 29 12:40:21 PM UTC 24
Peak memory	263948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251451291 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.3251451291 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/45.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/45.kmac_entropy_refresh.644682021
Short name	T623
Test name
Test status
Simulation time	1601944987 ps
CPU time	29.92 seconds
Started	Aug 29 12:24:00 PM UTC 24
Finished	Aug 29 12:24:32 PM UTC 24
Peak memory	261904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644682021 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.644682021 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/45.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/45.kmac_error.3464693630
Short name	T647
Test name
Test status
Simulation time	1750960819 ps
CPU time	153.24 seconds
Started	Aug 29 12:24:04 PM UTC 24
Finished	Aug 29 12:26:41 PM UTC 24
Peak memory	296720 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464693630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.3464693630 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/45.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/45.kmac_key_error.950597704
Short name	T619
Test name
Test status
Simulation time	149668318 ps
CPU time	1.87 seconds
Started	Aug 29 12:24:11 PM UTC 24
Finished	Aug 29 12:24:14 PM UTC 24
Peak memory	229788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950597704 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.950597704 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/45.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/45.kmac_long_msg_and_output.3363079665
Short name	T711
Test name
Test status
Simulation time	58617809945 ps
CPU time	1543.06 seconds
Started	Aug 29 12:23:25 PM UTC 24
Finished	Aug 29 12:49:26 PM UTC 24
Peak memory	1136620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363079665 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_and_output.3363079665 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/45.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/45.kmac_sideload.2721693165
Short name	T648
Test name
Test status
Simulation time	6599634830 ps
CPU time	191.23 seconds
Started	Aug 29 12:23:26 PM UTC 24
Finished	Aug 29 12:26:41 PM UTC 24
Peak memory	366496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721693165 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.2721693165 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/45.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/45.kmac_smoke.594315075
Short name	T617
Test name
Test status
Simulation time	1748670734 ps
CPU time	44.45 seconds
Started	Aug 29 12:23:24 PM UTC 24
Finished	Aug 29 12:24:10 PM UTC 24
Peak memory	230572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594315075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.594315075 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/45.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/45.kmac_stress_all.3641618435
Short name	T178
Test name
Test status
Simulation time	11493364086 ps
CPU time	583.92 seconds
Started	Aug 29 12:24:15 PM UTC 24
Finished	Aug 29 12:34:06 PM UTC 24
Peak memory	333656 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641618435 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.3641618435 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/45.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/46.kmac_alert_test.3597258518
Short name	T631
Test name
Test status
Simulation time	68016089 ps
CPU time	1.3 seconds
Started	Aug 29 12:25:06 PM UTC 24
Finished	Aug 29 12:25:08 PM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597258518 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.3597258518 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/46.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/46.kmac_app.1929691823
Short name	T639
Test name
Test status
Simulation time	5558220882 ps
CPU time	93 seconds
Started	Aug 29 12:24:36 PM UTC 24
Finished	Aug 29 12:26:11 PM UTC 24
Peak memory	261964 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929691823 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.1929691823 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/46.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/46.kmac_burst_write.4173640524
Short name	T690
Test name
Test status
Simulation time	63363326445 ps
CPU time	548.05 seconds
Started	Aug 29 12:24:33 PM UTC 24
Finished	Aug 29 12:33:49 PM UTC 24
Peak memory	251672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173640524 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.4173640524 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/46.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/46.kmac_entropy_refresh.2022222822
Short name	T665
Test name
Test status
Simulation time	67809630649 ps
CPU time	188.92 seconds
Started	Aug 29 12:24:45 PM UTC 24
Finished	Aug 29 12:27:58 PM UTC 24
Peak memory	382804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022222822 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.2022222822 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/46.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/46.kmac_error.473607672
Short name	T640
Test name
Test status
Simulation time	2607753163 ps
CPU time	79.57 seconds
Started	Aug 29 12:24:51 PM UTC 24
Finished	Aug 29 12:26:13 PM UTC 24
Peak memory	284576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473607672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.473607672 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/46.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/46.kmac_key_error.1078404412
Short name	T628
Test name
Test status
Simulation time	113910400 ps
CPU time	2.28 seconds
Started	Aug 29 12:24:57 PM UTC 24
Finished	Aug 29 12:25:01 PM UTC 24
Peak memory	230304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078404412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.1078404412 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/46.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/46.kmac_lc_escalation.2625728127
Short name	T630
Test name
Test status
Simulation time	136504311 ps
CPU time	2.1 seconds
Started	Aug 29 12:25:02 PM UTC 24
Finished	Aug 29 12:25:05 PM UTC 24
Peak memory	230444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625728127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.2625728127 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/46.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/46.kmac_long_msg_and_output.4007723315
Short name	T722
Test name
Test status
Simulation time	80466937705 ps
CPU time	2929.67 seconds
Started	Aug 29 12:24:21 PM UTC 24
Finished	Aug 29 01:13:47 PM UTC 24
Peak memory	3375016 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007723315 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_and_output.4007723315 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/46.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/46.kmac_sideload.2238884327
Short name	T669
Test name
Test status
Simulation time	9765304361 ps
CPU time	228.04 seconds
Started	Aug 29 12:24:31 PM UTC 24
Finished	Aug 29 12:28:24 PM UTC 24
Peak memory	313084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238884327 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.2238884327 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/46.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/46.kmac_smoke.2303693790
Short name	T626
Test name
Test status
Simulation time	2864413308 ps
CPU time	30.17 seconds
Started	Aug 29 12:24:19 PM UTC 24
Finished	Aug 29 12:24:50 PM UTC 24
Peak memory	230764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303693790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.2303693790 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/46.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/46.kmac_stress_all.1922292852
Short name	T700
Test name
Test status
Simulation time	26304241531 ps
CPU time	838.57 seconds
Started	Aug 29 12:25:04 PM UTC 24
Finished	Aug 29 12:39:13 PM UTC 24
Peak memory	577632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922292852 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.1922292852 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/46.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/47.kmac_alert_test.1452227605
Short name	T644
Test name
Test status
Simulation time	122863311 ps
CPU time	1.13 seconds
Started	Aug 29 12:26:18 PM UTC 24
Finished	Aug 29 12:26:20 PM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452227605 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.1452227605 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/47.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/47.kmac_app.4146665677
Short name	T674
Test name
Test status
Simulation time	64713304647 ps
CPU time	261.45 seconds
Started	Aug 29 12:25:27 PM UTC 24
Finished	Aug 29 12:29:53 PM UTC 24
Peak memory	456532 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146665677 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.4146665677 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/47.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/47.kmac_burst_write.4083272984
Short name	T696
Test name
Test status
Simulation time	53073416768 ps
CPU time	618.29 seconds
Started	Aug 29 12:25:22 PM UTC 24
Finished	Aug 29 12:35:49 PM UTC 24
Peak memory	253792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083272984 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.4083272984 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/47.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/47.kmac_entropy_refresh.329373886
Short name	T658
Test name
Test status
Simulation time	13607104779 ps
CPU time	98.1 seconds
Started	Aug 29 12:25:34 PM UTC 24
Finished	Aug 29 12:27:15 PM UTC 24
Peak memory	280404 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329373886 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.329373886 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/47.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/47.kmac_error.3051372026
Short name	T678
Test name
Test status
Simulation time	25696102174 ps
CPU time	277.87 seconds
Started	Aug 29 12:25:57 PM UTC 24
Finished	Aug 29 12:30:40 PM UTC 24
Peak memory	350048 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051372026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.3051372026 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/47.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/47.kmac_key_error.3171709079
Short name	T643
Test name
Test status
Simulation time	6248154476 ps
CPU time	12.57 seconds
Started	Aug 29 12:26:04 PM UTC 24
Finished	Aug 29 12:26:19 PM UTC 24
Peak memory	230652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171709079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.3171709079 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/47.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/47.kmac_lc_escalation.1305313026
Short name	T649
Test name
Test status
Simulation time	932337090 ps
CPU time	27 seconds
Started	Aug 29 12:26:13 PM UTC 24
Finished	Aug 29 12:26:41 PM UTC 24
Peak memory	253720 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305313026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.1305313026 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/47.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/47.kmac_long_msg_and_output.2294651277
Short name	T724
Test name
Test status
Simulation time	1042693416674 ps
CPU time	3185.54 seconds
Started	Aug 29 12:25:18 PM UTC 24
Finished	Aug 29 01:18:58 PM UTC 24
Peak memory	3534748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294651277 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_and_output.2294651277 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/47.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/47.kmac_sideload.3678440435
Short name	T638
Test name
Test status
Simulation time	1022934066 ps
CPU time	40.45 seconds
Started	Aug 29 12:25:22 PM UTC 24
Finished	Aug 29 12:26:04 PM UTC 24
Peak memory	251796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678440435 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.3678440435 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/47.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/47.kmac_smoke.231740701
Short name	T636
Test name
Test status
Simulation time	997459963 ps
CPU time	23.45 seconds
Started	Aug 29 12:25:09 PM UTC 24
Finished	Aug 29 12:25:33 PM UTC 24
Peak memory	230636 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231740701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.231740701 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/47.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/47.kmac_stress_all.2597174838
Short name	T697
Test name
Test status
Simulation time	152719508245 ps
CPU time	601.19 seconds
Started	Aug 29 12:26:14 PM UTC 24
Finished	Aug 29 12:36:23 PM UTC 24
Peak memory	649380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597174838 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.2597174838 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/47.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/48.kmac_alert_test.3229520770
Short name	T653
Test name
Test status
Simulation time	26407059 ps
CPU time	1.19 seconds
Started	Aug 29 12:27:04 PM UTC 24
Finished	Aug 29 12:27:06 PM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229520770 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.3229520770 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/48.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/48.kmac_app.1718579790
Short name	T680
Test name
Test status
Simulation time	14160200390 ps
CPU time	305.83 seconds
Started	Aug 29 12:26:28 PM UTC 24
Finished	Aug 29 12:31:39 PM UTC 24
Peak memory	475028 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718579790 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.1718579790 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/48.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/48.kmac_burst_write.3361313075
Short name	T688
Test name
Test status
Simulation time	4124659389 ps
CPU time	409.21 seconds
Started	Aug 29 12:26:27 PM UTC 24
Finished	Aug 29 12:33:23 PM UTC 24
Peak memory	243552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361313075 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.3361313075 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/48.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/48.kmac_entropy_refresh.3469288188
Short name	T654
Test name
Test status
Simulation time	851131821 ps
CPU time	23.3 seconds
Started	Aug 29 12:26:41 PM UTC 24
Finished	Aug 29 12:27:06 PM UTC 24
Peak memory	235220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469288188 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.3469288188 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/48.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/48.kmac_error.873899671
Short name	T673
Test name
Test status
Simulation time	3280705803 ps
CPU time	171.77 seconds
Started	Aug 29 12:26:41 PM UTC 24
Finished	Aug 29 12:29:36 PM UTC 24
Peak memory	294872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873899671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.873899671 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/48.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/48.kmac_key_error.3941412675
Short name	T652
Test name
Test status
Simulation time	7029139959 ps
CPU time	20.45 seconds
Started	Aug 29 12:26:41 PM UTC 24
Finished	Aug 29 12:27:03 PM UTC 24
Peak memory	230584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941412675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.3941412675 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/48.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/48.kmac_lc_escalation.1903524206
Short name	T100
Test name
Test status
Simulation time	55258980 ps
CPU time	1.81 seconds
Started	Aug 29 12:26:47 PM UTC 24
Finished	Aug 29 12:26:49 PM UTC 24
Peak memory	229720 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903524206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.1903524206 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/48.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/48.kmac_long_msg_and_output.3623342560
Short name	T728
Test name
Test status
Simulation time	710307945145 ps
CPU time	4864.12 seconds
Started	Aug 29 12:26:20 PM UTC 24
Finished	Aug 29 01:48:18 PM UTC 24
Peak memory	4624304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623342560 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_and_output.3623342560 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/48.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/48.kmac_sideload.1139269324
Short name	T681
Test name
Test status
Simulation time	59565436981 ps
CPU time	323.75 seconds
Started	Aug 29 12:26:21 PM UTC 24
Finished	Aug 29 12:31:50 PM UTC 24
Peak memory	522064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139269324 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.1139269324 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/48.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/48.kmac_smoke.2113363924
Short name	T646
Test name
Test status
Simulation time	404584918 ps
CPU time	7.58 seconds
Started	Aug 29 12:26:19 PM UTC 24
Finished	Aug 29 12:26:28 PM UTC 24
Peak memory	230596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113363924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.2113363924 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/48.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/48.kmac_stress_all.3746425744
Short name	T685
Test name
Test status
Simulation time	13144309848 ps
CPU time	357.66 seconds
Started	Aug 29 12:26:51 PM UTC 24
Finished	Aug 29 12:32:54 PM UTC 24
Peak memory	528160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746425744 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.3746425744 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/48.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/49.kmac_alert_test.3256458263
Short name	T662
Test name
Test status
Simulation time	29859808 ps
CPU time	1.1 seconds
Started	Aug 29 12:27:29 PM UTC 24
Finished	Aug 29 12:27:31 PM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256458263 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.3256458263 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/49.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/49.kmac_app.2407655470
Short name	T667
Test name
Test status
Simulation time	25483088430 ps
CPU time	59.97 seconds
Started	Aug 29 12:27:12 PM UTC 24
Finished	Aug 29 12:28:14 PM UTC 24
Peak memory	272220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407655470 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.2407655470 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/49.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/49.kmac_burst_write.1132537074
Short name	T660
Test name
Test status
Simulation time	337508691 ps
CPU time	13.31 seconds
Started	Aug 29 12:27:09 PM UTC 24
Finished	Aug 29 12:27:23 PM UTC 24
Peak memory	230640 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132537074 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.1132537074 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/49.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/49.kmac_entropy_refresh.1873481897
Short name	T675
Test name
Test status
Simulation time	7525613962 ps
CPU time	163.39 seconds
Started	Aug 29 12:27:14 PM UTC 24
Finished	Aug 29 12:30:01 PM UTC 24
Peak memory	350164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873481897 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.1873481897 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/49.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/49.kmac_error.3779101872
Short name	T672
Test name
Test status
Simulation time	4807576809 ps
CPU time	123.26 seconds
Started	Aug 29 12:27:15 PM UTC 24
Finished	Aug 29 12:29:21 PM UTC 24
Peak memory	341836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779101872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.3779101872 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/49.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/49.kmac_key_error.2994602512
Short name	T661
Test name
Test status
Simulation time	76140128 ps
CPU time	1.69 seconds
Started	Aug 29 12:27:24 PM UTC 24
Finished	Aug 29 12:27:26 PM UTC 24
Peak memory	229904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994602512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.2994602512 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/49.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/49.kmac_lc_escalation.2483939236
Short name	T70
Test name
Test status
Simulation time	116074082 ps
CPU time	1.84 seconds
Started	Aug 29 12:27:25 PM UTC 24
Finished	Aug 29 12:27:28 PM UTC 24
Peak memory	229804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483939236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.2483939236 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/49.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/49.kmac_long_msg_and_output.3546733113
Short name	T691
Test name
Test status
Simulation time	21152371120 ps
CPU time	396.73 seconds
Started	Aug 29 12:27:07 PM UTC 24
Finished	Aug 29 12:33:49 PM UTC 24
Peak memory	708384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546733113 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_and_output.3546733113 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/49.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/49.kmac_sideload.3605170468
Short name	T689
Test name
Test status
Simulation time	33769045511 ps
CPU time	390.94 seconds
Started	Aug 29 12:27:07 PM UTC 24
Finished	Aug 29 12:33:43 PM UTC 24
Peak memory	610120 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605170468 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.3605170468 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/49.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/49.kmac_smoke.916114829
Short name	T664
Test name
Test status
Simulation time	2785865783 ps
CPU time	29.7 seconds
Started	Aug 29 12:27:04 PM UTC 24
Finished	Aug 29 12:27:35 PM UTC 24
Peak memory	230580 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916114829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.916114829 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/49.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/49.kmac_stress_all.3308070682
Short name	T699
Test name
Test status
Simulation time	58838996833 ps
CPU time	656.74 seconds
Started	Aug 29 12:27:27 PM UTC 24
Finished	Aug 29 12:38:32 PM UTC 24
Peak memory	485212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308070682 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.3308070682 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/49.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/5.kmac_alert_test.1042634091
Short name	T203
Test name
Test status
Simulation time	26377596 ps
CPU time	1.19 seconds
Started	Aug 29 11:47:49 AM UTC 24
Finished	Aug 29 11:47:51 AM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042634091 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.1042634091 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/5.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/5.kmac_app.3212280745
Short name	T220
Test name
Test status
Simulation time	17589553445 ps
CPU time	130.01 seconds
Started	Aug 29 11:47:08 AM UTC 24
Finished	Aug 29 11:49:21 AM UTC 24
Peak memory	300900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212280745 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.3212280745 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/5.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/5.kmac_app_with_partial_data.3447709375
Short name	T240
Test name
Test status
Simulation time	24357963508 ps
CPU time	227.03 seconds
Started	Aug 29 11:47:08 AM UTC 24
Finished	Aug 29 11:50:59 AM UTC 24
Peak memory	317276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447709375 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.3447709375 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/5.kmac_app_with_partial_data/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/5.kmac_burst_write.2026176622
Short name	T57
Test name
Test status
Simulation time	4889664982 ps
CPU time	521.05 seconds
Started	Aug 29 11:47:07 AM UTC 24
Finished	Aug 29 11:55:55 AM UTC 24
Peak memory	245528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026176622 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.2026176622 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/5.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/5.kmac_edn_timeout_error.1633730568
Short name	T204
Test name
Test status
Simulation time	579862268 ps
CPU time	20.89 seconds
Started	Aug 29 11:47:31 AM UTC 24
Finished	Aug 29 11:47:54 AM UTC 24
Peak memory	228328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633730568 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.1633730568 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/5.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_mode_error.3863165524
Short name	T207
Test name
Test status
Simulation time	3253028194 ps
CPU time	47 seconds
Started	Aug 29 11:47:37 AM UTC 24
Finished	Aug 29 11:48:26 AM UTC 24
Peak memory	235228 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863165524 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.3863165524 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/5.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_ready_error.4061272885
Short name	T169
Test name
Test status
Simulation time	44190088598 ps
CPU time	47.67 seconds
Started	Aug 29 11:47:37 AM UTC 24
Finished	Aug 29 11:48:26 AM UTC 24
Peak memory	230628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061272885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.4061272885 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/5.kmac_entropy_ready_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_refresh.2556115962
Short name	T245
Test name
Test status
Simulation time	7347900106 ps
CPU time	241.08 seconds
Started	Aug 29 11:47:09 AM UTC 24
Finished	Aug 29 11:51:14 AM UTC 24
Peak memory	374624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556115962 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.2556115962 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/5.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/5.kmac_error.4071267842
Short name	T84
Test name
Test status
Simulation time	10821214488 ps
CPU time	97.39 seconds
Started	Aug 29 11:47:27 AM UTC 24
Finished	Aug 29 11:49:06 AM UTC 24
Peak memory	296768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071267842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.4071267842 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/5.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/5.kmac_key_error.3523189709
Short name	T72
Test name
Test status
Simulation time	2077410122 ps
CPU time	10.57 seconds
Started	Aug 29 11:47:29 AM UTC 24
Finished	Aug 29 11:47:41 AM UTC 24
Peak memory	230400 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523189709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.3523189709 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/5.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/5.kmac_lc_escalation.2094476953
Short name	T101
Test name
Test status
Simulation time	43250043 ps
CPU time	1.52 seconds
Started	Aug 29 11:47:39 AM UTC 24
Finished	Aug 29 11:47:42 AM UTC 24
Peak memory	234648 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094476953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.2094476953 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/5.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/5.kmac_long_msg_and_output.911205380
Short name	T362
Test name
Test status
Simulation time	32833916381 ps
CPU time	770.44 seconds
Started	Aug 29 11:47:02 AM UTC 24
Finished	Aug 29 12:00:03 PM UTC 24
Peak memory	704340 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911205380 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and_output.911205380 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/5.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/5.kmac_mubi.464654511
Short name	T89
Test name
Test status
Simulation time	27189381010 ps
CPU time	382.91 seconds
Started	Aug 29 11:47:27 AM UTC 24
Finished	Aug 29 11:53:55 AM UTC 24
Peak memory	544860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464654511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.464654511 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/5.kmac_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/5.kmac_sideload.2150065368
Short name	T215
Test name
Test status
Simulation time	7956047288 ps
CPU time	125.09 seconds
Started	Aug 29 11:47:04 AM UTC 24
Finished	Aug 29 11:49:12 AM UTC 24
Peak memory	315356 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150065368 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.2150065368 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/5.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/5.kmac_smoke.3287569126
Short name	T153
Test name
Test status
Simulation time	1415497244 ps
CPU time	22.51 seconds
Started	Aug 29 11:47:02 AM UTC 24
Finished	Aug 29 11:47:26 AM UTC 24
Peak memory	230512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287569126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.3287569126 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/5.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/5.kmac_stress_all.475938931
Short name	T361
Test name
Test status
Simulation time	99849614366 ps
CPU time	721.31 seconds
Started	Aug 29 11:47:41 AM UTC 24
Finished	Aug 29 11:59:52 AM UTC 24
Peak memory	725272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475938931 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.475938931 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/5.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/6.kmac_alert_test.1156156371
Short name	T209
Test name
Test status
Simulation time	14387413 ps
CPU time	1.14 seconds
Started	Aug 29 11:48:27 AM UTC 24
Finished	Aug 29 11:48:29 AM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156156371 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.1156156371 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/6.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/6.kmac_app.1038856013
Short name	T251
Test name
Test status
Simulation time	22134703633 ps
CPU time	191.52 seconds
Started	Aug 29 11:48:06 AM UTC 24
Finished	Aug 29 11:51:21 AM UTC 24
Peak memory	356116 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038856013 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.1038856013 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/6.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/6.kmac_app_with_partial_data.3268420974
Short name	T288
Test name
Test status
Simulation time	67557434489 ps
CPU time	345.18 seconds
Started	Aug 29 11:48:06 AM UTC 24
Finished	Aug 29 11:53:56 AM UTC 24
Peak memory	497560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268420974 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.3268420974 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/6.kmac_app_with_partial_data/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/6.kmac_burst_write.4154223542
Short name	T158
Test name
Test status
Simulation time	12549288713 ps
CPU time	87.94 seconds
Started	Aug 29 11:48:03 AM UTC 24
Finished	Aug 29 11:49:33 AM UTC 24
Peak memory	232652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154223542 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.4154223542 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/6.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/6.kmac_edn_timeout_error.1161957105
Short name	T210
Test name
Test status
Simulation time	327599107 ps
CPU time	29.65 seconds
Started	Aug 29 11:48:13 AM UTC 24
Finished	Aug 29 11:48:44 AM UTC 24
Peak memory	240884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161957105 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.1161957105 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/6.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_mode_error.1421113217
Short name	T211
Test name
Test status
Simulation time	346120705 ps
CPU time	27.37 seconds
Started	Aug 29 11:48:18 AM UTC 24
Finished	Aug 29 11:48:46 AM UTC 24
Peak memory	235092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421113217 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.1421113217 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/6.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_ready_error.3176479996
Short name	T208
Test name
Test status
Simulation time	2357880842 ps
CPU time	5.95 seconds
Started	Aug 29 11:48:19 AM UTC 24
Finished	Aug 29 11:48:26 AM UTC 24
Peak memory	230704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176479996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.3176479996 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/6.kmac_entropy_ready_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_refresh.2761558024
Short name	T254
Test name
Test status
Simulation time	6982499758 ps
CPU time	206.49 seconds
Started	Aug 29 11:48:07 AM UTC 24
Finished	Aug 29 11:51:37 AM UTC 24
Peak memory	317212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761558024 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.2761558024 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/6.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/6.kmac_error.1687862871
Short name	T29
Test name
Test status
Simulation time	4171793529 ps
CPU time	163.57 seconds
Started	Aug 29 11:48:09 AM UTC 24
Finished	Aug 29 11:50:56 AM UTC 24
Peak memory	311240 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687862871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.1687862871 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/6.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/6.kmac_key_error.564656862
Short name	T73
Test name
Test status
Simulation time	503615900 ps
CPU time	6.35 seconds
Started	Aug 29 11:48:11 AM UTC 24
Finished	Aug 29 11:48:18 AM UTC 24
Peak memory	230432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564656862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.564656862 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/6.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/6.kmac_lc_escalation.2928434158
Short name	T102
Test name
Test status
Simulation time	268188685 ps
CPU time	2.22 seconds
Started	Aug 29 11:48:20 AM UTC 24
Finished	Aug 29 11:48:23 AM UTC 24
Peak memory	235140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928434158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.2928434158 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/6.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/6.kmac_long_msg_and_output.1765421127
Short name	T236
Test name
Test status
Simulation time	3295000852 ps
CPU time	143.21 seconds
Started	Aug 29 11:47:54 AM UTC 24
Finished	Aug 29 11:50:19 AM UTC 24
Peak memory	325600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765421127 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and_output.1765421127 +enable_mas king=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/6.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/6.kmac_mubi.4110244233
Short name	T65
Test name
Test status
Simulation time	5280788927 ps
CPU time	72.9 seconds
Started	Aug 29 11:48:08 AM UTC 24
Finished	Aug 29 11:49:23 AM UTC 24
Peak memory	270412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110244233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.4110244233 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/6.kmac_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/6.kmac_sideload.2442602013
Short name	T39
Test name
Test status
Simulation time	58454450330 ps
CPU time	438.63 seconds
Started	Aug 29 11:47:55 AM UTC 24
Finished	Aug 29 11:55:19 AM UTC 24
Peak memory	630808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442602013 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.2442602013 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/6.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/6.kmac_smoke.1039295383
Short name	T206
Test name
Test status
Simulation time	2834590695 ps
CPU time	9.39 seconds
Started	Aug 29 11:47:52 AM UTC 24
Finished	Aug 29 11:48:02 AM UTC 24
Peak memory	230688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039295383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.1039295383 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/6.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/6.kmac_stress_all.1273734288
Short name	T524
Test name
Test status
Simulation time	301981760276 ps
CPU time	1669.06 seconds
Started	Aug 29 11:48:24 AM UTC 24
Finished	Aug 29 12:16:32 PM UTC 24
Peak memory	1251552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273734288 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.1273734288 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/6.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/7.kmac_alert_test.3576296439
Short name	T219
Test name
Test status
Simulation time	63164789 ps
CPU time	1.24 seconds
Started	Aug 29 11:49:14 AM UTC 24
Finished	Aug 29 11:49:17 AM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576296439 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.3576296439 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/7.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/7.kmac_app.16746767
Short name	T257
Test name
Test status
Simulation time	32968360836 ps
CPU time	172.57 seconds
Started	Aug 29 11:48:44 AM UTC 24
Finished	Aug 29 11:51:40 AM UTC 24
Peak memory	383012 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16746767 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.16746767 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/7.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/7.kmac_app_with_partial_data.1596779354
Short name	T222
Test name
Test status
Simulation time	1448340757 ps
CPU time	39.19 seconds
Started	Aug 29 11:48:47 AM UTC 24
Finished	Aug 29 11:49:28 AM UTC 24
Peak memory	237392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596779354 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.1596779354 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/7.kmac_app_with_partial_data/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/7.kmac_edn_timeout_error.2620985838
Short name	T223
Test name
Test status
Simulation time	916276757 ps
CPU time	31.52 seconds
Started	Aug 29 11:48:58 AM UTC 24
Finished	Aug 29 11:49:31 AM UTC 24
Peak memory	242792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620985838 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.2620985838 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/7.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_mode_error.2549394751
Short name	T225
Test name
Test status
Simulation time	1312234511 ps
CPU time	37.71 seconds
Started	Aug 29 11:48:59 AM UTC 24
Finished	Aug 29 11:49:38 AM UTC 24
Peak memory	232480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549394751 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.2549394751 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/7.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_ready_error.3910870845
Short name	T231
Test name
Test status
Simulation time	4490626692 ps
CPU time	51.75 seconds
Started	Aug 29 11:49:07 AM UTC 24
Finished	Aug 29 11:50:00 AM UTC 24
Peak memory	230808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910870845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.3910870845 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/7.kmac_entropy_ready_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_refresh.1389600352
Short name	T171
Test name
Test status
Simulation time	12816062754 ps
CPU time	269.65 seconds
Started	Aug 29 11:48:50 AM UTC 24
Finished	Aug 29 11:53:24 AM UTC 24
Peak memory	335900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389600352 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.1389600352 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/7.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/7.kmac_error.1643727252
Short name	T38
Test name
Test status
Simulation time	2083917243 ps
CPU time	174.71 seconds
Started	Aug 29 11:48:55 AM UTC 24
Finished	Aug 29 11:51:53 AM UTC 24
Peak memory	317272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643727252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.1643727252 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/7.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/7.kmac_key_error.3694648342
Short name	T74
Test name
Test status
Simulation time	77318128 ps
CPU time	1.9 seconds
Started	Aug 29 11:48:55 AM UTC 24
Finished	Aug 29 11:48:58 AM UTC 24
Peak memory	229720 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694648342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.3694648342 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/7.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/7.kmac_lc_escalation.1761561611
Short name	T218
Test name
Test status
Simulation time	129665467 ps
CPU time	1.92 seconds
Started	Aug 29 11:49:12 AM UTC 24
Finished	Aug 29 11:49:15 AM UTC 24
Peak memory	229832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761561611 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.1761561611 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/7.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/7.kmac_long_msg_and_output.868295787
Short name	T432
Test name
Test status
Simulation time	141097733678 ps
CPU time	1123.25 seconds
Started	Aug 29 11:48:28 AM UTC 24
Finished	Aug 29 12:07:25 PM UTC 24
Peak memory	1568576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868295787 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_and_output.868295787 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/7.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/7.kmac_mubi.891649828
Short name	T88
Test name
Test status
Simulation time	11748292010 ps
CPU time	280.62 seconds
Started	Aug 29 11:48:52 AM UTC 24
Finished	Aug 29 11:53:36 AM UTC 24
Peak memory	508132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891649828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.891649828 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/7.kmac_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/7.kmac_sideload.1652278422
Short name	T289
Test name
Test status
Simulation time	13173116088 ps
CPU time	321.68 seconds
Started	Aug 29 11:48:30 AM UTC 24
Finished	Aug 29 11:53:58 AM UTC 24
Peak memory	487196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652278422 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.1652278422 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/7.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/7.kmac_smoke.2537399636
Short name	T224
Test name
Test status
Simulation time	3596884156 ps
CPU time	65.92 seconds
Started	Aug 29 11:48:27 AM UTC 24
Finished	Aug 29 11:49:35 AM UTC 24
Peak memory	234732 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537399636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.2537399636 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/7.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/7.kmac_stress_all.2303187046
Short name	T86
Test name
Test status
Simulation time	6716169599 ps
CPU time	139.91 seconds
Started	Aug 29 11:49:12 AM UTC 24
Finished	Aug 29 11:51:35 AM UTC 24
Peak memory	346196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303187046 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.2303187046 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/7.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/8.kmac_alert_test.1260103039
Short name	T230
Test name
Test status
Simulation time	51305129 ps
CPU time	1.2 seconds
Started	Aug 29 11:49:51 AM UTC 24
Finished	Aug 29 11:49:53 AM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260103039 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.1260103039 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/8.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/8.kmac_app.528639064
Short name	T233
Test name
Test status
Simulation time	2712049527 ps
CPU time	42.54 seconds
Started	Aug 29 11:49:24 AM UTC 24
Finished	Aug 29 11:50:08 AM UTC 24
Peak memory	239456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528639064 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.528639064 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/8.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/8.kmac_app_with_partial_data.393227037
Short name	T247
Test name
Test status
Simulation time	19632369939 ps
CPU time	105.91 seconds
Started	Aug 29 11:49:29 AM UTC 24
Finished	Aug 29 11:51:17 AM UTC 24
Peak memory	309020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393227037 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.393227037 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/8.kmac_app_with_partial_data/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/8.kmac_burst_write.510412709
Short name	T364
Test name
Test status
Simulation time	47954988472 ps
CPU time	641.29 seconds
Started	Aug 29 11:49:23 AM UTC 24
Finished	Aug 29 12:00:13 PM UTC 24
Peak memory	251744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510412709 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.510412709 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/8.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/8.kmac_edn_timeout_error.3542724038
Short name	T235
Test name
Test status
Simulation time	1779064927 ps
CPU time	38.86 seconds
Started	Aug 29 11:49:35 AM UTC 24
Finished	Aug 29 11:50:16 AM UTC 24
Peak memory	232436 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542724038 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.3542724038 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/8.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_mode_error.416393056
Short name	T237
Test name
Test status
Simulation time	2902448467 ps
CPU time	40.65 seconds
Started	Aug 29 11:49:39 AM UTC 24
Finished	Aug 29 11:50:22 AM UTC 24
Peak memory	235344 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416393056 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.416393056 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/8.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_ready_error.397964650
Short name	T241
Test name
Test status
Simulation time	11555992056 ps
CPU time	80.26 seconds
Started	Aug 29 11:49:41 AM UTC 24
Finished	Aug 29 11:51:04 AM UTC 24
Peak memory	230576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397964650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_u nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.397964650 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/8.kmac_entropy_ready_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_refresh.2565045684
Short name	T294
Test name
Test status
Simulation time	42353902298 ps
CPU time	281.11 seconds
Started	Aug 29 11:49:29 AM UTC 24
Finished	Aug 29 11:54:15 AM UTC 24
Peak memory	392968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565045684 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.2565045684 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/8.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/8.kmac_error.4156780942
Short name	T272
Test name
Test status
Simulation time	8360680293 ps
CPU time	170.88 seconds
Started	Aug 29 11:49:31 AM UTC 24
Finished	Aug 29 11:52:25 AM UTC 24
Peak memory	390924 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156780942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.4156780942 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/8.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/8.kmac_key_error.6551199
Short name	T75
Test name
Test status
Simulation time	2873875288 ps
CPU time	17 seconds
Started	Aug 29 11:49:34 AM UTC 24
Finished	Aug 29 11:49:52 AM UTC 24
Peak memory	230480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6551199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.6551199 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/8.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/8.kmac_lc_escalation.4132681537
Short name	T229
Test name
Test status
Simulation time	87046484 ps
CPU time	2.73 seconds
Started	Aug 29 11:49:47 AM UTC 24
Finished	Aug 29 11:49:50 AM UTC 24
Peak memory	230360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132681537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.4132681537 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/8.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/8.kmac_long_msg_and_output.372079913
Short name	T354
Test name
Test status
Simulation time	69817804867 ps
CPU time	588.24 seconds
Started	Aug 29 11:49:18 AM UTC 24
Finished	Aug 29 11:59:13 AM UTC 24
Peak memory	1001304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372079913 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_and_output.372079913 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/8.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/8.kmac_mubi.623708037
Short name	T87
Test name
Test status
Simulation time	20149488114 ps
CPU time	147.56 seconds
Started	Aug 29 11:49:30 AM UTC 24
Finished	Aug 29 11:52:01 AM UTC 24
Peak memory	362720 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623708037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.623708037 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/8.kmac_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/8.kmac_sideload.4056962469
Short name	T227
Test name
Test status
Simulation time	2638884976 ps
CPU time	22.71 seconds
Started	Aug 29 11:49:22 AM UTC 24
Finished	Aug 29 11:49:46 AM UTC 24
Peak memory	245528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056962469 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.4056962469 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/8.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/8.kmac_smoke.2496070227
Short name	T234
Test name
Test status
Simulation time	19143436429 ps
CPU time	50.28 seconds
Started	Aug 29 11:49:17 AM UTC 24
Finished	Aug 29 11:50:08 AM UTC 24
Peak memory	235472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496070227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.2496070227 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/8.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/8.kmac_stress_all.583519764
Short name	T497
Test name
Test status
Simulation time	91828747656 ps
CPU time	1437.24 seconds
Started	Aug 29 11:49:50 AM UTC 24
Finished	Aug 29 12:14:04 PM UTC 24
Peak memory	1315052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583519764 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.583519764 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/8.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/9.kmac_alert_test.2417884681
Short name	T239
Test name
Test status
Simulation time	23070172 ps
CPU time	1.16 seconds
Started	Aug 29 11:50:56 AM UTC 24
Finished	Aug 29 11:50:59 AM UTC 24
Peak memory	214272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417884681 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.2417884681 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/9.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/9.kmac_app.2870838429
Short name	T249
Test name
Test status
Simulation time	5872719288 ps
CPU time	74.15 seconds
Started	Aug 29 11:50:03 AM UTC 24
Finished	Aug 29 11:51:19 AM UTC 24
Peak memory	260064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870838429 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.2870838429 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/9.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/9.kmac_app_with_partial_data.2573488430
Short name	T248
Test name
Test status
Simulation time	1145522522 ps
CPU time	66.83 seconds
Started	Aug 29 11:50:09 AM UTC 24
Finished	Aug 29 11:51:18 AM UTC 24
Peak memory	251712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573488430 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.2573488430 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/9.kmac_app_with_partial_data/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/9.kmac_burst_write.3795844570
Short name	T55
Test name
Test status
Simulation time	1211804676 ps
CPU time	64.32 seconds
Started	Aug 29 11:50:01 AM UTC 24
Finished	Aug 29 11:51:07 AM UTC 24
Peak memory	234800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795844570 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.3795844570 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/9.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/9.kmac_edn_timeout_error.1911667808
Short name	T238
Test name
Test status
Simulation time	421762288 ps
CPU time	21.19 seconds
Started	Aug 29 11:50:30 AM UTC 24
Finished	Aug 29 11:50:52 AM UTC 24
Peak memory	235216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911667808 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.1911667808 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/9.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_mode_error.933615113
Short name	T243
Test name
Test status
Simulation time	1350375717 ps
CPU time	27.24 seconds
Started	Aug 29 11:50:39 AM UTC 24
Finished	Aug 29 11:51:08 AM UTC 24
Peak memory	232492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933615113 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.933615113 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/9.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_ready_error.4006844230
Short name	T256
Test name
Test status
Simulation time	81750879802 ps
CPU time	54.65 seconds
Started	Aug 29 11:50:43 AM UTC 24
Finished	Aug 29 11:51:39 AM UTC 24
Peak memory	230572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006844230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.4006844230 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/9.kmac_entropy_ready_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_refresh.3779963503
Short name	T261
Test name
Test status
Simulation time	4009492494 ps
CPU time	100.51 seconds
Started	Aug 29 11:50:09 AM UTC 24
Finished	Aug 29 11:51:52 AM UTC 24
Peak memory	288648 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779963503 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.3779963503 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/9.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/9.kmac_error.2131093661
Short name	T268
Test name
Test status
Simulation time	4751313886 ps
CPU time	116.09 seconds
Started	Aug 29 11:50:20 AM UTC 24
Finished	Aug 29 11:52:19 AM UTC 24
Peak memory	278304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131093661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.2131093661 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/9.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/9.kmac_key_error.2788294957
Short name	T76
Test name
Test status
Simulation time	878544331 ps
CPU time	5.31 seconds
Started	Aug 29 11:50:23 AM UTC 24
Finished	Aug 29 11:50:29 AM UTC 24
Peak memory	230380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788294957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.2788294957 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/9.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/9.kmac_lc_escalation.4092987320
Short name	T46
Test name
Test status
Simulation time	102442235 ps
CPU time	1.92 seconds
Started	Aug 29 11:50:43 AM UTC 24
Finished	Aug 29 11:50:46 AM UTC 24
Peak memory	229832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092987320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.4092987320 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/9.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/9.kmac_long_msg_and_output.721211424
Short name	T331
Test name
Test status
Simulation time	19051707942 ps
CPU time	434.11 seconds
Started	Aug 29 11:49:53 AM UTC 24
Finished	Aug 29 11:57:13 AM UTC 24
Peak memory	503644 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721211424 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and_output.721211424 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/9.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/9.kmac_mubi.2144591668
Short name	T308
Test name
Test status
Simulation time	21554323954 ps
CPU time	300.95 seconds
Started	Aug 29 11:50:16 AM UTC 24
Finished	Aug 29 11:55:22 AM UTC 24
Peak memory	344144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144591668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.2144591668 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/9.kmac_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/9.kmac_sideload.2569958871
Short name	T296
Test name
Test status
Simulation time	2877831505 ps
CPU time	275.77 seconds
Started	Aug 29 11:49:54 AM UTC 24
Finished	Aug 29 11:54:34 AM UTC 24
Peak memory	329692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569958871 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.2569958871 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/9.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/9.kmac_smoke.4163491470
Short name	T244
Test name
Test status
Simulation time	2638675471 ps
CPU time	75.43 seconds
Started	Aug 29 11:49:53 AM UTC 24
Finished	Aug 29 11:51:10 AM UTC 24
Peak memory	235472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163491470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.4163491470 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/9.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default/9.kmac_stress_all.1870957150
Short name	T457
Test name
Test status
Simulation time	16572206979 ps
CPU time	1144.55 seconds
Started	Aug 29 11:50:47 AM UTC 24
Finished	Aug 29 12:10:06 PM UTC 24
Peak memory	708772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870957150 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.1870957150 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/9.kmac_stress_all/latest