Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	17608372	1			T1	84		T3	15		T4	152
all_values[1]	17608372	1			T1	84		T3	15		T4	152
all_values[2]	17608372	1			T1	84		T3	15		T4	152

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

582792

1

T1

6

T4

6

T14

199

auto[1]

52242324

1

T1

246

T3

45

T4

450

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52594452

1

T1

237

T3

45

T4

441

auto[1]

230664

1

T1

15

T4

15

T14

15

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	188824	1			T4	4		T14	58		T18	291
all_values[0]	auto[0]	auto[1]	1395	1			T4	2		T14	4		T18	4
all_values[0]	auto[1]	auto[0]	17342660	1			T1	79		T3	15		T4	143
all_values[0]	auto[1]	auto[1]	75493	1			T1	5		T4	3		T14	1
all_values[1]	auto[0]	auto[0]	188350	1			T1	5		T21	2		T22	410
all_values[1]	auto[0]	auto[1]	1028	1			T1	1		T22	5		T75	1
all_values[1]	auto[1]	auto[0]	17343134	1			T1	74		T3	15		T4	147
all_values[1]	auto[1]	auto[1]	75860	1			T1	4		T4	5		T14	5
all_values[2]	auto[0]	auto[0]	202155	1			T14	132		T17	19		T43	4
all_values[2]	auto[0]	auto[1]	1040	1			T14	5		T17	4		T43	3
all_values[2]	auto[1]	auto[0]	17329329	1			T1	79		T3	15		T4	147
all_values[2]	auto[1]	auto[1]	75848	1			T1	5		T4	5		T15	4