Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
62998 |
1 |
|
|
T1 |
6 |
|
T3 |
2 |
|
T4 |
6 |
auto[1] |
53768 |
1 |
|
|
T14 |
4 |
|
T15 |
4 |
|
T18 |
42 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
29247 |
1 |
|
|
T4 |
2 |
|
T14 |
2 |
|
T17 |
32 |
lower_val |
28784 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
zero_val |
870 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
1 |
2 |
66.67 |
User Defined Bins for wait_timer_val
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
zero_val |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
58386 |
1 |
|
|
T1 |
2 |
|
T14 |
6 |
|
T15 |
4 |
lower_val |
58380 |
1 |
|
|
T1 |
4 |
|
T3 |
2 |
|
T4 |
6 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
6 |
12 |
66.67 |
6 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
* |
[zero_val] |
* |
-- |
-- |
6 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
7913 |
1 |
|
|
T17 |
13 |
|
T43 |
33 |
|
T21 |
32 |
higher_val |
higher_val |
auto[1] |
6777 |
1 |
|
|
T14 |
2 |
|
T18 |
9 |
|
T80 |
35 |
higher_val |
lower_val |
auto[0] |
7750 |
1 |
|
|
T4 |
2 |
|
T17 |
19 |
|
T43 |
27 |
higher_val |
lower_val |
auto[1] |
6807 |
1 |
|
|
T18 |
10 |
|
T80 |
31 |
|
T32 |
6 |
lower_val |
higher_val |
auto[0] |
7661 |
1 |
|
|
T1 |
1 |
|
T17 |
22 |
|
T43 |
27 |
lower_val |
higher_val |
auto[1] |
6702 |
1 |
|
|
T14 |
1 |
|
T18 |
4 |
|
T80 |
32 |
lower_val |
lower_val |
auto[0] |
7717 |
1 |
|
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
23 |
lower_val |
lower_val |
auto[1] |
6704 |
1 |
|
|
T18 |
2 |
|
T80 |
34 |
|
T75 |
1 |
zero_val |
higher_val |
auto[0] |
337 |
1 |
|
|
T14 |
1 |
|
T17 |
1 |
|
T22 |
1 |
zero_val |
higher_val |
auto[1] |
98 |
1 |
|
|
T147 |
2 |
|
T26 |
1 |
|
T148 |
2 |
zero_val |
lower_val |
auto[0] |
357 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
zero_val |
lower_val |
auto[1] |
78 |
1 |
|
|
T35 |
1 |
|
T149 |
2 |
|
T83 |
1 |