Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	17608372	1			T1	84		T3	15		T4	152
all_pins[1]	17608372	1			T1	84		T3	15		T4	152
all_pins[2]	17608372	1			T1	84		T3	15		T4	152

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	52488609	1			T1	247		T3	45		T4	453
values[0x1]	336507	1			T1	5		T4	3		T14	1
transitions[0x0=>0x1]	334848	1			T1	5		T4	3		T14	1
transitions[0x1=>0x0]	334872	1			T1	5		T4	3		T14	1

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	17532879	1			T1	79		T3	15		T4	149
all_pins[0]	values[0x1]	75493	1			T1	5		T4	3		T14	1
all_pins[0]	transitions[0x0=>0x1]	75481	1			T1	5		T4	3		T14	1
all_pins[0]	transitions[0x1=>0x0]	62	1			T140	4		T166	2		T167	5
all_pins[1]	values[0x0]	17608298	1			T1	84		T3	15		T4	152
all_pins[1]	values[0x1]	74	1			T140	4		T166	2		T167	5
all_pins[1]	transitions[0x0=>0x1]	57	1			T140	4		T166	2		T167	5
all_pins[1]	transitions[0x1=>0x0]	260923	1			T22	2891		T51	789		T35	3252
all_pins[2]	values[0x0]	17347432	1			T1	84		T3	15		T4	152
all_pins[2]	values[0x1]	260940	1			T22	2891		T51	789		T35	3252
all_pins[2]	transitions[0x0=>0x1]	259310	1			T22	2873		T51	789		T35	3225
all_pins[2]	transitions[0x1=>0x0]	73887	1			T1	5		T4	3		T14	1