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76 always_ff @(posedge clk_i or negedge rst_ni) begin
77 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
78 1/1 err_q <= '0;
Tests: T1 T2 T3
79 1/1 end else if (intg_err || reg_we_err) begin
Tests: T1 T2 T3
80 1/1 err_q <= 1'b1;
Tests: T7 T11 T12
81 end
MISSING_ELSE
82 end
83
84 // integrity error output is permanent and should be used for alert generation
85 // register errors are transactional
86 1/1 assign intg_err_o = err_q | intg_err | reg_we_err;
Tests: T1 T2 T3
87
88 // outgoing integrity generation
89 tlul_pkg::tl_d2h_t tl_o_pre;
90 tlul_rsp_intg_gen #(
91 .EnableRspIntgGen(1),
92 .EnableDataIntgGen(1)
93 ) u_rsp_intg_gen (
94 .tl_i(tl_o_pre),
95 .tl_o(tl_o)
96 );
97
98 tlul_pkg::tl_h2d_t tl_socket_h2d [3];
99 tlul_pkg::tl_d2h_t tl_socket_d2h [3];
100
101 logic [1:0] reg_steer;
102
103 // socket_1n connection
104 1/1 assign tl_reg_h2d = tl_socket_h2d[2];
Tests: T1 T2 T3
105 1/1 assign tl_socket_d2h[2] = tl_reg_d2h;
Tests: T1 T2 T3
106
107 1/1 assign tl_win_o[0] = tl_socket_h2d[0];
Tests: T1 T2 T3
108 1/1 assign tl_socket_d2h[0] = tl_win_i[0];
Tests: T1 T2 T3
109 1/1 assign tl_win_o[1] = tl_socket_h2d[1];
Tests: T1 T2 T3
110 1/1 assign tl_socket_d2h[1] = tl_win_i[1];
Tests: T1 T2 T3
111
112 // Create Socket_1n
113 tlul_socket_1n #(
114 .N (3),
115 .HReqPass (1'b1),
116 .HRspPass (1'b1),
117 .DReqPass ({3{1'b1}}),
118 .DRspPass ({3{1'b1}}),
119 .HReqDepth (4'h0),
120 .HRspDepth (4'h0),
121 .DReqDepth ({3{4'h0}}),
122 .DRspDepth ({3{4'h0}}),
123 .ExplicitErrs (1'b0)
124 ) u_socket (
125 .clk_i (clk_i),
126 .rst_ni (rst_ni),
127 .tl_h_i (tl_i),
128 .tl_h_o (tl_o_pre),
129 .tl_d_o (tl_socket_h2d),
130 .tl_d_i (tl_socket_d2h),
131 .dev_select_i (reg_steer)
132 );
133
134 // Create steering logic
135 always_comb begin
136 1/1 reg_steer =
Tests: T1 T2 T3
137 tl_i.a_address[AW-1:0] inside {[1024:1535]} ? 2'd0 :
138 tl_i.a_address[AW-1:0] inside {[2048:4095]} ? 2'd1 :
139 // Default set to register
140 2'd2;
141
142 // Override this in case of an integrity error
143 1/1 if (intg_err) begin
Tests: T1 T2 T3
144 1/1 reg_steer = 2'd2;
Tests: T58 T104 T105
145 end
MISSING_ELSE
146 end
147
148 tlul_adapter_reg #(
149 .RegAw(AW),
150 .RegDw(DW),
151 .EnableDataIntgGen(0)
152 ) u_reg_if (
153 .clk_i (clk_i),
154 .rst_ni (rst_ni),
155
156 .tl_i (tl_reg_h2d),
157 .tl_o (tl_reg_d2h),
158
159 .en_ifetch_i(prim_mubi_pkg::MuBi4False),
160 .intg_error_o(),
161
162 .we_o (reg_we),
163 .re_o (reg_re),
164 .addr_o (reg_addr),
165 .wdata_o (reg_wdata),
166 .be_o (reg_be),
167 .busy_i (reg_busy),
168 .rdata_i (reg_rdata),
169 .error_i (reg_error)
170 );
171
172 // cdc oversampling signals
173
174 1/1 assign reg_rdata = reg_rdata_next ;
Tests: T1 T2 T3
175 1/1 assign reg_error = addrmiss | wr_err | intg_err;
Tests: T1 T2 T4
176
177 // Define SW related signals
178 // Format: <reg>_<field>_{wd|we|qs}
179 // or <reg>_{wd|we|qs} if field == 1 or 0
180 logic intr_state_we;
181 logic intr_state_kmac_done_qs;
182 logic intr_state_kmac_done_wd;
183 logic intr_state_fifo_empty_qs;
184 logic intr_state_kmac_err_qs;
185 logic intr_state_kmac_err_wd;
186 logic intr_enable_we;
187 logic intr_enable_kmac_done_qs;
188 logic intr_enable_kmac_done_wd;
189 logic intr_enable_fifo_empty_qs;
190 logic intr_enable_fifo_empty_wd;
191 logic intr_enable_kmac_err_qs;
192 logic intr_enable_kmac_err_wd;
193 logic intr_test_we;
194 logic intr_test_kmac_done_wd;
195 logic intr_test_fifo_empty_wd;
196 logic intr_test_kmac_err_wd;
197 logic alert_test_we;
198 logic alert_test_recov_operation_err_wd;
199 logic alert_test_fatal_fault_err_wd;
200 logic cfg_regwen_re;
201 logic cfg_regwen_qs;
202 logic cfg_shadowed_re;
203 logic cfg_shadowed_we;
204 logic cfg_shadowed_kmac_en_qs;
205 logic cfg_shadowed_kmac_en_wd;
206 logic cfg_shadowed_kmac_en_storage_err;
207 logic cfg_shadowed_kmac_en_update_err;
208 logic [2:0] cfg_shadowed_kstrength_qs;
209 logic [2:0] cfg_shadowed_kstrength_wd;
210 logic cfg_shadowed_kstrength_storage_err;
211 logic cfg_shadowed_kstrength_update_err;
212 logic [1:0] cfg_shadowed_mode_qs;
213 logic [1:0] cfg_shadowed_mode_wd;
214 logic cfg_shadowed_mode_storage_err;
215 logic cfg_shadowed_mode_update_err;
216 logic cfg_shadowed_msg_endianness_qs;
217 logic cfg_shadowed_msg_endianness_wd;
218 logic cfg_shadowed_msg_endianness_storage_err;
219 logic cfg_shadowed_msg_endianness_update_err;
220 logic cfg_shadowed_state_endianness_qs;
221 logic cfg_shadowed_state_endianness_wd;
222 logic cfg_shadowed_state_endianness_storage_err;
223 logic cfg_shadowed_state_endianness_update_err;
224 logic cfg_shadowed_sideload_qs;
225 logic cfg_shadowed_sideload_wd;
226 logic cfg_shadowed_sideload_storage_err;
227 logic cfg_shadowed_sideload_update_err;
228 logic [1:0] cfg_shadowed_entropy_mode_qs;
229 logic [1:0] cfg_shadowed_entropy_mode_wd;
230 logic cfg_shadowed_entropy_mode_storage_err;
231 logic cfg_shadowed_entropy_mode_update_err;
232 logic cfg_shadowed_entropy_fast_process_qs;
233 logic cfg_shadowed_entropy_fast_process_wd;
234 logic cfg_shadowed_entropy_fast_process_storage_err;
235 logic cfg_shadowed_entropy_fast_process_update_err;
236 logic cfg_shadowed_msg_mask_qs;
237 logic cfg_shadowed_msg_mask_wd;
238 logic cfg_shadowed_msg_mask_storage_err;
239 logic cfg_shadowed_msg_mask_update_err;
240 logic cfg_shadowed_entropy_ready_qs;
241 logic cfg_shadowed_entropy_ready_wd;
242 logic cfg_shadowed_entropy_ready_storage_err;
243 logic cfg_shadowed_entropy_ready_update_err;
244 logic cfg_shadowed_en_unsupported_modestrength_qs;
245 logic cfg_shadowed_en_unsupported_modestrength_wd;
246 logic cfg_shadowed_en_unsupported_modestrength_storage_err;
247 logic cfg_shadowed_en_unsupported_modestrength_update_err;
248 logic cmd_we;
249 logic [5:0] cmd_cmd_wd;
250 logic cmd_entropy_req_wd;
251 logic cmd_hash_cnt_clr_wd;
252 logic cmd_err_processed_wd;
253 logic status_re;
254 logic status_sha3_idle_qs;
255 logic status_sha3_absorb_qs;
256 logic status_sha3_squeeze_qs;
257 logic [4:0] status_fifo_depth_qs;
258 logic status_fifo_empty_qs;
259 logic status_fifo_full_qs;
260 logic status_alert_fatal_fault_qs;
261 logic status_alert_recov_ctrl_update_err_qs;
262 logic entropy_period_we;
263 logic [9:0] entropy_period_prescaler_qs;
264 logic [9:0] entropy_period_prescaler_wd;
265 logic [15:0] entropy_period_wait_timer_qs;
266 logic [15:0] entropy_period_wait_timer_wd;
267 logic [9:0] entropy_refresh_hash_cnt_qs;
268 logic entropy_refresh_threshold_shadowed_re;
269 logic entropy_refresh_threshold_shadowed_we;
270 logic [9:0] entropy_refresh_threshold_shadowed_qs;
271 logic [9:0] entropy_refresh_threshold_shadowed_wd;
272 logic entropy_refresh_threshold_shadowed_storage_err;
273 logic entropy_refresh_threshold_shadowed_update_err;
274 logic entropy_seed_we;
275 logic [31:0] entropy_seed_wd;
276 logic key_share0_0_we;
277 logic [31:0] key_share0_0_wd;
278 logic key_share0_1_we;
279 logic [31:0] key_share0_1_wd;
280 logic key_share0_2_we;
281 logic [31:0] key_share0_2_wd;
282 logic key_share0_3_we;
283 logic [31:0] key_share0_3_wd;
284 logic key_share0_4_we;
285 logic [31:0] key_share0_4_wd;
286 logic key_share0_5_we;
287 logic [31:0] key_share0_5_wd;
288 logic key_share0_6_we;
289 logic [31:0] key_share0_6_wd;
290 logic key_share0_7_we;
291 logic [31:0] key_share0_7_wd;
292 logic key_share0_8_we;
293 logic [31:0] key_share0_8_wd;
294 logic key_share0_9_we;
295 logic [31:0] key_share0_9_wd;
296 logic key_share0_10_we;
297 logic [31:0] key_share0_10_wd;
298 logic key_share0_11_we;
299 logic [31:0] key_share0_11_wd;
300 logic key_share0_12_we;
301 logic [31:0] key_share0_12_wd;
302 logic key_share0_13_we;
303 logic [31:0] key_share0_13_wd;
304 logic key_share0_14_we;
305 logic [31:0] key_share0_14_wd;
306 logic key_share0_15_we;
307 logic [31:0] key_share0_15_wd;
308 logic key_share1_0_we;
309 logic [31:0] key_share1_0_wd;
310 logic key_share1_1_we;
311 logic [31:0] key_share1_1_wd;
312 logic key_share1_2_we;
313 logic [31:0] key_share1_2_wd;
314 logic key_share1_3_we;
315 logic [31:0] key_share1_3_wd;
316 logic key_share1_4_we;
317 logic [31:0] key_share1_4_wd;
318 logic key_share1_5_we;
319 logic [31:0] key_share1_5_wd;
320 logic key_share1_6_we;
321 logic [31:0] key_share1_6_wd;
322 logic key_share1_7_we;
323 logic [31:0] key_share1_7_wd;
324 logic key_share1_8_we;
325 logic [31:0] key_share1_8_wd;
326 logic key_share1_9_we;
327 logic [31:0] key_share1_9_wd;
328 logic key_share1_10_we;
329 logic [31:0] key_share1_10_wd;
330 logic key_share1_11_we;
331 logic [31:0] key_share1_11_wd;
332 logic key_share1_12_we;
333 logic [31:0] key_share1_12_wd;
334 logic key_share1_13_we;
335 logic [31:0] key_share1_13_wd;
336 logic key_share1_14_we;
337 logic [31:0] key_share1_14_wd;
338 logic key_share1_15_we;
339 logic [31:0] key_share1_15_wd;
340 logic key_len_we;
341 logic [2:0] key_len_wd;
342 logic prefix_0_we;
343 logic [31:0] prefix_0_qs;
344 logic [31:0] prefix_0_wd;
345 logic prefix_1_we;
346 logic [31:0] prefix_1_qs;
347 logic [31:0] prefix_1_wd;
348 logic prefix_2_we;
349 logic [31:0] prefix_2_qs;
350 logic [31:0] prefix_2_wd;
351 logic prefix_3_we;
352 logic [31:0] prefix_3_qs;
353 logic [31:0] prefix_3_wd;
354 logic prefix_4_we;
355 logic [31:0] prefix_4_qs;
356 logic [31:0] prefix_4_wd;
357 logic prefix_5_we;
358 logic [31:0] prefix_5_qs;
359 logic [31:0] prefix_5_wd;
360 logic prefix_6_we;
361 logic [31:0] prefix_6_qs;
362 logic [31:0] prefix_6_wd;
363 logic prefix_7_we;
364 logic [31:0] prefix_7_qs;
365 logic [31:0] prefix_7_wd;
366 logic prefix_8_we;
367 logic [31:0] prefix_8_qs;
368 logic [31:0] prefix_8_wd;
369 logic prefix_9_we;
370 logic [31:0] prefix_9_qs;
371 logic [31:0] prefix_9_wd;
372 logic prefix_10_we;
373 logic [31:0] prefix_10_qs;
374 logic [31:0] prefix_10_wd;
375 logic [31:0] err_code_qs;
376
377 // Register instances
378 // R[intr_state]: V(False)
379 // F[kmac_done]: 0:0
380 prim_subreg #(
381 .DW (1),
382 .SwAccess(prim_subreg_pkg::SwAccessW1C),
383 .RESVAL (1'h0),
384 .Mubi (1'b0)
385 ) u_intr_state_kmac_done (
386 .clk_i (clk_i),
387 .rst_ni (rst_ni),
388
389 // from register interface
390 .we (intr_state_we),
391 .wd (intr_state_kmac_done_wd),
392
393 // from internal hardware
394 .de (hw2reg.intr_state.kmac_done.de),
395 .d (hw2reg.intr_state.kmac_done.d),
396
397 // to internal hardware
398 .qe (),
399 .q (reg2hw.intr_state.kmac_done.q),
400 .ds (),
401
402 // to register interface (read)
403 .qs (intr_state_kmac_done_qs)
404 );
405
406 // F[fifo_empty]: 1:1
407 prim_subreg #(
408 .DW (1),
409 .SwAccess(prim_subreg_pkg::SwAccessRO),
410 .RESVAL (1'h0),
411 .Mubi (1'b0)
412 ) u_intr_state_fifo_empty (
413 .clk_i (clk_i),
414 .rst_ni (rst_ni),
415
416 // from register interface
417 .we (1'b0),
418 .wd ('0),
419
420 // from internal hardware
421 .de (hw2reg.intr_state.fifo_empty.de),
422 .d (hw2reg.intr_state.fifo_empty.d),
423
424 // to internal hardware
425 .qe (),
426 .q (reg2hw.intr_state.fifo_empty.q),
427 .ds (),
428
429 // to register interface (read)
430 .qs (intr_state_fifo_empty_qs)
431 );
432
433 // F[kmac_err]: 2:2
434 prim_subreg #(
435 .DW (1),
436 .SwAccess(prim_subreg_pkg::SwAccessW1C),
437 .RESVAL (1'h0),
438 .Mubi (1'b0)
439 ) u_intr_state_kmac_err (
440 .clk_i (clk_i),
441 .rst_ni (rst_ni),
442
443 // from register interface
444 .we (intr_state_we),
445 .wd (intr_state_kmac_err_wd),
446
447 // from internal hardware
448 .de (hw2reg.intr_state.kmac_err.de),
449 .d (hw2reg.intr_state.kmac_err.d),
450
451 // to internal hardware
452 .qe (),
453 .q (reg2hw.intr_state.kmac_err.q),
454 .ds (),
455
456 // to register interface (read)
457 .qs (intr_state_kmac_err_qs)
458 );
459
460
461 // R[intr_enable]: V(False)
462 // F[kmac_done]: 0:0
463 prim_subreg #(
464 .DW (1),
465 .SwAccess(prim_subreg_pkg::SwAccessRW),
466 .RESVAL (1'h0),
467 .Mubi (1'b0)
468 ) u_intr_enable_kmac_done (
469 .clk_i (clk_i),
470 .rst_ni (rst_ni),
471
472 // from register interface
473 .we (intr_enable_we),
474 .wd (intr_enable_kmac_done_wd),
475
476 // from internal hardware
477 .de (1'b0),
478 .d ('0),
479
480 // to internal hardware
481 .qe (),
482 .q (reg2hw.intr_enable.kmac_done.q),
483 .ds (),
484
485 // to register interface (read)
486 .qs (intr_enable_kmac_done_qs)
487 );
488
489 // F[fifo_empty]: 1:1
490 prim_subreg #(
491 .DW (1),
492 .SwAccess(prim_subreg_pkg::SwAccessRW),
493 .RESVAL (1'h0),
494 .Mubi (1'b0)
495 ) u_intr_enable_fifo_empty (
496 .clk_i (clk_i),
497 .rst_ni (rst_ni),
498
499 // from register interface
500 .we (intr_enable_we),
501 .wd (intr_enable_fifo_empty_wd),
502
503 // from internal hardware
504 .de (1'b0),
505 .d ('0),
506
507 // to internal hardware
508 .qe (),
509 .q (reg2hw.intr_enable.fifo_empty.q),
510 .ds (),
511
512 // to register interface (read)
513 .qs (intr_enable_fifo_empty_qs)
514 );
515
516 // F[kmac_err]: 2:2
517 prim_subreg #(
518 .DW (1),
519 .SwAccess(prim_subreg_pkg::SwAccessRW),
520 .RESVAL (1'h0),
521 .Mubi (1'b0)
522 ) u_intr_enable_kmac_err (
523 .clk_i (clk_i),
524 .rst_ni (rst_ni),
525
526 // from register interface
527 .we (intr_enable_we),
528 .wd (intr_enable_kmac_err_wd),
529
530 // from internal hardware
531 .de (1'b0),
532 .d ('0),
533
534 // to internal hardware
535 .qe (),
536 .q (reg2hw.intr_enable.kmac_err.q),
537 .ds (),
538
539 // to register interface (read)
540 .qs (intr_enable_kmac_err_qs)
541 );
542
543
544 // R[intr_test]: V(True)
545 logic intr_test_qe;
546 logic [2:0] intr_test_flds_we;
547 1/1 assign intr_test_qe = &intr_test_flds_we;
Tests: T53 T106 T57
548 // F[kmac_done]: 0:0
549 prim_subreg_ext #(
550 .DW (1)
551 ) u_intr_test_kmac_done (
552 .re (1'b0),
553 .we (intr_test_we),
554 .wd (intr_test_kmac_done_wd),
555 .d ('0),
556 .qre (),
557 .qe (intr_test_flds_we[0]),
558 .q (reg2hw.intr_test.kmac_done.q),
559 .ds (),
560 .qs ()
561 );
562 1/1 assign reg2hw.intr_test.kmac_done.qe = intr_test_qe;
Tests: T53 T106 T57
563
564 // F[fifo_empty]: 1:1
565 prim_subreg_ext #(
566 .DW (1)
567 ) u_intr_test_fifo_empty (
568 .re (1'b0),
569 .we (intr_test_we),
570 .wd (intr_test_fifo_empty_wd),
571 .d ('0),
572 .qre (),
573 .qe (intr_test_flds_we[1]),
574 .q (reg2hw.intr_test.fifo_empty.q),
575 .ds (),
576 .qs ()
577 );
578 1/1 assign reg2hw.intr_test.fifo_empty.qe = intr_test_qe;
Tests: T53 T106 T57
579
580 // F[kmac_err]: 2:2
581 prim_subreg_ext #(
582 .DW (1)
583 ) u_intr_test_kmac_err (
584 .re (1'b0),
585 .we (intr_test_we),
586 .wd (intr_test_kmac_err_wd),
587 .d ('0),
588 .qre (),
589 .qe (intr_test_flds_we[2]),
590 .q (reg2hw.intr_test.kmac_err.q),
591 .ds (),
592 .qs ()
593 );
594 1/1 assign reg2hw.intr_test.kmac_err.qe = intr_test_qe;
Tests: T53 T106 T57
595
596
597 // R[alert_test]: V(True)
598 logic alert_test_qe;
599 logic [1:0] alert_test_flds_we;
600 1/1 assign alert_test_qe = &alert_test_flds_we;
Tests: T2 T55 T56
601 // F[recov_operation_err]: 0:0
602 prim_subreg_ext #(
603 .DW (1)
604 ) u_alert_test_recov_operation_err (
605 .re (1'b0),
606 .we (alert_test_we),
607 .wd (alert_test_recov_operation_err_wd),
608 .d ('0),
609 .qre (),
610 .qe (alert_test_flds_we[0]),
611 .q (reg2hw.alert_test.recov_operation_err.q),
612 .ds (),
613 .qs ()
614 );
615 1/1 assign reg2hw.alert_test.recov_operation_err.qe = alert_test_qe;
Tests: T2 T55 T56
616
617 // F[fatal_fault_err]: 1:1
618 prim_subreg_ext #(
619 .DW (1)
620 ) u_alert_test_fatal_fault_err (
621 .re (1'b0),
622 .we (alert_test_we),
623 .wd (alert_test_fatal_fault_err_wd),
624 .d ('0),
625 .qre (),
626 .qe (alert_test_flds_we[1]),
627 .q (reg2hw.alert_test.fatal_fault_err.q),
628 .ds (),
629 .qs ()
630 );
631 1/1 assign reg2hw.alert_test.fatal_fault_err.qe = alert_test_qe;
Tests: T2 T55 T56
632
633
634 // R[cfg_regwen]: V(True)
635 prim_subreg_ext #(
636 .DW (1)
637 ) u_cfg_regwen (
638 .re (cfg_regwen_re),
639 .we (1'b0),
640 .wd ('0),
641 .d (hw2reg.cfg_regwen.d),
642 .qre (),
643 .qe (),
644 .q (),
645 .ds (),
646 .qs (cfg_regwen_qs)
647 );
648
649
650 // R[cfg_shadowed]: V(False)
651 logic cfg_shadowed_qe;
652 logic [10:0] cfg_shadowed_flds_we;
653 prim_flop #(
654 .Width(1),
655 .ResetValue(0)
656 ) u_cfg_shadowed0_qe (
657 .clk_i(clk_i),
658 .rst_ni(rst_ni),
659 .d_i(&cfg_shadowed_flds_we),
660 .q_o(cfg_shadowed_qe)
661 );
662 // Create REGWEN-gated WE signal
663 logic cfg_shadowed_gated_we;
664 1/1 assign cfg_shadowed_gated_we = cfg_shadowed_we & cfg_regwen_qs;
Tests: T1 T2 T3
665 // F[kmac_en]: 0:0
666 prim_subreg_shadow #(
667 .DW (1),
668 .SwAccess(prim_subreg_pkg::SwAccessRW),
669 .RESVAL (1'h0),
670 .Mubi (1'b0)
671 ) u_cfg_shadowed_kmac_en (
672 .clk_i (clk_i),
673 .rst_ni (rst_ni),
674 .rst_shadowed_ni (rst_shadowed_ni),
675
676 // from register interface
677 .re (cfg_shadowed_re),
678 .we (cfg_shadowed_gated_we),
679 .wd (cfg_shadowed_kmac_en_wd),
680
681 // from internal hardware
682 .de (1'b0),
683 .d ('0),
684
685 // to internal hardware
686 .qe (cfg_shadowed_flds_we[0]),
687 .q (reg2hw.cfg_shadowed.kmac_en.q),
688 .ds (),
689
690 // to register interface (read)
691 .qs (cfg_shadowed_kmac_en_qs),
692
693 // Shadow register phase. Relevant for hwext only.
694 .phase (),
695
696 // Shadow register error conditions
697 .err_update (cfg_shadowed_kmac_en_update_err),
698 .err_storage (cfg_shadowed_kmac_en_storage_err)
699 );
700 1/1 assign reg2hw.cfg_shadowed.kmac_en.qe = cfg_shadowed_qe;
Tests: T1 T2 T3
701
702 // F[kstrength]: 3:1
703 prim_subreg_shadow #(
704 .DW (3),
705 .SwAccess(prim_subreg_pkg::SwAccessRW),
706 .RESVAL (3'h0),
707 .Mubi (1'b0)
708 ) u_cfg_shadowed_kstrength (
709 .clk_i (clk_i),
710 .rst_ni (rst_ni),
711 .rst_shadowed_ni (rst_shadowed_ni),
712
713 // from register interface
714 .re (cfg_shadowed_re),
715 .we (cfg_shadowed_gated_we),
716 .wd (cfg_shadowed_kstrength_wd),
717
718 // from internal hardware
719 .de (1'b0),
720 .d ('0),
721
722 // to internal hardware
723 .qe (cfg_shadowed_flds_we[1]),
724 .q (reg2hw.cfg_shadowed.kstrength.q),
725 .ds (),
726
727 // to register interface (read)
728 .qs (cfg_shadowed_kstrength_qs),
729
730 // Shadow register phase. Relevant for hwext only.
731 .phase (),
732
733 // Shadow register error conditions
734 .err_update (cfg_shadowed_kstrength_update_err),
735 .err_storage (cfg_shadowed_kstrength_storage_err)
736 );
737 1/1 assign reg2hw.cfg_shadowed.kstrength.qe = cfg_shadowed_qe;
Tests: T1 T2 T3
738
739 // F[mode]: 5:4
740 prim_subreg_shadow #(
741 .DW (2),
742 .SwAccess(prim_subreg_pkg::SwAccessRW),
743 .RESVAL (2'h0),
744 .Mubi (1'b0)
745 ) u_cfg_shadowed_mode (
746 .clk_i (clk_i),
747 .rst_ni (rst_ni),
748 .rst_shadowed_ni (rst_shadowed_ni),
749
750 // from register interface
751 .re (cfg_shadowed_re),
752 .we (cfg_shadowed_gated_we),
753 .wd (cfg_shadowed_mode_wd),
754
755 // from internal hardware
756 .de (1'b0),
757 .d ('0),
758
759 // to internal hardware
760 .qe (cfg_shadowed_flds_we[2]),
761 .q (reg2hw.cfg_shadowed.mode.q),
762 .ds (),
763
764 // to register interface (read)
765 .qs (cfg_shadowed_mode_qs),
766
767 // Shadow register phase. Relevant for hwext only.
768 .phase (),
769
770 // Shadow register error conditions
771 .err_update (cfg_shadowed_mode_update_err),
772 .err_storage (cfg_shadowed_mode_storage_err)
773 );
774 1/1 assign reg2hw.cfg_shadowed.mode.qe = cfg_shadowed_qe;
Tests: T1 T2 T3
775
776 // F[msg_endianness]: 8:8
777 prim_subreg_shadow #(
778 .DW (1),
779 .SwAccess(prim_subreg_pkg::SwAccessRW),
780 .RESVAL (1'h0),
781 .Mubi (1'b0)
782 ) u_cfg_shadowed_msg_endianness (
783 .clk_i (clk_i),
784 .rst_ni (rst_ni),
785 .rst_shadowed_ni (rst_shadowed_ni),
786
787 // from register interface
788 .re (cfg_shadowed_re),
789 .we (cfg_shadowed_gated_we),
790 .wd (cfg_shadowed_msg_endianness_wd),
791
792 // from internal hardware
793 .de (1'b0),
794 .d ('0),
795
796 // to internal hardware
797 .qe (cfg_shadowed_flds_we[3]),
798 .q (reg2hw.cfg_shadowed.msg_endianness.q),
799 .ds (),
800
801 // to register interface (read)
802 .qs (cfg_shadowed_msg_endianness_qs),
803
804 // Shadow register phase. Relevant for hwext only.
805 .phase (),
806
807 // Shadow register error conditions
808 .err_update (cfg_shadowed_msg_endianness_update_err),
809 .err_storage (cfg_shadowed_msg_endianness_storage_err)
810 );
811 1/1 assign reg2hw.cfg_shadowed.msg_endianness.qe = cfg_shadowed_qe;
Tests: T1 T2 T3
812
813 // F[state_endianness]: 9:9
814 prim_subreg_shadow #(
815 .DW (1),
816 .SwAccess(prim_subreg_pkg::SwAccessRW),
817 .RESVAL (1'h0),
818 .Mubi (1'b0)
819 ) u_cfg_shadowed_state_endianness (
820 .clk_i (clk_i),
821 .rst_ni (rst_ni),
822 .rst_shadowed_ni (rst_shadowed_ni),
823
824 // from register interface
825 .re (cfg_shadowed_re),
826 .we (cfg_shadowed_gated_we),
827 .wd (cfg_shadowed_state_endianness_wd),
828
829 // from internal hardware
830 .de (1'b0),
831 .d ('0),
832
833 // to internal hardware
834 .qe (cfg_shadowed_flds_we[4]),
835 .q (reg2hw.cfg_shadowed.state_endianness.q),
836 .ds (),
837
838 // to register interface (read)
839 .qs (cfg_shadowed_state_endianness_qs),
840
841 // Shadow register phase. Relevant for hwext only.
842 .phase (),
843
844 // Shadow register error conditions
845 .err_update (cfg_shadowed_state_endianness_update_err),
846 .err_storage (cfg_shadowed_state_endianness_storage_err)
847 );
848 1/1 assign reg2hw.cfg_shadowed.state_endianness.qe = cfg_shadowed_qe;
Tests: T1 T2 T3
849
850 // F[sideload]: 12:12
851 prim_subreg_shadow #(
852 .DW (1),
853 .SwAccess(prim_subreg_pkg::SwAccessRW),
854 .RESVAL (1'h0),
855 .Mubi (1'b0)
856 ) u_cfg_shadowed_sideload (
857 .clk_i (clk_i),
858 .rst_ni (rst_ni),
859 .rst_shadowed_ni (rst_shadowed_ni),
860
861 // from register interface
862 .re (cfg_shadowed_re),
863 .we (cfg_shadowed_gated_we),
864 .wd (cfg_shadowed_sideload_wd),
865
866 // from internal hardware
867 .de (1'b0),
868 .d ('0),
869
870 // to internal hardware
871 .qe (cfg_shadowed_flds_we[5]),
872 .q (reg2hw.cfg_shadowed.sideload.q),
873 .ds (),
874
875 // to register interface (read)
876 .qs (cfg_shadowed_sideload_qs),
877
878 // Shadow register phase. Relevant for hwext only.
879 .phase (),
880
881 // Shadow register error conditions
882 .err_update (cfg_shadowed_sideload_update_err),
883 .err_storage (cfg_shadowed_sideload_storage_err)
884 );
885 1/1 assign reg2hw.cfg_shadowed.sideload.qe = cfg_shadowed_qe;
Tests: T1 T2 T3
886
887 // F[entropy_mode]: 17:16
888 prim_subreg_shadow #(
889 .DW (2),
890 .SwAccess(prim_subreg_pkg::SwAccessRW),
891 .RESVAL (2'h0),
892 .Mubi (1'b0)
893 ) u_cfg_shadowed_entropy_mode (
894 .clk_i (clk_i),
895 .rst_ni (rst_ni),
896 .rst_shadowed_ni (rst_shadowed_ni),
897
898 // from register interface
899 .re (cfg_shadowed_re),
900 .we (cfg_shadowed_gated_we),
901 .wd (cfg_shadowed_entropy_mode_wd),
902
903 // from internal hardware
904 .de (1'b0),
905 .d ('0),
906
907 // to internal hardware
908 .qe (cfg_shadowed_flds_we[6]),
909 .q (reg2hw.cfg_shadowed.entropy_mode.q),
910 .ds (),
911
912 // to register interface (read)
913 .qs (cfg_shadowed_entropy_mode_qs),
914
915 // Shadow register phase. Relevant for hwext only.
916 .phase (),
917
918 // Shadow register error conditions
919 .err_update (cfg_shadowed_entropy_mode_update_err),
920 .err_storage (cfg_shadowed_entropy_mode_storage_err)
921 );
922 1/1 assign reg2hw.cfg_shadowed.entropy_mode.qe = cfg_shadowed_qe;
Tests: T1 T2 T3
923
924 // F[entropy_fast_process]: 19:19
925 prim_subreg_shadow #(
926 .DW (1),
927 .SwAccess(prim_subreg_pkg::SwAccessRW),
928 .RESVAL (1'h0),
929 .Mubi (1'b0)
930 ) u_cfg_shadowed_entropy_fast_process (
931 .clk_i (clk_i),
932 .rst_ni (rst_ni),
933 .rst_shadowed_ni (rst_shadowed_ni),
934
935 // from register interface
936 .re (cfg_shadowed_re),
937 .we (cfg_shadowed_gated_we),
938 .wd (cfg_shadowed_entropy_fast_process_wd),
939
940 // from internal hardware
941 .de (1'b0),
942 .d ('0),
943
944 // to internal hardware
945 .qe (cfg_shadowed_flds_we[7]),
946 .q (reg2hw.cfg_shadowed.entropy_fast_process.q),
947 .ds (),
948
949 // to register interface (read)
950 .qs (cfg_shadowed_entropy_fast_process_qs),
951
952 // Shadow register phase. Relevant for hwext only.
953 .phase (),
954
955 // Shadow register error conditions
956 .err_update (cfg_shadowed_entropy_fast_process_update_err),
957 .err_storage (cfg_shadowed_entropy_fast_process_storage_err)
958 );
959 1/1 assign reg2hw.cfg_shadowed.entropy_fast_process.qe = cfg_shadowed_qe;
Tests: T1 T2 T3
960
961 // F[msg_mask]: 20:20
962 prim_subreg_shadow #(
963 .DW (1),
964 .SwAccess(prim_subreg_pkg::SwAccessRW),
965 .RESVAL (1'h0),
966 .Mubi (1'b0)
967 ) u_cfg_shadowed_msg_mask (
968 .clk_i (clk_i),
969 .rst_ni (rst_ni),
970 .rst_shadowed_ni (rst_shadowed_ni),
971
972 // from register interface
973 .re (cfg_shadowed_re),
974 .we (cfg_shadowed_gated_we),
975 .wd (cfg_shadowed_msg_mask_wd),
976
977 // from internal hardware
978 .de (1'b0),
979 .d ('0),
980
981 // to internal hardware
982 .qe (cfg_shadowed_flds_we[8]),
983 .q (reg2hw.cfg_shadowed.msg_mask.q),
984 .ds (),
985
986 // to register interface (read)
987 .qs (cfg_shadowed_msg_mask_qs),
988
989 // Shadow register phase. Relevant for hwext only.
990 .phase (),
991
992 // Shadow register error conditions
993 .err_update (cfg_shadowed_msg_mask_update_err),
994 .err_storage (cfg_shadowed_msg_mask_storage_err)
995 );
996 1/1 assign reg2hw.cfg_shadowed.msg_mask.qe = cfg_shadowed_qe;
Tests: T1 T2 T3
997
998 // F[entropy_ready]: 24:24
999 prim_subreg_shadow #(
1000 .DW (1),
1001 .SwAccess(prim_subreg_pkg::SwAccessRW),
1002 .RESVAL (1'h0),
1003 .Mubi (1'b0)
1004 ) u_cfg_shadowed_entropy_ready (
1005 .clk_i (clk_i),
1006 .rst_ni (rst_ni),
1007 .rst_shadowed_ni (rst_shadowed_ni),
1008
1009 // from register interface
1010 .re (cfg_shadowed_re),
1011 .we (cfg_shadowed_gated_we),
1012 .wd (cfg_shadowed_entropy_ready_wd),
1013
1014 // from internal hardware
1015 .de (1'b0),
1016 .d ('0),
1017
1018 // to internal hardware
1019 .qe (cfg_shadowed_flds_we[9]),
1020 .q (reg2hw.cfg_shadowed.entropy_ready.q),
1021 .ds (),
1022
1023 // to register interface (read)
1024 .qs (cfg_shadowed_entropy_ready_qs),
1025
1026 // Shadow register phase. Relevant for hwext only.
1027 .phase (),
1028
1029 // Shadow register error conditions
1030 .err_update (cfg_shadowed_entropy_ready_update_err),
1031 .err_storage (cfg_shadowed_entropy_ready_storage_err)
1032 );
1033 1/1 assign reg2hw.cfg_shadowed.entropy_ready.qe = cfg_shadowed_qe;
Tests: T1 T2 T3
1034
1035 // F[en_unsupported_modestrength]: 26:26
1036 prim_subreg_shadow #(
1037 .DW (1),
1038 .SwAccess(prim_subreg_pkg::SwAccessRW),
1039 .RESVAL (1'h0),
1040 .Mubi (1'b0)
1041 ) u_cfg_shadowed_en_unsupported_modestrength (
1042 .clk_i (clk_i),
1043 .rst_ni (rst_ni),
1044 .rst_shadowed_ni (rst_shadowed_ni),
1045
1046 // from register interface
1047 .re (cfg_shadowed_re),
1048 .we (cfg_shadowed_gated_we),
1049 .wd (cfg_shadowed_en_unsupported_modestrength_wd),
1050
1051 // from internal hardware
1052 .de (1'b0),
1053 .d ('0),
1054
1055 // to internal hardware
1056 .qe (cfg_shadowed_flds_we[10]),
1057 .q (reg2hw.cfg_shadowed.en_unsupported_modestrength.q),
1058 .ds (),
1059
1060 // to register interface (read)
1061 .qs (cfg_shadowed_en_unsupported_modestrength_qs),
1062
1063 // Shadow register phase. Relevant for hwext only.
1064 .phase (),
1065
1066 // Shadow register error conditions
1067 .err_update (cfg_shadowed_en_unsupported_modestrength_update_err),
1068 .err_storage (cfg_shadowed_en_unsupported_modestrength_storage_err)
1069 );
1070 1/1 assign reg2hw.cfg_shadowed.en_unsupported_modestrength.qe = cfg_shadowed_qe;
Tests: T1 T2 T3
1071
1072
1073 // R[cmd]: V(True)
1074 logic cmd_qe;
1075 logic [3:0] cmd_flds_we;
1076 1/1 assign cmd_qe = &cmd_flds_we;
Tests: T1 T3 T4
1077 // F[cmd]: 5:0
1078 prim_subreg_ext #(
1079 .DW (6)
1080 ) u_cmd_cmd (
1081 .re (1'b0),
1082 .we (cmd_we),
1083 .wd (cmd_cmd_wd),
1084 .d ('0),
1085 .qre (),
1086 .qe (cmd_flds_we[0]),
1087 .q (reg2hw.cmd.cmd.q),
1088 .ds (),
1089 .qs ()
1090 );
1091 1/1 assign reg2hw.cmd.cmd.qe = cmd_qe;
Tests: T1 T3 T4
1092
1093 // F[entropy_req]: 8:8
1094 prim_subreg_ext #(
1095 .DW (1)
1096 ) u_cmd_entropy_req (
1097 .re (1'b0),
1098 .we (cmd_we),
1099 .wd (cmd_entropy_req_wd),
1100 .d ('0),
1101 .qre (),
1102 .qe (cmd_flds_we[1]),
1103 .q (reg2hw.cmd.entropy_req.q),
1104 .ds (),
1105 .qs ()
1106 );
1107 1/1 assign reg2hw.cmd.entropy_req.qe = cmd_qe;
Tests: T1 T3 T4
1108
1109 // F[hash_cnt_clr]: 9:9
1110 prim_subreg_ext #(
1111 .DW (1)
1112 ) u_cmd_hash_cnt_clr (
1113 .re (1'b0),
1114 .we (cmd_we),
1115 .wd (cmd_hash_cnt_clr_wd),
1116 .d ('0),
1117 .qre (),
1118 .qe (cmd_flds_we[2]),
1119 .q (reg2hw.cmd.hash_cnt_clr.q),
1120 .ds (),
1121 .qs ()
1122 );
1123 1/1 assign reg2hw.cmd.hash_cnt_clr.qe = cmd_qe;
Tests: T1 T3 T4
1124
1125 // F[err_processed]: 10:10
1126 prim_subreg_ext #(
1127 .DW (1)
1128 ) u_cmd_err_processed (
1129 .re (1'b0),
1130 .we (cmd_we),
1131 .wd (cmd_err_processed_wd),
1132 .d ('0),
1133 .qre (),
1134 .qe (cmd_flds_we[3]),
1135 .q (reg2hw.cmd.err_processed.q),
1136 .ds (),
1137 .qs ()
1138 );
1139 1/1 assign reg2hw.cmd.err_processed.qe = cmd_qe;
Tests: T1 T3 T4
1140
1141
1142 // R[status]: V(True)
1143 // F[sha3_idle]: 0:0
1144 prim_subreg_ext #(
1145 .DW (1)
1146 ) u_status_sha3_idle (
1147 .re (status_re),
1148 .we (1'b0),
1149 .wd ('0),
1150 .d (hw2reg.status.sha3_idle.d),
1151 .qre (),
1152 .qe (),
1153 .q (),
1154 .ds (),
1155 .qs (status_sha3_idle_qs)
1156 );
1157
1158 // F[sha3_absorb]: 1:1
1159 prim_subreg_ext #(
1160 .DW (1)
1161 ) u_status_sha3_absorb (
1162 .re (status_re),
1163 .we (1'b0),
1164 .wd ('0),
1165 .d (hw2reg.status.sha3_absorb.d),
1166 .qre (),
1167 .qe (),
1168 .q (),
1169 .ds (),
1170 .qs (status_sha3_absorb_qs)
1171 );
1172
1173 // F[sha3_squeeze]: 2:2
1174 prim_subreg_ext #(
1175 .DW (1)
1176 ) u_status_sha3_squeeze (
1177 .re (status_re),
1178 .we (1'b0),
1179 .wd ('0),
1180 .d (hw2reg.status.sha3_squeeze.d),
1181 .qre (),
1182 .qe (),
1183 .q (),
1184 .ds (),
1185 .qs (status_sha3_squeeze_qs)
1186 );
1187
1188 // F[fifo_depth]: 12:8
1189 prim_subreg_ext #(
1190 .DW (5)
1191 ) u_status_fifo_depth (
1192 .re (status_re),
1193 .we (1'b0),
1194 .wd ('0),
1195 .d (hw2reg.status.fifo_depth.d),
1196 .qre (),
1197 .qe (),
1198 .q (),
1199 .ds (),
1200 .qs (status_fifo_depth_qs)
1201 );
1202
1203 // F[fifo_empty]: 14:14
1204 prim_subreg_ext #(
1205 .DW (1)
1206 ) u_status_fifo_empty (
1207 .re (status_re),
1208 .we (1'b0),
1209 .wd ('0),
1210 .d (hw2reg.status.fifo_empty.d),
1211 .qre (),
1212 .qe (),
1213 .q (),
1214 .ds (),
1215 .qs (status_fifo_empty_qs)
1216 );
1217
1218 // F[fifo_full]: 15:15
1219 prim_subreg_ext #(
1220 .DW (1)
1221 ) u_status_fifo_full (
1222 .re (status_re),
1223 .we (1'b0),
1224 .wd ('0),
1225 .d (hw2reg.status.fifo_full.d),
1226 .qre (),
1227 .qe (),
1228 .q (),
1229 .ds (),
1230 .qs (status_fifo_full_qs)
1231 );
1232
1233 // F[alert_fatal_fault]: 16:16
1234 prim_subreg_ext #(
1235 .DW (1)
1236 ) u_status_alert_fatal_fault (
1237 .re (status_re),
1238 .we (1'b0),
1239 .wd ('0),
1240 .d (hw2reg.status.alert_fatal_fault.d),
1241 .qre (),
1242 .qe (),
1243 .q (),
1244 .ds (),
1245 .qs (status_alert_fatal_fault_qs)
1246 );
1247
1248 // F[alert_recov_ctrl_update_err]: 17:17
1249 prim_subreg_ext #(
1250 .DW (1)
1251 ) u_status_alert_recov_ctrl_update_err (
1252 .re (status_re),
1253 .we (1'b0),
1254 .wd ('0),
1255 .d (hw2reg.status.alert_recov_ctrl_update_err.d),
1256 .qre (),
1257 .qe (),
1258 .q (),
1259 .ds (),
1260 .qs (status_alert_recov_ctrl_update_err_qs)
1261 );
1262
1263
1264 // R[entropy_period]: V(False)
1265 // Create REGWEN-gated WE signal
1266 logic entropy_period_gated_we;
1267 1/1 assign entropy_period_gated_we = entropy_period_we & cfg_regwen_qs;
Tests: T1 T2 T3
1268 // F[prescaler]: 9:0
1269 prim_subreg #(
1270 .DW (10),
1271 .SwAccess(prim_subreg_pkg::SwAccessRW),
1272 .RESVAL (10'h0),
1273 .Mubi (1'b0)
1274 ) u_entropy_period_prescaler (
1275 .clk_i (clk_i),
1276 .rst_ni (rst_ni),
1277
1278 // from register interface
1279 .we (entropy_period_gated_we),
1280 .wd (entropy_period_prescaler_wd),
1281
1282 // from internal hardware
1283 .de (1'b0),
1284 .d ('0),
1285
1286 // to internal hardware
1287 .qe (),
1288 .q (reg2hw.entropy_period.prescaler.q),
1289 .ds (),
1290
1291 // to register interface (read)
1292 .qs (entropy_period_prescaler_qs)
1293 );
1294
1295 // F[wait_timer]: 31:16
1296 prim_subreg #(
1297 .DW (16),
1298 .SwAccess(prim_subreg_pkg::SwAccessRW),
1299 .RESVAL (16'h0),
1300 .Mubi (1'b0)
1301 ) u_entropy_period_wait_timer (
1302 .clk_i (clk_i),
1303 .rst_ni (rst_ni),
1304
1305 // from register interface
1306 .we (entropy_period_gated_we),
1307 .wd (entropy_period_wait_timer_wd),
1308
1309 // from internal hardware
1310 .de (1'b0),
1311 .d ('0),
1312
1313 // to internal hardware
1314 .qe (),
1315 .q (reg2hw.entropy_period.wait_timer.q),
1316 .ds (),
1317
1318 // to register interface (read)
1319 .qs (entropy_period_wait_timer_qs)
1320 );
1321
1322
1323 // R[entropy_refresh_hash_cnt]: V(False)
1324 prim_subreg #(
1325 .DW (10),
1326 .SwAccess(prim_subreg_pkg::SwAccessRO),
1327 .RESVAL (10'h0),
1328 .Mubi (1'b0)
1329 ) u_entropy_refresh_hash_cnt (
1330 .clk_i (clk_i),
1331 .rst_ni (rst_ni),
1332
1333 // from register interface
1334 .we (1'b0),
1335 .wd ('0),
1336
1337 // from internal hardware
1338 .de (hw2reg.entropy_refresh_hash_cnt.de),
1339 .d (hw2reg.entropy_refresh_hash_cnt.d),
1340
1341 // to internal hardware
1342 .qe (),
1343 .q (),
1344 .ds (),
1345
1346 // to register interface (read)
1347 .qs (entropy_refresh_hash_cnt_qs)
1348 );
1349
1350
1351 // R[entropy_refresh_threshold_shadowed]: V(False)
1352 // Create REGWEN-gated WE signal
1353 logic entropy_refresh_threshold_shadowed_gated_we;
1354 1/1 assign entropy_refresh_threshold_shadowed_gated_we =
Tests: T1 T2 T3
1355 entropy_refresh_threshold_shadowed_we & cfg_regwen_qs;
1356 prim_subreg_shadow #(
1357 .DW (10),
1358 .SwAccess(prim_subreg_pkg::SwAccessRW),
1359 .RESVAL (10'h0),
1360 .Mubi (1'b0)
1361 ) u_entropy_refresh_threshold_shadowed (
1362 .clk_i (clk_i),
1363 .rst_ni (rst_ni),
1364 .rst_shadowed_ni (rst_shadowed_ni),
1365
1366 // from register interface
1367 .re (entropy_refresh_threshold_shadowed_re),
1368 .we (entropy_refresh_threshold_shadowed_gated_we),
1369 .wd (entropy_refresh_threshold_shadowed_wd),
1370
1371 // from internal hardware
1372 .de (1'b0),
1373 .d ('0),
1374
1375 // to internal hardware
1376 .qe (),
1377 .q (reg2hw.entropy_refresh_threshold_shadowed.q),
1378 .ds (),
1379
1380 // to register interface (read)
1381 .qs (entropy_refresh_threshold_shadowed_qs),
1382
1383 // Shadow register phase. Relevant for hwext only.
1384 .phase (),
1385
1386 // Shadow register error conditions
1387 .err_update (entropy_refresh_threshold_shadowed_update_err),
1388 .err_storage (entropy_refresh_threshold_shadowed_storage_err)
1389 );
1390
1391
1392 // R[entropy_seed]: V(True)
1393 logic entropy_seed_qe;
1394 logic [0:0] entropy_seed_flds_we;
1395 1/1 assign entropy_seed_qe = &entropy_seed_flds_we;
Tests: T3 T6 T7
1396 prim_subreg_ext #(
1397 .DW (32)
1398 ) u_entropy_seed (
1399 .re (1'b0),
1400 .we (entropy_seed_we),
1401 .wd (entropy_seed_wd),
1402 .d ('0),
1403 .qre (),
1404 .qe (entropy_seed_flds_we[0]),
1405 .q (reg2hw.entropy_seed.q),
1406 .ds (),
1407 .qs ()
1408 );
1409 1/1 assign reg2hw.entropy_seed.qe = entropy_seed_qe;
Tests: T3 T6 T7
1410
1411
1412 // Subregister 0 of Multireg key_share0
1413 // R[key_share0_0]: V(True)
1414 logic key_share0_0_qe;
1415 logic [0:0] key_share0_0_flds_we;
1416 1/1 assign key_share0_0_qe = &key_share0_0_flds_we;
Tests: T1 T4 T13
1417 // Create REGWEN-gated WE signal
1418 logic key_share0_0_gated_we;
1419 1/1 assign key_share0_0_gated_we = key_share0_0_we & cfg_regwen_qs;
Tests: T1 T2 T3
1420 prim_subreg_ext #(
1421 .DW (32)
1422 ) u_key_share0_0 (
1423 .re (1'b0),
1424 .we (key_share0_0_gated_we),
1425 .wd (key_share0_0_wd),
1426 .d ('0),
1427 .qre (),
1428 .qe (key_share0_0_flds_we[0]),
1429 .q (reg2hw.key_share0[0].q),
1430 .ds (),
1431 .qs ()
1432 );
1433 1/1 assign reg2hw.key_share0[0].qe = key_share0_0_qe;
Tests: T1 T4 T13
1434
1435
1436 // Subregister 1 of Multireg key_share0
1437 // R[key_share0_1]: V(True)
1438 logic key_share0_1_qe;
1439 logic [0:0] key_share0_1_flds_we;
1440 1/1 assign key_share0_1_qe = &key_share0_1_flds_we;
Tests: T1 T4 T13
1441 // Create REGWEN-gated WE signal
1442 logic key_share0_1_gated_we;
1443 1/1 assign key_share0_1_gated_we = key_share0_1_we & cfg_regwen_qs;
Tests: T1 T2 T3
1444 prim_subreg_ext #(
1445 .DW (32)
1446 ) u_key_share0_1 (
1447 .re (1'b0),
1448 .we (key_share0_1_gated_we),
1449 .wd (key_share0_1_wd),
1450 .d ('0),
1451 .qre (),
1452 .qe (key_share0_1_flds_we[0]),
1453 .q (reg2hw.key_share0[1].q),
1454 .ds (),
1455 .qs ()
1456 );
1457 1/1 assign reg2hw.key_share0[1].qe = key_share0_1_qe;
Tests: T1 T4 T13
1458
1459
1460 // Subregister 2 of Multireg key_share0
1461 // R[key_share0_2]: V(True)
1462 logic key_share0_2_qe;
1463 logic [0:0] key_share0_2_flds_we;
1464 1/1 assign key_share0_2_qe = &key_share0_2_flds_we;
Tests: T1 T4 T13
1465 // Create REGWEN-gated WE signal
1466 logic key_share0_2_gated_we;
1467 1/1 assign key_share0_2_gated_we = key_share0_2_we & cfg_regwen_qs;
Tests: T1 T2 T3
1468 prim_subreg_ext #(
1469 .DW (32)
1470 ) u_key_share0_2 (
1471 .re (1'b0),
1472 .we (key_share0_2_gated_we),
1473 .wd (key_share0_2_wd),
1474 .d ('0),
1475 .qre (),
1476 .qe (key_share0_2_flds_we[0]),
1477 .q (reg2hw.key_share0[2].q),
1478 .ds (),
1479 .qs ()
1480 );
1481 1/1 assign reg2hw.key_share0[2].qe = key_share0_2_qe;
Tests: T1 T4 T13
1482
1483
1484 // Subregister 3 of Multireg key_share0
1485 // R[key_share0_3]: V(True)
1486 logic key_share0_3_qe;
1487 logic [0:0] key_share0_3_flds_we;
1488 1/1 assign key_share0_3_qe = &key_share0_3_flds_we;
Tests: T1 T4 T13
1489 // Create REGWEN-gated WE signal
1490 logic key_share0_3_gated_we;
1491 1/1 assign key_share0_3_gated_we = key_share0_3_we & cfg_regwen_qs;
Tests: T1 T2 T3
1492 prim_subreg_ext #(
1493 .DW (32)
1494 ) u_key_share0_3 (
1495 .re (1'b0),
1496 .we (key_share0_3_gated_we),
1497 .wd (key_share0_3_wd),
1498 .d ('0),
1499 .qre (),
1500 .qe (key_share0_3_flds_we[0]),
1501 .q (reg2hw.key_share0[3].q),
1502 .ds (),
1503 .qs ()
1504 );
1505 1/1 assign reg2hw.key_share0[3].qe = key_share0_3_qe;
Tests: T1 T4 T13
1506
1507
1508 // Subregister 4 of Multireg key_share0
1509 // R[key_share0_4]: V(True)
1510 logic key_share0_4_qe;
1511 logic [0:0] key_share0_4_flds_we;
1512 1/1 assign key_share0_4_qe = &key_share0_4_flds_we;
Tests: T1 T4 T13
1513 // Create REGWEN-gated WE signal
1514 logic key_share0_4_gated_we;
1515 1/1 assign key_share0_4_gated_we = key_share0_4_we & cfg_regwen_qs;
Tests: T1 T2 T3
1516 prim_subreg_ext #(
1517 .DW (32)
1518 ) u_key_share0_4 (
1519 .re (1'b0),
1520 .we (key_share0_4_gated_we),
1521 .wd (key_share0_4_wd),
1522 .d ('0),
1523 .qre (),
1524 .qe (key_share0_4_flds_we[0]),
1525 .q (reg2hw.key_share0[4].q),
1526 .ds (),
1527 .qs ()
1528 );
1529 1/1 assign reg2hw.key_share0[4].qe = key_share0_4_qe;
Tests: T1 T4 T13
1530
1531
1532 // Subregister 5 of Multireg key_share0
1533 // R[key_share0_5]: V(True)
1534 logic key_share0_5_qe;
1535 logic [0:0] key_share0_5_flds_we;
1536 1/1 assign key_share0_5_qe = &key_share0_5_flds_we;
Tests: T1 T4 T13
1537 // Create REGWEN-gated WE signal
1538 logic key_share0_5_gated_we;
1539 1/1 assign key_share0_5_gated_we = key_share0_5_we & cfg_regwen_qs;
Tests: T1 T2 T3
1540 prim_subreg_ext #(
1541 .DW (32)
1542 ) u_key_share0_5 (
1543 .re (1'b0),
1544 .we (key_share0_5_gated_we),
1545 .wd (key_share0_5_wd),
1546 .d ('0),
1547 .qre (),
1548 .qe (key_share0_5_flds_we[0]),
1549 .q (reg2hw.key_share0[5].q),
1550 .ds (),
1551 .qs ()
1552 );
1553 1/1 assign reg2hw.key_share0[5].qe = key_share0_5_qe;
Tests: T1 T4 T13
1554
1555
1556 // Subregister 6 of Multireg key_share0
1557 // R[key_share0_6]: V(True)
1558 logic key_share0_6_qe;
1559 logic [0:0] key_share0_6_flds_we;
1560 1/1 assign key_share0_6_qe = &key_share0_6_flds_we;
Tests: T1 T4 T13
1561 // Create REGWEN-gated WE signal
1562 logic key_share0_6_gated_we;
1563 1/1 assign key_share0_6_gated_we = key_share0_6_we & cfg_regwen_qs;
Tests: T1 T2 T3
1564 prim_subreg_ext #(
1565 .DW (32)
1566 ) u_key_share0_6 (
1567 .re (1'b0),
1568 .we (key_share0_6_gated_we),
1569 .wd (key_share0_6_wd),
1570 .d ('0),
1571 .qre (),
1572 .qe (key_share0_6_flds_we[0]),
1573 .q (reg2hw.key_share0[6].q),
1574 .ds (),
1575 .qs ()
1576 );
1577 1/1 assign reg2hw.key_share0[6].qe = key_share0_6_qe;
Tests: T1 T4 T13
1578
1579
1580 // Subregister 7 of Multireg key_share0
1581 // R[key_share0_7]: V(True)
1582 logic key_share0_7_qe;
1583 logic [0:0] key_share0_7_flds_we;
1584 1/1 assign key_share0_7_qe = &key_share0_7_flds_we;
Tests: T1 T4 T13
1585 // Create REGWEN-gated WE signal
1586 logic key_share0_7_gated_we;
1587 1/1 assign key_share0_7_gated_we = key_share0_7_we & cfg_regwen_qs;
Tests: T1 T2 T3
1588 prim_subreg_ext #(
1589 .DW (32)
1590 ) u_key_share0_7 (
1591 .re (1'b0),
1592 .we (key_share0_7_gated_we),
1593 .wd (key_share0_7_wd),
1594 .d ('0),
1595 .qre (),
1596 .qe (key_share0_7_flds_we[0]),
1597 .q (reg2hw.key_share0[7].q),
1598 .ds (),
1599 .qs ()
1600 );
1601 1/1 assign reg2hw.key_share0[7].qe = key_share0_7_qe;
Tests: T1 T4 T13
1602
1603
1604 // Subregister 8 of Multireg key_share0
1605 // R[key_share0_8]: V(True)
1606 logic key_share0_8_qe;
1607 logic [0:0] key_share0_8_flds_we;
1608 1/1 assign key_share0_8_qe = &key_share0_8_flds_we;
Tests: T1 T4 T13
1609 // Create REGWEN-gated WE signal
1610 logic key_share0_8_gated_we;
1611 1/1 assign key_share0_8_gated_we = key_share0_8_we & cfg_regwen_qs;
Tests: T1 T2 T3
1612 prim_subreg_ext #(
1613 .DW (32)
1614 ) u_key_share0_8 (
1615 .re (1'b0),
1616 .we (key_share0_8_gated_we),
1617 .wd (key_share0_8_wd),
1618 .d ('0),
1619 .qre (),
1620 .qe (key_share0_8_flds_we[0]),
1621 .q (reg2hw.key_share0[8].q),
1622 .ds (),
1623 .qs ()
1624 );
1625 1/1 assign reg2hw.key_share0[8].qe = key_share0_8_qe;
Tests: T1 T4 T13
1626
1627
1628 // Subregister 9 of Multireg key_share0
1629 // R[key_share0_9]: V(True)
1630 logic key_share0_9_qe;
1631 logic [0:0] key_share0_9_flds_we;
1632 1/1 assign key_share0_9_qe = &key_share0_9_flds_we;
Tests: T1 T4 T13
1633 // Create REGWEN-gated WE signal
1634 logic key_share0_9_gated_we;
1635 1/1 assign key_share0_9_gated_we = key_share0_9_we & cfg_regwen_qs;
Tests: T1 T2 T3
1636 prim_subreg_ext #(
1637 .DW (32)
1638 ) u_key_share0_9 (
1639 .re (1'b0),
1640 .we (key_share0_9_gated_we),
1641 .wd (key_share0_9_wd),
1642 .d ('0),
1643 .qre (),
1644 .qe (key_share0_9_flds_we[0]),
1645 .q (reg2hw.key_share0[9].q),
1646 .ds (),
1647 .qs ()
1648 );
1649 1/1 assign reg2hw.key_share0[9].qe = key_share0_9_qe;
Tests: T1 T4 T13
1650
1651
1652 // Subregister 10 of Multireg key_share0
1653 // R[key_share0_10]: V(True)
1654 logic key_share0_10_qe;
1655 logic [0:0] key_share0_10_flds_we;
1656 1/1 assign key_share0_10_qe = &key_share0_10_flds_we;
Tests: T1 T4 T13
1657 // Create REGWEN-gated WE signal
1658 logic key_share0_10_gated_we;
1659 1/1 assign key_share0_10_gated_we = key_share0_10_we & cfg_regwen_qs;
Tests: T1 T2 T3
1660 prim_subreg_ext #(
1661 .DW (32)
1662 ) u_key_share0_10 (
1663 .re (1'b0),
1664 .we (key_share0_10_gated_we),
1665 .wd (key_share0_10_wd),
1666 .d ('0),
1667 .qre (),
1668 .qe (key_share0_10_flds_we[0]),
1669 .q (reg2hw.key_share0[10].q),
1670 .ds (),
1671 .qs ()
1672 );
1673 1/1 assign reg2hw.key_share0[10].qe = key_share0_10_qe;
Tests: T1 T4 T13
1674
1675
1676 // Subregister 11 of Multireg key_share0
1677 // R[key_share0_11]: V(True)
1678 logic key_share0_11_qe;
1679 logic [0:0] key_share0_11_flds_we;
1680 1/1 assign key_share0_11_qe = &key_share0_11_flds_we;
Tests: T1 T4 T13
1681 // Create REGWEN-gated WE signal
1682 logic key_share0_11_gated_we;
1683 1/1 assign key_share0_11_gated_we = key_share0_11_we & cfg_regwen_qs;
Tests: T1 T2 T3
1684 prim_subreg_ext #(
1685 .DW (32)
1686 ) u_key_share0_11 (
1687 .re (1'b0),
1688 .we (key_share0_11_gated_we),
1689 .wd (key_share0_11_wd),
1690 .d ('0),
1691 .qre (),
1692 .qe (key_share0_11_flds_we[0]),
1693 .q (reg2hw.key_share0[11].q),
1694 .ds (),
1695 .qs ()
1696 );
1697 1/1 assign reg2hw.key_share0[11].qe = key_share0_11_qe;
Tests: T1 T4 T13
1698
1699
1700 // Subregister 12 of Multireg key_share0
1701 // R[key_share0_12]: V(True)
1702 logic key_share0_12_qe;
1703 logic [0:0] key_share0_12_flds_we;
1704 1/1 assign key_share0_12_qe = &key_share0_12_flds_we;
Tests: T1 T4 T13
1705 // Create REGWEN-gated WE signal
1706 logic key_share0_12_gated_we;
1707 1/1 assign key_share0_12_gated_we = key_share0_12_we & cfg_regwen_qs;
Tests: T1 T2 T3
1708 prim_subreg_ext #(
1709 .DW (32)
1710 ) u_key_share0_12 (
1711 .re (1'b0),
1712 .we (key_share0_12_gated_we),
1713 .wd (key_share0_12_wd),
1714 .d ('0),
1715 .qre (),
1716 .qe (key_share0_12_flds_we[0]),
1717 .q (reg2hw.key_share0[12].q),
1718 .ds (),
1719 .qs ()
1720 );
1721 1/1 assign reg2hw.key_share0[12].qe = key_share0_12_qe;
Tests: T1 T4 T13
1722
1723
1724 // Subregister 13 of Multireg key_share0
1725 // R[key_share0_13]: V(True)
1726 logic key_share0_13_qe;
1727 logic [0:0] key_share0_13_flds_we;
1728 1/1 assign key_share0_13_qe = &key_share0_13_flds_we;
Tests: T1 T4 T13
1729 // Create REGWEN-gated WE signal
1730 logic key_share0_13_gated_we;
1731 1/1 assign key_share0_13_gated_we = key_share0_13_we & cfg_regwen_qs;
Tests: T1 T2 T3
1732 prim_subreg_ext #(
1733 .DW (32)
1734 ) u_key_share0_13 (
1735 .re (1'b0),
1736 .we (key_share0_13_gated_we),
1737 .wd (key_share0_13_wd),
1738 .d ('0),
1739 .qre (),
1740 .qe (key_share0_13_flds_we[0]),
1741 .q (reg2hw.key_share0[13].q),
1742 .ds (),
1743 .qs ()
1744 );
1745 1/1 assign reg2hw.key_share0[13].qe = key_share0_13_qe;
Tests: T1 T4 T13
1746
1747
1748 // Subregister 14 of Multireg key_share0
1749 // R[key_share0_14]: V(True)
1750 logic key_share0_14_qe;
1751 logic [0:0] key_share0_14_flds_we;
1752 1/1 assign key_share0_14_qe = &key_share0_14_flds_we;
Tests: T1 T4 T13
1753 // Create REGWEN-gated WE signal
1754 logic key_share0_14_gated_we;
1755 1/1 assign key_share0_14_gated_we = key_share0_14_we & cfg_regwen_qs;
Tests: T1 T2 T3
1756 prim_subreg_ext #(
1757 .DW (32)
1758 ) u_key_share0_14 (
1759 .re (1'b0),
1760 .we (key_share0_14_gated_we),
1761 .wd (key_share0_14_wd),
1762 .d ('0),
1763 .qre (),
1764 .qe (key_share0_14_flds_we[0]),
1765 .q (reg2hw.key_share0[14].q),
1766 .ds (),
1767 .qs ()
1768 );
1769 1/1 assign reg2hw.key_share0[14].qe = key_share0_14_qe;
Tests: T1 T4 T13
1770
1771
1772 // Subregister 15 of Multireg key_share0
1773 // R[key_share0_15]: V(True)
1774 logic key_share0_15_qe;
1775 logic [0:0] key_share0_15_flds_we;
1776 1/1 assign key_share0_15_qe = &key_share0_15_flds_we;
Tests: T1 T4 T13
1777 // Create REGWEN-gated WE signal
1778 logic key_share0_15_gated_we;
1779 1/1 assign key_share0_15_gated_we = key_share0_15_we & cfg_regwen_qs;
Tests: T1 T2 T3
1780 prim_subreg_ext #(
1781 .DW (32)
1782 ) u_key_share0_15 (
1783 .re (1'b0),
1784 .we (key_share0_15_gated_we),
1785 .wd (key_share0_15_wd),
1786 .d ('0),
1787 .qre (),
1788 .qe (key_share0_15_flds_we[0]),
1789 .q (reg2hw.key_share0[15].q),
1790 .ds (),
1791 .qs ()
1792 );
1793 1/1 assign reg2hw.key_share0[15].qe = key_share0_15_qe;
Tests: T1 T4 T13
1794
1795
1796 // Subregister 0 of Multireg key_share1
1797 // R[key_share1_0]: V(True)
1798 logic key_share1_0_qe;
1799 logic [0:0] key_share1_0_flds_we;
1800 1/1 assign key_share1_0_qe = &key_share1_0_flds_we;
Tests: T1 T4 T13
1801 // Create REGWEN-gated WE signal
1802 logic key_share1_0_gated_we;
1803 1/1 assign key_share1_0_gated_we = key_share1_0_we & cfg_regwen_qs;
Tests: T1 T2 T3
1804 prim_subreg_ext #(
1805 .DW (32)
1806 ) u_key_share1_0 (
1807 .re (1'b0),
1808 .we (key_share1_0_gated_we),
1809 .wd (key_share1_0_wd),
1810 .d ('0),
1811 .qre (),
1812 .qe (key_share1_0_flds_we[0]),
1813 .q (reg2hw.key_share1[0].q),
1814 .ds (),
1815 .qs ()
1816 );
1817 1/1 assign reg2hw.key_share1[0].qe = key_share1_0_qe;
Tests: T1 T4 T13
1818
1819
1820 // Subregister 1 of Multireg key_share1
1821 // R[key_share1_1]: V(True)
1822 logic key_share1_1_qe;
1823 logic [0:0] key_share1_1_flds_we;
1824 1/1 assign key_share1_1_qe = &key_share1_1_flds_we;
Tests: T1 T4 T13
1825 // Create REGWEN-gated WE signal
1826 logic key_share1_1_gated_we;
1827 1/1 assign key_share1_1_gated_we = key_share1_1_we & cfg_regwen_qs;
Tests: T1 T2 T3
1828 prim_subreg_ext #(
1829 .DW (32)
1830 ) u_key_share1_1 (
1831 .re (1'b0),
1832 .we (key_share1_1_gated_we),
1833 .wd (key_share1_1_wd),
1834 .d ('0),
1835 .qre (),
1836 .qe (key_share1_1_flds_we[0]),
1837 .q (reg2hw.key_share1[1].q),
1838 .ds (),
1839 .qs ()
1840 );
1841 1/1 assign reg2hw.key_share1[1].qe = key_share1_1_qe;
Tests: T1 T4 T13
1842
1843
1844 // Subregister 2 of Multireg key_share1
1845 // R[key_share1_2]: V(True)
1846 logic key_share1_2_qe;
1847 logic [0:0] key_share1_2_flds_we;
1848 1/1 assign key_share1_2_qe = &key_share1_2_flds_we;
Tests: T1 T4 T13
1849 // Create REGWEN-gated WE signal
1850 logic key_share1_2_gated_we;
1851 1/1 assign key_share1_2_gated_we = key_share1_2_we & cfg_regwen_qs;
Tests: T1 T2 T3
1852 prim_subreg_ext #(
1853 .DW (32)
1854 ) u_key_share1_2 (
1855 .re (1'b0),
1856 .we (key_share1_2_gated_we),
1857 .wd (key_share1_2_wd),
1858 .d ('0),
1859 .qre (),
1860 .qe (key_share1_2_flds_we[0]),
1861 .q (reg2hw.key_share1[2].q),
1862 .ds (),
1863 .qs ()
1864 );
1865 1/1 assign reg2hw.key_share1[2].qe = key_share1_2_qe;
Tests: T1 T4 T13
1866
1867
1868 // Subregister 3 of Multireg key_share1
1869 // R[key_share1_3]: V(True)
1870 logic key_share1_3_qe;
1871 logic [0:0] key_share1_3_flds_we;
1872 1/1 assign key_share1_3_qe = &key_share1_3_flds_we;
Tests: T1 T4 T13
1873 // Create REGWEN-gated WE signal
1874 logic key_share1_3_gated_we;
1875 1/1 assign key_share1_3_gated_we = key_share1_3_we & cfg_regwen_qs;
Tests: T1 T2 T3
1876 prim_subreg_ext #(
1877 .DW (32)
1878 ) u_key_share1_3 (
1879 .re (1'b0),
1880 .we (key_share1_3_gated_we),
1881 .wd (key_share1_3_wd),
1882 .d ('0),
1883 .qre (),
1884 .qe (key_share1_3_flds_we[0]),
1885 .q (reg2hw.key_share1[3].q),
1886 .ds (),
1887 .qs ()
1888 );
1889 1/1 assign reg2hw.key_share1[3].qe = key_share1_3_qe;
Tests: T1 T4 T13
1890
1891
1892 // Subregister 4 of Multireg key_share1
1893 // R[key_share1_4]: V(True)
1894 logic key_share1_4_qe;
1895 logic [0:0] key_share1_4_flds_we;
1896 1/1 assign key_share1_4_qe = &key_share1_4_flds_we;
Tests: T1 T4 T13
1897 // Create REGWEN-gated WE signal
1898 logic key_share1_4_gated_we;
1899 1/1 assign key_share1_4_gated_we = key_share1_4_we & cfg_regwen_qs;
Tests: T1 T2 T3
1900 prim_subreg_ext #(
1901 .DW (32)
1902 ) u_key_share1_4 (
1903 .re (1'b0),
1904 .we (key_share1_4_gated_we),
1905 .wd (key_share1_4_wd),
1906 .d ('0),
1907 .qre (),
1908 .qe (key_share1_4_flds_we[0]),
1909 .q (reg2hw.key_share1[4].q),
1910 .ds (),
1911 .qs ()
1912 );
1913 1/1 assign reg2hw.key_share1[4].qe = key_share1_4_qe;
Tests: T1 T4 T13
1914
1915
1916 // Subregister 5 of Multireg key_share1
1917 // R[key_share1_5]: V(True)
1918 logic key_share1_5_qe;
1919 logic [0:0] key_share1_5_flds_we;
1920 1/1 assign key_share1_5_qe = &key_share1_5_flds_we;
Tests: T1 T4 T13
1921 // Create REGWEN-gated WE signal
1922 logic key_share1_5_gated_we;
1923 1/1 assign key_share1_5_gated_we = key_share1_5_we & cfg_regwen_qs;
Tests: T1 T2 T3
1924 prim_subreg_ext #(
1925 .DW (32)
1926 ) u_key_share1_5 (
1927 .re (1'b0),
1928 .we (key_share1_5_gated_we),
1929 .wd (key_share1_5_wd),
1930 .d ('0),
1931 .qre (),
1932 .qe (key_share1_5_flds_we[0]),
1933 .q (reg2hw.key_share1[5].q),
1934 .ds (),
1935 .qs ()
1936 );
1937 1/1 assign reg2hw.key_share1[5].qe = key_share1_5_qe;
Tests: T1 T4 T13
1938
1939
1940 // Subregister 6 of Multireg key_share1
1941 // R[key_share1_6]: V(True)
1942 logic key_share1_6_qe;
1943 logic [0:0] key_share1_6_flds_we;
1944 1/1 assign key_share1_6_qe = &key_share1_6_flds_we;
Tests: T1 T4 T13
1945 // Create REGWEN-gated WE signal
1946 logic key_share1_6_gated_we;
1947 1/1 assign key_share1_6_gated_we = key_share1_6_we & cfg_regwen_qs;
Tests: T1 T2 T3
1948 prim_subreg_ext #(
1949 .DW (32)
1950 ) u_key_share1_6 (
1951 .re (1'b0),
1952 .we (key_share1_6_gated_we),
1953 .wd (key_share1_6_wd),
1954 .d ('0),
1955 .qre (),
1956 .qe (key_share1_6_flds_we[0]),
1957 .q (reg2hw.key_share1[6].q),
1958 .ds (),
1959 .qs ()
1960 );
1961 1/1 assign reg2hw.key_share1[6].qe = key_share1_6_qe;
Tests: T1 T4 T13
1962
1963
1964 // Subregister 7 of Multireg key_share1
1965 // R[key_share1_7]: V(True)
1966 logic key_share1_7_qe;
1967 logic [0:0] key_share1_7_flds_we;
1968 1/1 assign key_share1_7_qe = &key_share1_7_flds_we;
Tests: T1 T4 T13
1969 // Create REGWEN-gated WE signal
1970 logic key_share1_7_gated_we;
1971 1/1 assign key_share1_7_gated_we = key_share1_7_we & cfg_regwen_qs;
Tests: T1 T2 T3
1972 prim_subreg_ext #(
1973 .DW (32)
1974 ) u_key_share1_7 (
1975 .re (1'b0),
1976 .we (key_share1_7_gated_we),
1977 .wd (key_share1_7_wd),
1978 .d ('0),
1979 .qre (),
1980 .qe (key_share1_7_flds_we[0]),
1981 .q (reg2hw.key_share1[7].q),
1982 .ds (),
1983 .qs ()
1984 );
1985 1/1 assign reg2hw.key_share1[7].qe = key_share1_7_qe;
Tests: T1 T4 T13
1986
1987
1988 // Subregister 8 of Multireg key_share1
1989 // R[key_share1_8]: V(True)
1990 logic key_share1_8_qe;
1991 logic [0:0] key_share1_8_flds_we;
1992 1/1 assign key_share1_8_qe = &key_share1_8_flds_we;
Tests: T1 T4 T13
1993 // Create REGWEN-gated WE signal
1994 logic key_share1_8_gated_we;
1995 1/1 assign key_share1_8_gated_we = key_share1_8_we & cfg_regwen_qs;
Tests: T1 T2 T3
1996 prim_subreg_ext #(
1997 .DW (32)
1998 ) u_key_share1_8 (
1999 .re (1'b0),
2000 .we (key_share1_8_gated_we),
2001 .wd (key_share1_8_wd),
2002 .d ('0),
2003 .qre (),
2004 .qe (key_share1_8_flds_we[0]),
2005 .q (reg2hw.key_share1[8].q),
2006 .ds (),
2007 .qs ()
2008 );
2009 1/1 assign reg2hw.key_share1[8].qe = key_share1_8_qe;
Tests: T1 T4 T13
2010
2011
2012 // Subregister 9 of Multireg key_share1
2013 // R[key_share1_9]: V(True)
2014 logic key_share1_9_qe;
2015 logic [0:0] key_share1_9_flds_we;
2016 1/1 assign key_share1_9_qe = &key_share1_9_flds_we;
Tests: T1 T4 T13
2017 // Create REGWEN-gated WE signal
2018 logic key_share1_9_gated_we;
2019 1/1 assign key_share1_9_gated_we = key_share1_9_we & cfg_regwen_qs;
Tests: T1 T2 T3
2020 prim_subreg_ext #(
2021 .DW (32)
2022 ) u_key_share1_9 (
2023 .re (1'b0),
2024 .we (key_share1_9_gated_we),
2025 .wd (key_share1_9_wd),
2026 .d ('0),
2027 .qre (),
2028 .qe (key_share1_9_flds_we[0]),
2029 .q (reg2hw.key_share1[9].q),
2030 .ds (),
2031 .qs ()
2032 );
2033 1/1 assign reg2hw.key_share1[9].qe = key_share1_9_qe;
Tests: T1 T4 T13
2034
2035
2036 // Subregister 10 of Multireg key_share1
2037 // R[key_share1_10]: V(True)
2038 logic key_share1_10_qe;
2039 logic [0:0] key_share1_10_flds_we;
2040 1/1 assign key_share1_10_qe = &key_share1_10_flds_we;
Tests: T1 T4 T13
2041 // Create REGWEN-gated WE signal
2042 logic key_share1_10_gated_we;
2043 1/1 assign key_share1_10_gated_we = key_share1_10_we & cfg_regwen_qs;
Tests: T1 T2 T3
2044 prim_subreg_ext #(
2045 .DW (32)
2046 ) u_key_share1_10 (
2047 .re (1'b0),
2048 .we (key_share1_10_gated_we),
2049 .wd (key_share1_10_wd),
2050 .d ('0),
2051 .qre (),
2052 .qe (key_share1_10_flds_we[0]),
2053 .q (reg2hw.key_share1[10].q),
2054 .ds (),
2055 .qs ()
2056 );
2057 1/1 assign reg2hw.key_share1[10].qe = key_share1_10_qe;
Tests: T1 T4 T13
2058
2059
2060 // Subregister 11 of Multireg key_share1
2061 // R[key_share1_11]: V(True)
2062 logic key_share1_11_qe;
2063 logic [0:0] key_share1_11_flds_we;
2064 1/1 assign key_share1_11_qe = &key_share1_11_flds_we;
Tests: T1 T4 T13
2065 // Create REGWEN-gated WE signal
2066 logic key_share1_11_gated_we;
2067 1/1 assign key_share1_11_gated_we = key_share1_11_we & cfg_regwen_qs;
Tests: T1 T2 T3
2068 prim_subreg_ext #(
2069 .DW (32)
2070 ) u_key_share1_11 (
2071 .re (1'b0),
2072 .we (key_share1_11_gated_we),
2073 .wd (key_share1_11_wd),
2074 .d ('0),
2075 .qre (),
2076 .qe (key_share1_11_flds_we[0]),
2077 .q (reg2hw.key_share1[11].q),
2078 .ds (),
2079 .qs ()
2080 );
2081 1/1 assign reg2hw.key_share1[11].qe = key_share1_11_qe;
Tests: T1 T4 T13
2082
2083
2084 // Subregister 12 of Multireg key_share1
2085 // R[key_share1_12]: V(True)
2086 logic key_share1_12_qe;
2087 logic [0:0] key_share1_12_flds_we;
2088 1/1 assign key_share1_12_qe = &key_share1_12_flds_we;
Tests: T1 T4 T13
2089 // Create REGWEN-gated WE signal
2090 logic key_share1_12_gated_we;
2091 1/1 assign key_share1_12_gated_we = key_share1_12_we & cfg_regwen_qs;
Tests: T1 T2 T3
2092 prim_subreg_ext #(
2093 .DW (32)
2094 ) u_key_share1_12 (
2095 .re (1'b0),
2096 .we (key_share1_12_gated_we),
2097 .wd (key_share1_12_wd),
2098 .d ('0),
2099 .qre (),
2100 .qe (key_share1_12_flds_we[0]),
2101 .q (reg2hw.key_share1[12].q),
2102 .ds (),
2103 .qs ()
2104 );
2105 1/1 assign reg2hw.key_share1[12].qe = key_share1_12_qe;
Tests: T1 T4 T13
2106
2107
2108 // Subregister 13 of Multireg key_share1
2109 // R[key_share1_13]: V(True)
2110 logic key_share1_13_qe;
2111 logic [0:0] key_share1_13_flds_we;
2112 1/1 assign key_share1_13_qe = &key_share1_13_flds_we;
Tests: T1 T4 T13
2113 // Create REGWEN-gated WE signal
2114 logic key_share1_13_gated_we;
2115 1/1 assign key_share1_13_gated_we = key_share1_13_we & cfg_regwen_qs;
Tests: T1 T2 T3
2116 prim_subreg_ext #(
2117 .DW (32)
2118 ) u_key_share1_13 (
2119 .re (1'b0),
2120 .we (key_share1_13_gated_we),
2121 .wd (key_share1_13_wd),
2122 .d ('0),
2123 .qre (),
2124 .qe (key_share1_13_flds_we[0]),
2125 .q (reg2hw.key_share1[13].q),
2126 .ds (),
2127 .qs ()
2128 );
2129 1/1 assign reg2hw.key_share1[13].qe = key_share1_13_qe;
Tests: T1 T4 T13
2130
2131
2132 // Subregister 14 of Multireg key_share1
2133 // R[key_share1_14]: V(True)
2134 logic key_share1_14_qe;
2135 logic [0:0] key_share1_14_flds_we;
2136 1/1 assign key_share1_14_qe = &key_share1_14_flds_we;
Tests: T1 T4 T13
2137 // Create REGWEN-gated WE signal
2138 logic key_share1_14_gated_we;
2139 1/1 assign key_share1_14_gated_we = key_share1_14_we & cfg_regwen_qs;
Tests: T1 T2 T3
2140 prim_subreg_ext #(
2141 .DW (32)
2142 ) u_key_share1_14 (
2143 .re (1'b0),
2144 .we (key_share1_14_gated_we),
2145 .wd (key_share1_14_wd),
2146 .d ('0),
2147 .qre (),
2148 .qe (key_share1_14_flds_we[0]),
2149 .q (reg2hw.key_share1[14].q),
2150 .ds (),
2151 .qs ()
2152 );
2153 1/1 assign reg2hw.key_share1[14].qe = key_share1_14_qe;
Tests: T1 T4 T13
2154
2155
2156 // Subregister 15 of Multireg key_share1
2157 // R[key_share1_15]: V(True)
2158 logic key_share1_15_qe;
2159 logic [0:0] key_share1_15_flds_we;
2160 1/1 assign key_share1_15_qe = &key_share1_15_flds_we;
Tests: T1 T4 T13
2161 // Create REGWEN-gated WE signal
2162 logic key_share1_15_gated_we;
2163 1/1 assign key_share1_15_gated_we = key_share1_15_we & cfg_regwen_qs;
Tests: T1 T2 T3
2164 prim_subreg_ext #(
2165 .DW (32)
2166 ) u_key_share1_15 (
2167 .re (1'b0),
2168 .we (key_share1_15_gated_we),
2169 .wd (key_share1_15_wd),
2170 .d ('0),
2171 .qre (),
2172 .qe (key_share1_15_flds_we[0]),
2173 .q (reg2hw.key_share1[15].q),
2174 .ds (),
2175 .qs ()
2176 );
2177 1/1 assign reg2hw.key_share1[15].qe = key_share1_15_qe;
Tests: T1 T4 T13
2178
2179
2180 // R[key_len]: V(False)
2181 // Create REGWEN-gated WE signal
2182 logic key_len_gated_we;
2183 1/1 assign key_len_gated_we = key_len_we & cfg_regwen_qs;
Tests: T1 T2 T3
2184 prim_subreg #(
2185 .DW (3),
2186 .SwAccess(prim_subreg_pkg::SwAccessWO),
2187 .RESVAL (3'h0),
2188 .Mubi (1'b0)
2189 ) u_key_len (
2190 .clk_i (clk_i),
2191 .rst_ni (rst_ni),
2192
2193 // from register interface
2194 .we (key_len_gated_we),
2195 .wd (key_len_wd),
2196
2197 // from internal hardware
2198 .de (1'b0),
2199 .d ('0),
2200
2201 // to internal hardware
2202 .qe (),
2203 .q (reg2hw.key_len.q),
2204 .ds (),
2205
2206 // to register interface (read)
2207 .qs ()
2208 );
2209
2210
2211 // Subregister 0 of Multireg prefix
2212 // R[prefix_0]: V(False)
2213 // Create REGWEN-gated WE signal
2214 logic prefix_0_gated_we;
2215 1/1 assign prefix_0_gated_we = prefix_0_we & cfg_regwen_qs;
Tests: T1 T2 T3
2216 prim_subreg #(
2217 .DW (32),
2218 .SwAccess(prim_subreg_pkg::SwAccessRW),
2219 .RESVAL (32'h0),
2220 .Mubi (1'b0)
2221 ) u_prefix_0 (
2222 .clk_i (clk_i),
2223 .rst_ni (rst_ni),
2224
2225 // from register interface
2226 .we (prefix_0_gated_we),
2227 .wd (prefix_0_wd),
2228
2229 // from internal hardware
2230 .de (1'b0),
2231 .d ('0),
2232
2233 // to internal hardware
2234 .qe (),
2235 .q (reg2hw.prefix[0].q),
2236 .ds (),
2237
2238 // to register interface (read)
2239 .qs (prefix_0_qs)
2240 );
2241
2242
2243 // Subregister 1 of Multireg prefix
2244 // R[prefix_1]: V(False)
2245 // Create REGWEN-gated WE signal
2246 logic prefix_1_gated_we;
2247 1/1 assign prefix_1_gated_we = prefix_1_we & cfg_regwen_qs;
Tests: T1 T2 T3
2248 prim_subreg #(
2249 .DW (32),
2250 .SwAccess(prim_subreg_pkg::SwAccessRW),
2251 .RESVAL (32'h0),
2252 .Mubi (1'b0)
2253 ) u_prefix_1 (
2254 .clk_i (clk_i),
2255 .rst_ni (rst_ni),
2256
2257 // from register interface
2258 .we (prefix_1_gated_we),
2259 .wd (prefix_1_wd),
2260
2261 // from internal hardware
2262 .de (1'b0),
2263 .d ('0),
2264
2265 // to internal hardware
2266 .qe (),
2267 .q (reg2hw.prefix[1].q),
2268 .ds (),
2269
2270 // to register interface (read)
2271 .qs (prefix_1_qs)
2272 );
2273
2274
2275 // Subregister 2 of Multireg prefix
2276 // R[prefix_2]: V(False)
2277 // Create REGWEN-gated WE signal
2278 logic prefix_2_gated_we;
2279 1/1 assign prefix_2_gated_we = prefix_2_we & cfg_regwen_qs;
Tests: T1 T2 T3
2280 prim_subreg #(
2281 .DW (32),
2282 .SwAccess(prim_subreg_pkg::SwAccessRW),
2283 .RESVAL (32'h0),
2284 .Mubi (1'b0)
2285 ) u_prefix_2 (
2286 .clk_i (clk_i),
2287 .rst_ni (rst_ni),
2288
2289 // from register interface
2290 .we (prefix_2_gated_we),
2291 .wd (prefix_2_wd),
2292
2293 // from internal hardware
2294 .de (1'b0),
2295 .d ('0),
2296
2297 // to internal hardware
2298 .qe (),
2299 .q (reg2hw.prefix[2].q),
2300 .ds (),
2301
2302 // to register interface (read)
2303 .qs (prefix_2_qs)
2304 );
2305
2306
2307 // Subregister 3 of Multireg prefix
2308 // R[prefix_3]: V(False)
2309 // Create REGWEN-gated WE signal
2310 logic prefix_3_gated_we;
2311 1/1 assign prefix_3_gated_we = prefix_3_we & cfg_regwen_qs;
Tests: T1 T2 T3
2312 prim_subreg #(
2313 .DW (32),
2314 .SwAccess(prim_subreg_pkg::SwAccessRW),
2315 .RESVAL (32'h0),
2316 .Mubi (1'b0)
2317 ) u_prefix_3 (
2318 .clk_i (clk_i),
2319 .rst_ni (rst_ni),
2320
2321 // from register interface
2322 .we (prefix_3_gated_we),
2323 .wd (prefix_3_wd),
2324
2325 // from internal hardware
2326 .de (1'b0),
2327 .d ('0),
2328
2329 // to internal hardware
2330 .qe (),
2331 .q (reg2hw.prefix[3].q),
2332 .ds (),
2333
2334 // to register interface (read)
2335 .qs (prefix_3_qs)
2336 );
2337
2338
2339 // Subregister 4 of Multireg prefix
2340 // R[prefix_4]: V(False)
2341 // Create REGWEN-gated WE signal
2342 logic prefix_4_gated_we;
2343 1/1 assign prefix_4_gated_we = prefix_4_we & cfg_regwen_qs;
Tests: T1 T2 T3
2344 prim_subreg #(
2345 .DW (32),
2346 .SwAccess(prim_subreg_pkg::SwAccessRW),
2347 .RESVAL (32'h0),
2348 .Mubi (1'b0)
2349 ) u_prefix_4 (
2350 .clk_i (clk_i),
2351 .rst_ni (rst_ni),
2352
2353 // from register interface
2354 .we (prefix_4_gated_we),
2355 .wd (prefix_4_wd),
2356
2357 // from internal hardware
2358 .de (1'b0),
2359 .d ('0),
2360
2361 // to internal hardware
2362 .qe (),
2363 .q (reg2hw.prefix[4].q),
2364 .ds (),
2365
2366 // to register interface (read)
2367 .qs (prefix_4_qs)
2368 );
2369
2370
2371 // Subregister 5 of Multireg prefix
2372 // R[prefix_5]: V(False)
2373 // Create REGWEN-gated WE signal
2374 logic prefix_5_gated_we;
2375 1/1 assign prefix_5_gated_we = prefix_5_we & cfg_regwen_qs;
Tests: T1 T2 T3
2376 prim_subreg #(
2377 .DW (32),
2378 .SwAccess(prim_subreg_pkg::SwAccessRW),
2379 .RESVAL (32'h0),
2380 .Mubi (1'b0)
2381 ) u_prefix_5 (
2382 .clk_i (clk_i),
2383 .rst_ni (rst_ni),
2384
2385 // from register interface
2386 .we (prefix_5_gated_we),
2387 .wd (prefix_5_wd),
2388
2389 // from internal hardware
2390 .de (1'b0),
2391 .d ('0),
2392
2393 // to internal hardware
2394 .qe (),
2395 .q (reg2hw.prefix[5].q),
2396 .ds (),
2397
2398 // to register interface (read)
2399 .qs (prefix_5_qs)
2400 );
2401
2402
2403 // Subregister 6 of Multireg prefix
2404 // R[prefix_6]: V(False)
2405 // Create REGWEN-gated WE signal
2406 logic prefix_6_gated_we;
2407 1/1 assign prefix_6_gated_we = prefix_6_we & cfg_regwen_qs;
Tests: T1 T2 T3
2408 prim_subreg #(
2409 .DW (32),
2410 .SwAccess(prim_subreg_pkg::SwAccessRW),
2411 .RESVAL (32'h0),
2412 .Mubi (1'b0)
2413 ) u_prefix_6 (
2414 .clk_i (clk_i),
2415 .rst_ni (rst_ni),
2416
2417 // from register interface
2418 .we (prefix_6_gated_we),
2419 .wd (prefix_6_wd),
2420
2421 // from internal hardware
2422 .de (1'b0),
2423 .d ('0),
2424
2425 // to internal hardware
2426 .qe (),
2427 .q (reg2hw.prefix[6].q),
2428 .ds (),
2429
2430 // to register interface (read)
2431 .qs (prefix_6_qs)
2432 );
2433
2434
2435 // Subregister 7 of Multireg prefix
2436 // R[prefix_7]: V(False)
2437 // Create REGWEN-gated WE signal
2438 logic prefix_7_gated_we;
2439 1/1 assign prefix_7_gated_we = prefix_7_we & cfg_regwen_qs;
Tests: T1 T2 T3
2440 prim_subreg #(
2441 .DW (32),
2442 .SwAccess(prim_subreg_pkg::SwAccessRW),
2443 .RESVAL (32'h0),
2444 .Mubi (1'b0)
2445 ) u_prefix_7 (
2446 .clk_i (clk_i),
2447 .rst_ni (rst_ni),
2448
2449 // from register interface
2450 .we (prefix_7_gated_we),
2451 .wd (prefix_7_wd),
2452
2453 // from internal hardware
2454 .de (1'b0),
2455 .d ('0),
2456
2457 // to internal hardware
2458 .qe (),
2459 .q (reg2hw.prefix[7].q),
2460 .ds (),
2461
2462 // to register interface (read)
2463 .qs (prefix_7_qs)
2464 );
2465
2466
2467 // Subregister 8 of Multireg prefix
2468 // R[prefix_8]: V(False)
2469 // Create REGWEN-gated WE signal
2470 logic prefix_8_gated_we;
2471 1/1 assign prefix_8_gated_we = prefix_8_we & cfg_regwen_qs;
Tests: T1 T2 T3
2472 prim_subreg #(
2473 .DW (32),
2474 .SwAccess(prim_subreg_pkg::SwAccessRW),
2475 .RESVAL (32'h0),
2476 .Mubi (1'b0)
2477 ) u_prefix_8 (
2478 .clk_i (clk_i),
2479 .rst_ni (rst_ni),
2480
2481 // from register interface
2482 .we (prefix_8_gated_we),
2483 .wd (prefix_8_wd),
2484
2485 // from internal hardware
2486 .de (1'b0),
2487 .d ('0),
2488
2489 // to internal hardware
2490 .qe (),
2491 .q (reg2hw.prefix[8].q),
2492 .ds (),
2493
2494 // to register interface (read)
2495 .qs (prefix_8_qs)
2496 );
2497
2498
2499 // Subregister 9 of Multireg prefix
2500 // R[prefix_9]: V(False)
2501 // Create REGWEN-gated WE signal
2502 logic prefix_9_gated_we;
2503 1/1 assign prefix_9_gated_we = prefix_9_we & cfg_regwen_qs;
Tests: T1 T2 T3
2504 prim_subreg #(
2505 .DW (32),
2506 .SwAccess(prim_subreg_pkg::SwAccessRW),
2507 .RESVAL (32'h0),
2508 .Mubi (1'b0)
2509 ) u_prefix_9 (
2510 .clk_i (clk_i),
2511 .rst_ni (rst_ni),
2512
2513 // from register interface
2514 .we (prefix_9_gated_we),
2515 .wd (prefix_9_wd),
2516
2517 // from internal hardware
2518 .de (1'b0),
2519 .d ('0),
2520
2521 // to internal hardware
2522 .qe (),
2523 .q (reg2hw.prefix[9].q),
2524 .ds (),
2525
2526 // to register interface (read)
2527 .qs (prefix_9_qs)
2528 );
2529
2530
2531 // Subregister 10 of Multireg prefix
2532 // R[prefix_10]: V(False)
2533 // Create REGWEN-gated WE signal
2534 logic prefix_10_gated_we;
2535 1/1 assign prefix_10_gated_we = prefix_10_we & cfg_regwen_qs;
Tests: T1 T2 T3
2536 prim_subreg #(
2537 .DW (32),
2538 .SwAccess(prim_subreg_pkg::SwAccessRW),
2539 .RESVAL (32'h0),
2540 .Mubi (1'b0)
2541 ) u_prefix_10 (
2542 .clk_i (clk_i),
2543 .rst_ni (rst_ni),
2544
2545 // from register interface
2546 .we (prefix_10_gated_we),
2547 .wd (prefix_10_wd),
2548
2549 // from internal hardware
2550 .de (1'b0),
2551 .d ('0),
2552
2553 // to internal hardware
2554 .qe (),
2555 .q (reg2hw.prefix[10].q),
2556 .ds (),
2557
2558 // to register interface (read)
2559 .qs (prefix_10_qs)
2560 );
2561
2562
2563 // R[err_code]: V(False)
2564 prim_subreg #(
2565 .DW (32),
2566 .SwAccess(prim_subreg_pkg::SwAccessRO),
2567 .RESVAL (32'h0),
2568 .Mubi (1'b0)
2569 ) u_err_code (
2570 .clk_i (clk_i),
2571 .rst_ni (rst_ni),
2572
2573 // from register interface
2574 .we (1'b0),
2575 .wd ('0),
2576
2577 // from internal hardware
2578 .de (hw2reg.err_code.de),
2579 .d (hw2reg.err_code.d),
2580
2581 // to internal hardware
2582 .qe (),
2583 .q (),
2584 .ds (),
2585
2586 // to register interface (read)
2587 .qs (err_code_qs)
2588 );
2589
2590
2591
2592 logic [56:0] addr_hit;
2593 always_comb begin
2594 1/1 addr_hit = '0;
Tests: T1 T2 T3
2595 1/1 addr_hit[ 0] = (reg_addr == KMAC_INTR_STATE_OFFSET);
Tests: T1 T2 T3
2596 1/1 addr_hit[ 1] = (reg_addr == KMAC_INTR_ENABLE_OFFSET);
Tests: T1 T2 T3
2597 1/1 addr_hit[ 2] = (reg_addr == KMAC_INTR_TEST_OFFSET);
Tests: T1 T2 T3
2598 1/1 addr_hit[ 3] = (reg_addr == KMAC_ALERT_TEST_OFFSET);
Tests: T1 T2 T3
2599 1/1 addr_hit[ 4] = (reg_addr == KMAC_CFG_REGWEN_OFFSET);
Tests: T1 T2 T3
2600 1/1 addr_hit[ 5] = (reg_addr == KMAC_CFG_SHADOWED_OFFSET);
Tests: T1 T2 T3
2601 1/1 addr_hit[ 6] = (reg_addr == KMAC_CMD_OFFSET);
Tests: T1 T2 T3
2602 1/1 addr_hit[ 7] = (reg_addr == KMAC_STATUS_OFFSET);
Tests: T1 T2 T3
2603 1/1 addr_hit[ 8] = (reg_addr == KMAC_ENTROPY_PERIOD_OFFSET);
Tests: T1 T2 T3
2604 1/1 addr_hit[ 9] = (reg_addr == KMAC_ENTROPY_REFRESH_HASH_CNT_OFFSET);
Tests: T1 T2 T3
2605 1/1 addr_hit[10] = (reg_addr == KMAC_ENTROPY_REFRESH_THRESHOLD_SHADOWED_OFFSET);
Tests: T1 T2 T3
2606 1/1 addr_hit[11] = (reg_addr == KMAC_ENTROPY_SEED_OFFSET);
Tests: T1 T2 T3
2607 1/1 addr_hit[12] = (reg_addr == KMAC_KEY_SHARE0_0_OFFSET);
Tests: T1 T2 T3
2608 1/1 addr_hit[13] = (reg_addr == KMAC_KEY_SHARE0_1_OFFSET);
Tests: T1 T2 T3
2609 1/1 addr_hit[14] = (reg_addr == KMAC_KEY_SHARE0_2_OFFSET);
Tests: T1 T2 T3
2610 1/1 addr_hit[15] = (reg_addr == KMAC_KEY_SHARE0_3_OFFSET);
Tests: T1 T2 T3
2611 1/1 addr_hit[16] = (reg_addr == KMAC_KEY_SHARE0_4_OFFSET);
Tests: T1 T2 T3
2612 1/1 addr_hit[17] = (reg_addr == KMAC_KEY_SHARE0_5_OFFSET);
Tests: T1 T2 T3
2613 1/1 addr_hit[18] = (reg_addr == KMAC_KEY_SHARE0_6_OFFSET);
Tests: T1 T2 T3
2614 1/1 addr_hit[19] = (reg_addr == KMAC_KEY_SHARE0_7_OFFSET);
Tests: T1 T2 T3
2615 1/1 addr_hit[20] = (reg_addr == KMAC_KEY_SHARE0_8_OFFSET);
Tests: T1 T2 T3
2616 1/1 addr_hit[21] = (reg_addr == KMAC_KEY_SHARE0_9_OFFSET);
Tests: T1 T2 T3
2617 1/1 addr_hit[22] = (reg_addr == KMAC_KEY_SHARE0_10_OFFSET);
Tests: T1 T2 T3
2618 1/1 addr_hit[23] = (reg_addr == KMAC_KEY_SHARE0_11_OFFSET);
Tests: T1 T2 T3
2619 1/1 addr_hit[24] = (reg_addr == KMAC_KEY_SHARE0_12_OFFSET);
Tests: T1 T2 T3
2620 1/1 addr_hit[25] = (reg_addr == KMAC_KEY_SHARE0_13_OFFSET);
Tests: T1 T2 T3
2621 1/1 addr_hit[26] = (reg_addr == KMAC_KEY_SHARE0_14_OFFSET);
Tests: T1 T2 T3
2622 1/1 addr_hit[27] = (reg_addr == KMAC_KEY_SHARE0_15_OFFSET);
Tests: T1 T2 T3
2623 1/1 addr_hit[28] = (reg_addr == KMAC_KEY_SHARE1_0_OFFSET);
Tests: T1 T2 T3
2624 1/1 addr_hit[29] = (reg_addr == KMAC_KEY_SHARE1_1_OFFSET);
Tests: T1 T2 T3
2625 1/1 addr_hit[30] = (reg_addr == KMAC_KEY_SHARE1_2_OFFSET);
Tests: T1 T2 T3
2626 1/1 addr_hit[31] = (reg_addr == KMAC_KEY_SHARE1_3_OFFSET);
Tests: T1 T2 T3
2627 1/1 addr_hit[32] = (reg_addr == KMAC_KEY_SHARE1_4_OFFSET);
Tests: T1 T2 T3
2628 1/1 addr_hit[33] = (reg_addr == KMAC_KEY_SHARE1_5_OFFSET);
Tests: T1 T2 T3
2629 1/1 addr_hit[34] = (reg_addr == KMAC_KEY_SHARE1_6_OFFSET);
Tests: T1 T2 T3
2630 1/1 addr_hit[35] = (reg_addr == KMAC_KEY_SHARE1_7_OFFSET);
Tests: T1 T2 T3
2631 1/1 addr_hit[36] = (reg_addr == KMAC_KEY_SHARE1_8_OFFSET);
Tests: T1 T2 T3
2632 1/1 addr_hit[37] = (reg_addr == KMAC_KEY_SHARE1_9_OFFSET);
Tests: T1 T2 T3
2633 1/1 addr_hit[38] = (reg_addr == KMAC_KEY_SHARE1_10_OFFSET);
Tests: T1 T2 T3
2634 1/1 addr_hit[39] = (reg_addr == KMAC_KEY_SHARE1_11_OFFSET);
Tests: T1 T2 T3
2635 1/1 addr_hit[40] = (reg_addr == KMAC_KEY_SHARE1_12_OFFSET);
Tests: T1 T2 T3
2636 1/1 addr_hit[41] = (reg_addr == KMAC_KEY_SHARE1_13_OFFSET);
Tests: T1 T2 T3
2637 1/1 addr_hit[42] = (reg_addr == KMAC_KEY_SHARE1_14_OFFSET);
Tests: T1 T2 T3
2638 1/1 addr_hit[43] = (reg_addr == KMAC_KEY_SHARE1_15_OFFSET);
Tests: T1 T2 T3
2639 1/1 addr_hit[44] = (reg_addr == KMAC_KEY_LEN_OFFSET);
Tests: T1 T2 T3
2640 1/1 addr_hit[45] = (reg_addr == KMAC_PREFIX_0_OFFSET);
Tests: T1 T2 T3
2641 1/1 addr_hit[46] = (reg_addr == KMAC_PREFIX_1_OFFSET);
Tests: T1 T2 T3
2642 1/1 addr_hit[47] = (reg_addr == KMAC_PREFIX_2_OFFSET);
Tests: T1 T2 T3
2643 1/1 addr_hit[48] = (reg_addr == KMAC_PREFIX_3_OFFSET);
Tests: T1 T2 T3
2644 1/1 addr_hit[49] = (reg_addr == KMAC_PREFIX_4_OFFSET);
Tests: T1 T2 T3
2645 1/1 addr_hit[50] = (reg_addr == KMAC_PREFIX_5_OFFSET);
Tests: T1 T2 T3
2646 1/1 addr_hit[51] = (reg_addr == KMAC_PREFIX_6_OFFSET);
Tests: T1 T2 T3
2647 1/1 addr_hit[52] = (reg_addr == KMAC_PREFIX_7_OFFSET);
Tests: T1 T2 T3
2648 1/1 addr_hit[53] = (reg_addr == KMAC_PREFIX_8_OFFSET);
Tests: T1 T2 T3
2649 1/1 addr_hit[54] = (reg_addr == KMAC_PREFIX_9_OFFSET);
Tests: T1 T2 T3
2650 1/1 addr_hit[55] = (reg_addr == KMAC_PREFIX_10_OFFSET);
Tests: T1 T2 T3
2651 1/1 addr_hit[56] = (reg_addr == KMAC_ERR_CODE_OFFSET);
Tests: T1 T2 T3
2652 end
2653
2654 1/1 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
Tests: T1 T2 T3
2655
2656 // Check sub-word write is permitted
2657 always_comb begin
2658 1/1 wr_err = (reg_we &
Tests: T1 T2 T3
2659 ((addr_hit[ 0] & (|(KMAC_PERMIT[ 0] & ~reg_be))) |
2660 (addr_hit[ 1] & (|(KMAC_PERMIT[ 1] & ~reg_be))) |
2661 (addr_hit[ 2] & (|(KMAC_PERMIT[ 2] & ~reg_be))) |
2662 (addr_hit[ 3] & (|(KMAC_PERMIT[ 3] & ~reg_be))) |
2663 (addr_hit[ 4] & (|(KMAC_PERMIT[ 4] & ~reg_be))) |
2664 (addr_hit[ 5] & (|(KMAC_PERMIT[ 5] & ~reg_be))) |
2665 (addr_hit[ 6] & (|(KMAC_PERMIT[ 6] & ~reg_be))) |
2666 (addr_hit[ 7] & (|(KMAC_PERMIT[ 7] & ~reg_be))) |
2667 (addr_hit[ 8] & (|(KMAC_PERMIT[ 8] & ~reg_be))) |
2668 (addr_hit[ 9] & (|(KMAC_PERMIT[ 9] & ~reg_be))) |
2669 (addr_hit[10] & (|(KMAC_PERMIT[10] & ~reg_be))) |
2670 (addr_hit[11] & (|(KMAC_PERMIT[11] & ~reg_be))) |
2671 (addr_hit[12] & (|(KMAC_PERMIT[12] & ~reg_be))) |
2672 (addr_hit[13] & (|(KMAC_PERMIT[13] & ~reg_be))) |
2673 (addr_hit[14] & (|(KMAC_PERMIT[14] & ~reg_be))) |
2674 (addr_hit[15] & (|(KMAC_PERMIT[15] & ~reg_be))) |
2675 (addr_hit[16] & (|(KMAC_PERMIT[16] & ~reg_be))) |
2676 (addr_hit[17] & (|(KMAC_PERMIT[17] & ~reg_be))) |
2677 (addr_hit[18] & (|(KMAC_PERMIT[18] & ~reg_be))) |
2678 (addr_hit[19] & (|(KMAC_PERMIT[19] & ~reg_be))) |
2679 (addr_hit[20] & (|(KMAC_PERMIT[20] & ~reg_be))) |
2680 (addr_hit[21] & (|(KMAC_PERMIT[21] & ~reg_be))) |
2681 (addr_hit[22] & (|(KMAC_PERMIT[22] & ~reg_be))) |
2682 (addr_hit[23] & (|(KMAC_PERMIT[23] & ~reg_be))) |
2683 (addr_hit[24] & (|(KMAC_PERMIT[24] & ~reg_be))) |
2684 (addr_hit[25] & (|(KMAC_PERMIT[25] & ~reg_be))) |
2685 (addr_hit[26] & (|(KMAC_PERMIT[26] & ~reg_be))) |
2686 (addr_hit[27] & (|(KMAC_PERMIT[27] & ~reg_be))) |
2687 (addr_hit[28] & (|(KMAC_PERMIT[28] & ~reg_be))) |
2688 (addr_hit[29] & (|(KMAC_PERMIT[29] & ~reg_be))) |
2689 (addr_hit[30] & (|(KMAC_PERMIT[30] & ~reg_be))) |
2690 (addr_hit[31] & (|(KMAC_PERMIT[31] & ~reg_be))) |
2691 (addr_hit[32] & (|(KMAC_PERMIT[32] & ~reg_be))) |
2692 (addr_hit[33] & (|(KMAC_PERMIT[33] & ~reg_be))) |
2693 (addr_hit[34] & (|(KMAC_PERMIT[34] & ~reg_be))) |
2694 (addr_hit[35] & (|(KMAC_PERMIT[35] & ~reg_be))) |
2695 (addr_hit[36] & (|(KMAC_PERMIT[36] & ~reg_be))) |
2696 (addr_hit[37] & (|(KMAC_PERMIT[37] & ~reg_be))) |
2697 (addr_hit[38] & (|(KMAC_PERMIT[38] & ~reg_be))) |
2698 (addr_hit[39] & (|(KMAC_PERMIT[39] & ~reg_be))) |
2699 (addr_hit[40] & (|(KMAC_PERMIT[40] & ~reg_be))) |
2700 (addr_hit[41] & (|(KMAC_PERMIT[41] & ~reg_be))) |
2701 (addr_hit[42] & (|(KMAC_PERMIT[42] & ~reg_be))) |
2702 (addr_hit[43] & (|(KMAC_PERMIT[43] & ~reg_be))) |
2703 (addr_hit[44] & (|(KMAC_PERMIT[44] & ~reg_be))) |
2704 (addr_hit[45] & (|(KMAC_PERMIT[45] & ~reg_be))) |
2705 (addr_hit[46] & (|(KMAC_PERMIT[46] & ~reg_be))) |
2706 (addr_hit[47] & (|(KMAC_PERMIT[47] & ~reg_be))) |
2707 (addr_hit[48] & (|(KMAC_PERMIT[48] & ~reg_be))) |
2708 (addr_hit[49] & (|(KMAC_PERMIT[49] & ~reg_be))) |
2709 (addr_hit[50] & (|(KMAC_PERMIT[50] & ~reg_be))) |
2710 (addr_hit[51] & (|(KMAC_PERMIT[51] & ~reg_be))) |
2711 (addr_hit[52] & (|(KMAC_PERMIT[52] & ~reg_be))) |
2712 (addr_hit[53] & (|(KMAC_PERMIT[53] & ~reg_be))) |
2713 (addr_hit[54] & (|(KMAC_PERMIT[54] & ~reg_be))) |
2714 (addr_hit[55] & (|(KMAC_PERMIT[55] & ~reg_be))) |
2715 (addr_hit[56] & (|(KMAC_PERMIT[56] & ~reg_be)))));
2716 end
2717
2718 // Generate write-enables
2719 1/1 assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
Tests: T1 T2 T3
2720
2721 1/1 assign intr_state_kmac_done_wd = reg_wdata[0];
Tests: T1 T2 T3
2722
2723 1/1 assign intr_state_kmac_err_wd = reg_wdata[2];
Tests: T1 T2 T3
2724 1/1 assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;
Tests: T1 T2 T3
2725
2726 1/1 assign intr_enable_kmac_done_wd = reg_wdata[0];
Tests: T1 T2 T3
2727
2728 1/1 assign intr_enable_fifo_empty_wd = reg_wdata[1];
Tests: T1 T2 T3
2729
2730 1/1 assign intr_enable_kmac_err_wd = reg_wdata[2];
Tests: T1 T2 T3
2731 1/1 assign intr_test_we = addr_hit[2] & reg_we & !reg_error;
Tests: T1 T2 T3
2732
2733 1/1 assign intr_test_kmac_done_wd = reg_wdata[0];
Tests: T1 T2 T3
2734
2735 1/1 assign intr_test_fifo_empty_wd = reg_wdata[1];
Tests: T1 T2 T3
2736
2737 1/1 assign intr_test_kmac_err_wd = reg_wdata[2];
Tests: T1 T2 T3
2738 1/1 assign alert_test_we = addr_hit[3] & reg_we & !reg_error;
Tests: T1 T2 T3
2739
2740 1/1 assign alert_test_recov_operation_err_wd = reg_wdata[0];
Tests: T1 T2 T3
2741
2742 1/1 assign alert_test_fatal_fault_err_wd = reg_wdata[1];
Tests: T1 T2 T3
2743 1/1 assign cfg_regwen_re = addr_hit[4] & reg_re & !reg_error;
Tests: T1 T2 T3
2744 1/1 assign cfg_shadowed_re = addr_hit[5] & reg_re & !reg_error;
Tests: T1 T2 T3
2745 1/1 assign cfg_shadowed_we = addr_hit[5] & reg_we & !reg_error;
Tests: T1 T2 T3
2746
2747 1/1 assign cfg_shadowed_kmac_en_wd = reg_wdata[0];
Tests: T1 T2 T3
2748
2749 1/1 assign cfg_shadowed_kstrength_wd = reg_wdata[3:1];
Tests: T1 T2 T3
2750
2751 1/1 assign cfg_shadowed_mode_wd = reg_wdata[5:4];
Tests: T1 T2 T3
2752
2753 1/1 assign cfg_shadowed_msg_endianness_wd = reg_wdata[8];
Tests: T1 T2 T3
2754
2755 1/1 assign cfg_shadowed_state_endianness_wd = reg_wdata[9];
Tests: T1 T2 T3
2756
2757 1/1 assign cfg_shadowed_sideload_wd = reg_wdata[12];
Tests: T1 T2 T3
2758
2759 1/1 assign cfg_shadowed_entropy_mode_wd = reg_wdata[17:16];
Tests: T1 T2 T3
2760
2761 1/1 assign cfg_shadowed_entropy_fast_process_wd = reg_wdata[19];
Tests: T1 T2 T3
2762
2763 1/1 assign cfg_shadowed_msg_mask_wd = reg_wdata[20];
Tests: T1 T2 T3
2764
2765 1/1 assign cfg_shadowed_entropy_ready_wd = reg_wdata[24];
Tests: T1 T2 T3
2766
2767 1/1 assign cfg_shadowed_en_unsupported_modestrength_wd = reg_wdata[26];
Tests: T1 T2 T3
2768 1/1 assign cmd_we = addr_hit[6] & reg_we & !reg_error;
Tests: T1 T2 T3
2769
2770 1/1 assign cmd_cmd_wd = reg_wdata[5:0];
Tests: T1 T2 T3
2771
2772 1/1 assign cmd_entropy_req_wd = reg_wdata[8];
Tests: T1 T2 T3
2773
2774 1/1 assign cmd_hash_cnt_clr_wd = reg_wdata[9];
Tests: T1 T2 T3
2775
2776 1/1 assign cmd_err_processed_wd = reg_wdata[10];
Tests: T1 T2 T3
2777 1/1 assign status_re = addr_hit[7] & reg_re & !reg_error;
Tests: T1 T2 T3
2778 1/1 assign entropy_period_we = addr_hit[8] & reg_we & !reg_error;
Tests: T1 T2 T3
2779
2780 1/1 assign entropy_period_prescaler_wd = reg_wdata[9:0];
Tests: T1 T2 T3
2781
2782 1/1 assign entropy_period_wait_timer_wd = reg_wdata[31:16];
Tests: T1 T2 T3
2783 1/1 assign entropy_refresh_threshold_shadowed_re = addr_hit[10] & reg_re & !reg_error;
Tests: T1 T2 T3
2784 1/1 assign entropy_refresh_threshold_shadowed_we = addr_hit[10] & reg_we & !reg_error;
Tests: T1 T2 T3
2785
2786 1/1 assign entropy_refresh_threshold_shadowed_wd = reg_wdata[9:0];
Tests: T1 T2 T3
2787 1/1 assign entropy_seed_we = addr_hit[11] & reg_we & !reg_error;
Tests: T1 T2 T3
2788
2789 1/1 assign entropy_seed_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2790 1/1 assign key_share0_0_we = addr_hit[12] & reg_we & !reg_error;
Tests: T1 T2 T3
2791
2792 1/1 assign key_share0_0_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2793 1/1 assign key_share0_1_we = addr_hit[13] & reg_we & !reg_error;
Tests: T1 T2 T3
2794
2795 1/1 assign key_share0_1_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2796 1/1 assign key_share0_2_we = addr_hit[14] & reg_we & !reg_error;
Tests: T1 T2 T3
2797
2798 1/1 assign key_share0_2_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2799 1/1 assign key_share0_3_we = addr_hit[15] & reg_we & !reg_error;
Tests: T1 T2 T3
2800
2801 1/1 assign key_share0_3_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2802 1/1 assign key_share0_4_we = addr_hit[16] & reg_we & !reg_error;
Tests: T1 T2 T3
2803
2804 1/1 assign key_share0_4_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2805 1/1 assign key_share0_5_we = addr_hit[17] & reg_we & !reg_error;
Tests: T1 T2 T3
2806
2807 1/1 assign key_share0_5_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2808 1/1 assign key_share0_6_we = addr_hit[18] & reg_we & !reg_error;
Tests: T1 T2 T3
2809
2810 1/1 assign key_share0_6_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2811 1/1 assign key_share0_7_we = addr_hit[19] & reg_we & !reg_error;
Tests: T1 T2 T3
2812
2813 1/1 assign key_share0_7_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2814 1/1 assign key_share0_8_we = addr_hit[20] & reg_we & !reg_error;
Tests: T1 T2 T3
2815
2816 1/1 assign key_share0_8_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2817 1/1 assign key_share0_9_we = addr_hit[21] & reg_we & !reg_error;
Tests: T1 T2 T3
2818
2819 1/1 assign key_share0_9_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2820 1/1 assign key_share0_10_we = addr_hit[22] & reg_we & !reg_error;
Tests: T1 T2 T3
2821
2822 1/1 assign key_share0_10_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2823 1/1 assign key_share0_11_we = addr_hit[23] & reg_we & !reg_error;
Tests: T1 T2 T3
2824
2825 1/1 assign key_share0_11_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2826 1/1 assign key_share0_12_we = addr_hit[24] & reg_we & !reg_error;
Tests: T1 T2 T3
2827
2828 1/1 assign key_share0_12_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2829 1/1 assign key_share0_13_we = addr_hit[25] & reg_we & !reg_error;
Tests: T1 T2 T3
2830
2831 1/1 assign key_share0_13_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2832 1/1 assign key_share0_14_we = addr_hit[26] & reg_we & !reg_error;
Tests: T1 T2 T3
2833
2834 1/1 assign key_share0_14_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2835 1/1 assign key_share0_15_we = addr_hit[27] & reg_we & !reg_error;
Tests: T1 T2 T3
2836
2837 1/1 assign key_share0_15_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2838 1/1 assign key_share1_0_we = addr_hit[28] & reg_we & !reg_error;
Tests: T1 T2 T3
2839
2840 1/1 assign key_share1_0_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2841 1/1 assign key_share1_1_we = addr_hit[29] & reg_we & !reg_error;
Tests: T1 T2 T3
2842
2843 1/1 assign key_share1_1_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2844 1/1 assign key_share1_2_we = addr_hit[30] & reg_we & !reg_error;
Tests: T1 T2 T3
2845
2846 1/1 assign key_share1_2_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2847 1/1 assign key_share1_3_we = addr_hit[31] & reg_we & !reg_error;
Tests: T1 T2 T3
2848
2849 1/1 assign key_share1_3_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2850 1/1 assign key_share1_4_we = addr_hit[32] & reg_we & !reg_error;
Tests: T1 T2 T3
2851
2852 1/1 assign key_share1_4_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2853 1/1 assign key_share1_5_we = addr_hit[33] & reg_we & !reg_error;
Tests: T1 T2 T3
2854
2855 1/1 assign key_share1_5_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2856 1/1 assign key_share1_6_we = addr_hit[34] & reg_we & !reg_error;
Tests: T1 T2 T3
2857
2858 1/1 assign key_share1_6_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2859 1/1 assign key_share1_7_we = addr_hit[35] & reg_we & !reg_error;
Tests: T1 T2 T3
2860
2861 1/1 assign key_share1_7_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2862 1/1 assign key_share1_8_we = addr_hit[36] & reg_we & !reg_error;
Tests: T1 T2 T3
2863
2864 1/1 assign key_share1_8_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2865 1/1 assign key_share1_9_we = addr_hit[37] & reg_we & !reg_error;
Tests: T1 T2 T3
2866
2867 1/1 assign key_share1_9_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2868 1/1 assign key_share1_10_we = addr_hit[38] & reg_we & !reg_error;
Tests: T1 T2 T3
2869
2870 1/1 assign key_share1_10_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2871 1/1 assign key_share1_11_we = addr_hit[39] & reg_we & !reg_error;
Tests: T1 T2 T3
2872
2873 1/1 assign key_share1_11_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2874 1/1 assign key_share1_12_we = addr_hit[40] & reg_we & !reg_error;
Tests: T1 T2 T3
2875
2876 1/1 assign key_share1_12_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2877 1/1 assign key_share1_13_we = addr_hit[41] & reg_we & !reg_error;
Tests: T1 T2 T3
2878
2879 1/1 assign key_share1_13_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2880 1/1 assign key_share1_14_we = addr_hit[42] & reg_we & !reg_error;
Tests: T1 T2 T3
2881
2882 1/1 assign key_share1_14_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2883 1/1 assign key_share1_15_we = addr_hit[43] & reg_we & !reg_error;
Tests: T1 T2 T3
2884
2885 1/1 assign key_share1_15_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2886 1/1 assign key_len_we = addr_hit[44] & reg_we & !reg_error;
Tests: T1 T2 T3
2887
2888 1/1 assign key_len_wd = reg_wdata[2:0];
Tests: T1 T2 T3
2889 1/1 assign prefix_0_we = addr_hit[45] & reg_we & !reg_error;
Tests: T1 T2 T3
2890
2891 1/1 assign prefix_0_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2892 1/1 assign prefix_1_we = addr_hit[46] & reg_we & !reg_error;
Tests: T1 T2 T3
2893
2894 1/1 assign prefix_1_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2895 1/1 assign prefix_2_we = addr_hit[47] & reg_we & !reg_error;
Tests: T1 T2 T3
2896
2897 1/1 assign prefix_2_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2898 1/1 assign prefix_3_we = addr_hit[48] & reg_we & !reg_error;
Tests: T1 T2 T3
2899
2900 1/1 assign prefix_3_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2901 1/1 assign prefix_4_we = addr_hit[49] & reg_we & !reg_error;
Tests: T1 T2 T3
2902
2903 1/1 assign prefix_4_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2904 1/1 assign prefix_5_we = addr_hit[50] & reg_we & !reg_error;
Tests: T1 T2 T3
2905
2906 1/1 assign prefix_5_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2907 1/1 assign prefix_6_we = addr_hit[51] & reg_we & !reg_error;
Tests: T1 T2 T3
2908
2909 1/1 assign prefix_6_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2910 1/1 assign prefix_7_we = addr_hit[52] & reg_we & !reg_error;
Tests: T1 T2 T3
2911
2912 1/1 assign prefix_7_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2913 1/1 assign prefix_8_we = addr_hit[53] & reg_we & !reg_error;
Tests: T1 T2 T3
2914
2915 1/1 assign prefix_8_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2916 1/1 assign prefix_9_we = addr_hit[54] & reg_we & !reg_error;
Tests: T1 T2 T3
2917
2918 1/1 assign prefix_9_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2919 1/1 assign prefix_10_we = addr_hit[55] & reg_we & !reg_error;
Tests: T1 T2 T3
2920
2921 1/1 assign prefix_10_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2922
2923 // Assign write-enables to checker logic vector.
2924 always_comb begin
2925 1/1 reg_we_check = '0;
Tests: T1 T2 T3
2926 1/1 reg_we_check[0] = intr_state_we;
Tests: T1 T2 T3
2927 1/1 reg_we_check[1] = intr_enable_we;
Tests: T1 T2 T3
2928 1/1 reg_we_check[2] = intr_test_we;
Tests: T1 T2 T3
2929 1/1 reg_we_check[3] = alert_test_we;
Tests: T1 T2 T3
2930 1/1 reg_we_check[4] = 1'b0;
Tests: T1 T2 T3
2931 1/1 reg_we_check[5] = cfg_shadowed_gated_we;
Tests: T1 T2 T3
2932 1/1 reg_we_check[6] = cmd_we;
Tests: T1 T2 T3
2933 1/1 reg_we_check[7] = 1'b0;
Tests: T1 T2 T3
2934 1/1 reg_we_check[8] = entropy_period_gated_we;
Tests: T1 T2 T3
2935 1/1 reg_we_check[9] = 1'b0;
Tests: T1 T2 T3
2936 1/1 reg_we_check[10] = entropy_refresh_threshold_shadowed_gated_we;
Tests: T1 T2 T3
2937 1/1 reg_we_check[11] = entropy_seed_we;
Tests: T1 T2 T3
2938 1/1 reg_we_check[12] = key_share0_0_gated_we;
Tests: T1 T2 T3
2939 1/1 reg_we_check[13] = key_share0_1_gated_we;
Tests: T1 T2 T3
2940 1/1 reg_we_check[14] = key_share0_2_gated_we;
Tests: T1 T2 T3
2941 1/1 reg_we_check[15] = key_share0_3_gated_we;
Tests: T1 T2 T3
2942 1/1 reg_we_check[16] = key_share0_4_gated_we;
Tests: T1 T2 T3
2943 1/1 reg_we_check[17] = key_share0_5_gated_we;
Tests: T1 T2 T3
2944 1/1 reg_we_check[18] = key_share0_6_gated_we;
Tests: T1 T2 T3
2945 1/1 reg_we_check[19] = key_share0_7_gated_we;
Tests: T1 T2 T3
2946 1/1 reg_we_check[20] = key_share0_8_gated_we;
Tests: T1 T2 T3
2947 1/1 reg_we_check[21] = key_share0_9_gated_we;
Tests: T1 T2 T3
2948 1/1 reg_we_check[22] = key_share0_10_gated_we;
Tests: T1 T2 T3
2949 1/1 reg_we_check[23] = key_share0_11_gated_we;
Tests: T1 T2 T3
2950 1/1 reg_we_check[24] = key_share0_12_gated_we;
Tests: T1 T2 T3
2951 1/1 reg_we_check[25] = key_share0_13_gated_we;
Tests: T1 T2 T3
2952 1/1 reg_we_check[26] = key_share0_14_gated_we;
Tests: T1 T2 T3
2953 1/1 reg_we_check[27] = key_share0_15_gated_we;
Tests: T1 T2 T3
2954 1/1 reg_we_check[28] = key_share1_0_gated_we;
Tests: T1 T2 T3
2955 1/1 reg_we_check[29] = key_share1_1_gated_we;
Tests: T1 T2 T3
2956 1/1 reg_we_check[30] = key_share1_2_gated_we;
Tests: T1 T2 T3
2957 1/1 reg_we_check[31] = key_share1_3_gated_we;
Tests: T1 T2 T3
2958 1/1 reg_we_check[32] = key_share1_4_gated_we;
Tests: T1 T2 T3
2959 1/1 reg_we_check[33] = key_share1_5_gated_we;
Tests: T1 T2 T3
2960 1/1 reg_we_check[34] = key_share1_6_gated_we;
Tests: T1 T2 T3
2961 1/1 reg_we_check[35] = key_share1_7_gated_we;
Tests: T1 T2 T3
2962 1/1 reg_we_check[36] = key_share1_8_gated_we;
Tests: T1 T2 T3
2963 1/1 reg_we_check[37] = key_share1_9_gated_we;
Tests: T1 T2 T3
2964 1/1 reg_we_check[38] = key_share1_10_gated_we;
Tests: T1 T2 T3
2965 1/1 reg_we_check[39] = key_share1_11_gated_we;
Tests: T1 T2 T3
2966 1/1 reg_we_check[40] = key_share1_12_gated_we;
Tests: T1 T2 T3
2967 1/1 reg_we_check[41] = key_share1_13_gated_we;
Tests: T1 T2 T3
2968 1/1 reg_we_check[42] = key_share1_14_gated_we;
Tests: T1 T2 T3
2969 1/1 reg_we_check[43] = key_share1_15_gated_we;
Tests: T1 T2 T3
2970 1/1 reg_we_check[44] = key_len_gated_we;
Tests: T1 T2 T3
2971 1/1 reg_we_check[45] = prefix_0_gated_we;
Tests: T1 T2 T3
2972 1/1 reg_we_check[46] = prefix_1_gated_we;
Tests: T1 T2 T3
2973 1/1 reg_we_check[47] = prefix_2_gated_we;
Tests: T1 T2 T3
2974 1/1 reg_we_check[48] = prefix_3_gated_we;
Tests: T1 T2 T3
2975 1/1 reg_we_check[49] = prefix_4_gated_we;
Tests: T1 T2 T3
2976 1/1 reg_we_check[50] = prefix_5_gated_we;
Tests: T1 T2 T3
2977 1/1 reg_we_check[51] = prefix_6_gated_we;
Tests: T1 T2 T3
2978 1/1 reg_we_check[52] = prefix_7_gated_we;
Tests: T1 T2 T3
2979 1/1 reg_we_check[53] = prefix_8_gated_we;
Tests: T1 T2 T3
2980 1/1 reg_we_check[54] = prefix_9_gated_we;
Tests: T1 T2 T3
2981 1/1 reg_we_check[55] = prefix_10_gated_we;
Tests: T1 T2 T3
2982 1/1 reg_we_check[56] = 1'b0;
Tests: T1 T2 T3
2983 end
2984
2985 // Read data return
2986 always_comb begin
2987 1/1 reg_rdata_next = '0;
Tests: T1 T2 T3
2988 1/1 unique case (1'b1)
Tests: T1 T2 T3
2989 addr_hit[0]: begin
2990 1/1 reg_rdata_next[0] = intr_state_kmac_done_qs;
Tests: T1 T2 T3
2991 1/1 reg_rdata_next[1] = intr_state_fifo_empty_qs;
Tests: T1 T2 T3
2992 1/1 reg_rdata_next[2] = intr_state_kmac_err_qs;
Tests: T1 T2 T3
2993 end
2994
2995 addr_hit[1]: begin
2996 1/1 reg_rdata_next[0] = intr_enable_kmac_done_qs;
Tests: T1 T2 T3
2997 1/1 reg_rdata_next[1] = intr_enable_fifo_empty_qs;
Tests: T1 T2 T3
2998 1/1 reg_rdata_next[2] = intr_enable_kmac_err_qs;
Tests: T1 T2 T3
2999 end
3000
3001 addr_hit[2]: begin
3002 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T4
3003 1/1 reg_rdata_next[1] = '0;
Tests: T1 T2 T4
3004 1/1 reg_rdata_next[2] = '0;
Tests: T1 T2 T4
3005 end
3006
3007 addr_hit[3]: begin
3008 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T4
3009 1/1 reg_rdata_next[1] = '0;
Tests: T1 T2 T4
3010 end
3011
3012 addr_hit[4]: begin
3013 1/1 reg_rdata_next[0] = cfg_regwen_qs;
Tests: T1 T2 T3
3014 end
3015
3016 addr_hit[5]: begin
3017 1/1 reg_rdata_next[0] = cfg_shadowed_kmac_en_qs;
Tests: T1 T2 T3
3018 1/1 reg_rdata_next[3:1] = cfg_shadowed_kstrength_qs;
Tests: T1 T2 T3
3019 1/1 reg_rdata_next[5:4] = cfg_shadowed_mode_qs;
Tests: T1 T2 T3
3020 1/1 reg_rdata_next[8] = cfg_shadowed_msg_endianness_qs;
Tests: T1 T2 T3
3021 1/1 reg_rdata_next[9] = cfg_shadowed_state_endianness_qs;
Tests: T1 T2 T3
3022 1/1 reg_rdata_next[12] = cfg_shadowed_sideload_qs;
Tests: T1 T2 T3
3023 1/1 reg_rdata_next[17:16] = cfg_shadowed_entropy_mode_qs;
Tests: T1 T2 T3
3024 1/1 reg_rdata_next[19] = cfg_shadowed_entropy_fast_process_qs;
Tests: T1 T2 T3
3025 1/1 reg_rdata_next[20] = cfg_shadowed_msg_mask_qs;
Tests: T1 T2 T3
3026 1/1 reg_rdata_next[24] = cfg_shadowed_entropy_ready_qs;
Tests: T1 T2 T3
3027 1/1 reg_rdata_next[26] = cfg_shadowed_en_unsupported_modestrength_qs;
Tests: T1 T2 T3
3028 end
3029
3030 addr_hit[6]: begin
3031 1/1 reg_rdata_next[5:0] = '0;
Tests: T1 T2 T3
3032 1/1 reg_rdata_next[8] = '0;
Tests: T1 T2 T3
3033 1/1 reg_rdata_next[9] = '0;
Tests: T1 T2 T3
3034 1/1 reg_rdata_next[10] = '0;
Tests: T1 T2 T3
3035 end
3036
3037 addr_hit[7]: begin
3038 1/1 reg_rdata_next[0] = status_sha3_idle_qs;
Tests: T1 T2 T3
3039 1/1 reg_rdata_next[1] = status_sha3_absorb_qs;
Tests: T1 T2 T3
3040 1/1 reg_rdata_next[2] = status_sha3_squeeze_qs;
Tests: T1 T2 T3
3041 1/1 reg_rdata_next[12:8] = status_fifo_depth_qs;
Tests: T1 T2 T3
3042 1/1 reg_rdata_next[14] = status_fifo_empty_qs;
Tests: T1 T2 T3
3043 1/1 reg_rdata_next[15] = status_fifo_full_qs;
Tests: T1 T2 T3
3044 1/1 reg_rdata_next[16] = status_alert_fatal_fault_qs;
Tests: T1 T2 T3
3045 1/1 reg_rdata_next[17] = status_alert_recov_ctrl_update_err_qs;
Tests: T1 T2 T3
3046 end
3047
3048 addr_hit[8]: begin
3049 1/1 reg_rdata_next[9:0] = entropy_period_prescaler_qs;
Tests: T1 T2 T3
3050 1/1 reg_rdata_next[31:16] = entropy_period_wait_timer_qs;
Tests: T1 T2 T3
3051 end
3052
3053 addr_hit[9]: begin
3054 1/1 reg_rdata_next[9:0] = entropy_refresh_hash_cnt_qs;
Tests: T1 T2 T4
3055 end
3056
3057 addr_hit[10]: begin
3058 1/1 reg_rdata_next[9:0] = entropy_refresh_threshold_shadowed_qs;
Tests: T1 T2 T3
3059 end
3060
3061 addr_hit[11]: begin
3062 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3063 end
3064
3065 addr_hit[12]: begin
3066 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3067 end
3068
3069 addr_hit[13]: begin
3070 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3071 end
3072
3073 addr_hit[14]: begin
3074 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3075 end
3076
3077 addr_hit[15]: begin
3078 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3079 end
3080
3081 addr_hit[16]: begin
3082 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3083 end
3084
3085 addr_hit[17]: begin
3086 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3087 end
3088
3089 addr_hit[18]: begin
3090 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3091 end
3092
3093 addr_hit[19]: begin
3094 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3095 end
3096
3097 addr_hit[20]: begin
3098 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3099 end
3100
3101 addr_hit[21]: begin
3102 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3103 end
3104
3105 addr_hit[22]: begin
3106 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3107 end
3108
3109 addr_hit[23]: begin
3110 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3111 end
3112
3113 addr_hit[24]: begin
3114 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3115 end
3116
3117 addr_hit[25]: begin
3118 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3119 end
3120
3121 addr_hit[26]: begin
3122 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3123 end
3124
3125 addr_hit[27]: begin
3126 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3127 end
3128
3129 addr_hit[28]: begin
3130 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3131 end
3132
3133 addr_hit[29]: begin
3134 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3135 end
3136
3137 addr_hit[30]: begin
3138 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3139 end
3140
3141 addr_hit[31]: begin
3142 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3143 end
3144
3145 addr_hit[32]: begin
3146 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3147 end
3148
3149 addr_hit[33]: begin
3150 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3151 end
3152
3153 addr_hit[34]: begin
3154 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3155 end
3156
3157 addr_hit[35]: begin
3158 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3159 end
3160
3161 addr_hit[36]: begin
3162 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3163 end
3164
3165 addr_hit[37]: begin
3166 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3167 end
3168
3169 addr_hit[38]: begin
3170 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3171 end
3172
3173 addr_hit[39]: begin
3174 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3175 end
3176
3177 addr_hit[40]: begin
3178 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3179 end
3180
3181 addr_hit[41]: begin
3182 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3183 end
3184
3185 addr_hit[42]: begin
3186 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3187 end
3188
3189 addr_hit[43]: begin
3190 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
3191 end
3192
3193 addr_hit[44]: begin
3194 1/1 reg_rdata_next[2:0] = '0;
Tests: T1 T2 T3
3195 end
3196
3197 addr_hit[45]: begin
3198 1/1 reg_rdata_next[31:0] = prefix_0_qs;
Tests: T1 T2 T3
3199 end
3200
3201 addr_hit[46]: begin
3202 1/1 reg_rdata_next[31:0] = prefix_1_qs;
Tests: T1 T2 T3
3203 end
3204
3205 addr_hit[47]: begin
3206 1/1 reg_rdata_next[31:0] = prefix_2_qs;
Tests: T1 T2 T3
3207 end
3208
3209 addr_hit[48]: begin
3210 1/1 reg_rdata_next[31:0] = prefix_3_qs;
Tests: T1 T2 T3
3211 end
3212
3213 addr_hit[49]: begin
3214 1/1 reg_rdata_next[31:0] = prefix_4_qs;
Tests: T1 T2 T3
3215 end
3216
3217 addr_hit[50]: begin
3218 1/1 reg_rdata_next[31:0] = prefix_5_qs;
Tests: T1 T2 T3
3219 end
3220
3221 addr_hit[51]: begin
3222 1/1 reg_rdata_next[31:0] = prefix_6_qs;
Tests: T1 T2 T3
3223 end
3224
3225 addr_hit[52]: begin
3226 1/1 reg_rdata_next[31:0] = prefix_7_qs;
Tests: T1 T2 T3
3227 end
3228
3229 addr_hit[53]: begin
3230 1/1 reg_rdata_next[31:0] = prefix_8_qs;
Tests: T1 T2 T3
3231 end
3232
3233 addr_hit[54]: begin
3234 1/1 reg_rdata_next[31:0] = prefix_9_qs;
Tests: T1 T2 T3
3235 end
3236
3237 addr_hit[55]: begin
3238 1/1 reg_rdata_next[31:0] = prefix_10_qs;
Tests: T1 T2 T3
3239 end
3240
3241 addr_hit[56]: begin
3242 1/1 reg_rdata_next[31:0] = err_code_qs;
Tests: T1 T2 T3
3243 end
3244
3245 default: begin
3246 reg_rdata_next = '1;
3247 end
3248 endcase
3249 end
3250
3251 // shadow busy
3252 logic shadow_busy;
3253 logic rst_done;
3254 logic shadow_rst_done;
3255 always_ff @(posedge clk_i or negedge rst_ni) begin
3256 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
3257 1/1 rst_done <= '0;
Tests: T1 T2 T3
3258 end else begin
3259 1/1 rst_done <= 1'b1;
Tests: T1 T2 T3
3260 end
3261 end
3262
3263 always_ff @(posedge clk_i or negedge rst_shadowed_ni) begin
3264 1/1 if (!rst_shadowed_ni) begin
Tests: T1 T2 T3
3265 1/1 shadow_rst_done <= '0;
Tests: T1 T2 T3
3266 end else begin
3267 1/1 shadow_rst_done <= 1'b1;
Tests: T1 T2 T3
3268 end
3269 end
3270
3271 // both shadow and normal resets have been released
3272 1/1 assign shadow_busy = ~(rst_done & shadow_rst_done);
Tests: T1 T2 T3
3273
3274 // Collect up storage and update errors
3275 1/1 assign shadowed_storage_err_o = |{
Tests: T1 T2 T3
3276 cfg_shadowed_kmac_en_storage_err,
3277 cfg_shadowed_kstrength_storage_err,
3278 cfg_shadowed_mode_storage_err,
3279 cfg_shadowed_msg_endianness_storage_err,
3280 cfg_shadowed_state_endianness_storage_err,
3281 cfg_shadowed_sideload_storage_err,
3282 cfg_shadowed_entropy_mode_storage_err,
3283 cfg_shadowed_entropy_fast_process_storage_err,
3284 cfg_shadowed_msg_mask_storage_err,
3285 cfg_shadowed_entropy_ready_storage_err,
3286 cfg_shadowed_en_unsupported_modestrength_storage_err,
3287 entropy_refresh_threshold_shadowed_storage_err
3288 };
3289 1/1 assign shadowed_update_err_o = |{
Tests: T1 T2 T3
3290 cfg_shadowed_kmac_en_update_err,
3291 cfg_shadowed_kstrength_update_err,
3292 cfg_shadowed_mode_update_err,
3293 cfg_shadowed_msg_endianness_update_err,
3294 cfg_shadowed_state_endianness_update_err,
3295 cfg_shadowed_sideload_update_err,
3296 cfg_shadowed_entropy_mode_update_err,
3297 cfg_shadowed_entropy_fast_process_update_err,
3298 cfg_shadowed_msg_mask_update_err,
3299 cfg_shadowed_entropy_ready_update_err,
3300 cfg_shadowed_en_unsupported_modestrength_update_err,
3301 entropy_refresh_threshold_shadowed_update_err
3302 };
3303
3304 // register busy
3305 1/1 assign reg_busy = shadow_busy;
Tests: T1 T2 T3
3306
3307 // Unused signal tieoff
3308
3309 // wdata / byte enable are not always fully used
3310 // add a blanket unused statement to handle lint waivers
3311 logic unused_wdata;
3312 logic unused_be;
3313 1/1 assign unused_wdata = ^reg_wdata;
Tests: T1 T2 T3
3314 1/1 assign unused_be = ^reg_be;
Tests: T1 T2 T3