| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 92.37 | 95.89 | 92.30 | 100.00 | 69.42 | 94.11 | 98.84 | 96.01 |
| T767 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3528531114 | Sep 01 09:44:33 PM UTC 24 | Sep 01 09:44:37 PM UTC 24 | 68385991 ps | ||
| T112 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.3848418918 | Sep 01 09:44:32 PM UTC 24 | Sep 01 09:44:38 PM UTC 24 | 60318656 ps | ||
| T768 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.3444581844 | Sep 01 09:44:35 PM UTC 24 | Sep 01 09:44:38 PM UTC 24 | 78543867 ps | ||
| T96 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2712289041 | Sep 01 09:44:34 PM UTC 24 | Sep 01 09:44:38 PM UTC 24 | 259457070 ps | ||
| T769 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.3509565007 | Sep 01 09:44:35 PM UTC 24 | Sep 01 09:44:38 PM UTC 24 | 17509939 ps | ||
| T770 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.1658410756 | Sep 01 09:44:34 PM UTC 24 | Sep 01 09:44:39 PM UTC 24 | 132281409 ps | ||
| T771 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2016467892 | Sep 01 09:44:36 PM UTC 24 | Sep 01 09:44:40 PM UTC 24 | 336303510 ps | ||
| T772 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.1465701030 | Sep 01 09:44:34 PM UTC 24 | Sep 01 09:44:40 PM UTC 24 | 336695235 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.1811160366 | Sep 01 09:44:34 PM UTC 24 | Sep 01 09:44:40 PM UTC 24 | 524993117 ps | ||
| T773 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.642732797 | Sep 01 09:44:36 PM UTC 24 | Sep 01 09:44:40 PM UTC 24 | 258089435 ps | ||
| T774 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1186047055 | Sep 01 09:44:38 PM UTC 24 | Sep 01 09:44:41 PM UTC 24 | 103032945 ps | ||
| T775 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.2759610416 | Sep 01 09:44:38 PM UTC 24 | Sep 01 09:44:41 PM UTC 24 | 49719767 ps | ||
| T776 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.3904108950 | Sep 01 09:44:39 PM UTC 24 | Sep 01 09:44:41 PM UTC 24 | 40531099 ps | ||
| T777 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.2116154848 | Sep 01 09:44:39 PM UTC 24 | Sep 01 09:44:41 PM UTC 24 | 38453313 ps | ||
| T778 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.1732497184 | Sep 01 09:44:38 PM UTC 24 | Sep 01 09:44:42 PM UTC 24 | 117193786 ps | ||
| T779 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.4012344462 | Sep 01 09:44:40 PM UTC 24 | Sep 01 09:44:43 PM UTC 24 | 26635017 ps | ||
| T780 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.3461929697 | Sep 01 09:44:38 PM UTC 24 | Sep 01 09:44:43 PM UTC 24 | 733251888 ps | ||
| T781 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3726659484 | Sep 01 09:44:40 PM UTC 24 | Sep 01 09:44:43 PM UTC 24 | 83123923 ps | ||
| T782 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2400404524 | Sep 01 09:44:39 PM UTC 24 | Sep 01 09:44:44 PM UTC 24 | 167339960 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.1639475525 | Sep 01 09:44:42 PM UTC 24 | Sep 01 09:44:44 PM UTC 24 | 35252258 ps | ||
| T783 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.1009811170 | Sep 01 09:44:39 PM UTC 24 | Sep 01 09:44:44 PM UTC 24 | 106899210 ps | ||
| T784 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.4234267156 | Sep 01 09:44:43 PM UTC 24 | Sep 01 09:44:45 PM UTC 24 | 31901153 ps | ||
| T785 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.591478384 | Sep 01 09:44:43 PM UTC 24 | Sep 01 09:44:45 PM UTC 24 | 215235602 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.276296619 | Sep 01 09:44:41 PM UTC 24 | Sep 01 09:44:46 PM UTC 24 | 227581505 ps | ||
| T786 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2063002442 | Sep 01 09:44:43 PM UTC 24 | Sep 01 09:44:46 PM UTC 24 | 25932970 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.3428534413 | Sep 01 09:44:41 PM UTC 24 | Sep 01 09:44:46 PM UTC 24 | 68030052 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.3534439228 | Sep 01 09:44:44 PM UTC 24 | Sep 01 09:44:46 PM UTC 24 | 83124137 ps | ||
| T787 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.1336575233 | Sep 01 09:44:44 PM UTC 24 | Sep 01 09:44:47 PM UTC 24 | 85642509 ps | ||
| T788 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.1882825 | Sep 01 09:44:43 PM UTC 24 | Sep 01 09:44:48 PM UTC 24 | 47794378 ps | ||
| T789 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1256994340 | Sep 01 09:44:43 PM UTC 24 | Sep 01 09:44:48 PM UTC 24 | 119864391 ps | ||
| T790 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1667091978 | Sep 01 09:44:45 PM UTC 24 | Sep 01 09:44:48 PM UTC 24 | 55405917 ps | ||
| T791 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.3402793395 | Sep 01 09:44:47 PM UTC 24 | Sep 01 09:44:49 PM UTC 24 | 101997672 ps | ||
| T792 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.95297600 | Sep 01 09:44:44 PM UTC 24 | Sep 01 09:44:49 PM UTC 24 | 93251618 ps | ||
| T793 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.2291239536 | Sep 01 09:44:47 PM UTC 24 | Sep 01 09:44:49 PM UTC 24 | 22629503 ps | ||
| T794 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.472183420 | Sep 01 09:44:18 PM UTC 24 | Sep 01 09:44:49 PM UTC 24 | 4638947896 ps | ||
| T795 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.3699579885 | Sep 01 09:44:44 PM UTC 24 | Sep 01 09:44:50 PM UTC 24 | 62441273 ps | ||
| T796 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1404100500 | Sep 01 09:44:45 PM UTC 24 | Sep 01 09:44:50 PM UTC 24 | 32955002 ps | ||
| T797 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.1165856174 | Sep 01 09:44:47 PM UTC 24 | Sep 01 09:44:50 PM UTC 24 | 133510797 ps | ||
| T798 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.1045182066 | Sep 01 09:44:47 PM UTC 24 | Sep 01 09:44:50 PM UTC 24 | 100275631 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.2359229640 | Sep 01 09:44:44 PM UTC 24 | Sep 01 09:44:50 PM UTC 24 | 184546753 ps | ||
| T799 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.453094667 | Sep 01 09:44:47 PM UTC 24 | Sep 01 09:44:51 PM UTC 24 | 90246783 ps | ||
| T800 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1898709446 | Sep 01 09:44:48 PM UTC 24 | Sep 01 09:44:51 PM UTC 24 | 292798581 ps | ||
| T801 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2370469320 | Sep 01 09:44:48 PM UTC 24 | Sep 01 09:44:51 PM UTC 24 | 185974529 ps | ||
| T802 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.682407239 | Sep 01 09:44:48 PM UTC 24 | Sep 01 09:44:51 PM UTC 24 | 89594679 ps | ||
| T803 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.1723667577 | Sep 01 09:44:47 PM UTC 24 | Sep 01 09:44:52 PM UTC 24 | 305732751 ps | ||
| T804 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.1156833544 | Sep 01 09:44:50 PM UTC 24 | Sep 01 09:44:53 PM UTC 24 | 55228092 ps | ||
| T805 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.2323223499 | Sep 01 09:44:50 PM UTC 24 | Sep 01 09:44:53 PM UTC 24 | 90517324 ps | ||
| T806 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.3185114344 | Sep 01 09:44:51 PM UTC 24 | Sep 01 09:44:53 PM UTC 24 | 52514245 ps | ||
| T807 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.1903933482 | Sep 01 09:44:49 PM UTC 24 | Sep 01 09:44:53 PM UTC 24 | 293125323 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.3484762011 | Sep 01 09:44:49 PM UTC 24 | Sep 01 09:44:54 PM UTC 24 | 837198211 ps | ||
| T808 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1773138576 | Sep 01 09:44:51 PM UTC 24 | Sep 01 09:44:54 PM UTC 24 | 160995921 ps | ||
| T809 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.648592036 | Sep 01 09:44:52 PM UTC 24 | Sep 01 09:44:54 PM UTC 24 | 27211472 ps | ||
| T810 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.2795992235 | Sep 01 09:44:52 PM UTC 24 | Sep 01 09:44:54 PM UTC 24 | 19323197 ps | ||
| T811 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3878099011 | Sep 01 09:44:50 PM UTC 24 | Sep 01 09:44:55 PM UTC 24 | 231796495 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.151886747 | Sep 01 09:44:52 PM UTC 24 | Sep 01 09:44:55 PM UTC 24 | 60268167 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.581869550 | Sep 01 09:44:52 PM UTC 24 | Sep 01 09:44:56 PM UTC 24 | 111542958 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.726434984 | Sep 01 09:44:53 PM UTC 24 | Sep 01 09:44:56 PM UTC 24 | 33692004 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.891094174 | Sep 01 09:44:52 PM UTC 24 | Sep 01 09:44:56 PM UTC 24 | 85538867 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.2556339566 | Sep 01 09:44:53 PM UTC 24 | Sep 01 09:44:56 PM UTC 24 | 174926420 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.407564113 | Sep 01 09:44:52 PM UTC 24 | Sep 01 09:44:56 PM UTC 24 | 108891356 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.131990672 | Sep 01 09:44:54 PM UTC 24 | Sep 01 09:44:57 PM UTC 24 | 16096133 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.1777607846 | Sep 01 09:44:53 PM UTC 24 | Sep 01 09:44:57 PM UTC 24 | 47869796 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.169785053 | Sep 01 09:44:55 PM UTC 24 | Sep 01 09:44:57 PM UTC 24 | 122796278 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.896198171 | Sep 01 09:44:52 PM UTC 24 | Sep 01 09:44:57 PM UTC 24 | 1035444686 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.569657334 | Sep 01 09:44:56 PM UTC 24 | Sep 01 09:44:59 PM UTC 24 | 241210684 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.2168029068 | Sep 01 09:44:56 PM UTC 24 | Sep 01 09:44:59 PM UTC 24 | 22439368 ps | ||
| T823 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.3730476790 | Sep 01 09:44:57 PM UTC 24 | Sep 01 09:44:59 PM UTC 24 | 13274036 ps | ||
| T824 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.3168598906 | Sep 01 09:44:55 PM UTC 24 | Sep 01 09:45:00 PM UTC 24 | 322970585 ps | ||
| T825 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.3882453747 | Sep 01 09:44:57 PM UTC 24 | Sep 01 09:45:00 PM UTC 24 | 340590536 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.3499032767 | Sep 01 09:44:56 PM UTC 24 | Sep 01 09:45:00 PM UTC 24 | 171712040 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.3741657136 | Sep 01 09:44:54 PM UTC 24 | Sep 01 09:45:00 PM UTC 24 | 1536224377 ps | ||
| T826 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2975886906 | Sep 01 09:44:57 PM UTC 24 | Sep 01 09:45:01 PM UTC 24 | 800735669 ps | ||
| T827 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2023979339 | Sep 01 09:44:57 PM UTC 24 | Sep 01 09:45:01 PM UTC 24 | 790660968 ps | ||
| T828 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.147517254 | Sep 01 09:44:56 PM UTC 24 | Sep 01 09:45:01 PM UTC 24 | 153296666 ps | ||
| T829 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.1040465823 | Sep 01 09:45:00 PM UTC 24 | Sep 01 09:45:02 PM UTC 24 | 19662575 ps | ||
| T830 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.245286875 | Sep 01 09:44:57 PM UTC 24 | Sep 01 09:45:02 PM UTC 24 | 225216443 ps | ||
| T831 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.1306333760 | Sep 01 09:44:58 PM UTC 24 | Sep 01 09:45:03 PM UTC 24 | 67590741 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.904801968 | Sep 01 09:44:57 PM UTC 24 | Sep 01 09:45:03 PM UTC 24 | 412903475 ps | ||
| T832 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.3460374293 | Sep 01 09:45:01 PM UTC 24 | Sep 01 09:45:04 PM UTC 24 | 109889963 ps | ||
| T833 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.688841698 | Sep 01 09:45:01 PM UTC 24 | Sep 01 09:45:04 PM UTC 24 | 102015170 ps | ||
| T834 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1523116616 | Sep 01 09:44:58 PM UTC 24 | Sep 01 09:45:04 PM UTC 24 | 340256974 ps | ||
| T835 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.3289712858 | Sep 01 09:45:02 PM UTC 24 | Sep 01 09:45:04 PM UTC 24 | 14703875 ps | ||
| T836 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1911075624 | Sep 01 09:45:01 PM UTC 24 | Sep 01 09:45:05 PM UTC 24 | 1069695212 ps | ||
| T837 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.693214134 | Sep 01 09:45:02 PM UTC 24 | Sep 01 09:45:05 PM UTC 24 | 31221569 ps | ||
| T838 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.1637918397 | Sep 01 09:45:01 PM UTC 24 | Sep 01 09:45:05 PM UTC 24 | 46952299 ps | ||
| T839 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3560377241 | Sep 01 09:45:01 PM UTC 24 | Sep 01 09:45:05 PM UTC 24 | 666339367 ps | ||
| T840 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.4247618839 | Sep 01 09:45:01 PM UTC 24 | Sep 01 09:45:06 PM UTC 24 | 173749722 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.1682109335 | Sep 01 09:44:59 PM UTC 24 | Sep 01 09:45:06 PM UTC 24 | 265859439 ps | ||
| T841 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3372306695 | Sep 01 09:45:03 PM UTC 24 | Sep 01 09:45:07 PM UTC 24 | 54024528 ps | ||
| T842 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.1443424836 | Sep 01 09:45:03 PM UTC 24 | Sep 01 09:45:07 PM UTC 24 | 127487666 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.1536436291 | Sep 01 09:45:05 PM UTC 24 | Sep 01 09:45:07 PM UTC 24 | 17722441 ps | ||
| T843 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.506425489 | Sep 01 09:45:03 PM UTC 24 | Sep 01 09:45:08 PM UTC 24 | 138256845 ps | ||
| T844 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.769643323 | Sep 01 09:45:06 PM UTC 24 | Sep 01 09:45:08 PM UTC 24 | 26603906 ps | ||
| T845 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.3519084231 | Sep 01 09:45:06 PM UTC 24 | Sep 01 09:45:08 PM UTC 24 | 11491958 ps | ||
| T846 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.1790968793 | Sep 01 09:45:05 PM UTC 24 | Sep 01 09:45:09 PM UTC 24 | 132717185 ps | ||
| T847 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.1782592839 | Sep 01 09:45:06 PM UTC 24 | Sep 01 09:45:09 PM UTC 24 | 38511845 ps | ||
| T848 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.1277306300 | Sep 01 09:45:04 PM UTC 24 | Sep 01 09:45:09 PM UTC 24 | 373735480 ps | ||
| T849 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.421270986 | Sep 01 09:45:06 PM UTC 24 | Sep 01 09:45:09 PM UTC 24 | 40020337 ps | ||
| T850 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.2299893605 | Sep 01 09:45:06 PM UTC 24 | Sep 01 09:45:09 PM UTC 24 | 199364601 ps | ||
| T851 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.1310279861 | Sep 01 09:45:07 PM UTC 24 | Sep 01 09:45:09 PM UTC 24 | 25612888 ps | ||
| T852 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.2560464818 | Sep 01 09:45:07 PM UTC 24 | Sep 01 09:45:10 PM UTC 24 | 13597646 ps | ||
| T853 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.1579075567 | Sep 01 09:45:07 PM UTC 24 | Sep 01 09:45:10 PM UTC 24 | 26913021 ps | ||
| T854 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.3370951357 | Sep 01 09:45:07 PM UTC 24 | Sep 01 09:45:10 PM UTC 24 | 13298309 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.3968793636 | Sep 01 09:45:05 PM UTC 24 | Sep 01 09:45:10 PM UTC 24 | 125594728 ps | ||
| T855 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.2334886775 | Sep 01 09:45:09 PM UTC 24 | Sep 01 09:45:11 PM UTC 24 | 40424111 ps | ||
| T856 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.2713811352 | Sep 01 09:45:08 PM UTC 24 | Sep 01 09:45:11 PM UTC 24 | 16429744 ps | ||
| T857 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.1784504372 | Sep 01 09:45:02 PM UTC 24 | Sep 01 09:45:11 PM UTC 24 | 831220474 ps | ||
| T858 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.2591815978 | Sep 01 09:45:10 PM UTC 24 | Sep 01 09:45:12 PM UTC 24 | 27630646 ps | ||
| T859 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.2630813338 | Sep 01 09:45:10 PM UTC 24 | Sep 01 09:45:12 PM UTC 24 | 12981384 ps | ||
| T860 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.2739385279 | Sep 01 09:45:10 PM UTC 24 | Sep 01 09:45:12 PM UTC 24 | 41272709 ps | ||
| T861 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.2217326929 | Sep 01 09:45:10 PM UTC 24 | Sep 01 09:45:12 PM UTC 24 | 70874922 ps | ||
| T862 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.1851267403 | Sep 01 09:45:10 PM UTC 24 | Sep 01 09:45:12 PM UTC 24 | 17138012 ps | ||
| T863 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.3380536906 | Sep 01 09:45:10 PM UTC 24 | Sep 01 09:45:12 PM UTC 24 | 18745231 ps | ||
| T864 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.3979807402 | Sep 01 09:45:10 PM UTC 24 | Sep 01 09:45:12 PM UTC 24 | 23969634 ps | ||
| T865 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.878685037 | Sep 01 09:45:11 PM UTC 24 | Sep 01 09:45:14 PM UTC 24 | 43185846 ps | ||
| T866 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.2649034579 | Sep 01 09:45:11 PM UTC 24 | Sep 01 09:45:14 PM UTC 24 | 40695533 ps | ||
| T867 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.4119484278 | Sep 01 09:45:11 PM UTC 24 | Sep 01 09:45:14 PM UTC 24 | 53045765 ps | ||
| T868 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.542684967 | Sep 01 09:45:12 PM UTC 24 | Sep 01 09:45:14 PM UTC 24 | 11069623 ps | ||
| T869 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.4272548746 | Sep 01 09:45:11 PM UTC 24 | Sep 01 09:45:14 PM UTC 24 | 15374127 ps | ||
| T870 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.1584327614 | Sep 01 09:45:12 PM UTC 24 | Sep 01 09:45:14 PM UTC 24 | 24969982 ps | ||
| T871 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.2007439272 | Sep 01 09:45:12 PM UTC 24 | Sep 01 09:45:14 PM UTC 24 | 29460515 ps | ||
| T872 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.3084804944 | Sep 01 09:45:12 PM UTC 24 | Sep 01 09:45:14 PM UTC 24 | 40370769 ps | ||
| T873 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.3025714329 | Sep 01 09:45:12 PM UTC 24 | Sep 01 09:45:14 PM UTC 24 | 31074589 ps | ||
| T874 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.821324289 | Sep 01 09:45:13 PM UTC 24 | Sep 01 09:45:15 PM UTC 24 | 18605227 ps | ||
| T875 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.1548441689 | Sep 01 09:45:13 PM UTC 24 | Sep 01 09:45:15 PM UTC 24 | 41065433 ps | ||
| T876 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.3000749855 | Sep 01 09:45:13 PM UTC 24 | Sep 01 09:45:15 PM UTC 24 | 110134536 ps | ||
| T877 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.2765925592 | Sep 01 09:45:13 PM UTC 24 | Sep 01 09:45:15 PM UTC 24 | 25823896 ps | ||
| T878 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.26310312 | Sep 01 09:45:13 PM UTC 24 | Sep 01 09:45:16 PM UTC 24 | 27844752 ps | ||
| T879 | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.3752122885 | Sep 01 09:45:13 PM UTC 24 | Sep 01 09:45:16 PM UTC 24 | 69186999 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/1.kmac_smoke.4280078331 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 1496298708 ps |
| CPU time | 21.37 seconds |
| Started | Sep 01 08:48:25 PM UTC 24 |
| Finished | Sep 01 08:48:48 PM UTC 24 |
| Peak memory | 230528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280078331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.4280078331 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/0.kmac_app_with_partial_data.2567894660 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 18820795582 ps |
| CPU time | 89.86 seconds |
| Started | Sep 01 08:48:22 PM UTC 24 |
| Finished | Sep 01 08:49:54 PM UTC 24 |
| Peak memory | 264176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567894660 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.2567894660 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/0.kmac_sec_cm.2918752675 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 18633466849 ps |
| CPU time | 75.72 seconds |
| Started | Sep 01 08:48:22 PM UTC 24 |
| Finished | Sep 01 08:49:41 PM UTC 24 |
| Peak memory | 289688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918752675 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.2918752675 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_intg_err.2905832850 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 80472488 ps |
| CPU time | 3.67 seconds |
| Started | Sep 01 09:43:38 PM UTC 24 |
| Finished | Sep 01 09:43:42 PM UTC 24 |
| Peak memory | 231488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905832850 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.2905832850 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/2.kmac_stress_all_with_rand_reset.2818620308 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 10812146251 ps |
| CPU time | 109.22 seconds |
| Started | Sep 01 08:50:18 PM UTC 24 |
| Finished | Sep 01 08:52:10 PM UTC 24 |
| Peak memory | 288672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2818620308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all_ with_rand_reset.2818620308 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/1.kmac_key_error.1793932122 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 8709862990 ps |
| CPU time | 14.48 seconds |
| Started | Sep 01 08:48:48 PM UTC 24 |
| Finished | Sep 01 08:49:04 PM UTC 24 |
| Peak memory | 230600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793932122 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.1793932122 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/3.kmac_lc_escalation.3591296561 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 89007877 ps |
| CPU time | 2.22 seconds |
| Started | Sep 01 08:51:57 PM UTC 24 |
| Finished | Sep 01 08:52:00 PM UTC 24 |
| Peak memory | 232508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591296561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.3591296561 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/0.kmac_error.1250963927 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 3966936970 ps |
| CPU time | 332.49 seconds |
| Started | Sep 01 08:48:22 PM UTC 24 |
| Finished | Sep 01 08:54:00 PM UTC 24 |
| Peak memory | 374528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250963927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.1250963927 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.3240209372 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 752301320 ps |
| CPU time | 3.82 seconds |
| Started | Sep 01 09:44:14 PM UTC 24 |
| Finished | Sep 01 09:44:19 PM UTC 24 |
| Peak memory | 229800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240209372 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors_with_csr_rw. 3240209372 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/1.kmac_stress_all.1592907190 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 5816482183 ps |
| CPU time | 233.43 seconds |
| Started | Sep 01 08:49:07 PM UTC 24 |
| Finished | Sep 01 08:53:05 PM UTC 24 |
| Peak memory | 299012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592907190 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.1592907190 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/1.kmac_lc_escalation.3209537031 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 66327900 ps |
| CPU time | 1.98 seconds |
| Started | Sep 01 08:49:05 PM UTC 24 |
| Finished | Sep 01 08:49:08 PM UTC 24 |
| Peak memory | 234480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209537031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.3209537031 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/38.kmac_lc_escalation.1077672488 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 3178015261 ps |
| CPU time | 22.02 seconds |
| Started | Sep 01 09:29:38 PM UTC 24 |
| Finished | Sep 01 09:30:01 PM UTC 24 |
| Peak memory | 247664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077672488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.1077672488 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/38.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_intr_test.535740170 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 16838492 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 09:44:00 PM UTC 24 |
| Finished | Sep 01 09:44:02 PM UTC 24 |
| Peak memory | 219000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535740170 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.535740170 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/0.kmac_app.1232886209 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 622532556 ps |
| CPU time | 28.82 seconds |
| Started | Sep 01 08:48:22 PM UTC 24 |
| Finished | Sep 01 08:48:52 PM UTC 24 |
| Peak memory | 239404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232886209 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.1232886209 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/10.kmac_lc_escalation.1019572743 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 27668013 ps |
| CPU time | 1.78 seconds |
| Started | Sep 01 08:59:11 PM UTC 24 |
| Finished | Sep 01 08:59:14 PM UTC 24 |
| Peak memory | 231720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019572743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.1019572743 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/10.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/9.kmac_lc_escalation.270190178 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 50452187 ps |
| CPU time | 1.9 seconds |
| Started | Sep 01 08:58:26 PM UTC 24 |
| Finished | Sep 01 08:58:29 PM UTC 24 |
| Peak memory | 231848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270190178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.270190178 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/9.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors.1282926321 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 49754459 ps |
| CPU time | 1.67 seconds |
| Started | Sep 01 09:44:14 PM UTC 24 |
| Finished | Sep 01 09:44:17 PM UTC 24 |
| Peak memory | 228736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282926321 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors.1282926321 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_partial_access.4191956927 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 102138412 ps |
| CPU time | 1.78 seconds |
| Started | Sep 01 09:43:57 PM UTC 24 |
| Finished | Sep 01 09:44:00 PM UTC 24 |
| Peak memory | 228872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191956927 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial_access.4191956927 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/0.kmac_alert_test.1771555443 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 234622161 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 08:48:22 PM UTC 24 |
| Finished | Sep 01 08:48:25 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771555443 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.1771555443 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.3741657136 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 1536224377 ps |
| CPU time | 4.78 seconds |
| Started | Sep 01 09:44:54 PM UTC 24 |
| Finished | Sep 01 09:45:00 PM UTC 24 |
| Peak memory | 229480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741657136 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.3741657136 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/15.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_128.637983536 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 6673466786 ps |
| CPU time | 232.14 seconds |
| Started | Sep 01 08:48:20 PM UTC 24 |
| Finished | Sep 01 08:52:16 PM UTC 24 |
| Peak memory | 442156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637983536 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.63798353 6 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.1639475525 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 35252258 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 09:44:42 PM UTC 24 |
| Finished | Sep 01 09:44:44 PM UTC 24 |
| Peak memory | 219056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639475525 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.1639475525 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/10.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.4162341514 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 1153440050 ps |
| CPU time | 6.59 seconds |
| Started | Sep 01 09:44:18 PM UTC 24 |
| Finished | Sep 01 09:44:26 PM UTC 24 |
| Peak memory | 219068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162341514 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.4162341514 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_256.3563442260 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 23088005468 ps |
| CPU time | 444.22 seconds |
| Started | Sep 01 08:48:20 PM UTC 24 |
| Finished | Sep 01 08:55:50 PM UTC 24 |
| Peak memory | 360092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563442260 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.3563442 260 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.147517254 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 153296666 ps |
| CPU time | 4.19 seconds |
| Started | Sep 01 09:44:56 PM UTC 24 |
| Finished | Sep 01 09:45:01 PM UTC 24 |
| Peak memory | 230060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147517254 -asse rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors_with_csr_rw. 147517254 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_ready_error.3792169222 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 6022452135 ps |
| CPU time | 86.68 seconds |
| Started | Sep 01 08:54:44 PM UTC 24 |
| Finished | Sep 01 08:56:13 PM UTC 24 |
| Peak memory | 230592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792169222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.3792169222 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/5.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/1.kmac_error.356263182 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 6474166758 ps |
| CPU time | 281.78 seconds |
| Started | Sep 01 08:48:48 PM UTC 24 |
| Finished | Sep 01 08:53:35 PM UTC 24 |
| Peak memory | 342060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356263182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.356263182 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/5.kmac_stress_all.1332500527 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 45885893825 ps |
| CPU time | 376.25 seconds |
| Started | Sep 01 08:54:52 PM UTC 24 |
| Finished | Sep 01 09:01:15 PM UTC 24 |
| Peak memory | 376824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332500527 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.1332500527 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/5.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/30.kmac_stress_all.2528923666 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 3276488126 ps |
| CPU time | 280.38 seconds |
| Started | Sep 01 09:20:56 PM UTC 24 |
| Finished | Sep 01 09:25:41 PM UTC 24 |
| Peak memory | 270660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528923666 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.2528923666 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/30.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.2359229640 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 184546753 ps |
| CPU time | 5.03 seconds |
| Started | Sep 01 09:44:44 PM UTC 24 |
| Finished | Sep 01 09:44:50 PM UTC 24 |
| Peak memory | 219220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359229640 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.2359229640 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/11.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.131990672 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 16096133 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 09:44:54 PM UTC 24 |
| Finished | Sep 01 09:44:57 PM UTC 24 |
| Peak memory | 218936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131990672 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.131990672 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/15.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3278513152 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 77403661 ps |
| CPU time | 1.79 seconds |
| Started | Sep 01 09:43:34 PM UTC 24 |
| Finished | Sep 01 09:43:37 PM UTC 24 |
| Peak memory | 228736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278513152 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors.3278513152 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_refresh.3811933332 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 26933026044 ps |
| CPU time | 168.23 seconds |
| Started | Sep 01 08:48:22 PM UTC 24 |
| Finished | Sep 01 08:51:13 PM UTC 24 |
| Peak memory | 292644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811933332 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.3811933332 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/31.kmac_error.56030000 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 2743908199 ps |
| CPU time | 95.17 seconds |
| Started | Sep 01 09:21:52 PM UTC 24 |
| Finished | Sep 01 09:23:30 PM UTC 24 |
| Peak memory | 284520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56030000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.56030000 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/31.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_aliasing.4147258088 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 5415867517 ps |
| CPU time | 16.95 seconds |
| Started | Sep 01 09:43:42 PM UTC 24 |
| Finished | Sep 01 09:44:00 PM UTC 24 |
| Peak memory | 229576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147258088 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.4147258088 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.3698549267 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 3445588657 ps |
| CPU time | 27.93 seconds |
| Started | Sep 01 09:43:41 PM UTC 24 |
| Finished | Sep 01 09:44:10 PM UTC 24 |
| Peak memory | 219336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698549267 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.3698549267 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_hw_reset.2466058904 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 98878653 ps |
| CPU time | 1.66 seconds |
| Started | Sep 01 09:43:39 PM UTC 24 |
| Finished | Sep 01 09:43:41 PM UTC 24 |
| Peak memory | 219012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466058904 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.2466058904 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.57370557 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 86674897 ps |
| CPU time | 1.68 seconds |
| Started | Sep 01 09:43:42 PM UTC 24 |
| Finished | Sep 01 09:43:45 PM UTC 24 |
| Peak memory | 228876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=57370557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_me m_rw_with_rand_reset.57370557 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_rw.2217916571 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 102677667 ps |
| CPU time | 1.45 seconds |
| Started | Sep 01 09:43:39 PM UTC 24 |
| Finished | Sep 01 09:43:41 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217916571 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.2217916571 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_intr_test.2219487374 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 80282767 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 09:43:38 PM UTC 24 |
| Finished | Sep 01 09:43:40 PM UTC 24 |
| Peak memory | 218992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219487374 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.2219487374 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_partial_access.3038667208 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 289618352 ps |
| CPU time | 1.87 seconds |
| Started | Sep 01 09:43:35 PM UTC 24 |
| Finished | Sep 01 09:43:38 PM UTC 24 |
| Peak memory | 228868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038667208 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial_access.3038667208 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_walk.1412539799 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 16282052 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 09:43:34 PM UTC 24 |
| Finished | Sep 01 09:43:36 PM UTC 24 |
| Peak memory | 218600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412539799 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.1412539799 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_same_csr_outstanding.2238304487 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 1009118189 ps |
| CPU time | 3.73 seconds |
| Started | Sep 01 09:43:42 PM UTC 24 |
| Finished | Sep 01 09:43:47 PM UTC 24 |
| Peak memory | 229456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238304487 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_outstanding.2238304487 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.4261421158 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 40376412 ps |
| CPU time | 2.37 seconds |
| Started | Sep 01 09:43:34 PM UTC 24 |
| Finished | Sep 01 09:43:38 PM UTC 24 |
| Peak memory | 229860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261421158 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors_with_csr_rw. 4261421158 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_errors.463053127 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 55732069 ps |
| CPU time | 3.47 seconds |
| Started | Sep 01 09:43:36 PM UTC 24 |
| Finished | Sep 01 09:43:41 PM UTC 24 |
| Peak memory | 229520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463053127 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.463053127 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_aliasing.2077527086 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 143621495 ps |
| CPU time | 9.38 seconds |
| Started | Sep 01 09:43:51 PM UTC 24 |
| Finished | Sep 01 09:44:01 PM UTC 24 |
| Peak memory | 219272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077527086 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.2077527086 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.2780677163 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 5979539359 ps |
| CPU time | 24.6 seconds |
| Started | Sep 01 09:43:51 PM UTC 24 |
| Finished | Sep 01 09:44:17 PM UTC 24 |
| Peak memory | 219208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780677163 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.2780677163 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_hw_reset.2170081961 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 42263242 ps |
| CPU time | 1.46 seconds |
| Started | Sep 01 09:43:49 PM UTC 24 |
| Finished | Sep 01 09:43:51 PM UTC 24 |
| Peak memory | 219052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170081961 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.2170081961 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.572486336 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 68981027 ps |
| CPU time | 3.57 seconds |
| Started | Sep 01 09:43:52 PM UTC 24 |
| Finished | Sep 01 09:43:57 PM UTC 24 |
| Peak memory | 231504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=572486336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_m em_rw_with_rand_reset.572486336 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_rw.440599354 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 28587276 ps |
| CPU time | 1.61 seconds |
| Started | Sep 01 09:43:50 PM UTC 24 |
| Finished | Sep 01 09:43:52 PM UTC 24 |
| Peak memory | 228932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440599354 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.440599354 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_intr_test.1210579997 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 23587180 ps |
| CPU time | 0.97 seconds |
| Started | Sep 01 09:43:48 PM UTC 24 |
| Finished | Sep 01 09:43:50 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210579997 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.1210579997 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_partial_access.2448400792 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 133385194 ps |
| CPU time | 2.28 seconds |
| Started | Sep 01 09:43:45 PM UTC 24 |
| Finished | Sep 01 09:43:49 PM UTC 24 |
| Peak memory | 229452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448400792 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial_access.2448400792 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_walk.4214619664 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 34291495 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 09:43:44 PM UTC 24 |
| Finished | Sep 01 09:43:46 PM UTC 24 |
| Peak memory | 218992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214619664 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.4214619664 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_same_csr_outstanding.4270809591 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 342634338 ps |
| CPU time | 3.18 seconds |
| Started | Sep 01 09:43:52 PM UTC 24 |
| Finished | Sep 01 09:43:56 PM UTC 24 |
| Peak memory | 229456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270809591 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_outstanding.4270809591 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors.977471914 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 66659126 ps |
| CPU time | 1.59 seconds |
| Started | Sep 01 09:43:42 PM UTC 24 |
| Finished | Sep 01 09:43:45 PM UTC 24 |
| Peak memory | 228676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977471914 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors.977471914 +enable_masking =0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.2691713927 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 606473665 ps |
| CPU time | 3.01 seconds |
| Started | Sep 01 09:43:43 PM UTC 24 |
| Finished | Sep 01 09:43:47 PM UTC 24 |
| Peak memory | 229860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691713927 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors_with_csr_rw. 2691713927 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_errors.3139240764 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 52763975 ps |
| CPU time | 4.18 seconds |
| Started | Sep 01 09:43:45 PM UTC 24 |
| Finished | Sep 01 09:43:51 PM UTC 24 |
| Peak memory | 229576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139240764 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.3139240764 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_intg_err.3540667615 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 190626958 ps |
| CPU time | 6.95 seconds |
| Started | Sep 01 09:43:48 PM UTC 24 |
| Finished | Sep 01 09:43:56 PM UTC 24 |
| Peak memory | 229440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540667615 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.3540667615 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2063002442 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 25932970 ps |
| CPU time | 1.97 seconds |
| Started | Sep 01 09:44:43 PM UTC 24 |
| Finished | Sep 01 09:44:46 PM UTC 24 |
| Peak memory | 228876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2063002442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr _mem_rw_with_rand_reset.2063002442 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/10.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.4234267156 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 31901153 ps |
| CPU time | 1.65 seconds |
| Started | Sep 01 09:44:43 PM UTC 24 |
| Finished | Sep 01 09:44:45 PM UTC 24 |
| Peak memory | 218956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234267156 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.4234267156 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/10.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1256994340 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 119864391 ps |
| CPU time | 3.9 seconds |
| Started | Sep 01 09:44:43 PM UTC 24 |
| Finished | Sep 01 09:44:48 PM UTC 24 |
| Peak memory | 229576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256994340 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr_outstanding.1256994340 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/10.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.4012344462 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 26635017 ps |
| CPU time | 1.64 seconds |
| Started | Sep 01 09:44:40 PM UTC 24 |
| Finished | Sep 01 09:44:43 PM UTC 24 |
| Peak memory | 228808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012344462 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors.4012344462 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3726659484 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 83123923 ps |
| CPU time | 2.01 seconds |
| Started | Sep 01 09:44:40 PM UTC 24 |
| Finished | Sep 01 09:44:43 PM UTC 24 |
| Peak memory | 228804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726659484 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors_with_csr_rw .3726659484 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.3428534413 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 68030052 ps |
| CPU time | 3.39 seconds |
| Started | Sep 01 09:44:41 PM UTC 24 |
| Finished | Sep 01 09:44:46 PM UTC 24 |
| Peak memory | 229684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428534413 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.3428534413 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/10.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.276296619 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 227581505 ps |
| CPU time | 3.12 seconds |
| Started | Sep 01 09:44:41 PM UTC 24 |
| Finished | Sep 01 09:44:46 PM UTC 24 |
| Peak memory | 229520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276296619 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.276296619 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/10.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1404100500 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 32955002 ps |
| CPU time | 3.42 seconds |
| Started | Sep 01 09:44:45 PM UTC 24 |
| Finished | Sep 01 09:44:50 PM UTC 24 |
| Peak memory | 231544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1404100500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr _mem_rw_with_rand_reset.1404100500 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/11.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.1336575233 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 85642509 ps |
| CPU time | 1.73 seconds |
| Started | Sep 01 09:44:44 PM UTC 24 |
| Finished | Sep 01 09:44:47 PM UTC 24 |
| Peak memory | 218896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336575233 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.1336575233 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/11.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.3534439228 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 83124137 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 09:44:44 PM UTC 24 |
| Finished | Sep 01 09:44:46 PM UTC 24 |
| Peak memory | 219056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534439228 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.3534439228 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/11.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.95297600 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 93251618 ps |
| CPU time | 3.66 seconds |
| Started | Sep 01 09:44:44 PM UTC 24 |
| Finished | Sep 01 09:44:49 PM UTC 24 |
| Peak memory | 229580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95297600 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr_outstanding.95297600 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/11.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.591478384 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 215235602 ps |
| CPU time | 1.57 seconds |
| Started | Sep 01 09:44:43 PM UTC 24 |
| Finished | Sep 01 09:44:45 PM UTC 24 |
| Peak memory | 218564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591478384 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors.591478384 +enable_maskin g=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/11.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.1882825 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 47794378 ps |
| CPU time | 3.64 seconds |
| Started | Sep 01 09:44:43 PM UTC 24 |
| Finished | Sep 01 09:44:48 PM UTC 24 |
| Peak memory | 236980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors_with_csr_rw.18 82825 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.3699579885 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 62441273 ps |
| CPU time | 4.79 seconds |
| Started | Sep 01 09:44:44 PM UTC 24 |
| Finished | Sep 01 09:44:50 PM UTC 24 |
| Peak memory | 229580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699579885 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.3699579885 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/11.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2370469320 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 185974529 ps |
| CPU time | 2.08 seconds |
| Started | Sep 01 09:44:48 PM UTC 24 |
| Finished | Sep 01 09:44:51 PM UTC 24 |
| Peak memory | 229460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2370469320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr _mem_rw_with_rand_reset.2370469320 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/12.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.2291239536 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 22629503 ps |
| CPU time | 1.44 seconds |
| Started | Sep 01 09:44:47 PM UTC 24 |
| Finished | Sep 01 09:44:49 PM UTC 24 |
| Peak memory | 218940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291239536 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.2291239536 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/12.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.3402793395 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 101997672 ps |
| CPU time | 1.01 seconds |
| Started | Sep 01 09:44:47 PM UTC 24 |
| Finished | Sep 01 09:44:49 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402793395 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.3402793395 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/12.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.1045182066 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 100275631 ps |
| CPU time | 2.27 seconds |
| Started | Sep 01 09:44:47 PM UTC 24 |
| Finished | Sep 01 09:44:50 PM UTC 24 |
| Peak memory | 229576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045182066 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr_outstanding.1045182066 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/12.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1667091978 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 55405917 ps |
| CPU time | 2.05 seconds |
| Started | Sep 01 09:44:45 PM UTC 24 |
| Finished | Sep 01 09:44:48 PM UTC 24 |
| Peak memory | 229808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667091978 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors.1667091978 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/12.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.1165856174 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 133510797 ps |
| CPU time | 2.43 seconds |
| Started | Sep 01 09:44:47 PM UTC 24 |
| Finished | Sep 01 09:44:50 PM UTC 24 |
| Peak memory | 229888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165856174 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors_with_csr_rw .1165856174 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.453094667 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 90246783 ps |
| CPU time | 3.04 seconds |
| Started | Sep 01 09:44:47 PM UTC 24 |
| Finished | Sep 01 09:44:51 PM UTC 24 |
| Peak memory | 229752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453094667 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.453094667 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/12.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.1723667577 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 305732751 ps |
| CPU time | 4.28 seconds |
| Started | Sep 01 09:44:47 PM UTC 24 |
| Finished | Sep 01 09:44:52 PM UTC 24 |
| Peak memory | 229460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723667577 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.1723667577 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/12.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1773138576 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 160995921 ps |
| CPU time | 2.42 seconds |
| Started | Sep 01 09:44:51 PM UTC 24 |
| Finished | Sep 01 09:44:54 PM UTC 24 |
| Peak memory | 229588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1773138576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr _mem_rw_with_rand_reset.1773138576 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/13.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.2323223499 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 90517324 ps |
| CPU time | 1.39 seconds |
| Started | Sep 01 09:44:50 PM UTC 24 |
| Finished | Sep 01 09:44:53 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323223499 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.2323223499 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/13.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.1156833544 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 55228092 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 09:44:50 PM UTC 24 |
| Finished | Sep 01 09:44:53 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156833544 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.1156833544 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/13.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3878099011 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 231796495 ps |
| CPU time | 3.7 seconds |
| Started | Sep 01 09:44:50 PM UTC 24 |
| Finished | Sep 01 09:44:55 PM UTC 24 |
| Peak memory | 229448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878099011 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr_outstanding.3878099011 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/13.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1898709446 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 292798581 ps |
| CPU time | 1.94 seconds |
| Started | Sep 01 09:44:48 PM UTC 24 |
| Finished | Sep 01 09:44:51 PM UTC 24 |
| Peak memory | 228808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898709446 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors.1898709446 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/13.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.682407239 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 89594679 ps |
| CPU time | 2.31 seconds |
| Started | Sep 01 09:44:48 PM UTC 24 |
| Finished | Sep 01 09:44:51 PM UTC 24 |
| Peak memory | 229472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682407239 -asse rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors_with_csr_rw. 682407239 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.1903933482 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 293125323 ps |
| CPU time | 3.21 seconds |
| Started | Sep 01 09:44:49 PM UTC 24 |
| Finished | Sep 01 09:44:53 PM UTC 24 |
| Peak memory | 229648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903933482 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.1903933482 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/13.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.3484762011 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 837198211 ps |
| CPU time | 3.28 seconds |
| Started | Sep 01 09:44:49 PM UTC 24 |
| Finished | Sep 01 09:44:54 PM UTC 24 |
| Peak memory | 229464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484762011 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.3484762011 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/13.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.891094174 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 85538867 ps |
| CPU time | 2.86 seconds |
| Started | Sep 01 09:44:52 PM UTC 24 |
| Finished | Sep 01 09:44:56 PM UTC 24 |
| Peak memory | 231500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=891094174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_ mem_rw_with_rand_reset.891094174 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/14.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.2795992235 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 19323197 ps |
| CPU time | 1.3 seconds |
| Started | Sep 01 09:44:52 PM UTC 24 |
| Finished | Sep 01 09:44:54 PM UTC 24 |
| Peak memory | 218908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795992235 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.2795992235 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/14.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.648592036 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 27211472 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 09:44:52 PM UTC 24 |
| Finished | Sep 01 09:44:54 PM UTC 24 |
| Peak memory | 218936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648592036 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.648592036 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/14.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.151886747 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 60268167 ps |
| CPU time | 2.3 seconds |
| Started | Sep 01 09:44:52 PM UTC 24 |
| Finished | Sep 01 09:44:55 PM UTC 24 |
| Peak memory | 229424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151886747 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr_outstanding.151886747 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/14.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.3185114344 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 52514245 ps |
| CPU time | 1.75 seconds |
| Started | Sep 01 09:44:51 PM UTC 24 |
| Finished | Sep 01 09:44:53 PM UTC 24 |
| Peak memory | 228748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185114344 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors.3185114344 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/14.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.407564113 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 108891356 ps |
| CPU time | 3.54 seconds |
| Started | Sep 01 09:44:52 PM UTC 24 |
| Finished | Sep 01 09:44:56 PM UTC 24 |
| Peak memory | 229884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407564113 -asse rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors_with_csr_rw. 407564113 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/14.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.581869550 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 111542958 ps |
| CPU time | 2.85 seconds |
| Started | Sep 01 09:44:52 PM UTC 24 |
| Finished | Sep 01 09:44:56 PM UTC 24 |
| Peak memory | 229656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581869550 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.581869550 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/14.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.896198171 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 1035444686 ps |
| CPU time | 4.31 seconds |
| Started | Sep 01 09:44:52 PM UTC 24 |
| Finished | Sep 01 09:44:57 PM UTC 24 |
| Peak memory | 229392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896198171 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.896198171 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/14.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.2168029068 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 22439368 ps |
| CPU time | 2.51 seconds |
| Started | Sep 01 09:44:56 PM UTC 24 |
| Finished | Sep 01 09:44:59 PM UTC 24 |
| Peak memory | 229460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2168029068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr _mem_rw_with_rand_reset.2168029068 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/15.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.169785053 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 122796278 ps |
| CPU time | 1.35 seconds |
| Started | Sep 01 09:44:55 PM UTC 24 |
| Finished | Sep 01 09:44:57 PM UTC 24 |
| Peak memory | 218948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169785053 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.169785053 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/15.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.3168598906 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 322970585 ps |
| CPU time | 3.96 seconds |
| Started | Sep 01 09:44:55 PM UTC 24 |
| Finished | Sep 01 09:45:00 PM UTC 24 |
| Peak memory | 229576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168598906 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr_outstanding.3168598906 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/15.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.726434984 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 33692004 ps |
| CPU time | 1.7 seconds |
| Started | Sep 01 09:44:53 PM UTC 24 |
| Finished | Sep 01 09:44:56 PM UTC 24 |
| Peak memory | 228804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726434984 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors.726434984 +enable_maskin g=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/15.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.1777607846 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 47869796 ps |
| CPU time | 2.43 seconds |
| Started | Sep 01 09:44:53 PM UTC 24 |
| Finished | Sep 01 09:44:57 PM UTC 24 |
| Peak memory | 229684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777607846 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors_with_csr_rw .1777607846 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.2556339566 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 174926420 ps |
| CPU time | 1.86 seconds |
| Started | Sep 01 09:44:53 PM UTC 24 |
| Finished | Sep 01 09:44:56 PM UTC 24 |
| Peak memory | 228932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556339566 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.2556339566 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/15.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2975886906 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 800735669 ps |
| CPU time | 2.39 seconds |
| Started | Sep 01 09:44:57 PM UTC 24 |
| Finished | Sep 01 09:45:01 PM UTC 24 |
| Peak memory | 229460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2975886906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr _mem_rw_with_rand_reset.2975886906 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/16.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.3882453747 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 340590536 ps |
| CPU time | 1.97 seconds |
| Started | Sep 01 09:44:57 PM UTC 24 |
| Finished | Sep 01 09:45:00 PM UTC 24 |
| Peak memory | 218952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882453747 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.3882453747 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/16.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.3730476790 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 13274036 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 09:44:57 PM UTC 24 |
| Finished | Sep 01 09:44:59 PM UTC 24 |
| Peak memory | 219056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730476790 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.3730476790 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/16.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.245286875 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 225216443 ps |
| CPU time | 4.01 seconds |
| Started | Sep 01 09:44:57 PM UTC 24 |
| Finished | Sep 01 09:45:02 PM UTC 24 |
| Peak memory | 229388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245286875 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr_outstanding.245286875 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/16.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.569657334 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 241210684 ps |
| CPU time | 1.74 seconds |
| Started | Sep 01 09:44:56 PM UTC 24 |
| Finished | Sep 01 09:44:59 PM UTC 24 |
| Peak memory | 228804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569657334 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors.569657334 +enable_maskin g=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/16.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.3499032767 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 171712040 ps |
| CPU time | 3.29 seconds |
| Started | Sep 01 09:44:56 PM UTC 24 |
| Finished | Sep 01 09:45:00 PM UTC 24 |
| Peak memory | 229648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499032767 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.3499032767 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/16.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.904801968 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 412903475 ps |
| CPU time | 4.48 seconds |
| Started | Sep 01 09:44:57 PM UTC 24 |
| Finished | Sep 01 09:45:03 PM UTC 24 |
| Peak memory | 229600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904801968 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.904801968 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/16.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1911075624 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 1069695212 ps |
| CPU time | 2.85 seconds |
| Started | Sep 01 09:45:01 PM UTC 24 |
| Finished | Sep 01 09:45:05 PM UTC 24 |
| Peak memory | 231508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1911075624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr _mem_rw_with_rand_reset.1911075624 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/17.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.3460374293 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 109889963 ps |
| CPU time | 1.73 seconds |
| Started | Sep 01 09:45:01 PM UTC 24 |
| Finished | Sep 01 09:45:04 PM UTC 24 |
| Peak memory | 218908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460374293 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.3460374293 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/17.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.1040465823 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 19662575 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 09:45:00 PM UTC 24 |
| Finished | Sep 01 09:45:02 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040465823 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.1040465823 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/17.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.4247618839 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 173749722 ps |
| CPU time | 3.69 seconds |
| Started | Sep 01 09:45:01 PM UTC 24 |
| Finished | Sep 01 09:45:06 PM UTC 24 |
| Peak memory | 229364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247618839 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr_outstanding.4247618839 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/17.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2023979339 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 790660968 ps |
| CPU time | 2.55 seconds |
| Started | Sep 01 09:44:57 PM UTC 24 |
| Finished | Sep 01 09:45:01 PM UTC 24 |
| Peak memory | 229808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023979339 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors.2023979339 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/17.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1523116616 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 340256974 ps |
| CPU time | 4.19 seconds |
| Started | Sep 01 09:44:58 PM UTC 24 |
| Finished | Sep 01 09:45:04 PM UTC 24 |
| Peak memory | 229864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523116616 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors_with_csr_rw .1523116616 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.1306333760 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 67590741 ps |
| CPU time | 3 seconds |
| Started | Sep 01 09:44:58 PM UTC 24 |
| Finished | Sep 01 09:45:03 PM UTC 24 |
| Peak memory | 229516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306333760 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.1306333760 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/17.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.1682109335 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 265859439 ps |
| CPU time | 6.67 seconds |
| Started | Sep 01 09:44:59 PM UTC 24 |
| Finished | Sep 01 09:45:06 PM UTC 24 |
| Peak memory | 229400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682109335 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.1682109335 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/17.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.1443424836 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 127487666 ps |
| CPU time | 2.44 seconds |
| Started | Sep 01 09:45:03 PM UTC 24 |
| Finished | Sep 01 09:45:07 PM UTC 24 |
| Peak memory | 229344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1443424836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr _mem_rw_with_rand_reset.1443424836 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/18.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.693214134 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 31221569 ps |
| CPU time | 1.74 seconds |
| Started | Sep 01 09:45:02 PM UTC 24 |
| Finished | Sep 01 09:45:05 PM UTC 24 |
| Peak memory | 218904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693214134 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.693214134 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/18.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.3289712858 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 14703875 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 09:45:02 PM UTC 24 |
| Finished | Sep 01 09:45:04 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289712858 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.3289712858 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/18.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.506425489 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 138256845 ps |
| CPU time | 3.47 seconds |
| Started | Sep 01 09:45:03 PM UTC 24 |
| Finished | Sep 01 09:45:08 PM UTC 24 |
| Peak memory | 229552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506425489 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr_outstanding.506425489 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/18.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.688841698 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 102015170 ps |
| CPU time | 1.68 seconds |
| Started | Sep 01 09:45:01 PM UTC 24 |
| Finished | Sep 01 09:45:04 PM UTC 24 |
| Peak memory | 218588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688841698 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors.688841698 +enable_maskin g=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/18.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3560377241 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 666339367 ps |
| CPU time | 3.32 seconds |
| Started | Sep 01 09:45:01 PM UTC 24 |
| Finished | Sep 01 09:45:05 PM UTC 24 |
| Peak memory | 236528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560377241 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors_with_csr_rw .3560377241 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.1637918397 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 46952299 ps |
| CPU time | 3.06 seconds |
| Started | Sep 01 09:45:01 PM UTC 24 |
| Finished | Sep 01 09:45:05 PM UTC 24 |
| Peak memory | 229624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637918397 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.1637918397 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/18.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.1784504372 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 831220474 ps |
| CPU time | 7.46 seconds |
| Started | Sep 01 09:45:02 PM UTC 24 |
| Finished | Sep 01 09:45:11 PM UTC 24 |
| Peak memory | 229400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784504372 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.1784504372 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/18.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.421270986 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 40020337 ps |
| CPU time | 2.22 seconds |
| Started | Sep 01 09:45:06 PM UTC 24 |
| Finished | Sep 01 09:45:09 PM UTC 24 |
| Peak memory | 229584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=421270986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_ mem_rw_with_rand_reset.421270986 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/19.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.1782592839 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 38511845 ps |
| CPU time | 1.86 seconds |
| Started | Sep 01 09:45:06 PM UTC 24 |
| Finished | Sep 01 09:45:09 PM UTC 24 |
| Peak memory | 228876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782592839 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.1782592839 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/19.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.1536436291 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 17722441 ps |
| CPU time | 1.26 seconds |
| Started | Sep 01 09:45:05 PM UTC 24 |
| Finished | Sep 01 09:45:07 PM UTC 24 |
| Peak memory | 219056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536436291 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.1536436291 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/19.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.2299893605 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 199364601 ps |
| CPU time | 2.32 seconds |
| Started | Sep 01 09:45:06 PM UTC 24 |
| Finished | Sep 01 09:45:09 PM UTC 24 |
| Peak memory | 229388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299893605 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr_outstanding.2299893605 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/19.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3372306695 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 54024528 ps |
| CPU time | 2.23 seconds |
| Started | Sep 01 09:45:03 PM UTC 24 |
| Finished | Sep 01 09:45:07 PM UTC 24 |
| Peak memory | 229956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372306695 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors.3372306695 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/19.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.1277306300 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 373735480 ps |
| CPU time | 4.28 seconds |
| Started | Sep 01 09:45:04 PM UTC 24 |
| Finished | Sep 01 09:45:09 PM UTC 24 |
| Peak memory | 236508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277306300 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors_with_csr_rw .1277306300 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.1790968793 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 132717185 ps |
| CPU time | 2.81 seconds |
| Started | Sep 01 09:45:05 PM UTC 24 |
| Finished | Sep 01 09:45:09 PM UTC 24 |
| Peak memory | 229648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790968793 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.1790968793 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/19.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.3968793636 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 125594728 ps |
| CPU time | 4.14 seconds |
| Started | Sep 01 09:45:05 PM UTC 24 |
| Finished | Sep 01 09:45:10 PM UTC 24 |
| Peak memory | 229480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968793636 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.3968793636 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/19.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.3102953183 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 788741761 ps |
| CPU time | 12.93 seconds |
| Started | Sep 01 09:44:02 PM UTC 24 |
| Finished | Sep 01 09:44:16 PM UTC 24 |
| Peak memory | 229384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102953183 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.3102953183 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.1119193987 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 542502099 ps |
| CPU time | 14.63 seconds |
| Started | Sep 01 09:44:01 PM UTC 24 |
| Finished | Sep 01 09:44:17 PM UTC 24 |
| Peak memory | 219400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119193987 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.1119193987 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_hw_reset.3070207831 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 49794140 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 09:44:01 PM UTC 24 |
| Finished | Sep 01 09:44:03 PM UTC 24 |
| Peak memory | 219052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070207831 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.3070207831 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.154158917 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 638236248 ps |
| CPU time | 3.53 seconds |
| Started | Sep 01 09:44:03 PM UTC 24 |
| Finished | Sep 01 09:44:08 PM UTC 24 |
| Peak memory | 231500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=154158917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_m em_rw_with_rand_reset.154158917 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_rw.3061030713 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 90705731 ps |
| CPU time | 1.43 seconds |
| Started | Sep 01 09:44:01 PM UTC 24 |
| Finished | Sep 01 09:44:03 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061030713 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.3061030713 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_walk.662567505 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 15421198 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 09:43:56 PM UTC 24 |
| Finished | Sep 01 09:43:58 PM UTC 24 |
| Peak memory | 219052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662567505 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.662567505 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3675601838 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 167116191 ps |
| CPU time | 3.44 seconds |
| Started | Sep 01 09:44:02 PM UTC 24 |
| Finished | Sep 01 09:44:07 PM UTC 24 |
| Peak memory | 229396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675601838 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_outstanding.3675601838 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors.1312249239 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 193927765 ps |
| CPU time | 1.49 seconds |
| Started | Sep 01 09:43:53 PM UTC 24 |
| Finished | Sep 01 09:43:56 PM UTC 24 |
| Peak memory | 228736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312249239 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors.1312249239 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.1913127288 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 314901011 ps |
| CPU time | 3.06 seconds |
| Started | Sep 01 09:43:56 PM UTC 24 |
| Finished | Sep 01 09:44:00 PM UTC 24 |
| Peak memory | 229772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913127288 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors_with_csr_rw. 1913127288 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_errors.900471983 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 25404495 ps |
| CPU time | 2.12 seconds |
| Started | Sep 01 09:43:57 PM UTC 24 |
| Finished | Sep 01 09:44:01 PM UTC 24 |
| Peak memory | 229520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900471983 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.900471983 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_intg_err.2779153413 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 155750865 ps |
| CPU time | 4.35 seconds |
| Started | Sep 01 09:43:59 PM UTC 24 |
| Finished | Sep 01 09:44:04 PM UTC 24 |
| Peak memory | 229440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779153413 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.2779153413 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.769643323 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 26603906 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 09:45:06 PM UTC 24 |
| Finished | Sep 01 09:45:08 PM UTC 24 |
| Peak memory | 218936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769643323 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.769643323 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/20.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.3519084231 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 11491958 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 09:45:06 PM UTC 24 |
| Finished | Sep 01 09:45:08 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519084231 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.3519084231 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/21.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.1310279861 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 25612888 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 09:45:07 PM UTC 24 |
| Finished | Sep 01 09:45:09 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310279861 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.1310279861 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/22.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.2560464818 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 13597646 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 09:45:07 PM UTC 24 |
| Finished | Sep 01 09:45:10 PM UTC 24 |
| Peak memory | 219056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560464818 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.2560464818 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/23.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.1579075567 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 26913021 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 09:45:07 PM UTC 24 |
| Finished | Sep 01 09:45:10 PM UTC 24 |
| Peak memory | 219056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579075567 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.1579075567 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/24.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.3370951357 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 13298309 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 09:45:07 PM UTC 24 |
| Finished | Sep 01 09:45:10 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370951357 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.3370951357 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/25.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.2713811352 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 16429744 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 09:45:08 PM UTC 24 |
| Finished | Sep 01 09:45:11 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713811352 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.2713811352 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/26.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.2334886775 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 40424111 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 09:45:09 PM UTC 24 |
| Finished | Sep 01 09:45:11 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334886775 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.2334886775 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/27.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.2739385279 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 41272709 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 09:45:10 PM UTC 24 |
| Finished | Sep 01 09:45:12 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739385279 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.2739385279 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/28.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.2591815978 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 27630646 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 09:45:10 PM UTC 24 |
| Finished | Sep 01 09:45:12 PM UTC 24 |
| Peak memory | 219056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591815978 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.2591815978 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/29.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.1951934990 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 1008501209 ps |
| CPU time | 13.63 seconds |
| Started | Sep 01 09:44:12 PM UTC 24 |
| Finished | Sep 01 09:44:27 PM UTC 24 |
| Peak memory | 219144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951934990 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.1951934990 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.411230819 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 589277300 ps |
| CPU time | 18.34 seconds |
| Started | Sep 01 09:44:11 PM UTC 24 |
| Finished | Sep 01 09:44:30 PM UTC 24 |
| Peak memory | 219232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411230819 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.411230819 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_hw_reset.432503029 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 30659393 ps |
| CPU time | 1.76 seconds |
| Started | Sep 01 09:44:09 PM UTC 24 |
| Finished | Sep 01 09:44:12 PM UTC 24 |
| Peak memory | 218956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432503029 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.432503029 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.2963960054 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 42843039 ps |
| CPU time | 2.28 seconds |
| Started | Sep 01 09:44:12 PM UTC 24 |
| Finished | Sep 01 09:44:15 PM UTC 24 |
| Peak memory | 229460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2963960054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_ mem_rw_with_rand_reset.2963960054 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_rw.2432243923 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 23298714 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 09:44:11 PM UTC 24 |
| Finished | Sep 01 09:44:13 PM UTC 24 |
| Peak memory | 218868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432243923 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.2432243923 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_intr_test.3183030702 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 33914267 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 09:44:09 PM UTC 24 |
| Finished | Sep 01 09:44:11 PM UTC 24 |
| Peak memory | 218992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183030702 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.3183030702 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_partial_access.2127833492 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 21892912 ps |
| CPU time | 2.05 seconds |
| Started | Sep 01 09:44:07 PM UTC 24 |
| Finished | Sep 01 09:44:10 PM UTC 24 |
| Peak memory | 229136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127833492 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial_access.2127833492 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_walk.1096132053 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 44761980 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 09:44:05 PM UTC 24 |
| Finished | Sep 01 09:44:07 PM UTC 24 |
| Peak memory | 219052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096132053 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.1096132053 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_same_csr_outstanding.3600033911 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 112314732 ps |
| CPU time | 3.74 seconds |
| Started | Sep 01 09:44:12 PM UTC 24 |
| Finished | Sep 01 09:44:17 PM UTC 24 |
| Peak memory | 229396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600033911 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_outstanding.3600033911 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors.3966798527 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 42132576 ps |
| CPU time | 1.82 seconds |
| Started | Sep 01 09:44:04 PM UTC 24 |
| Finished | Sep 01 09:44:07 PM UTC 24 |
| Peak memory | 228668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966798527 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors.3966798527 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.2649396656 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 101198903 ps |
| CPU time | 2.49 seconds |
| Started | Sep 01 09:44:04 PM UTC 24 |
| Finished | Sep 01 09:44:08 PM UTC 24 |
| Peak memory | 229464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649396656 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors_with_csr_rw. 2649396656 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_errors.1452456761 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 116902984 ps |
| CPU time | 2.35 seconds |
| Started | Sep 01 09:44:07 PM UTC 24 |
| Finished | Sep 01 09:44:11 PM UTC 24 |
| Peak memory | 229288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452456761 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.1452456761 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_intg_err.1756733945 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 350952140 ps |
| CPU time | 3.78 seconds |
| Started | Sep 01 09:44:09 PM UTC 24 |
| Finished | Sep 01 09:44:13 PM UTC 24 |
| Peak memory | 229572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756733945 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.1756733945 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.2630813338 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 12981384 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 09:45:10 PM UTC 24 |
| Finished | Sep 01 09:45:12 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630813338 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.2630813338 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/30.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.1851267403 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 17138012 ps |
| CPU time | 1.17 seconds |
| Started | Sep 01 09:45:10 PM UTC 24 |
| Finished | Sep 01 09:45:12 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851267403 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.1851267403 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/31.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.2217326929 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 70874922 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 09:45:10 PM UTC 24 |
| Finished | Sep 01 09:45:12 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217326929 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.2217326929 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/32.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.3979807402 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 23969634 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 09:45:10 PM UTC 24 |
| Finished | Sep 01 09:45:12 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979807402 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.3979807402 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/33.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.3380536906 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 18745231 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 09:45:10 PM UTC 24 |
| Finished | Sep 01 09:45:12 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380536906 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.3380536906 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/34.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.878685037 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 43185846 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 09:45:11 PM UTC 24 |
| Finished | Sep 01 09:45:14 PM UTC 24 |
| Peak memory | 218940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878685037 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.878685037 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/35.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.4119484278 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 53045765 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 09:45:11 PM UTC 24 |
| Finished | Sep 01 09:45:14 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119484278 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.4119484278 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/36.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.2649034579 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 40695533 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 09:45:11 PM UTC 24 |
| Finished | Sep 01 09:45:14 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649034579 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.2649034579 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/37.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.4272548746 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 15374127 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 09:45:11 PM UTC 24 |
| Finished | Sep 01 09:45:14 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272548746 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.4272548746 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/38.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.542684967 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 11069623 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 09:45:12 PM UTC 24 |
| Finished | Sep 01 09:45:14 PM UTC 24 |
| Peak memory | 218936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542684967 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.542684967 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/39.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.3282319003 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 76110259 ps |
| CPU time | 4.56 seconds |
| Started | Sep 01 09:44:20 PM UTC 24 |
| Finished | Sep 01 09:44:26 PM UTC 24 |
| Peak memory | 219204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282319003 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.3282319003 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.472183420 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 4638947896 ps |
| CPU time | 29.71 seconds |
| Started | Sep 01 09:44:18 PM UTC 24 |
| Finished | Sep 01 09:44:49 PM UTC 24 |
| Peak memory | 219344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472183420 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.472183420 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_hw_reset.2966852792 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 68552687 ps |
| CPU time | 1.56 seconds |
| Started | Sep 01 09:44:18 PM UTC 24 |
| Finished | Sep 01 09:44:21 PM UTC 24 |
| Peak memory | 217752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966852792 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.2966852792 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2054977438 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 132486652 ps |
| CPU time | 3.48 seconds |
| Started | Sep 01 09:44:21 PM UTC 24 |
| Finished | Sep 01 09:44:26 PM UTC 24 |
| Peak memory | 231508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2054977438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_ mem_rw_with_rand_reset.2054977438 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.1019248979 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 18180246 ps |
| CPU time | 1.6 seconds |
| Started | Sep 01 09:44:18 PM UTC 24 |
| Finished | Sep 01 09:44:21 PM UTC 24 |
| Peak memory | 218952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019248979 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.1019248979 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_intr_test.3276341329 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 18041670 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 09:44:18 PM UTC 24 |
| Finished | Sep 01 09:44:20 PM UTC 24 |
| Peak memory | 217740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276341329 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.3276341329 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_partial_access.2883546548 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 205610502 ps |
| CPU time | 1.96 seconds |
| Started | Sep 01 09:44:16 PM UTC 24 |
| Finished | Sep 01 09:44:20 PM UTC 24 |
| Peak memory | 228872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883546548 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial_access.2883546548 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_walk.3371188124 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 52553439 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 09:44:14 PM UTC 24 |
| Finished | Sep 01 09:44:17 PM UTC 24 |
| Peak memory | 219052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371188124 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.3371188124 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.3828811735 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 153105745 ps |
| CPU time | 3.4 seconds |
| Started | Sep 01 09:44:21 PM UTC 24 |
| Finished | Sep 01 09:44:26 PM UTC 24 |
| Peak memory | 229584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828811735 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_outstanding.3828811735 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.355935995 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 128705648 ps |
| CPU time | 3.65 seconds |
| Started | Sep 01 09:44:17 PM UTC 24 |
| Finished | Sep 01 09:44:22 PM UTC 24 |
| Peak memory | 229712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355935995 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.355935995 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.2007439272 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 29460515 ps |
| CPU time | 1.17 seconds |
| Started | Sep 01 09:45:12 PM UTC 24 |
| Finished | Sep 01 09:45:14 PM UTC 24 |
| Peak memory | 219056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007439272 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.2007439272 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/40.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.3084804944 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 40370769 ps |
| CPU time | 1.17 seconds |
| Started | Sep 01 09:45:12 PM UTC 24 |
| Finished | Sep 01 09:45:14 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084804944 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.3084804944 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/41.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.1584327614 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 24969982 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 09:45:12 PM UTC 24 |
| Finished | Sep 01 09:45:14 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584327614 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.1584327614 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/42.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.3025714329 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 31074589 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 09:45:12 PM UTC 24 |
| Finished | Sep 01 09:45:14 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025714329 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.3025714329 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/43.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.3000749855 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 110134536 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 09:45:13 PM UTC 24 |
| Finished | Sep 01 09:45:15 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000749855 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.3000749855 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/44.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.1548441689 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 41065433 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 09:45:13 PM UTC 24 |
| Finished | Sep 01 09:45:15 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548441689 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.1548441689 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/45.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.2765925592 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 25823896 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 09:45:13 PM UTC 24 |
| Finished | Sep 01 09:45:15 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765925592 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.2765925592 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/46.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.821324289 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 18605227 ps |
| CPU time | 0.93 seconds |
| Started | Sep 01 09:45:13 PM UTC 24 |
| Finished | Sep 01 09:45:15 PM UTC 24 |
| Peak memory | 218936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821324289 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.821324289 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/47.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.26310312 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 27844752 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 09:45:13 PM UTC 24 |
| Finished | Sep 01 09:45:16 PM UTC 24 |
| Peak memory | 218980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26310312 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.26310312 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/48.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.3752122885 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 69186999 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 09:45:13 PM UTC 24 |
| Finished | Sep 01 09:45:16 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752122885 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.3752122885 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/49.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.2666618508 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 60868071 ps |
| CPU time | 3.41 seconds |
| Started | Sep 01 09:44:27 PM UTC 24 |
| Finished | Sep 01 09:44:31 PM UTC 24 |
| Peak memory | 231508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2666618508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_ mem_rw_with_rand_reset.2666618508 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/5.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_rw.3529957777 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 18055039 ps |
| CPU time | 1.45 seconds |
| Started | Sep 01 09:44:26 PM UTC 24 |
| Finished | Sep 01 09:44:28 PM UTC 24 |
| Peak memory | 228916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529957777 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.3529957777 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/5.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.2668405193 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 29698557 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 09:44:25 PM UTC 24 |
| Finished | Sep 01 09:44:27 PM UTC 24 |
| Peak memory | 218992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668405193 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.2668405193 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/5.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_same_csr_outstanding.2031441751 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 113548952 ps |
| CPU time | 3.11 seconds |
| Started | Sep 01 09:44:27 PM UTC 24 |
| Finished | Sep 01 09:44:31 PM UTC 24 |
| Peak memory | 229704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031441751 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_outstanding.2031441751 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/5.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.2620691608 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 25195884 ps |
| CPU time | 1.76 seconds |
| Started | Sep 01 09:44:21 PM UTC 24 |
| Finished | Sep 01 09:44:24 PM UTC 24 |
| Peak memory | 228800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620691608 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors.2620691608 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1551214232 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 422668803 ps |
| CPU time | 3.11 seconds |
| Started | Sep 01 09:44:22 PM UTC 24 |
| Finished | Sep 01 09:44:27 PM UTC 24 |
| Peak memory | 229464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551214232 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors_with_csr_rw. 1551214232 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.3747294362 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 68662662 ps |
| CPU time | 3.31 seconds |
| Started | Sep 01 09:44:22 PM UTC 24 |
| Finished | Sep 01 09:44:27 PM UTC 24 |
| Peak memory | 229708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747294362 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.3747294362 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/5.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.4083995672 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 1006134315 ps |
| CPU time | 4.73 seconds |
| Started | Sep 01 09:44:23 PM UTC 24 |
| Finished | Sep 01 09:44:29 PM UTC 24 |
| Peak memory | 229508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083995672 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.4083995672 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/5.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3018756577 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 177882569 ps |
| CPU time | 2.62 seconds |
| Started | Sep 01 09:44:30 PM UTC 24 |
| Finished | Sep 01 09:44:34 PM UTC 24 |
| Peak memory | 229460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3018756577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_ mem_rw_with_rand_reset.3018756577 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/6.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_rw.616568794 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 91353946 ps |
| CPU time | 1.44 seconds |
| Started | Sep 01 09:44:28 PM UTC 24 |
| Finished | Sep 01 09:44:31 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616568794 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.616568794 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/6.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_intr_test.1678868439 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 18159165 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 09:44:28 PM UTC 24 |
| Finished | Sep 01 09:44:30 PM UTC 24 |
| Peak memory | 218952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678868439 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.1678868439 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/6.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.1411015920 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 345294016 ps |
| CPU time | 2.73 seconds |
| Started | Sep 01 09:44:29 PM UTC 24 |
| Finished | Sep 01 09:44:33 PM UTC 24 |
| Peak memory | 229396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411015920 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_outstanding.1411015920 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/6.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.2643975555 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 141746265 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 09:44:27 PM UTC 24 |
| Finished | Sep 01 09:44:29 PM UTC 24 |
| Peak memory | 218644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643975555 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors.2643975555 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.547922907 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 105977288 ps |
| CPU time | 2.69 seconds |
| Started | Sep 01 09:44:27 PM UTC 24 |
| Finished | Sep 01 09:44:31 PM UTC 24 |
| Peak memory | 229804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547922907 -asse rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors_with_csr_rw.5 47922907 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.3637209568 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 377802941 ps |
| CPU time | 3.95 seconds |
| Started | Sep 01 09:44:28 PM UTC 24 |
| Finished | Sep 01 09:44:33 PM UTC 24 |
| Peak memory | 229744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637209568 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.3637209568 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/6.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.1964733338 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 247083526 ps |
| CPU time | 4.23 seconds |
| Started | Sep 01 09:44:28 PM UTC 24 |
| Finished | Sep 01 09:44:34 PM UTC 24 |
| Peak memory | 229340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964733338 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.1964733338 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/6.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.1658410756 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 132281409 ps |
| CPU time | 3.31 seconds |
| Started | Sep 01 09:44:34 PM UTC 24 |
| Finished | Sep 01 09:44:39 PM UTC 24 |
| Peak memory | 231508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1658410756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_ mem_rw_with_rand_reset.1658410756 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/7.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.786412596 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 16637686 ps |
| CPU time | 1.65 seconds |
| Started | Sep 01 09:44:32 PM UTC 24 |
| Finished | Sep 01 09:44:35 PM UTC 24 |
| Peak memory | 218956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786412596 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.786412596 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/7.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.339268863 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 53904480 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 09:44:32 PM UTC 24 |
| Finished | Sep 01 09:44:34 PM UTC 24 |
| Peak memory | 219000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339268863 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.339268863 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/7.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3528531114 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 68385991 ps |
| CPU time | 2.53 seconds |
| Started | Sep 01 09:44:33 PM UTC 24 |
| Finished | Sep 01 09:44:37 PM UTC 24 |
| Peak memory | 229456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528531114 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_outstanding.3528531114 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/7.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors.1771264445 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 52587002 ps |
| CPU time | 2.22 seconds |
| Started | Sep 01 09:44:30 PM UTC 24 |
| Finished | Sep 01 09:44:34 PM UTC 24 |
| Peak memory | 229960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771264445 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors.1771264445 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.1320919907 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 215187585 ps |
| CPU time | 3.91 seconds |
| Started | Sep 01 09:44:32 PM UTC 24 |
| Finished | Sep 01 09:44:37 PM UTC 24 |
| Peak memory | 236752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320919907 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors_with_csr_rw. 1320919907 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.3848418918 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 60318656 ps |
| CPU time | 4.84 seconds |
| Started | Sep 01 09:44:32 PM UTC 24 |
| Finished | Sep 01 09:44:38 PM UTC 24 |
| Peak memory | 229704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848418918 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.3848418918 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/7.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.3542970363 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 114650750 ps |
| CPU time | 3.9 seconds |
| Started | Sep 01 09:44:32 PM UTC 24 |
| Finished | Sep 01 09:44:37 PM UTC 24 |
| Peak memory | 229440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542970363 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.3542970363 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/7.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.642732797 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 258089435 ps |
| CPU time | 3.35 seconds |
| Started | Sep 01 09:44:36 PM UTC 24 |
| Finished | Sep 01 09:44:40 PM UTC 24 |
| Peak memory | 229456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=642732797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_m em_rw_with_rand_reset.642732797 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/8.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.3509565007 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 17509939 ps |
| CPU time | 1.37 seconds |
| Started | Sep 01 09:44:35 PM UTC 24 |
| Finished | Sep 01 09:44:38 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509565007 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.3509565007 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/8.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.3444581844 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 78543867 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 09:44:35 PM UTC 24 |
| Finished | Sep 01 09:44:38 PM UTC 24 |
| Peak memory | 218992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444581844 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.3444581844 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/8.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2016467892 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 336303510 ps |
| CPU time | 2.62 seconds |
| Started | Sep 01 09:44:36 PM UTC 24 |
| Finished | Sep 01 09:44:40 PM UTC 24 |
| Peak memory | 229372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016467892 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_outstanding.2016467892 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/8.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.3413704050 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 19516062 ps |
| CPU time | 1.45 seconds |
| Started | Sep 01 09:44:34 PM UTC 24 |
| Finished | Sep 01 09:44:37 PM UTC 24 |
| Peak memory | 228860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413704050 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors.3413704050 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2712289041 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 259457070 ps |
| CPU time | 2.96 seconds |
| Started | Sep 01 09:44:34 PM UTC 24 |
| Finished | Sep 01 09:44:38 PM UTC 24 |
| Peak memory | 229860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712289041 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors_with_csr_rw. 2712289041 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.1465701030 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 336695235 ps |
| CPU time | 4.62 seconds |
| Started | Sep 01 09:44:34 PM UTC 24 |
| Finished | Sep 01 09:44:40 PM UTC 24 |
| Peak memory | 229576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465701030 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.1465701030 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/8.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.1811160366 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 524993117 ps |
| CPU time | 4.77 seconds |
| Started | Sep 01 09:44:34 PM UTC 24 |
| Finished | Sep 01 09:44:40 PM UTC 24 |
| Peak memory | 229440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811160366 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.1811160366 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/8.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.1009811170 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 106899210 ps |
| CPU time | 3.9 seconds |
| Started | Sep 01 09:44:39 PM UTC 24 |
| Finished | Sep 01 09:44:44 PM UTC 24 |
| Peak memory | 231512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1009811170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_ mem_rw_with_rand_reset.1009811170 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/9.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.2116154848 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 38453313 ps |
| CPU time | 1.26 seconds |
| Started | Sep 01 09:44:39 PM UTC 24 |
| Finished | Sep 01 09:44:41 PM UTC 24 |
| Peak memory | 218956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116154848 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.2116154848 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/9.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.3904108950 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 40531099 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 09:44:39 PM UTC 24 |
| Finished | Sep 01 09:44:41 PM UTC 24 |
| Peak memory | 219052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904108950 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.3904108950 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/9.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2400404524 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 167339960 ps |
| CPU time | 3.36 seconds |
| Started | Sep 01 09:44:39 PM UTC 24 |
| Finished | Sep 01 09:44:44 PM UTC 24 |
| Peak memory | 229648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400404524 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_outstanding.2400404524 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/9.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.2759610416 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 49719767 ps |
| CPU time | 2.2 seconds |
| Started | Sep 01 09:44:38 PM UTC 24 |
| Finished | Sep 01 09:44:41 PM UTC 24 |
| Peak memory | 229956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759610416 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors.2759610416 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1186047055 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 103032945 ps |
| CPU time | 2.23 seconds |
| Started | Sep 01 09:44:38 PM UTC 24 |
| Finished | Sep 01 09:44:41 PM UTC 24 |
| Peak memory | 229880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186047055 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors_with_csr_rw. 1186047055 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.1732497184 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 117193786 ps |
| CPU time | 3.17 seconds |
| Started | Sep 01 09:44:38 PM UTC 24 |
| Finished | Sep 01 09:44:42 PM UTC 24 |
| Peak memory | 229684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732497184 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.1732497184 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/9.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.3461929697 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 733251888 ps |
| CPU time | 3.91 seconds |
| Started | Sep 01 09:44:38 PM UTC 24 |
| Finished | Sep 01 09:44:43 PM UTC 24 |
| Peak memory | 229356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461929697 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.3461929697 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/9.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/0.kmac_burst_write.2137929854 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 4579863221 ps |
| CPU time | 467.53 seconds |
| Started | Sep 01 08:48:20 PM UTC 24 |
| Finished | Sep 01 08:56:14 PM UTC 24 |
| Peak memory | 243544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137929854 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.2137929854 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/0.kmac_edn_timeout_error.3512977560 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 582397399 ps |
| CPU time | 10.49 seconds |
| Started | Sep 01 08:48:22 PM UTC 24 |
| Finished | Sep 01 08:48:34 PM UTC 24 |
| Peak memory | 228272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512977560 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.3512977560 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_mode_error.136976022 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 2249596203 ps |
| CPU time | 22.9 seconds |
| Started | Sep 01 08:48:22 PM UTC 24 |
| Finished | Sep 01 08:48:47 PM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136976022 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.136976022 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_ready_error.3506592118 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 2885354677 ps |
| CPU time | 43.21 seconds |
| Started | Sep 01 08:48:22 PM UTC 24 |
| Finished | Sep 01 08:49:08 PM UTC 24 |
| Peak memory | 230792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506592118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.3506592118 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/0.kmac_key_error.2004887043 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1114489681 ps |
| CPU time | 12.07 seconds |
| Started | Sep 01 08:48:22 PM UTC 24 |
| Finished | Sep 01 08:48:36 PM UTC 24 |
| Peak memory | 230356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004887043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.2004887043 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/0.kmac_lc_escalation.1894420576 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 67755610 ps |
| CPU time | 2.57 seconds |
| Started | Sep 01 08:48:22 PM UTC 24 |
| Finished | Sep 01 08:48:26 PM UTC 24 |
| Peak memory | 230336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894420576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.1894420576 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/0.kmac_long_msg_and_output.2864091397 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 237249972240 ps |
| CPU time | 1615.23 seconds |
| Started | Sep 01 08:48:20 PM UTC 24 |
| Finished | Sep 01 09:15:35 PM UTC 24 |
| Peak memory | 1898292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864091397 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_and_output.2864091397 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/0.kmac_mubi.758367803 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3490636912 ps |
| CPU time | 67.32 seconds |
| Started | Sep 01 08:48:22 PM UTC 24 |
| Finished | Sep 01 08:49:32 PM UTC 24 |
| Peak memory | 270380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758367803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.758367803 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/0.kmac_sideload.4138232705 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 16782895585 ps |
| CPU time | 383.66 seconds |
| Started | Sep 01 08:48:20 PM UTC 24 |
| Finished | Sep 01 08:54:49 PM UTC 24 |
| Peak memory | 567088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138232705 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.4138232705 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/0.kmac_smoke.2731974985 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 7298047012 ps |
| CPU time | 100.05 seconds |
| Started | Sep 01 08:48:20 PM UTC 24 |
| Finished | Sep 01 08:50:02 PM UTC 24 |
| Peak memory | 234696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731974985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.2731974985 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/0.kmac_stress_all.3696247395 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 54093802797 ps |
| CPU time | 1728.64 seconds |
| Started | Sep 01 08:48:22 PM UTC 24 |
| Finished | Sep 01 09:17:33 PM UTC 24 |
| Peak memory | 1022260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696247395 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.3696247395 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac.1504079443 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 134186191 ps |
| CPU time | 2.88 seconds |
| Started | Sep 01 08:48:20 PM UTC 24 |
| Finished | Sep 01 08:48:24 PM UTC 24 |
| Peak memory | 230540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504079443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac.1504079443 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac_xof.1410239593 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1078224427 ps |
| CPU time | 4.44 seconds |
| Started | Sep 01 08:48:22 PM UTC 24 |
| Finished | Sep 01 08:48:28 PM UTC 24 |
| Peak memory | 230708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410239593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.1410239593 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_224.1557075970 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 239347440663 ps |
| CPU time | 2656.98 seconds |
| Started | Sep 01 08:48:20 PM UTC 24 |
| Finished | Sep 01 09:33:09 PM UTC 24 |
| Peak memory | 3213148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557075970 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.1557075970 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_256.1612875244 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 59173733453 ps |
| CPU time | 2409.36 seconds |
| Started | Sep 01 08:48:20 PM UTC 24 |
| Finished | Sep 01 09:28:58 PM UTC 24 |
| Peak memory | 2977432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612875244 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.1612875244 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_384.3162110795 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 46312911457 ps |
| CPU time | 1762.97 seconds |
| Started | Sep 01 08:48:20 PM UTC 24 |
| Finished | Sep 01 09:18:04 PM UTC 24 |
| Peak memory | 2356884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162110795 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.3162110795 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_512.3589022743 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 128814845111 ps |
| CPU time | 1150.22 seconds |
| Started | Sep 01 08:48:20 PM UTC 24 |
| Finished | Sep 01 09:07:44 PM UTC 24 |
| Peak memory | 1707672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589022743 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.3589022743 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/1.kmac_alert_test.2539504567 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 45762420 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 08:49:08 PM UTC 24 |
| Finished | Sep 01 08:49:11 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539504567 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.2539504567 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/1.kmac_app.2215684718 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 2942569958 ps |
| CPU time | 133.21 seconds |
| Started | Sep 01 08:48:39 PM UTC 24 |
| Finished | Sep 01 08:50:55 PM UTC 24 |
| Peak memory | 284576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215684718 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.2215684718 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/1.kmac_app_with_partial_data.2279945461 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4077071256 ps |
| CPU time | 130.44 seconds |
| Started | Sep 01 08:48:41 PM UTC 24 |
| Finished | Sep 01 08:50:54 PM UTC 24 |
| Peak memory | 304892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279945461 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.2279945461 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/1.kmac_burst_write.4224048417 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 60470149594 ps |
| CPU time | 852.37 seconds |
| Started | Sep 01 08:48:26 PM UTC 24 |
| Finished | Sep 01 09:02:49 PM UTC 24 |
| Peak memory | 266224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224048417 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.4224048417 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/1.kmac_edn_timeout_error.4200711504 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 345443808 ps |
| CPU time | 11.68 seconds |
| Started | Sep 01 08:48:54 PM UTC 24 |
| Finished | Sep 01 08:49:06 PM UTC 24 |
| Peak memory | 232496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200711504 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.4200711504 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_mode_error.3036997336 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 785946758 ps |
| CPU time | 29.3 seconds |
| Started | Sep 01 08:48:54 PM UTC 24 |
| Finished | Sep 01 08:49:24 PM UTC 24 |
| Peak memory | 235004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036997336 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.3036997336 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_ready_error.3767986870 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 2983038097 ps |
| CPU time | 43.79 seconds |
| Started | Sep 01 08:48:56 PM UTC 24 |
| Finished | Sep 01 08:49:41 PM UTC 24 |
| Peak memory | 230872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767986870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.3767986870 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_refresh.72950579 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9082291953 ps |
| CPU time | 189.72 seconds |
| Started | Sep 01 08:48:43 PM UTC 24 |
| Finished | Sep 01 08:51:56 PM UTC 24 |
| Peak memory | 386788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72950579 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.72950579 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/1.kmac_long_msg_and_output.4049135434 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 153573787928 ps |
| CPU time | 3613.53 seconds |
| Started | Sep 01 08:48:25 PM UTC 24 |
| Finished | Sep 01 09:49:20 PM UTC 24 |
| Peak memory | 3755824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049135434 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_and_output.4049135434 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/1.kmac_mubi.2541573937 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 12364310248 ps |
| CPU time | 263.31 seconds |
| Started | Sep 01 08:48:47 PM UTC 24 |
| Finished | Sep 01 08:53:15 PM UTC 24 |
| Peak memory | 315432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541573937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.2541573937 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/1.kmac_sec_cm.1384028320 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 74793754007 ps |
| CPU time | 91.46 seconds |
| Started | Sep 01 08:49:07 PM UTC 24 |
| Finished | Sep 01 08:50:41 PM UTC 24 |
| Peak memory | 287428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384028320 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.1384028320 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/1.kmac_sideload.610541689 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 4423788226 ps |
| CPU time | 112.84 seconds |
| Started | Sep 01 08:48:25 PM UTC 24 |
| Finished | Sep 01 08:50:20 PM UTC 24 |
| Peak memory | 319284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610541689 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.610541689 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac.3592440644 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 127995824 ps |
| CPU time | 2.55 seconds |
| Started | Sep 01 08:48:36 PM UTC 24 |
| Finished | Sep 01 08:48:40 PM UTC 24 |
| Peak memory | 230460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592440644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac.3592440644 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac_xof.3587244632 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 150671326 ps |
| CPU time | 3.96 seconds |
| Started | Sep 01 08:48:37 PM UTC 24 |
| Finished | Sep 01 08:48:42 PM UTC 24 |
| Peak memory | 230520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587244632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.3587244632 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_224.2822675790 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1803805618 ps |
| CPU time | 46.47 seconds |
| Started | Sep 01 08:48:27 PM UTC 24 |
| Finished | Sep 01 08:49:15 PM UTC 24 |
| Peak memory | 257732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822675790 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.2822675790 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_256.227246874 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 57580898635 ps |
| CPU time | 2365.53 seconds |
| Started | Sep 01 08:48:28 PM UTC 24 |
| Finished | Sep 01 09:28:22 PM UTC 24 |
| Peak memory | 2985872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227246874 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.227246874 + enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_384.233573131 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 3169437267 ps |
| CPU time | 34.45 seconds |
| Started | Sep 01 08:48:30 PM UTC 24 |
| Finished | Sep 01 08:49:06 PM UTC 24 |
| Peak memory | 230516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233573131 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.233573131 + enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_512.2748012589 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 47699466646 ps |
| CPU time | 1287.92 seconds |
| Started | Sep 01 08:48:31 PM UTC 24 |
| Finished | Sep 01 09:10:15 PM UTC 24 |
| Peak memory | 1715864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748012589 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.2748012589 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_128.2017629763 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 14284003307 ps |
| CPU time | 291.53 seconds |
| Started | Sep 01 08:48:34 PM UTC 24 |
| Finished | Sep 01 08:53:30 PM UTC 24 |
| Peak memory | 280252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017629763 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.2017629 763 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_256.902109808 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 34148905071 ps |
| CPU time | 1817.16 seconds |
| Started | Sep 01 08:48:35 PM UTC 24 |
| Finished | Sep 01 09:19:14 PM UTC 24 |
| Peak memory | 1154896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902109808 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.90210980 8 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/10.kmac_alert_test.1900985285 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 49544366 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 08:59:15 PM UTC 24 |
| Finished | Sep 01 08:59:17 PM UTC 24 |
| Peak memory | 216348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900985285 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.1900985285 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/10.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/10.kmac_app.852906294 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 5005497913 ps |
| CPU time | 128.67 seconds |
| Started | Sep 01 08:58:49 PM UTC 24 |
| Finished | Sep 01 09:01:01 PM UTC 24 |
| Peak memory | 278244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852906294 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.852906294 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/10.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/10.kmac_burst_write.1015072820 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 25992227620 ps |
| CPU time | 567.77 seconds |
| Started | Sep 01 08:58:46 PM UTC 24 |
| Finished | Sep 01 09:08:22 PM UTC 24 |
| Peak memory | 253728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015072820 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.1015072820 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/10.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/10.kmac_edn_timeout_error.2363763929 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 334387355 ps |
| CPU time | 5.46 seconds |
| Started | Sep 01 08:59:08 PM UTC 24 |
| Finished | Sep 01 08:59:14 PM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363763929 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.2363763929 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/10.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/10.kmac_entropy_mode_error.1259892296 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 1239103208 ps |
| CPU time | 39.9 seconds |
| Started | Sep 01 08:59:11 PM UTC 24 |
| Finished | Sep 01 08:59:53 PM UTC 24 |
| Peak memory | 235040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259892296 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.1259892296 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/10.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/10.kmac_entropy_refresh.2999953854 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 3932644280 ps |
| CPU time | 48.61 seconds |
| Started | Sep 01 08:58:50 PM UTC 24 |
| Finished | Sep 01 08:59:41 PM UTC 24 |
| Peak memory | 247520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999953854 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.2999953854 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/10.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/10.kmac_error.1478441065 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 7806529395 ps |
| CPU time | 83.65 seconds |
| Started | Sep 01 08:58:51 PM UTC 24 |
| Finished | Sep 01 09:00:17 PM UTC 24 |
| Peak memory | 284456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478441065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.1478441065 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/10.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/10.kmac_key_error.1658323130 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 1847712323 ps |
| CPU time | 8.18 seconds |
| Started | Sep 01 08:59:01 PM UTC 24 |
| Finished | Sep 01 08:59:10 PM UTC 24 |
| Peak memory | 230376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658323130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.1658323130 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/10.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/10.kmac_long_msg_and_output.3853323626 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 2104123016 ps |
| CPU time | 212.34 seconds |
| Started | Sep 01 08:58:42 PM UTC 24 |
| Finished | Sep 01 09:02:18 PM UTC 24 |
| Peak memory | 349880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853323626 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_and_output.3853323626 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/10.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/10.kmac_sideload.4151872581 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 43203846241 ps |
| CPU time | 185.79 seconds |
| Started | Sep 01 08:58:44 PM UTC 24 |
| Finished | Sep 01 09:01:54 PM UTC 24 |
| Peak memory | 352004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151872581 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.4151872581 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/10.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/10.kmac_smoke.2426978932 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 297423831 ps |
| CPU time | 21.21 seconds |
| Started | Sep 01 08:58:37 PM UTC 24 |
| Finished | Sep 01 08:58:59 PM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426978932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.2426978932 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/10.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/10.kmac_stress_all.2256021809 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 7481518127 ps |
| CPU time | 324.7 seconds |
| Started | Sep 01 08:59:15 PM UTC 24 |
| Finished | Sep 01 09:04:44 PM UTC 24 |
| Peak memory | 344324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256021809 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.2256021809 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/10.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/11.kmac_alert_test.2752696027 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 16532957 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 09:00:12 PM UTC 24 |
| Finished | Sep 01 09:00:14 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752696027 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.2752696027 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/11.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/11.kmac_app.2496632836 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 11164836788 ps |
| CPU time | 317.2 seconds |
| Started | Sep 01 08:59:41 PM UTC 24 |
| Finished | Sep 01 09:05:03 PM UTC 24 |
| Peak memory | 354020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496632836 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.2496632836 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/11.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/11.kmac_burst_write.4215151814 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 74533627669 ps |
| CPU time | 838.39 seconds |
| Started | Sep 01 08:59:31 PM UTC 24 |
| Finished | Sep 01 09:13:41 PM UTC 24 |
| Peak memory | 261864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215151814 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.4215151814 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/11.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/11.kmac_edn_timeout_error.3733772697 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 1760746495 ps |
| CPU time | 33.95 seconds |
| Started | Sep 01 08:59:54 PM UTC 24 |
| Finished | Sep 01 09:00:29 PM UTC 24 |
| Peak memory | 232320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733772697 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.3733772697 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/11.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/11.kmac_entropy_mode_error.2403760558 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 4430570201 ps |
| CPU time | 35.69 seconds |
| Started | Sep 01 09:00:01 PM UTC 24 |
| Finished | Sep 01 09:00:42 PM UTC 24 |
| Peak memory | 235120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403760558 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.2403760558 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/11.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/11.kmac_entropy_refresh.1957947101 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 30713827802 ps |
| CPU time | 351.35 seconds |
| Started | Sep 01 08:59:42 PM UTC 24 |
| Finished | Sep 01 09:05:39 PM UTC 24 |
| Peak memory | 485232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957947101 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.1957947101 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/11.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/11.kmac_error.1317461703 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 748451538 ps |
| CPU time | 25.96 seconds |
| Started | Sep 01 08:59:43 PM UTC 24 |
| Finished | Sep 01 09:00:11 PM UTC 24 |
| Peak memory | 251624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317461703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.1317461703 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/11.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/11.kmac_key_error.2618235284 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 2814009942 ps |
| CPU time | 13.9 seconds |
| Started | Sep 01 08:59:45 PM UTC 24 |
| Finished | Sep 01 09:00:00 PM UTC 24 |
| Peak memory | 230392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618235284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.2618235284 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/11.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/11.kmac_lc_escalation.1103143141 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 52612406 ps |
| CPU time | 2.07 seconds |
| Started | Sep 01 09:00:07 PM UTC 24 |
| Finished | Sep 01 09:00:10 PM UTC 24 |
| Peak memory | 230380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103143141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.1103143141 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/11.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/11.kmac_long_msg_and_output.3401939206 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 282641511390 ps |
| CPU time | 2415.62 seconds |
| Started | Sep 01 08:59:18 PM UTC 24 |
| Finished | Sep 01 09:40:01 PM UTC 24 |
| Peak memory | 2805476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401939206 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_and_output.3401939206 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/11.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/11.kmac_sideload.1401567093 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 4823765514 ps |
| CPU time | 132.48 seconds |
| Started | Sep 01 08:59:29 PM UTC 24 |
| Finished | Sep 01 09:01:44 PM UTC 24 |
| Peak memory | 362236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401567093 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.1401567093 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/11.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/11.kmac_smoke.335148224 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 895890910 ps |
| CPU time | 26.58 seconds |
| Started | Sep 01 08:59:15 PM UTC 24 |
| Finished | Sep 01 08:59:43 PM UTC 24 |
| Peak memory | 232764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335148224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.335148224 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/11.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/11.kmac_stress_all.3901213655 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 7832282249 ps |
| CPU time | 176.02 seconds |
| Started | Sep 01 09:00:11 PM UTC 24 |
| Finished | Sep 01 09:03:10 PM UTC 24 |
| Peak memory | 313340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901213655 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.3901213655 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/11.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/12.kmac_alert_test.3948170126 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 13814165 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 09:01:11 PM UTC 24 |
| Finished | Sep 01 09:01:13 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948170126 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.3948170126 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/12.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/12.kmac_app.3219015460 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 31278426889 ps |
| CPU time | 413.08 seconds |
| Started | Sep 01 09:00:29 PM UTC 24 |
| Finished | Sep 01 09:07:28 PM UTC 24 |
| Peak memory | 520036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219015460 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.3219015460 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/12.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/12.kmac_burst_write.1323345997 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 20641380407 ps |
| CPU time | 619.19 seconds |
| Started | Sep 01 09:00:18 PM UTC 24 |
| Finished | Sep 01 09:10:46 PM UTC 24 |
| Peak memory | 247588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323345997 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.1323345997 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/12.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/12.kmac_edn_timeout_error.2030206424 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 1246806630 ps |
| CPU time | 25.16 seconds |
| Started | Sep 01 09:00:58 PM UTC 24 |
| Finished | Sep 01 09:01:24 PM UTC 24 |
| Peak memory | 235024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030206424 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.2030206424 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/12.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/12.kmac_entropy_mode_error.3918587633 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 105303058 ps |
| CPU time | 9.31 seconds |
| Started | Sep 01 09:01:00 PM UTC 24 |
| Finished | Sep 01 09:01:10 PM UTC 24 |
| Peak memory | 230328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918587633 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.3918587633 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/12.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/12.kmac_entropy_refresh.371986106 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 616390510 ps |
| CPU time | 26.57 seconds |
| Started | Sep 01 09:00:31 PM UTC 24 |
| Finished | Sep 01 09:00:59 PM UTC 24 |
| Peak memory | 235380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371986106 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.371986106 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/12.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/12.kmac_error.3873285452 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 58833904684 ps |
| CPU time | 315.39 seconds |
| Started | Sep 01 09:00:44 PM UTC 24 |
| Finished | Sep 01 09:06:04 PM UTC 24 |
| Peak memory | 515952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873285452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.3873285452 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/12.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/12.kmac_key_error.3557879403 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 4960405446 ps |
| CPU time | 11.94 seconds |
| Started | Sep 01 09:00:44 PM UTC 24 |
| Finished | Sep 01 09:00:57 PM UTC 24 |
| Peak memory | 230608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557879403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.3557879403 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/12.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/12.kmac_lc_escalation.1664367753 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 90030670 ps |
| CPU time | 1.83 seconds |
| Started | Sep 01 09:01:01 PM UTC 24 |
| Finished | Sep 01 09:01:04 PM UTC 24 |
| Peak memory | 231720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664367753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.1664367753 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/12.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/12.kmac_long_msg_and_output.2698389604 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 45049160165 ps |
| CPU time | 819.27 seconds |
| Started | Sep 01 09:00:15 PM UTC 24 |
| Finished | Sep 01 09:14:04 PM UTC 24 |
| Peak memory | 1232680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698389604 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_and_output.2698389604 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/12.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/12.kmac_sideload.4053758821 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 23522401782 ps |
| CPU time | 120.3 seconds |
| Started | Sep 01 09:00:17 PM UTC 24 |
| Finished | Sep 01 09:02:20 PM UTC 24 |
| Peak memory | 351992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053758821 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.4053758821 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/12.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/12.kmac_smoke.2964004205 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 2951503421 ps |
| CPU time | 15.3 seconds |
| Started | Sep 01 09:00:14 PM UTC 24 |
| Finished | Sep 01 09:00:31 PM UTC 24 |
| Peak memory | 234668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964004205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.2964004205 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/12.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/12.kmac_stress_all.124439431 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 3788659852 ps |
| CPU time | 124.67 seconds |
| Started | Sep 01 09:01:05 PM UTC 24 |
| Finished | Sep 01 09:03:12 PM UTC 24 |
| Peak memory | 317212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124439431 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.124439431 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/12.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/13.kmac_alert_test.4272993826 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 26309553 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 09:02:06 PM UTC 24 |
| Finished | Sep 01 09:02:09 PM UTC 24 |
| Peak memory | 216232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272993826 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.4272993826 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/13.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/13.kmac_app.724883722 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 876206885 ps |
| CPU time | 17.67 seconds |
| Started | Sep 01 09:01:34 PM UTC 24 |
| Finished | Sep 01 09:01:53 PM UTC 24 |
| Peak memory | 234948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724883722 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.724883722 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/13.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/13.kmac_burst_write.2050567072 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 6950866106 ps |
| CPU time | 120.24 seconds |
| Started | Sep 01 09:01:32 PM UTC 24 |
| Finished | Sep 01 09:03:34 PM UTC 24 |
| Peak memory | 234752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050567072 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.2050567072 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/13.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/13.kmac_edn_timeout_error.3704068493 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 12539093495 ps |
| CPU time | 37.09 seconds |
| Started | Sep 01 09:01:55 PM UTC 24 |
| Finished | Sep 01 09:02:34 PM UTC 24 |
| Peak memory | 232568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704068493 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.3704068493 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/13.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/13.kmac_entropy_mode_error.2222252650 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 290809381 ps |
| CPU time | 18.76 seconds |
| Started | Sep 01 09:01:55 PM UTC 24 |
| Finished | Sep 01 09:02:15 PM UTC 24 |
| Peak memory | 235424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222252650 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.2222252650 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/13.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/13.kmac_entropy_refresh.714884595 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 76664347019 ps |
| CPU time | 516.87 seconds |
| Started | Sep 01 09:01:46 PM UTC 24 |
| Finished | Sep 01 09:10:30 PM UTC 24 |
| Peak memory | 536300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714884595 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.714884595 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/13.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/13.kmac_error.3766755118 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 35392901823 ps |
| CPU time | 237.76 seconds |
| Started | Sep 01 09:01:46 PM UTC 24 |
| Finished | Sep 01 09:05:47 PM UTC 24 |
| Peak memory | 442404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766755118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.3766755118 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/13.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/13.kmac_key_error.3957493736 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 3336321176 ps |
| CPU time | 16.16 seconds |
| Started | Sep 01 09:01:54 PM UTC 24 |
| Finished | Sep 01 09:02:11 PM UTC 24 |
| Peak memory | 230716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957493736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.3957493736 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/13.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/13.kmac_lc_escalation.1560932769 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 64633968 ps |
| CPU time | 1.89 seconds |
| Started | Sep 01 09:02:02 PM UTC 24 |
| Finished | Sep 01 09:02:05 PM UTC 24 |
| Peak memory | 229684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560932769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.1560932769 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/13.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/13.kmac_long_msg_and_output.1579597386 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 128288280047 ps |
| CPU time | 4955.61 seconds |
| Started | Sep 01 09:01:15 PM UTC 24 |
| Finished | Sep 01 10:24:46 PM UTC 24 |
| Peak memory | 4638496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579597386 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_and_output.1579597386 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/13.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/13.kmac_sideload.2895009644 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 12653264732 ps |
| CPU time | 413.51 seconds |
| Started | Sep 01 09:01:25 PM UTC 24 |
| Finished | Sep 01 09:08:25 PM UTC 24 |
| Peak memory | 562992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895009644 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.2895009644 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/13.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/13.kmac_smoke.415042158 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 1217781542 ps |
| CPU time | 17.82 seconds |
| Started | Sep 01 09:01:14 PM UTC 24 |
| Finished | Sep 01 09:01:33 PM UTC 24 |
| Peak memory | 232520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415042158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.415042158 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/13.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/13.kmac_stress_all.2106057641 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 6444472105 ps |
| CPU time | 334.13 seconds |
| Started | Sep 01 09:02:03 PM UTC 24 |
| Finished | Sep 01 09:07:43 PM UTC 24 |
| Peak memory | 311424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106057641 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.2106057641 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/13.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/14.kmac_alert_test.3922955071 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 17967773 ps |
| CPU time | 1.3 seconds |
| Started | Sep 01 09:03:09 PM UTC 24 |
| Finished | Sep 01 09:03:12 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922955071 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.3922955071 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/14.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/14.kmac_app.2908768044 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 2210647122 ps |
| CPU time | 57.91 seconds |
| Started | Sep 01 09:02:19 PM UTC 24 |
| Finished | Sep 01 09:03:18 PM UTC 24 |
| Peak memory | 261952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908768044 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.2908768044 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/14.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/14.kmac_burst_write.2283594651 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 6420382157 ps |
| CPU time | 572.85 seconds |
| Started | Sep 01 09:02:19 PM UTC 24 |
| Finished | Sep 01 09:11:59 PM UTC 24 |
| Peak memory | 247564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283594651 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.2283594651 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/14.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/14.kmac_edn_timeout_error.2071063035 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 1189963071 ps |
| CPU time | 16.69 seconds |
| Started | Sep 01 09:02:59 PM UTC 24 |
| Finished | Sep 01 09:03:17 PM UTC 24 |
| Peak memory | 235036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071063035 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.2071063035 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/14.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/14.kmac_entropy_mode_error.2872603742 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 3139429873 ps |
| CPU time | 56.84 seconds |
| Started | Sep 01 09:03:04 PM UTC 24 |
| Finished | Sep 01 09:04:03 PM UTC 24 |
| Peak memory | 235232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872603742 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.2872603742 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/14.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/14.kmac_entropy_refresh.1563781777 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 23740725772 ps |
| CPU time | 295.07 seconds |
| Started | Sep 01 09:02:21 PM UTC 24 |
| Finished | Sep 01 09:07:21 PM UTC 24 |
| Peak memory | 321324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563781777 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.1563781777 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/14.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/14.kmac_error.3081223622 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 34470469164 ps |
| CPU time | 380.81 seconds |
| Started | Sep 01 09:02:35 PM UTC 24 |
| Finished | Sep 01 09:09:02 PM UTC 24 |
| Peak memory | 470764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081223622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.3081223622 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/14.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/14.kmac_key_error.2041279270 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 1848733628 ps |
| CPU time | 6.82 seconds |
| Started | Sep 01 09:02:50 PM UTC 24 |
| Finished | Sep 01 09:02:58 PM UTC 24 |
| Peak memory | 230396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041279270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.2041279270 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/14.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/14.kmac_lc_escalation.3094749922 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 46516608 ps |
| CPU time | 1.74 seconds |
| Started | Sep 01 09:03:07 PM UTC 24 |
| Finished | Sep 01 09:03:10 PM UTC 24 |
| Peak memory | 231772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094749922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.3094749922 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/14.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/14.kmac_long_msg_and_output.3496541153 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 1771147267 ps |
| CPU time | 206.13 seconds |
| Started | Sep 01 09:02:12 PM UTC 24 |
| Finished | Sep 01 09:05:43 PM UTC 24 |
| Peak memory | 323280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496541153 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_and_output.3496541153 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/14.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/14.kmac_sideload.3025324401 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 10185647953 ps |
| CPU time | 326.05 seconds |
| Started | Sep 01 09:02:15 PM UTC 24 |
| Finished | Sep 01 09:07:47 PM UTC 24 |
| Peak memory | 497524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025324401 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.3025324401 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/14.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/14.kmac_smoke.292278352 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 9872974665 ps |
| CPU time | 57.63 seconds |
| Started | Sep 01 09:02:09 PM UTC 24 |
| Finished | Sep 01 09:03:09 PM UTC 24 |
| Peak memory | 230768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292278352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.292278352 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/14.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/14.kmac_stress_all.457617579 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 742912268845 ps |
| CPU time | 1339 seconds |
| Started | Sep 01 09:03:09 PM UTC 24 |
| Finished | Sep 01 09:25:45 PM UTC 24 |
| Peak memory | 1251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457617579 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.457617579 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/14.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/15.kmac_alert_test.3619372614 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 23157796 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 09:04:11 PM UTC 24 |
| Finished | Sep 01 09:04:14 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619372614 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.3619372614 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/15.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/15.kmac_app.2585751865 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 11886314676 ps |
| CPU time | 279.31 seconds |
| Started | Sep 01 09:03:14 PM UTC 24 |
| Finished | Sep 01 09:07:57 PM UTC 24 |
| Peak memory | 452400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585751865 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.2585751865 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/15.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/15.kmac_burst_write.2072202343 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 235638046740 ps |
| CPU time | 599.53 seconds |
| Started | Sep 01 09:03:13 PM UTC 24 |
| Finished | Sep 01 09:13:20 PM UTC 24 |
| Peak memory | 253716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072202343 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.2072202343 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/15.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/15.kmac_edn_timeout_error.747317015 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 1716876826 ps |
| CPU time | 39.63 seconds |
| Started | Sep 01 09:03:41 PM UTC 24 |
| Finished | Sep 01 09:04:22 PM UTC 24 |
| Peak memory | 232312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747317015 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.747317015 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/15.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/15.kmac_entropy_mode_error.2412538923 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 1389333660 ps |
| CPU time | 34.62 seconds |
| Started | Sep 01 09:03:44 PM UTC 24 |
| Finished | Sep 01 09:04:21 PM UTC 24 |
| Peak memory | 234976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412538923 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.2412538923 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/15.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/15.kmac_entropy_refresh.1662168411 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 15130708153 ps |
| CPU time | 137.59 seconds |
| Started | Sep 01 09:03:18 PM UTC 24 |
| Finished | Sep 01 09:05:38 PM UTC 24 |
| Peak memory | 288756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662168411 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.1662168411 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/15.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/15.kmac_error.1961611985 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 9981267443 ps |
| CPU time | 150.78 seconds |
| Started | Sep 01 09:03:19 PM UTC 24 |
| Finished | Sep 01 09:05:52 PM UTC 24 |
| Peak memory | 329524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961611985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.1961611985 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/15.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/15.kmac_key_error.4022585280 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 274575393 ps |
| CPU time | 3.72 seconds |
| Started | Sep 01 09:03:35 PM UTC 24 |
| Finished | Sep 01 09:03:40 PM UTC 24 |
| Peak memory | 230444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022585280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.4022585280 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/15.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/15.kmac_lc_escalation.2713680748 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 88701038 ps |
| CPU time | 1.96 seconds |
| Started | Sep 01 09:04:03 PM UTC 24 |
| Finished | Sep 01 09:04:06 PM UTC 24 |
| Peak memory | 234220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713680748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.2713680748 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/15.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/15.kmac_long_msg_and_output.1370591953 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 197656879844 ps |
| CPU time | 1580.34 seconds |
| Started | Sep 01 09:03:12 PM UTC 24 |
| Finished | Sep 01 09:29:50 PM UTC 24 |
| Peak memory | 2127664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370591953 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_and_output.1370591953 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/15.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/15.kmac_sideload.1961607492 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 88288822451 ps |
| CPU time | 594.39 seconds |
| Started | Sep 01 09:03:13 PM UTC 24 |
| Finished | Sep 01 09:13:15 PM UTC 24 |
| Peak memory | 628468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961607492 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.1961607492 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/15.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/15.kmac_smoke.2534899033 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 4218172060 ps |
| CPU time | 31.78 seconds |
| Started | Sep 01 09:03:10 PM UTC 24 |
| Finished | Sep 01 09:03:44 PM UTC 24 |
| Peak memory | 230676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534899033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.2534899033 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/15.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/15.kmac_stress_all.119243128 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 21570219904 ps |
| CPU time | 590.68 seconds |
| Started | Sep 01 09:04:07 PM UTC 24 |
| Finished | Sep 01 09:14:06 PM UTC 24 |
| Peak memory | 632552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119243128 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.119243128 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/15.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/16.kmac_alert_test.2365540510 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 31423976 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 09:05:49 PM UTC 24 |
| Finished | Sep 01 09:05:51 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365540510 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.2365540510 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/16.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/16.kmac_app.2858052923 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 11182607469 ps |
| CPU time | 169.87 seconds |
| Started | Sep 01 09:04:53 PM UTC 24 |
| Finished | Sep 01 09:07:46 PM UTC 24 |
| Peak memory | 352232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858052923 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.2858052923 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/16.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/16.kmac_burst_write.2950108622 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 20569771111 ps |
| CPU time | 225.07 seconds |
| Started | Sep 01 09:04:46 PM UTC 24 |
| Finished | Sep 01 09:08:34 PM UTC 24 |
| Peak memory | 251944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950108622 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.2950108622 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/16.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/16.kmac_edn_timeout_error.3041615792 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 285357960 ps |
| CPU time | 5.93 seconds |
| Started | Sep 01 09:05:39 PM UTC 24 |
| Finished | Sep 01 09:05:46 PM UTC 24 |
| Peak memory | 230392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041615792 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.3041615792 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/16.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/16.kmac_entropy_mode_error.4075789103 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 2670837775 ps |
| CPU time | 42.83 seconds |
| Started | Sep 01 09:05:44 PM UTC 24 |
| Finished | Sep 01 09:06:29 PM UTC 24 |
| Peak memory | 232648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075789103 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.4075789103 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/16.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/16.kmac_entropy_refresh.3346242392 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 56267978565 ps |
| CPU time | 292.35 seconds |
| Started | Sep 01 09:05:04 PM UTC 24 |
| Finished | Sep 01 09:10:01 PM UTC 24 |
| Peak memory | 308968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346242392 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.3346242392 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/16.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/16.kmac_error.2729743246 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 2451118170 ps |
| CPU time | 250.7 seconds |
| Started | Sep 01 09:05:18 PM UTC 24 |
| Finished | Sep 01 09:09:33 PM UTC 24 |
| Peak memory | 319280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729743246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.2729743246 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/16.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/16.kmac_key_error.1062147591 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 1780399627 ps |
| CPU time | 4.75 seconds |
| Started | Sep 01 09:05:38 PM UTC 24 |
| Finished | Sep 01 09:05:44 PM UTC 24 |
| Peak memory | 230584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062147591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.1062147591 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/16.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/16.kmac_lc_escalation.3156065733 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 49835480 ps |
| CPU time | 2.58 seconds |
| Started | Sep 01 09:05:45 PM UTC 24 |
| Finished | Sep 01 09:05:49 PM UTC 24 |
| Peak memory | 230460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156065733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.3156065733 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/16.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/16.kmac_long_msg_and_output.1726270519 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 187067475973 ps |
| CPU time | 3675.79 seconds |
| Started | Sep 01 09:04:22 PM UTC 24 |
| Finished | Sep 01 10:06:19 PM UTC 24 |
| Peak memory | 3743460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726270519 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_and_output.1726270519 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/16.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/16.kmac_sideload.892865371 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 4022176555 ps |
| CPU time | 84.04 seconds |
| Started | Sep 01 09:04:24 PM UTC 24 |
| Finished | Sep 01 09:05:50 PM UTC 24 |
| Peak memory | 263980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892865371 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.892865371 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/16.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/16.kmac_smoke.2348498771 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 9846814906 ps |
| CPU time | 60.73 seconds |
| Started | Sep 01 09:04:15 PM UTC 24 |
| Finished | Sep 01 09:05:17 PM UTC 24 |
| Peak memory | 230604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348498771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.2348498771 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/16.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/16.kmac_stress_all.4255331971 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 15503328553 ps |
| CPU time | 476.86 seconds |
| Started | Sep 01 09:05:48 PM UTC 24 |
| Finished | Sep 01 09:13:51 PM UTC 24 |
| Peak memory | 442424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255331971 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.4255331971 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/16.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/17.kmac_alert_test.1441230397 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 12316732 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 09:07:15 PM UTC 24 |
| Finished | Sep 01 09:07:18 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441230397 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.1441230397 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/17.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/17.kmac_app.4190105841 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 1349391831 ps |
| CPU time | 71.71 seconds |
| Started | Sep 01 09:06:04 PM UTC 24 |
| Finished | Sep 01 09:07:18 PM UTC 24 |
| Peak memory | 253608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190105841 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.4190105841 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/17.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/17.kmac_burst_write.956126714 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 1189542041 ps |
| CPU time | 130.64 seconds |
| Started | Sep 01 09:05:53 PM UTC 24 |
| Finished | Sep 01 09:08:06 PM UTC 24 |
| Peak memory | 235176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956126714 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.956126714 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/17.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/17.kmac_edn_timeout_error.1001751257 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 455209052 ps |
| CPU time | 5.04 seconds |
| Started | Sep 01 09:06:53 PM UTC 24 |
| Finished | Sep 01 09:06:59 PM UTC 24 |
| Peak memory | 228212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001751257 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.1001751257 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/17.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/17.kmac_entropy_mode_error.763694109 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 190865513 ps |
| CPU time | 17.87 seconds |
| Started | Sep 01 09:06:55 PM UTC 24 |
| Finished | Sep 01 09:07:14 PM UTC 24 |
| Peak memory | 235100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763694109 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.763694109 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/17.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/17.kmac_entropy_refresh.2571900700 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 12805740265 ps |
| CPU time | 290.33 seconds |
| Started | Sep 01 09:06:29 PM UTC 24 |
| Finished | Sep 01 09:11:24 PM UTC 24 |
| Peak memory | 458576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571900700 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.2571900700 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/17.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/17.kmac_error.165156691 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 55619512126 ps |
| CPU time | 298.95 seconds |
| Started | Sep 01 09:06:36 PM UTC 24 |
| Finished | Sep 01 09:11:40 PM UTC 24 |
| Peak memory | 332688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165156691 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.165156691 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/17.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/17.kmac_key_error.2615236904 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 5237136590 ps |
| CPU time | 14.03 seconds |
| Started | Sep 01 09:06:37 PM UTC 24 |
| Finished | Sep 01 09:06:52 PM UTC 24 |
| Peak memory | 230728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615236904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.2615236904 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/17.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/17.kmac_lc_escalation.3286286302 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 96856723 ps |
| CPU time | 1.9 seconds |
| Started | Sep 01 09:07:00 PM UTC 24 |
| Finished | Sep 01 09:07:03 PM UTC 24 |
| Peak memory | 229788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286286302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.3286286302 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/17.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/17.kmac_long_msg_and_output.477537328 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 532093009872 ps |
| CPU time | 5221.01 seconds |
| Started | Sep 01 09:05:51 PM UTC 24 |
| Finished | Sep 01 10:33:50 PM UTC 24 |
| Peak memory | 4808504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477537328 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_and_output.477537328 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/17.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/17.kmac_sideload.3110906720 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 1887145166 ps |
| CPU time | 179.48 seconds |
| Started | Sep 01 09:05:52 PM UTC 24 |
| Finished | Sep 01 09:08:55 PM UTC 24 |
| Peak memory | 294568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110906720 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.3110906720 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/17.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/17.kmac_smoke.1473409865 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 3625015298 ps |
| CPU time | 62.55 seconds |
| Started | Sep 01 09:05:50 PM UTC 24 |
| Finished | Sep 01 09:06:54 PM UTC 24 |
| Peak memory | 230676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473409865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.1473409865 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/17.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/17.kmac_stress_all.2289544521 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 46202858804 ps |
| CPU time | 242.14 seconds |
| Started | Sep 01 09:07:04 PM UTC 24 |
| Finished | Sep 01 09:11:10 PM UTC 24 |
| Peak memory | 349976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289544521 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.2289544521 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/17.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/18.kmac_alert_test.21877162 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 25614815 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 09:07:58 PM UTC 24 |
| Finished | Sep 01 09:08:00 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21877162 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.21877162 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/18.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/18.kmac_app.2730697467 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 24512103718 ps |
| CPU time | 242.55 seconds |
| Started | Sep 01 09:07:29 PM UTC 24 |
| Finished | Sep 01 09:11:36 PM UTC 24 |
| Peak memory | 335932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730697467 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.2730697467 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/18.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/18.kmac_burst_write.331202755 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 8381433985 ps |
| CPU time | 287.62 seconds |
| Started | Sep 01 09:07:21 PM UTC 24 |
| Finished | Sep 01 09:12:14 PM UTC 24 |
| Peak memory | 241428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331202755 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.331202755 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/18.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/18.kmac_edn_timeout_error.155596587 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 510853610 ps |
| CPU time | 9.94 seconds |
| Started | Sep 01 09:07:47 PM UTC 24 |
| Finished | Sep 01 09:07:58 PM UTC 24 |
| Peak memory | 230344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155596587 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.155596587 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/18.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/18.kmac_entropy_mode_error.1324805840 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 1489891581 ps |
| CPU time | 53.76 seconds |
| Started | Sep 01 09:07:48 PM UTC 24 |
| Finished | Sep 01 09:08:43 PM UTC 24 |
| Peak memory | 235024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324805840 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.1324805840 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/18.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/18.kmac_entropy_refresh.2021392551 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 25971253306 ps |
| CPU time | 280.32 seconds |
| Started | Sep 01 09:07:40 PM UTC 24 |
| Finished | Sep 01 09:12:24 PM UTC 24 |
| Peak memory | 335660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021392551 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.2021392551 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/18.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/18.kmac_error.1773498666 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 9587741314 ps |
| CPU time | 257.84 seconds |
| Started | Sep 01 09:07:44 PM UTC 24 |
| Finished | Sep 01 09:12:06 PM UTC 24 |
| Peak memory | 417588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773498666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.1773498666 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/18.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/18.kmac_key_error.1405750943 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 2808093991 ps |
| CPU time | 7.09 seconds |
| Started | Sep 01 09:07:45 PM UTC 24 |
| Finished | Sep 01 09:07:53 PM UTC 24 |
| Peak memory | 232492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405750943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.1405750943 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/18.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/18.kmac_lc_escalation.2420622857 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 39416164 ps |
| CPU time | 1.89 seconds |
| Started | Sep 01 09:07:54 PM UTC 24 |
| Finished | Sep 01 09:07:57 PM UTC 24 |
| Peak memory | 229680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420622857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.2420622857 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/18.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/18.kmac_long_msg_and_output.1152120360 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 42170497503 ps |
| CPU time | 577.39 seconds |
| Started | Sep 01 09:07:18 PM UTC 24 |
| Finished | Sep 01 09:17:03 PM UTC 24 |
| Peak memory | 974640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152120360 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_and_output.1152120360 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/18.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/18.kmac_sideload.1394591162 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 11115564781 ps |
| CPU time | 225.97 seconds |
| Started | Sep 01 09:07:19 PM UTC 24 |
| Finished | Sep 01 09:11:09 PM UTC 24 |
| Peak memory | 313080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394591162 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.1394591162 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/18.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/18.kmac_smoke.2976376815 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 1696624190 ps |
| CPU time | 47.53 seconds |
| Started | Sep 01 09:07:18 PM UTC 24 |
| Finished | Sep 01 09:08:07 PM UTC 24 |
| Peak memory | 230512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976376815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.2976376815 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/18.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/18.kmac_stress_all.1892710035 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 10583584542 ps |
| CPU time | 187.26 seconds |
| Started | Sep 01 09:07:58 PM UTC 24 |
| Finished | Sep 01 09:11:08 PM UTC 24 |
| Peak memory | 272732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892710035 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.1892710035 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/18.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/19.kmac_alert_test.3549723278 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 64421652 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 09:08:55 PM UTC 24 |
| Finished | Sep 01 09:08:58 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549723278 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.3549723278 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/19.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/19.kmac_app.1407229682 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 8163542301 ps |
| CPU time | 165.65 seconds |
| Started | Sep 01 09:08:20 PM UTC 24 |
| Finished | Sep 01 09:11:08 PM UTC 24 |
| Peak memory | 286436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407229682 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.1407229682 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/19.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/19.kmac_burst_write.2408665415 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 40084713641 ps |
| CPU time | 763.11 seconds |
| Started | Sep 01 09:08:08 PM UTC 24 |
| Finished | Sep 01 09:21:01 PM UTC 24 |
| Peak memory | 263980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408665415 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.2408665415 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/19.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/19.kmac_edn_timeout_error.1229998743 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 1411421375 ps |
| CPU time | 37.05 seconds |
| Started | Sep 01 09:08:43 PM UTC 24 |
| Finished | Sep 01 09:09:21 PM UTC 24 |
| Peak memory | 235172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229998743 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.1229998743 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/19.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/19.kmac_entropy_mode_error.1568489879 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 1108597000 ps |
| CPU time | 27.13 seconds |
| Started | Sep 01 09:08:44 PM UTC 24 |
| Finished | Sep 01 09:09:12 PM UTC 24 |
| Peak memory | 234992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568489879 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.1568489879 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/19.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/19.kmac_entropy_refresh.1489034859 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 75844279305 ps |
| CPU time | 504.37 seconds |
| Started | Sep 01 09:08:23 PM UTC 24 |
| Finished | Sep 01 09:16:54 PM UTC 24 |
| Peak memory | 556776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489034859 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.1489034859 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/19.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/19.kmac_error.2355425306 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 1871226924 ps |
| CPU time | 67.18 seconds |
| Started | Sep 01 09:08:26 PM UTC 24 |
| Finished | Sep 01 09:09:35 PM UTC 24 |
| Peak memory | 282296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355425306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.2355425306 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/19.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/19.kmac_key_error.3179759096 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 856622137 ps |
| CPU time | 5.35 seconds |
| Started | Sep 01 09:08:36 PM UTC 24 |
| Finished | Sep 01 09:08:42 PM UTC 24 |
| Peak memory | 230664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179759096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.3179759096 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/19.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/19.kmac_lc_escalation.734570273 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 28916247 ps |
| CPU time | 1.86 seconds |
| Started | Sep 01 09:08:46 PM UTC 24 |
| Finished | Sep 01 09:08:49 PM UTC 24 |
| Peak memory | 231792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734570273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.734570273 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/19.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/19.kmac_long_msg_and_output.2518305648 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 117595442113 ps |
| CPU time | 4524.1 seconds |
| Started | Sep 01 09:08:01 PM UTC 24 |
| Finished | Sep 01 10:24:16 PM UTC 24 |
| Peak memory | 4163564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518305648 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_and_output.2518305648 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/19.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/19.kmac_sideload.1064890850 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 3442208862 ps |
| CPU time | 317.86 seconds |
| Started | Sep 01 09:08:07 PM UTC 24 |
| Finished | Sep 01 09:13:30 PM UTC 24 |
| Peak memory | 360176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064890850 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.1064890850 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/19.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/19.kmac_smoke.1429273017 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 1060227907 ps |
| CPU time | 18.64 seconds |
| Started | Sep 01 09:07:59 PM UTC 24 |
| Finished | Sep 01 09:08:19 PM UTC 24 |
| Peak memory | 232576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429273017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.1429273017 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/19.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/19.kmac_stress_all.917442459 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 57149308919 ps |
| CPU time | 1741.84 seconds |
| Started | Sep 01 09:08:50 PM UTC 24 |
| Finished | Sep 01 09:38:14 PM UTC 24 |
| Peak memory | 970556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917442459 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.917442459 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/19.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/2.kmac_alert_test.2230023293 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 47883279 ps |
| CPU time | 1.3 seconds |
| Started | Sep 01 08:50:38 PM UTC 24 |
| Finished | Sep 01 08:50:41 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230023293 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.2230023293 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/2.kmac_app.3898879018 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 18549069254 ps |
| CPU time | 217.53 seconds |
| Started | Sep 01 08:49:42 PM UTC 24 |
| Finished | Sep 01 08:53:23 PM UTC 24 |
| Peak memory | 395196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898879018 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.3898879018 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/2.kmac_app_with_partial_data.292435153 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 6599636103 ps |
| CPU time | 64.19 seconds |
| Started | Sep 01 08:49:43 PM UTC 24 |
| Finished | Sep 01 08:50:49 PM UTC 24 |
| Peak memory | 264172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292435153 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.292435153 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/2.kmac_burst_write.1308396784 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 2459574644 ps |
| CPU time | 259.27 seconds |
| Started | Sep 01 08:49:16 PM UTC 24 |
| Finished | Sep 01 08:53:39 PM UTC 24 |
| Peak memory | 237356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308396784 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.1308396784 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/2.kmac_edn_timeout_error.1580373890 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 18390524805 ps |
| CPU time | 58.72 seconds |
| Started | Sep 01 08:50:03 PM UTC 24 |
| Finished | Sep 01 08:51:03 PM UTC 24 |
| Peak memory | 235048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580373890 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.1580373890 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_mode_error.3196925817 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 766142966 ps |
| CPU time | 31.86 seconds |
| Started | Sep 01 08:50:04 PM UTC 24 |
| Finished | Sep 01 08:50:37 PM UTC 24 |
| Peak memory | 234984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196925817 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.3196925817 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_ready_error.3246648068 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 5764970485 ps |
| CPU time | 66.89 seconds |
| Started | Sep 01 08:50:06 PM UTC 24 |
| Finished | Sep 01 08:51:15 PM UTC 24 |
| Peak memory | 230532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246648068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.3246648068 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_refresh.3255587660 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9910037339 ps |
| CPU time | 210.68 seconds |
| Started | Sep 01 08:49:46 PM UTC 24 |
| Finished | Sep 01 08:53:20 PM UTC 24 |
| Peak memory | 386864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255587660 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.3255587660 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/2.kmac_error.3876092129 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 3380311421 ps |
| CPU time | 60.33 seconds |
| Started | Sep 01 08:49:54 PM UTC 24 |
| Finished | Sep 01 08:50:57 PM UTC 24 |
| Peak memory | 268084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876092129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.3876092129 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/2.kmac_key_error.1753250987 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 2527423162 ps |
| CPU time | 14.14 seconds |
| Started | Sep 01 08:49:58 PM UTC 24 |
| Finished | Sep 01 08:50:13 PM UTC 24 |
| Peak memory | 230640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753250987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.1753250987 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/2.kmac_lc_escalation.1795377180 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 157650257 ps |
| CPU time | 2.02 seconds |
| Started | Sep 01 08:50:14 PM UTC 24 |
| Finished | Sep 01 08:50:17 PM UTC 24 |
| Peak memory | 230528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795377180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.1795377180 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/2.kmac_long_msg_and_output.3976612405 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 21209589495 ps |
| CPU time | 1157.81 seconds |
| Started | Sep 01 08:49:11 PM UTC 24 |
| Finished | Sep 01 09:08:46 PM UTC 24 |
| Peak memory | 911396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976612405 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and_output.3976612405 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/2.kmac_mubi.958642463 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 12896772559 ps |
| CPU time | 396.17 seconds |
| Started | Sep 01 08:49:54 PM UTC 24 |
| Finished | Sep 01 08:56:37 PM UTC 24 |
| Peak memory | 526580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958642463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.958642463 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/2.kmac_sec_cm.3989673119 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 3238682712 ps |
| CPU time | 32.18 seconds |
| Started | Sep 01 08:50:21 PM UTC 24 |
| Finished | Sep 01 08:50:55 PM UTC 24 |
| Peak memory | 265224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989673119 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.3989673119 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/2.kmac_sideload.3395279307 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 12853195354 ps |
| CPU time | 379.75 seconds |
| Started | Sep 01 08:49:13 PM UTC 24 |
| Finished | Sep 01 08:55:37 PM UTC 24 |
| Peak memory | 564988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395279307 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.3395279307 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/2.kmac_smoke.507288644 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 980598911 ps |
| CPU time | 52.77 seconds |
| Started | Sep 01 08:49:08 PM UTC 24 |
| Finished | Sep 01 08:50:03 PM UTC 24 |
| Peak memory | 230652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507288644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.507288644 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/2.kmac_stress_all.1628025812 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 98656453072 ps |
| CPU time | 689.96 seconds |
| Started | Sep 01 08:50:15 PM UTC 24 |
| Finished | Sep 01 09:01:54 PM UTC 24 |
| Peak memory | 1034036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628025812 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.1628025812 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac.99420058 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 200525984 ps |
| CPU time | 4.18 seconds |
| Started | Sep 01 08:49:37 PM UTC 24 |
| Finished | Sep 01 08:49:42 PM UTC 24 |
| Peak memory | 230516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99420058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vec tors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac.99420058 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac_xof.3277727838 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 54747787 ps |
| CPU time | 2.64 seconds |
| Started | Sep 01 08:49:42 PM UTC 24 |
| Finished | Sep 01 08:49:46 PM UTC 24 |
| Peak memory | 229996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277727838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.3277727838 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_224.956855038 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 138781475692 ps |
| CPU time | 2820.88 seconds |
| Started | Sep 01 08:49:21 PM UTC 24 |
| Finished | Sep 01 09:36:54 PM UTC 24 |
| Peak memory | 3145552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956855038 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.956855038 + enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_256.846132298 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 193480238285 ps |
| CPU time | 2502.35 seconds |
| Started | Sep 01 08:49:25 PM UTC 24 |
| Finished | Sep 01 09:31:37 PM UTC 24 |
| Peak memory | 3086156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846132298 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.846132298 + enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_384.2133137164 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 59244842666 ps |
| CPU time | 1824.83 seconds |
| Started | Sep 01 08:49:27 PM UTC 24 |
| Finished | Sep 01 09:20:13 PM UTC 24 |
| Peak memory | 2320024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133137164 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.2133137164 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_512.3258030060 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 47419609937 ps |
| CPU time | 1249.88 seconds |
| Started | Sep 01 08:49:29 PM UTC 24 |
| Finished | Sep 01 09:10:34 PM UTC 24 |
| Peak memory | 1674908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258030060 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.3258030060 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_128.3510230946 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 169899536458 ps |
| CPU time | 293.53 seconds |
| Started | Sep 01 08:49:32 PM UTC 24 |
| Finished | Sep 01 08:54:30 PM UTC 24 |
| Peak memory | 440016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510230946 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.3510230 946 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_256.390549284 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 5440778879 ps |
| CPU time | 330.58 seconds |
| Started | Sep 01 08:49:33 PM UTC 24 |
| Finished | Sep 01 08:55:08 PM UTC 24 |
| Peak memory | 263828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390549284 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.39054928 4 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/20.kmac_alert_test.2664695795 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 53637818 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 09:10:28 PM UTC 24 |
| Finished | Sep 01 09:10:31 PM UTC 24 |
| Peak memory | 216292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664695795 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.2664695795 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/20.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/20.kmac_app.1812698055 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 22071274865 ps |
| CPU time | 277.55 seconds |
| Started | Sep 01 09:09:34 PM UTC 24 |
| Finished | Sep 01 09:14:16 PM UTC 24 |
| Peak memory | 347936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812698055 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.1812698055 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/20.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/20.kmac_burst_write.624375408 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 24513515283 ps |
| CPU time | 634.76 seconds |
| Started | Sep 01 09:09:23 PM UTC 24 |
| Finished | Sep 01 09:20:06 PM UTC 24 |
| Peak memory | 253744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624375408 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.624375408 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/20.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/20.kmac_entropy_refresh.489139 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 9662562389 ps |
| CPU time | 218.1 seconds |
| Started | Sep 01 09:09:36 PM UTC 24 |
| Finished | Sep 01 09:13:18 PM UTC 24 |
| Peak memory | 374512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489139 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.489139 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/20.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/20.kmac_error.1183361823 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 2837262428 ps |
| CPU time | 259.52 seconds |
| Started | Sep 01 09:09:39 PM UTC 24 |
| Finished | Sep 01 09:14:03 PM UTC 24 |
| Peak memory | 327424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183361823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.1183361823 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/20.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/20.kmac_key_error.3195775773 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 115360732 ps |
| CPU time | 1.67 seconds |
| Started | Sep 01 09:10:02 PM UTC 24 |
| Finished | Sep 01 09:10:05 PM UTC 24 |
| Peak memory | 229800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195775773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.3195775773 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/20.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/20.kmac_lc_escalation.468811248 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 973242821 ps |
| CPU time | 21 seconds |
| Started | Sep 01 09:10:05 PM UTC 24 |
| Finished | Sep 01 09:10:27 PM UTC 24 |
| Peak memory | 261864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468811248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.468811248 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/20.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/20.kmac_long_msg_and_output.3020036351 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 19619787142 ps |
| CPU time | 792.71 seconds |
| Started | Sep 01 09:09:02 PM UTC 24 |
| Finished | Sep 01 09:22:25 PM UTC 24 |
| Peak memory | 1128224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020036351 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_and_output.3020036351 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/20.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/20.kmac_sideload.3765698573 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 2353792760 ps |
| CPU time | 216.55 seconds |
| Started | Sep 01 09:09:14 PM UTC 24 |
| Finished | Sep 01 09:12:54 PM UTC 24 |
| Peak memory | 309020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765698573 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.3765698573 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/20.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/20.kmac_smoke.1516162972 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 2563148813 ps |
| CPU time | 38.43 seconds |
| Started | Sep 01 09:08:58 PM UTC 24 |
| Finished | Sep 01 09:09:38 PM UTC 24 |
| Peak memory | 235068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516162972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.1516162972 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/20.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/20.kmac_stress_all.2940626449 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 106104570396 ps |
| CPU time | 1170.2 seconds |
| Started | Sep 01 09:10:15 PM UTC 24 |
| Finished | Sep 01 09:30:01 PM UTC 24 |
| Peak memory | 415472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940626449 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.2940626449 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/20.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/21.kmac_alert_test.2197543237 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 16132306 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 09:11:19 PM UTC 24 |
| Finished | Sep 01 09:11:21 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197543237 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.2197543237 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/21.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/21.kmac_app.3913219878 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 71393350291 ps |
| CPU time | 336.32 seconds |
| Started | Sep 01 09:10:46 PM UTC 24 |
| Finished | Sep 01 09:16:28 PM UTC 24 |
| Peak memory | 337776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913219878 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.3913219878 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/21.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/21.kmac_burst_write.2527036250 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 23324651058 ps |
| CPU time | 764.73 seconds |
| Started | Sep 01 09:10:35 PM UTC 24 |
| Finished | Sep 01 09:23:31 PM UTC 24 |
| Peak memory | 257824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527036250 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.2527036250 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/21.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/21.kmac_entropy_refresh.954386720 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 18049579281 ps |
| CPU time | 118.89 seconds |
| Started | Sep 01 09:11:01 PM UTC 24 |
| Finished | Sep 01 09:13:03 PM UTC 24 |
| Peak memory | 272288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954386720 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.954386720 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/21.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/21.kmac_error.3553145890 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 6747155446 ps |
| CPU time | 151.4 seconds |
| Started | Sep 01 09:11:09 PM UTC 24 |
| Finished | Sep 01 09:13:44 PM UTC 24 |
| Peak memory | 374424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553145890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.3553145890 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/21.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/21.kmac_key_error.2736846339 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 839563403 ps |
| CPU time | 8.49 seconds |
| Started | Sep 01 09:11:09 PM UTC 24 |
| Finished | Sep 01 09:11:19 PM UTC 24 |
| Peak memory | 230512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736846339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.2736846339 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/21.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/21.kmac_lc_escalation.1053829470 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 157888242 ps |
| CPU time | 6.26 seconds |
| Started | Sep 01 09:11:11 PM UTC 24 |
| Finished | Sep 01 09:11:18 PM UTC 24 |
| Peak memory | 234680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053829470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.1053829470 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/21.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/21.kmac_long_msg_and_output.1131916359 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 23523608581 ps |
| CPU time | 2902.74 seconds |
| Started | Sep 01 09:10:32 PM UTC 24 |
| Finished | Sep 01 09:59:30 PM UTC 24 |
| Peak memory | 1697696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131916359 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_and_output.1131916359 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/21.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/21.kmac_sideload.1677650875 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 5764560974 ps |
| CPU time | 107.5 seconds |
| Started | Sep 01 09:10:34 PM UTC 24 |
| Finished | Sep 01 09:12:24 PM UTC 24 |
| Peak memory | 306968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677650875 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.1677650875 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/21.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/21.kmac_smoke.584339870 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 1861189788 ps |
| CPU time | 28.87 seconds |
| Started | Sep 01 09:10:30 PM UTC 24 |
| Finished | Sep 01 09:11:01 PM UTC 24 |
| Peak memory | 230676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584339870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.584339870 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/21.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/21.kmac_stress_all.811847120 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 28766462680 ps |
| CPU time | 742.28 seconds |
| Started | Sep 01 09:11:11 PM UTC 24 |
| Finished | Sep 01 09:23:43 PM UTC 24 |
| Peak memory | 575276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811847120 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.811847120 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/21.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/22.kmac_alert_test.2685646524 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 55739432 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 09:12:11 PM UTC 24 |
| Finished | Sep 01 09:12:13 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685646524 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.2685646524 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/22.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/22.kmac_app.1143731756 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 6219373998 ps |
| CPU time | 102.51 seconds |
| Started | Sep 01 09:11:41 PM UTC 24 |
| Finished | Sep 01 09:13:26 PM UTC 24 |
| Peak memory | 290668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143731756 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.1143731756 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/22.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/22.kmac_burst_write.2838592154 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 9323472453 ps |
| CPU time | 126.91 seconds |
| Started | Sep 01 09:11:37 PM UTC 24 |
| Finished | Sep 01 09:13:46 PM UTC 24 |
| Peak memory | 235280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838592154 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.2838592154 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/22.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/22.kmac_entropy_refresh.1304798834 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 13290307525 ps |
| CPU time | 241.56 seconds |
| Started | Sep 01 09:11:41 PM UTC 24 |
| Finished | Sep 01 09:15:47 PM UTC 24 |
| Peak memory | 384760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304798834 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.1304798834 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/22.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/22.kmac_error.1674576236 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 3677859586 ps |
| CPU time | 293.32 seconds |
| Started | Sep 01 09:12:00 PM UTC 24 |
| Finished | Sep 01 09:16:58 PM UTC 24 |
| Peak memory | 356096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674576236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.1674576236 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/22.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/22.kmac_key_error.1922932193 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 4373654382 ps |
| CPU time | 6.71 seconds |
| Started | Sep 01 09:12:01 PM UTC 24 |
| Finished | Sep 01 09:12:09 PM UTC 24 |
| Peak memory | 230636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922932193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.1922932193 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/22.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/22.kmac_lc_escalation.1523168700 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 39195285 ps |
| CPU time | 1.83 seconds |
| Started | Sep 01 09:12:07 PM UTC 24 |
| Finished | Sep 01 09:12:10 PM UTC 24 |
| Peak memory | 231780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523168700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.1523168700 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/22.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/22.kmac_long_msg_and_output.2176315233 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 45983500265 ps |
| CPU time | 2552.42 seconds |
| Started | Sep 01 09:11:22 PM UTC 24 |
| Finished | Sep 01 09:54:25 PM UTC 24 |
| Peak memory | 1613624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176315233 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_and_output.2176315233 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/22.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/22.kmac_sideload.2551967193 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 13723078386 ps |
| CPU time | 132.28 seconds |
| Started | Sep 01 09:11:25 PM UTC 24 |
| Finished | Sep 01 09:13:40 PM UTC 24 |
| Peak memory | 323384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551967193 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.2551967193 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/22.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/22.kmac_smoke.417257654 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 304248834 ps |
| CPU time | 19.36 seconds |
| Started | Sep 01 09:11:20 PM UTC 24 |
| Finished | Sep 01 09:11:40 PM UTC 24 |
| Peak memory | 230768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417257654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.417257654 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/22.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/22.kmac_stress_all.1576579634 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 66227929792 ps |
| CPU time | 1725.53 seconds |
| Started | Sep 01 09:12:10 PM UTC 24 |
| Finished | Sep 01 09:41:16 PM UTC 24 |
| Peak memory | 1267980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576579634 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.1576579634 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/22.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/23.kmac_alert_test.809508593 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 59259548 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 09:13:23 PM UTC 24 |
| Finished | Sep 01 09:13:26 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809508593 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.809508593 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/23.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/23.kmac_app.2730166467 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 65552051916 ps |
| CPU time | 205.95 seconds |
| Started | Sep 01 09:12:50 PM UTC 24 |
| Finished | Sep 01 09:16:19 PM UTC 24 |
| Peak memory | 385076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730166467 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.2730166467 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/23.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/23.kmac_burst_write.3749017007 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 24756174461 ps |
| CPU time | 994.48 seconds |
| Started | Sep 01 09:12:25 PM UTC 24 |
| Finished | Sep 01 09:29:12 PM UTC 24 |
| Peak memory | 266020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749017007 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.3749017007 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/23.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/23.kmac_entropy_refresh.3511757225 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 10865031447 ps |
| CPU time | 141.95 seconds |
| Started | Sep 01 09:12:55 PM UTC 24 |
| Finished | Sep 01 09:15:19 PM UTC 24 |
| Peak memory | 274156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511757225 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.3511757225 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/23.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/23.kmac_error.2181504699 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 64173216264 ps |
| CPU time | 282.72 seconds |
| Started | Sep 01 09:13:04 PM UTC 24 |
| Finished | Sep 01 09:17:51 PM UTC 24 |
| Peak memory | 454444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181504699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.2181504699 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/23.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/23.kmac_key_error.2993311293 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 1918180330 ps |
| CPU time | 10.91 seconds |
| Started | Sep 01 09:13:16 PM UTC 24 |
| Finished | Sep 01 09:13:28 PM UTC 24 |
| Peak memory | 230392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993311293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.2993311293 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/23.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/23.kmac_lc_escalation.1424096494 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 88541505 ps |
| CPU time | 2.74 seconds |
| Started | Sep 01 09:13:19 PM UTC 24 |
| Finished | Sep 01 09:13:23 PM UTC 24 |
| Peak memory | 235300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424096494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.1424096494 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/23.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/23.kmac_long_msg_and_output.1741676656 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 27364184838 ps |
| CPU time | 417.89 seconds |
| Started | Sep 01 09:12:14 PM UTC 24 |
| Finished | Sep 01 09:19:18 PM UTC 24 |
| Peak memory | 757524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741676656 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_and_output.1741676656 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/23.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/23.kmac_sideload.362583742 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 709040516 ps |
| CPU time | 60.28 seconds |
| Started | Sep 01 09:12:25 PM UTC 24 |
| Finished | Sep 01 09:13:27 PM UTC 24 |
| Peak memory | 249708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362583742 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.362583742 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/23.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/23.kmac_smoke.195785463 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 531545173 ps |
| CPU time | 33.08 seconds |
| Started | Sep 01 09:12:14 PM UTC 24 |
| Finished | Sep 01 09:12:49 PM UTC 24 |
| Peak memory | 232516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195785463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.195785463 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/23.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/23.kmac_stress_all.314041379 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 82427793171 ps |
| CPU time | 1658.27 seconds |
| Started | Sep 01 09:13:21 PM UTC 24 |
| Finished | Sep 01 09:41:20 PM UTC 24 |
| Peak memory | 1071120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314041379 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.314041379 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/23.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/24.kmac_alert_test.3781251828 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 30628492 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 09:13:51 PM UTC 24 |
| Finished | Sep 01 09:13:54 PM UTC 24 |
| Peak memory | 216232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781251828 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.3781251828 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/24.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/24.kmac_app.943745945 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 13785188606 ps |
| CPU time | 100.18 seconds |
| Started | Sep 01 09:13:31 PM UTC 24 |
| Finished | Sep 01 09:15:13 PM UTC 24 |
| Peak memory | 306960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943745945 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.943745945 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/24.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/24.kmac_burst_write.1708928368 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 33556565529 ps |
| CPU time | 785.54 seconds |
| Started | Sep 01 09:13:29 PM UTC 24 |
| Finished | Sep 01 09:26:45 PM UTC 24 |
| Peak memory | 251672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708928368 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.1708928368 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/24.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/24.kmac_entropy_refresh.3314440519 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 16282797589 ps |
| CPU time | 438.17 seconds |
| Started | Sep 01 09:13:41 PM UTC 24 |
| Finished | Sep 01 09:21:06 PM UTC 24 |
| Peak memory | 511772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314440519 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.3314440519 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/24.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/24.kmac_error.3342433156 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 6674286408 ps |
| CPU time | 168.31 seconds |
| Started | Sep 01 09:13:42 PM UTC 24 |
| Finished | Sep 01 09:16:33 PM UTC 24 |
| Peak memory | 417788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342433156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.3342433156 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/24.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/24.kmac_key_error.3276642780 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 181099188 ps |
| CPU time | 2.09 seconds |
| Started | Sep 01 09:13:44 PM UTC 24 |
| Finished | Sep 01 09:13:47 PM UTC 24 |
| Peak memory | 230376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276642780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.3276642780 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/24.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/24.kmac_lc_escalation.2965884102 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 29616617 ps |
| CPU time | 2.12 seconds |
| Started | Sep 01 09:13:47 PM UTC 24 |
| Finished | Sep 01 09:13:50 PM UTC 24 |
| Peak memory | 230520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965884102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.2965884102 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/24.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/24.kmac_long_msg_and_output.3802299520 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 94270623411 ps |
| CPU time | 4936.81 seconds |
| Started | Sep 01 09:13:26 PM UTC 24 |
| Finished | Sep 01 10:36:40 PM UTC 24 |
| Peak memory | 4458276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802299520 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_and_output.3802299520 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/24.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/24.kmac_sideload.2578512763 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 1483321901 ps |
| CPU time | 111.8 seconds |
| Started | Sep 01 09:13:28 PM UTC 24 |
| Finished | Sep 01 09:15:22 PM UTC 24 |
| Peak memory | 282332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578512763 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.2578512763 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/24.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/24.kmac_smoke.1550298380 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 4258247236 ps |
| CPU time | 62.97 seconds |
| Started | Sep 01 09:13:26 PM UTC 24 |
| Finished | Sep 01 09:14:31 PM UTC 24 |
| Peak memory | 230584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550298380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.1550298380 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/24.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/24.kmac_stress_all.1874734797 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 144111941554 ps |
| CPU time | 4068.36 seconds |
| Started | Sep 01 09:13:48 PM UTC 24 |
| Finished | Sep 01 10:22:23 PM UTC 24 |
| Peak memory | 1693684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874734797 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.1874734797 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/24.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/25.kmac_alert_test.2985529848 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 19477819 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 09:14:40 PM UTC 24 |
| Finished | Sep 01 09:14:42 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985529848 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.2985529848 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/25.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/25.kmac_app.478716993 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 25148211991 ps |
| CPU time | 97.38 seconds |
| Started | Sep 01 09:14:07 PM UTC 24 |
| Finished | Sep 01 09:15:46 PM UTC 24 |
| Peak memory | 263908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478716993 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.478716993 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/25.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/25.kmac_burst_write.1061656054 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 100130656049 ps |
| CPU time | 1168.71 seconds |
| Started | Sep 01 09:14:06 PM UTC 24 |
| Finished | Sep 01 09:33:49 PM UTC 24 |
| Peak memory | 268284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061656054 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.1061656054 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/25.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/25.kmac_entropy_refresh.4150891150 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 30584212753 ps |
| CPU time | 231.17 seconds |
| Started | Sep 01 09:14:17 PM UTC 24 |
| Finished | Sep 01 09:18:12 PM UTC 24 |
| Peak memory | 305004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150891150 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.4150891150 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/25.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/25.kmac_key_error.689719921 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 3276280938 ps |
| CPU time | 17.11 seconds |
| Started | Sep 01 09:14:33 PM UTC 24 |
| Finished | Sep 01 09:14:51 PM UTC 24 |
| Peak memory | 230444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689719921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.689719921 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/25.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/25.kmac_lc_escalation.1014417333 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 122559510 ps |
| CPU time | 2.17 seconds |
| Started | Sep 01 09:14:36 PM UTC 24 |
| Finished | Sep 01 09:14:39 PM UTC 24 |
| Peak memory | 230456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014417333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.1014417333 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/25.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/25.kmac_long_msg_and_output.590651277 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 47848866653 ps |
| CPU time | 1978.4 seconds |
| Started | Sep 01 09:13:54 PM UTC 24 |
| Finished | Sep 01 09:47:16 PM UTC 24 |
| Peak memory | 2392112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590651277 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_and_output.590651277 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/25.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/25.kmac_sideload.2565432136 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 8485263521 ps |
| CPU time | 222.94 seconds |
| Started | Sep 01 09:14:03 PM UTC 24 |
| Finished | Sep 01 09:17:50 PM UTC 24 |
| Peak memory | 311040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565432136 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.2565432136 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/25.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/25.kmac_smoke.1720867807 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 16298214856 ps |
| CPU time | 44.23 seconds |
| Started | Sep 01 09:13:51 PM UTC 24 |
| Finished | Sep 01 09:14:37 PM UTC 24 |
| Peak memory | 230544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720867807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.1720867807 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/25.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/25.kmac_stress_all.1257428818 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 13584403010 ps |
| CPU time | 993 seconds |
| Started | Sep 01 09:14:38 PM UTC 24 |
| Finished | Sep 01 09:31:23 PM UTC 24 |
| Peak memory | 696312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257428818 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.1257428818 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/25.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/26.kmac_alert_test.4261511550 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 49913935 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 09:15:57 PM UTC 24 |
| Finished | Sep 01 09:15:59 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261511550 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.4261511550 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/26.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/26.kmac_app.2036045644 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 25787359222 ps |
| CPU time | 183.42 seconds |
| Started | Sep 01 09:15:23 PM UTC 24 |
| Finished | Sep 01 09:18:29 PM UTC 24 |
| Peak memory | 366560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036045644 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.2036045644 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/26.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/26.kmac_burst_write.3196421163 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 16737839040 ps |
| CPU time | 387.3 seconds |
| Started | Sep 01 09:15:21 PM UTC 24 |
| Finished | Sep 01 09:21:54 PM UTC 24 |
| Peak memory | 251876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196421163 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.3196421163 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/26.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/26.kmac_entropy_refresh.2843846574 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 1124893058 ps |
| CPU time | 26.24 seconds |
| Started | Sep 01 09:15:36 PM UTC 24 |
| Finished | Sep 01 09:16:04 PM UTC 24 |
| Peak memory | 247732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843846574 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.2843846574 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/26.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/26.kmac_error.1523626369 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 10059538712 ps |
| CPU time | 398.97 seconds |
| Started | Sep 01 09:15:47 PM UTC 24 |
| Finished | Sep 01 09:22:32 PM UTC 24 |
| Peak memory | 511796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523626369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.1523626369 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/26.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/26.kmac_key_error.2570308780 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 1348716802 ps |
| CPU time | 2.93 seconds |
| Started | Sep 01 09:15:48 PM UTC 24 |
| Finished | Sep 01 09:15:52 PM UTC 24 |
| Peak memory | 230332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570308780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.2570308780 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/26.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/26.kmac_lc_escalation.1425541500 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 46395971 ps |
| CPU time | 1.96 seconds |
| Started | Sep 01 09:15:53 PM UTC 24 |
| Finished | Sep 01 09:15:56 PM UTC 24 |
| Peak memory | 229800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425541500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.1425541500 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/26.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/26.kmac_long_msg_and_output.2075627383 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 369110194424 ps |
| CPU time | 4796.72 seconds |
| Started | Sep 01 09:14:52 PM UTC 24 |
| Finished | Sep 01 10:35:43 PM UTC 24 |
| Peak memory | 4341548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075627383 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_and_output.2075627383 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/26.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/26.kmac_sideload.1329300589 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 7974523733 ps |
| CPU time | 203.16 seconds |
| Started | Sep 01 09:15:14 PM UTC 24 |
| Finished | Sep 01 09:18:41 PM UTC 24 |
| Peak memory | 296772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329300589 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.1329300589 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/26.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/26.kmac_smoke.1780126367 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 54814447251 ps |
| CPU time | 87.36 seconds |
| Started | Sep 01 09:14:43 PM UTC 24 |
| Finished | Sep 01 09:16:13 PM UTC 24 |
| Peak memory | 235016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780126367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.1780126367 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/26.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/26.kmac_stress_all.1864969036 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 103087870234 ps |
| CPU time | 653.77 seconds |
| Started | Sep 01 09:15:54 PM UTC 24 |
| Finished | Sep 01 09:26:57 PM UTC 24 |
| Peak memory | 362936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864969036 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.1864969036 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/26.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/27.kmac_alert_test.3745584408 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 17163315 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 09:16:55 PM UTC 24 |
| Finished | Sep 01 09:16:57 PM UTC 24 |
| Peak memory | 216232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745584408 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.3745584408 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/27.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/27.kmac_app.4074669011 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 8357051967 ps |
| CPU time | 22.17 seconds |
| Started | Sep 01 09:16:29 PM UTC 24 |
| Finished | Sep 01 09:16:52 PM UTC 24 |
| Peak memory | 239412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074669011 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.4074669011 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/27.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/27.kmac_burst_write.1091787696 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 3337233924 ps |
| CPU time | 187.5 seconds |
| Started | Sep 01 09:16:20 PM UTC 24 |
| Finished | Sep 01 09:19:30 PM UTC 24 |
| Peak memory | 235500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091787696 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.1091787696 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/27.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/27.kmac_entropy_refresh.1994556604 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 117135665119 ps |
| CPU time | 473.95 seconds |
| Started | Sep 01 09:16:34 PM UTC 24 |
| Finished | Sep 01 09:24:35 PM UTC 24 |
| Peak memory | 493292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994556604 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.1994556604 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/27.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/27.kmac_error.4062910199 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 2324098135 ps |
| CPU time | 123.04 seconds |
| Started | Sep 01 09:16:34 PM UTC 24 |
| Finished | Sep 01 09:18:40 PM UTC 24 |
| Peak memory | 282400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062910199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.4062910199 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/27.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/27.kmac_key_error.3409598864 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 8956330523 ps |
| CPU time | 7.9 seconds |
| Started | Sep 01 09:16:39 PM UTC 24 |
| Finished | Sep 01 09:16:48 PM UTC 24 |
| Peak memory | 230528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409598864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.3409598864 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/27.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/27.kmac_lc_escalation.1279105192 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 233099412 ps |
| CPU time | 16.22 seconds |
| Started | Sep 01 09:16:49 PM UTC 24 |
| Finished | Sep 01 09:17:07 PM UTC 24 |
| Peak memory | 245452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279105192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.1279105192 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/27.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/27.kmac_long_msg_and_output.1152749035 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 19445476962 ps |
| CPU time | 1847.78 seconds |
| Started | Sep 01 09:16:04 PM UTC 24 |
| Finished | Sep 01 09:47:14 PM UTC 24 |
| Peak memory | 1363760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152749035 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_and_output.1152749035 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/27.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/27.kmac_sideload.2702670072 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 1330922576 ps |
| CPU time | 136.34 seconds |
| Started | Sep 01 09:16:13 PM UTC 24 |
| Finished | Sep 01 09:18:33 PM UTC 24 |
| Peak memory | 274412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702670072 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.2702670072 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/27.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/27.kmac_smoke.4164920643 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 716229280 ps |
| CPU time | 36.32 seconds |
| Started | Sep 01 09:16:00 PM UTC 24 |
| Finished | Sep 01 09:16:38 PM UTC 24 |
| Peak memory | 230512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164920643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.4164920643 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/27.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/27.kmac_stress_all.84611405 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 75167526889 ps |
| CPU time | 2512.08 seconds |
| Started | Sep 01 09:16:53 PM UTC 24 |
| Finished | Sep 01 09:59:15 PM UTC 24 |
| Peak memory | 2983724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84611405 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.84611405 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/27.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/28.kmac_alert_test.3386379998 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 15697812 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 09:18:12 PM UTC 24 |
| Finished | Sep 01 09:18:15 PM UTC 24 |
| Peak memory | 216232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386379998 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.3386379998 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/28.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/28.kmac_app.3368993556 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 52604787980 ps |
| CPU time | 324.83 seconds |
| Started | Sep 01 09:17:34 PM UTC 24 |
| Finished | Sep 01 09:23:03 PM UTC 24 |
| Peak memory | 515884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368993556 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.3368993556 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/28.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/28.kmac_burst_write.2563572041 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 2701793495 ps |
| CPU time | 278.72 seconds |
| Started | Sep 01 09:17:08 PM UTC 24 |
| Finished | Sep 01 09:21:51 PM UTC 24 |
| Peak memory | 239340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563572041 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.2563572041 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/28.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/28.kmac_entropy_refresh.3282754585 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 31288329979 ps |
| CPU time | 251.94 seconds |
| Started | Sep 01 09:17:49 PM UTC 24 |
| Finished | Sep 01 09:22:04 PM UTC 24 |
| Peak memory | 477108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282754585 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.3282754585 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/28.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/28.kmac_error.70608982 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 5139671863 ps |
| CPU time | 199.46 seconds |
| Started | Sep 01 09:17:51 PM UTC 24 |
| Finished | Sep 01 09:21:14 PM UTC 24 |
| Peak memory | 313148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70608982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.70608982 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/28.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/28.kmac_key_error.2361757966 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 15762227363 ps |
| CPU time | 25.2 seconds |
| Started | Sep 01 09:17:52 PM UTC 24 |
| Finished | Sep 01 09:18:18 PM UTC 24 |
| Peak memory | 230716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361757966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.2361757966 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/28.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/28.kmac_lc_escalation.1768309218 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 30403996 ps |
| CPU time | 2.25 seconds |
| Started | Sep 01 09:18:05 PM UTC 24 |
| Finished | Sep 01 09:18:08 PM UTC 24 |
| Peak memory | 230404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768309218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.1768309218 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/28.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/28.kmac_long_msg_and_output.3151531155 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 197374925137 ps |
| CPU time | 3672.94 seconds |
| Started | Sep 01 09:16:59 PM UTC 24 |
| Finished | Sep 01 10:18:55 PM UTC 24 |
| Peak memory | 3628784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151531155 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_and_output.3151531155 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/28.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/28.kmac_sideload.3579215381 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 96079478519 ps |
| CPU time | 668.46 seconds |
| Started | Sep 01 09:17:03 PM UTC 24 |
| Finished | Sep 01 09:28:21 PM UTC 24 |
| Peak memory | 638772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579215381 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.3579215381 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/28.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/28.kmac_smoke.2933255728 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 2107014986 ps |
| CPU time | 48.03 seconds |
| Started | Sep 01 09:16:58 PM UTC 24 |
| Finished | Sep 01 09:17:48 PM UTC 24 |
| Peak memory | 230524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933255728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.2933255728 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/28.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/28.kmac_stress_all.2208561744 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 391919619459 ps |
| CPU time | 732.26 seconds |
| Started | Sep 01 09:18:09 PM UTC 24 |
| Finished | Sep 01 09:30:31 PM UTC 24 |
| Peak memory | 505856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208561744 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.2208561744 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/28.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/29.kmac_alert_test.2046545915 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 174405541 ps |
| CPU time | 1.33 seconds |
| Started | Sep 01 09:19:31 PM UTC 24 |
| Finished | Sep 01 09:19:34 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046545915 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.2046545915 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/29.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/29.kmac_app.1738702885 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 9888922917 ps |
| CPU time | 229.82 seconds |
| Started | Sep 01 09:18:41 PM UTC 24 |
| Finished | Sep 01 09:22:35 PM UTC 24 |
| Peak memory | 425840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738702885 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.1738702885 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/29.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/29.kmac_burst_write.2228239536 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 6618595835 ps |
| CPU time | 145.81 seconds |
| Started | Sep 01 09:18:34 PM UTC 24 |
| Finished | Sep 01 09:21:03 PM UTC 24 |
| Peak memory | 247596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228239536 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.2228239536 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/29.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/29.kmac_entropy_refresh.3188074499 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 2925725574 ps |
| CPU time | 46.76 seconds |
| Started | Sep 01 09:18:43 PM UTC 24 |
| Finished | Sep 01 09:19:31 PM UTC 24 |
| Peak memory | 255800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188074499 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.3188074499 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/29.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/29.kmac_error.1807813905 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 34132402341 ps |
| CPU time | 471.59 seconds |
| Started | Sep 01 09:18:50 PM UTC 24 |
| Finished | Sep 01 09:26:48 PM UTC 24 |
| Peak memory | 583476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807813905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.1807813905 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/29.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/29.kmac_key_error.3317950701 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 6826086675 ps |
| CPU time | 19.58 seconds |
| Started | Sep 01 09:19:15 PM UTC 24 |
| Finished | Sep 01 09:19:36 PM UTC 24 |
| Peak memory | 230444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317950701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.3317950701 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/29.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/29.kmac_lc_escalation.261882673 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 281396709 ps |
| CPU time | 8.75 seconds |
| Started | Sep 01 09:19:19 PM UTC 24 |
| Finished | Sep 01 09:19:29 PM UTC 24 |
| Peak memory | 235360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261882673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.261882673 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/29.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/29.kmac_long_msg_and_output.417902686 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 80377630149 ps |
| CPU time | 1641.7 seconds |
| Started | Sep 01 09:18:19 PM UTC 24 |
| Finished | Sep 01 09:46:00 PM UTC 24 |
| Peak memory | 2121452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417902686 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_and_output.417902686 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/29.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/29.kmac_sideload.2029716697 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 14320690549 ps |
| CPU time | 510.13 seconds |
| Started | Sep 01 09:18:31 PM UTC 24 |
| Finished | Sep 01 09:27:08 PM UTC 24 |
| Peak memory | 608112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029716697 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.2029716697 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/29.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/29.kmac_smoke.2191179415 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 5764975673 ps |
| CPU time | 32.55 seconds |
| Started | Sep 01 09:18:15 PM UTC 24 |
| Finished | Sep 01 09:18:49 PM UTC 24 |
| Peak memory | 230856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191179415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.2191179415 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/29.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/29.kmac_stress_all.3867385503 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 136352600433 ps |
| CPU time | 3006.62 seconds |
| Started | Sep 01 09:19:30 PM UTC 24 |
| Finished | Sep 01 10:10:13 PM UTC 24 |
| Peak memory | 1863888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867385503 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.3867385503 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/29.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/3.kmac_alert_test.3490936983 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 34959630 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 08:52:11 PM UTC 24 |
| Finished | Sep 01 08:52:13 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490936983 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.3490936983 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/3.kmac_app.3340122834 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 4355530224 ps |
| CPU time | 63.84 seconds |
| Started | Sep 01 08:51:24 PM UTC 24 |
| Finished | Sep 01 08:52:30 PM UTC 24 |
| Peak memory | 247576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340122834 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.3340122834 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/3.kmac_app_with_partial_data.1757783672 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 28346309460 ps |
| CPU time | 157.6 seconds |
| Started | Sep 01 08:51:25 PM UTC 24 |
| Finished | Sep 01 08:54:06 PM UTC 24 |
| Peak memory | 339752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757783672 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.1757783672 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/3.kmac_burst_write.3201487969 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 19254822345 ps |
| CPU time | 211.47 seconds |
| Started | Sep 01 08:50:55 PM UTC 24 |
| Finished | Sep 01 08:54:30 PM UTC 24 |
| Peak memory | 237312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201487969 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.3201487969 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/3.kmac_edn_timeout_error.2130111335 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 322305518 ps |
| CPU time | 25.27 seconds |
| Started | Sep 01 08:51:46 PM UTC 24 |
| Finished | Sep 01 08:52:13 PM UTC 24 |
| Peak memory | 234972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130111335 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.2130111335 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_mode_error.3557826518 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 283748416 ps |
| CPU time | 7.75 seconds |
| Started | Sep 01 08:51:48 PM UTC 24 |
| Finished | Sep 01 08:51:57 PM UTC 24 |
| Peak memory | 234996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557826518 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.3557826518 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_ready_error.3253303423 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 3698248264 ps |
| CPU time | 50.43 seconds |
| Started | Sep 01 08:51:53 PM UTC 24 |
| Finished | Sep 01 08:52:45 PM UTC 24 |
| Peak memory | 230588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253303423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.3253303423 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_refresh.2357634900 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 2332530579 ps |
| CPU time | 147.7 seconds |
| Started | Sep 01 08:51:31 PM UTC 24 |
| Finished | Sep 01 08:54:02 PM UTC 24 |
| Peak memory | 276480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357634900 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.2357634900 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/3.kmac_error.2948311508 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 10638379448 ps |
| CPU time | 374.07 seconds |
| Started | Sep 01 08:51:40 PM UTC 24 |
| Finished | Sep 01 08:58:00 PM UTC 24 |
| Peak memory | 514028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948311508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.2948311508 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/3.kmac_key_error.2780084269 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1585675851 ps |
| CPU time | 15.23 seconds |
| Started | Sep 01 08:51:46 PM UTC 24 |
| Finished | Sep 01 08:52:03 PM UTC 24 |
| Peak memory | 230592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780084269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.2780084269 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/3.kmac_long_msg_and_output.2725054254 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 8350107840 ps |
| CPU time | 341.59 seconds |
| Started | Sep 01 08:50:42 PM UTC 24 |
| Finished | Sep 01 08:56:28 PM UTC 24 |
| Peak memory | 405356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725054254 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_and_output.2725054254 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/3.kmac_mubi.3141447799 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 3237398561 ps |
| CPU time | 95.8 seconds |
| Started | Sep 01 08:51:36 PM UTC 24 |
| Finished | Sep 01 08:53:14 PM UTC 24 |
| Peak memory | 305196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141447799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.3141447799 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/3.kmac_sec_cm.1596708697 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 7892448490 ps |
| CPU time | 98.49 seconds |
| Started | Sep 01 08:52:04 PM UTC 24 |
| Finished | Sep 01 08:53:45 PM UTC 24 |
| Peak memory | 302068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596708697 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.1596708697 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/3.kmac_sideload.1657463494 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 53208287571 ps |
| CPU time | 412.28 seconds |
| Started | Sep 01 08:50:50 PM UTC 24 |
| Finished | Sep 01 08:57:48 PM UTC 24 |
| Peak memory | 530420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657463494 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.1657463494 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/3.kmac_smoke.519383790 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 3276562590 ps |
| CPU time | 52.08 seconds |
| Started | Sep 01 08:50:41 PM UTC 24 |
| Finished | Sep 01 08:51:35 PM UTC 24 |
| Peak memory | 230532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519383790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.519383790 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/3.kmac_stress_all.4281481922 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 47654342042 ps |
| CPU time | 1693.02 seconds |
| Started | Sep 01 08:51:58 PM UTC 24 |
| Finished | Sep 01 09:20:31 PM UTC 24 |
| Peak memory | 1230868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281481922 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.4281481922 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac.2534149116 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 97392859 ps |
| CPU time | 1.92 seconds |
| Started | Sep 01 08:51:15 PM UTC 24 |
| Finished | Sep 01 08:51:18 PM UTC 24 |
| Peak memory | 229676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534149116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac.2534149116 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac_xof.1518152703 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 61225844 ps |
| CPU time | 3.06 seconds |
| Started | Sep 01 08:51:20 PM UTC 24 |
| Finished | Sep 01 08:51:24 PM UTC 24 |
| Peak memory | 230540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518152703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.1518152703 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_224.2126371963 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 2472865798 ps |
| CPU time | 50.37 seconds |
| Started | Sep 01 08:50:56 PM UTC 24 |
| Finished | Sep 01 08:51:48 PM UTC 24 |
| Peak memory | 232572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126371963 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.2126371963 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_256.3221603669 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 1212220764 ps |
| CPU time | 47.55 seconds |
| Started | Sep 01 08:50:56 PM UTC 24 |
| Finished | Sep 01 08:51:45 PM UTC 24 |
| Peak memory | 230524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221603669 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.3221603669 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_384.1567632843 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 277070632816 ps |
| CPU time | 1862.12 seconds |
| Started | Sep 01 08:50:58 PM UTC 24 |
| Finished | Sep 01 09:22:22 PM UTC 24 |
| Peak memory | 2348692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567632843 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.1567632843 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_512.3778510884 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 269028872 ps |
| CPU time | 17.1 seconds |
| Started | Sep 01 08:51:04 PM UTC 24 |
| Finished | Sep 01 08:51:22 PM UTC 24 |
| Peak memory | 228412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778510884 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.3778510884 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_128.526956795 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 294484978123 ps |
| CPU time | 3013.33 seconds |
| Started | Sep 01 08:51:14 PM UTC 24 |
| Finished | Sep 01 09:42:03 PM UTC 24 |
| Peak memory | 3614364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526956795 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.52695679 5 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_256.1415590452 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 29688700540 ps |
| CPU time | 372.57 seconds |
| Started | Sep 01 08:51:14 PM UTC 24 |
| Finished | Sep 01 08:57:32 PM UTC 24 |
| Peak memory | 360092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415590452 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.1415590 452 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/3.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/30.kmac_alert_test.3104451371 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 18761840 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 09:20:57 PM UTC 24 |
| Finished | Sep 01 09:21:00 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104451371 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.3104451371 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/30.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/30.kmac_app.4212624302 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 10968804323 ps |
| CPU time | 292.65 seconds |
| Started | Sep 01 09:20:07 PM UTC 24 |
| Finished | Sep 01 09:25:04 PM UTC 24 |
| Peak memory | 458608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212624302 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.4212624302 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/30.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/30.kmac_burst_write.1068718364 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 31155717335 ps |
| CPU time | 727.85 seconds |
| Started | Sep 01 09:19:58 PM UTC 24 |
| Finished | Sep 01 09:32:16 PM UTC 24 |
| Peak memory | 257788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068718364 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.1068718364 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/30.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/30.kmac_entropy_refresh.3085995861 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 6852226527 ps |
| CPU time | 133.97 seconds |
| Started | Sep 01 09:20:15 PM UTC 24 |
| Finished | Sep 01 09:22:32 PM UTC 24 |
| Peak memory | 333536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085995861 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.3085995861 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/30.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/30.kmac_error.256680549 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 22610328764 ps |
| CPU time | 392.1 seconds |
| Started | Sep 01 09:20:32 PM UTC 24 |
| Finished | Sep 01 09:27:10 PM UTC 24 |
| Peak memory | 550700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256680549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.256680549 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/30.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/30.kmac_key_error.2687947277 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 7523203948 ps |
| CPU time | 10.07 seconds |
| Started | Sep 01 09:20:40 PM UTC 24 |
| Finished | Sep 01 09:20:51 PM UTC 24 |
| Peak memory | 230780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687947277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.2687947277 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/30.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/30.kmac_lc_escalation.2498249103 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 80299265 ps |
| CPU time | 2.13 seconds |
| Started | Sep 01 09:20:52 PM UTC 24 |
| Finished | Sep 01 09:20:55 PM UTC 24 |
| Peak memory | 230668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498249103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.2498249103 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/30.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/30.kmac_long_msg_and_output.4024291444 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 78511814484 ps |
| CPU time | 2720.78 seconds |
| Started | Sep 01 09:19:34 PM UTC 24 |
| Finished | Sep 01 10:05:27 PM UTC 24 |
| Peak memory | 3038952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024291444 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_and_output.4024291444 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/30.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/30.kmac_sideload.3651295729 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 13699833611 ps |
| CPU time | 319.15 seconds |
| Started | Sep 01 09:19:36 PM UTC 24 |
| Finished | Sep 01 09:25:01 PM UTC 24 |
| Peak memory | 335608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651295729 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.3651295729 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/30.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/30.kmac_smoke.743620973 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 2241291003 ps |
| CPU time | 65.24 seconds |
| Started | Sep 01 09:19:32 PM UTC 24 |
| Finished | Sep 01 09:20:39 PM UTC 24 |
| Peak memory | 230712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743620973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.743620973 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/30.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/31.kmac_alert_test.3881329831 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 63276184 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 09:22:12 PM UTC 24 |
| Finished | Sep 01 09:22:14 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881329831 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.3881329831 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/31.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/31.kmac_app.1573250366 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 3965866303 ps |
| CPU time | 44.04 seconds |
| Started | Sep 01 09:21:10 PM UTC 24 |
| Finished | Sep 01 09:21:55 PM UTC 24 |
| Peak memory | 243504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573250366 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.1573250366 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/31.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/31.kmac_burst_write.2359175247 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 7942069340 ps |
| CPU time | 207.72 seconds |
| Started | Sep 01 09:21:07 PM UTC 24 |
| Finished | Sep 01 09:24:38 PM UTC 24 |
| Peak memory | 241512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359175247 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.2359175247 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/31.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/31.kmac_entropy_refresh.119572566 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 4377336334 ps |
| CPU time | 55.05 seconds |
| Started | Sep 01 09:21:14 PM UTC 24 |
| Finished | Sep 01 09:22:11 PM UTC 24 |
| Peak memory | 268224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119572566 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.119572566 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/31.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/31.kmac_key_error.1042598913 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 21592670844 ps |
| CPU time | 24.02 seconds |
| Started | Sep 01 09:21:55 PM UTC 24 |
| Finished | Sep 01 09:22:20 PM UTC 24 |
| Peak memory | 232448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042598913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.1042598913 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/31.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/31.kmac_lc_escalation.264617664 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 860064680 ps |
| CPU time | 39.25 seconds |
| Started | Sep 01 09:21:57 PM UTC 24 |
| Finished | Sep 01 09:22:37 PM UTC 24 |
| Peak memory | 255796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264617664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.264617664 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/31.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/31.kmac_long_msg_and_output.2930938798 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 104998776499 ps |
| CPU time | 2403.18 seconds |
| Started | Sep 01 09:21:02 PM UTC 24 |
| Finished | Sep 01 10:01:33 PM UTC 24 |
| Peak memory | 2774828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930938798 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_and_output.2930938798 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/31.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/31.kmac_sideload.4062588344 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 1830418845 ps |
| CPU time | 141.87 seconds |
| Started | Sep 01 09:21:04 PM UTC 24 |
| Finished | Sep 01 09:23:28 PM UTC 24 |
| Peak memory | 292576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062588344 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.4062588344 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/31.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/31.kmac_smoke.905914594 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 107083164 ps |
| CPU time | 7.27 seconds |
| Started | Sep 01 09:21:01 PM UTC 24 |
| Finished | Sep 01 09:21:09 PM UTC 24 |
| Peak memory | 230464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905914594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.905914594 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/31.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/31.kmac_stress_all.3911686851 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 122751276754 ps |
| CPU time | 1594.86 seconds |
| Started | Sep 01 09:22:05 PM UTC 24 |
| Finished | Sep 01 09:48:59 PM UTC 24 |
| Peak memory | 1192056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911686851 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.3911686851 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/31.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/32.kmac_alert_test.251277605 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 21941322 ps |
| CPU time | 1.3 seconds |
| Started | Sep 01 09:22:39 PM UTC 24 |
| Finished | Sep 01 09:22:41 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251277605 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.251277605 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/32.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/32.kmac_app.1478368057 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 5665413845 ps |
| CPU time | 195.36 seconds |
| Started | Sep 01 09:22:26 PM UTC 24 |
| Finished | Sep 01 09:25:45 PM UTC 24 |
| Peak memory | 368496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478368057 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.1478368057 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/32.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/32.kmac_burst_write.2448003898 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 55409606055 ps |
| CPU time | 635.62 seconds |
| Started | Sep 01 09:22:23 PM UTC 24 |
| Finished | Sep 01 09:33:08 PM UTC 24 |
| Peak memory | 251884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448003898 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.2448003898 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/32.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/32.kmac_entropy_refresh.2347191549 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 43428713886 ps |
| CPU time | 414.13 seconds |
| Started | Sep 01 09:22:32 PM UTC 24 |
| Finished | Sep 01 09:29:33 PM UTC 24 |
| Peak memory | 540640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347191549 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.2347191549 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/32.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/32.kmac_error.3232430603 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 1403239118 ps |
| CPU time | 26.55 seconds |
| Started | Sep 01 09:22:32 PM UTC 24 |
| Finished | Sep 01 09:23:00 PM UTC 24 |
| Peak memory | 251812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232430603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.3232430603 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/32.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/32.kmac_key_error.755684008 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 90522304 ps |
| CPU time | 1.47 seconds |
| Started | Sep 01 09:22:36 PM UTC 24 |
| Finished | Sep 01 09:22:38 PM UTC 24 |
| Peak memory | 229800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755684008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.755684008 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/32.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/32.kmac_lc_escalation.3291390774 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 52760282 ps |
| CPU time | 2.02 seconds |
| Started | Sep 01 09:22:39 PM UTC 24 |
| Finished | Sep 01 09:22:42 PM UTC 24 |
| Peak memory | 235116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291390774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.3291390774 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/32.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/32.kmac_long_msg_and_output.1540348207 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 15063511552 ps |
| CPU time | 1573.71 seconds |
| Started | Sep 01 09:22:15 PM UTC 24 |
| Finished | Sep 01 09:48:49 PM UTC 24 |
| Peak memory | 1087468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540348207 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_and_output.1540348207 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/32.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/32.kmac_sideload.1284084535 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 34325258903 ps |
| CPU time | 389.21 seconds |
| Started | Sep 01 09:22:21 PM UTC 24 |
| Finished | Sep 01 09:28:56 PM UTC 24 |
| Peak memory | 581552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284084535 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.1284084535 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/32.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/32.kmac_smoke.1111082897 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 1281855015 ps |
| CPU time | 23.99 seconds |
| Started | Sep 01 09:22:13 PM UTC 24 |
| Finished | Sep 01 09:22:38 PM UTC 24 |
| Peak memory | 230724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111082897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.1111082897 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/32.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/32.kmac_stress_all.1542401241 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 80567544087 ps |
| CPU time | 2461.59 seconds |
| Started | Sep 01 09:22:39 PM UTC 24 |
| Finished | Sep 01 10:04:08 PM UTC 24 |
| Peak memory | 1749108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542401241 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.1542401241 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/32.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/33.kmac_alert_test.2574354033 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 30066845 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 09:23:39 PM UTC 24 |
| Finished | Sep 01 09:23:41 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574354033 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.2574354033 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/33.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/33.kmac_app.1170191156 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 56660479111 ps |
| CPU time | 352.76 seconds |
| Started | Sep 01 09:23:21 PM UTC 24 |
| Finished | Sep 01 09:29:19 PM UTC 24 |
| Peak memory | 501804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170191156 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.1170191156 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/33.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/33.kmac_burst_write.3008424931 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 572279202 ps |
| CPU time | 32.37 seconds |
| Started | Sep 01 09:23:04 PM UTC 24 |
| Finished | Sep 01 09:23:38 PM UTC 24 |
| Peak memory | 232632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008424931 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.3008424931 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/33.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/33.kmac_entropy_refresh.3669432425 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 13689606874 ps |
| CPU time | 228.21 seconds |
| Started | Sep 01 09:23:29 PM UTC 24 |
| Finished | Sep 01 09:27:21 PM UTC 24 |
| Peak memory | 333676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669432425 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.3669432425 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/33.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/33.kmac_error.1145839831 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 2788665664 ps |
| CPU time | 207.37 seconds |
| Started | Sep 01 09:23:30 PM UTC 24 |
| Finished | Sep 01 09:27:01 PM UTC 24 |
| Peak memory | 327532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145839831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.1145839831 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/33.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/33.kmac_key_error.1725320284 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 756907523 ps |
| CPU time | 2.67 seconds |
| Started | Sep 01 09:23:32 PM UTC 24 |
| Finished | Sep 01 09:23:35 PM UTC 24 |
| Peak memory | 230448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725320284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.1725320284 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/33.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/33.kmac_lc_escalation.3161372490 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 82197440 ps |
| CPU time | 1.44 seconds |
| Started | Sep 01 09:23:36 PM UTC 24 |
| Finished | Sep 01 09:23:38 PM UTC 24 |
| Peak memory | 231736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161372490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.3161372490 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/33.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/33.kmac_long_msg_and_output.2197651964 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 553450094764 ps |
| CPU time | 5993.36 seconds |
| Started | Sep 01 09:22:43 PM UTC 24 |
| Finished | Sep 01 11:03:41 PM UTC 24 |
| Peak memory | 4917036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197651964 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_and_output.2197651964 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/33.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/33.kmac_sideload.196544061 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 87383600867 ps |
| CPU time | 542.36 seconds |
| Started | Sep 01 09:23:01 PM UTC 24 |
| Finished | Sep 01 09:32:11 PM UTC 24 |
| Peak memory | 675620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196544061 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.196544061 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/33.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/33.kmac_smoke.2905895770 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 517656544 ps |
| CPU time | 36.71 seconds |
| Started | Sep 01 09:22:42 PM UTC 24 |
| Finished | Sep 01 09:23:20 PM UTC 24 |
| Peak memory | 232512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905895770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.2905895770 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/33.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/33.kmac_stress_all.2292630098 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 8712314369 ps |
| CPU time | 650.29 seconds |
| Started | Sep 01 09:23:39 PM UTC 24 |
| Finished | Sep 01 09:34:38 PM UTC 24 |
| Peak memory | 557128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292630098 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.2292630098 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/33.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/34.kmac_alert_test.1381676213 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 17332015 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 09:25:15 PM UTC 24 |
| Finished | Sep 01 09:25:17 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381676213 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.1381676213 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/34.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/34.kmac_app.3172277796 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 15663784438 ps |
| CPU time | 240.89 seconds |
| Started | Sep 01 09:24:38 PM UTC 24 |
| Finished | Sep 01 09:28:43 PM UTC 24 |
| Peak memory | 403224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172277796 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.3172277796 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/34.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/34.kmac_burst_write.3527281417 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 6305470214 ps |
| CPU time | 502.57 seconds |
| Started | Sep 01 09:24:37 PM UTC 24 |
| Finished | Sep 01 09:33:07 PM UTC 24 |
| Peak memory | 247604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527281417 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.3527281417 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/34.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/34.kmac_entropy_refresh.1382836563 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 31940126756 ps |
| CPU time | 113.78 seconds |
| Started | Sep 01 09:24:38 PM UTC 24 |
| Finished | Sep 01 09:26:34 PM UTC 24 |
| Peak memory | 300908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382836563 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.1382836563 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/34.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/34.kmac_error.301065899 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 26474126015 ps |
| CPU time | 199.61 seconds |
| Started | Sep 01 09:24:54 PM UTC 24 |
| Finished | Sep 01 09:28:17 PM UTC 24 |
| Peak memory | 438260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301065899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.301065899 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/34.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/34.kmac_key_error.1922912191 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 2330928577 ps |
| CPU time | 11.43 seconds |
| Started | Sep 01 09:25:01 PM UTC 24 |
| Finished | Sep 01 09:25:14 PM UTC 24 |
| Peak memory | 230652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922912191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.1922912191 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/34.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/34.kmac_lc_escalation.3829646745 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 260031954 ps |
| CPU time | 2.06 seconds |
| Started | Sep 01 09:25:05 PM UTC 24 |
| Finished | Sep 01 09:25:09 PM UTC 24 |
| Peak memory | 230444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829646745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.3829646745 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/34.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/34.kmac_long_msg_and_output.2013828354 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 218160233452 ps |
| CPU time | 1877.5 seconds |
| Started | Sep 01 09:23:44 PM UTC 24 |
| Finished | Sep 01 09:55:24 PM UTC 24 |
| Peak memory | 2170680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013828354 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_and_output.2013828354 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/34.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/34.kmac_sideload.1552313879 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 4936128377 ps |
| CPU time | 262.61 seconds |
| Started | Sep 01 09:24:37 PM UTC 24 |
| Finished | Sep 01 09:29:04 PM UTC 24 |
| Peak memory | 319480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552313879 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.1552313879 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/34.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/34.kmac_smoke.3117980731 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 25965694762 ps |
| CPU time | 70.08 seconds |
| Started | Sep 01 09:23:42 PM UTC 24 |
| Finished | Sep 01 09:24:54 PM UTC 24 |
| Peak memory | 235240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117980731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.3117980731 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/34.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/34.kmac_stress_all.1626454515 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 88524806253 ps |
| CPU time | 2544.54 seconds |
| Started | Sep 01 09:25:10 PM UTC 24 |
| Finished | Sep 01 10:08:04 PM UTC 24 |
| Peak memory | 1431672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626454515 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.1626454515 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/34.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/35.kmac_alert_test.3567578772 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 37046241 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 09:26:58 PM UTC 24 |
| Finished | Sep 01 09:27:00 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567578772 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.3567578772 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/35.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/35.kmac_app.3153227433 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 2036273280 ps |
| CPU time | 141.1 seconds |
| Started | Sep 01 09:25:47 PM UTC 24 |
| Finished | Sep 01 09:28:11 PM UTC 24 |
| Peak memory | 274280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153227433 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.3153227433 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/35.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/35.kmac_burst_write.3382112061 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 7792375885 ps |
| CPU time | 891.12 seconds |
| Started | Sep 01 09:25:46 PM UTC 24 |
| Finished | Sep 01 09:40:50 PM UTC 24 |
| Peak memory | 249576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382112061 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.3382112061 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/35.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/35.kmac_entropy_refresh.643509597 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 5109137980 ps |
| CPU time | 132.14 seconds |
| Started | Sep 01 09:25:50 PM UTC 24 |
| Finished | Sep 01 09:28:05 PM UTC 24 |
| Peak memory | 319420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643509597 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.643509597 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/35.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/35.kmac_error.2053308126 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 1390972421 ps |
| CPU time | 50.08 seconds |
| Started | Sep 01 09:26:35 PM UTC 24 |
| Finished | Sep 01 09:27:27 PM UTC 24 |
| Peak memory | 268012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053308126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.2053308126 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/35.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/35.kmac_key_error.3785802787 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 1243452001 ps |
| CPU time | 12.03 seconds |
| Started | Sep 01 09:26:46 PM UTC 24 |
| Finished | Sep 01 09:26:59 PM UTC 24 |
| Peak memory | 230596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785802787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.3785802787 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/35.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/35.kmac_lc_escalation.2548059506 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 559396332 ps |
| CPU time | 5.1 seconds |
| Started | Sep 01 09:26:49 PM UTC 24 |
| Finished | Sep 01 09:26:55 PM UTC 24 |
| Peak memory | 230736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548059506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.2548059506 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/35.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/35.kmac_long_msg_and_output.536391579 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 74944239770 ps |
| CPU time | 3595.38 seconds |
| Started | Sep 01 09:25:30 PM UTC 24 |
| Finished | Sep 01 10:26:07 PM UTC 24 |
| Peak memory | 3579632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536391579 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_and_output.536391579 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/35.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/35.kmac_sideload.702826833 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 3538706747 ps |
| CPU time | 112.03 seconds |
| Started | Sep 01 09:25:42 PM UTC 24 |
| Finished | Sep 01 09:27:37 PM UTC 24 |
| Peak memory | 309040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702826833 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.702826833 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/35.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/35.kmac_smoke.3078715433 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 14599499684 ps |
| CPU time | 30.06 seconds |
| Started | Sep 01 09:25:18 PM UTC 24 |
| Finished | Sep 01 09:25:49 PM UTC 24 |
| Peak memory | 230548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078715433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.3078715433 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/35.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/35.kmac_stress_all.3056798244 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 32348803161 ps |
| CPU time | 2723.89 seconds |
| Started | Sep 01 09:26:56 PM UTC 24 |
| Finished | Sep 01 10:12:53 PM UTC 24 |
| Peak memory | 952068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056798244 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.3056798244 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/35.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/36.kmac_alert_test.342141185 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 29296304 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 09:27:52 PM UTC 24 |
| Finished | Sep 01 09:27:54 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342141185 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.342141185 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/36.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/36.kmac_app.82162110 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 17710213762 ps |
| CPU time | 216.05 seconds |
| Started | Sep 01 09:27:11 PM UTC 24 |
| Finished | Sep 01 09:30:51 PM UTC 24 |
| Peak memory | 319340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82162110 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.82162110 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/36.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/36.kmac_burst_write.868701102 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 13676707598 ps |
| CPU time | 707.31 seconds |
| Started | Sep 01 09:27:09 PM UTC 24 |
| Finished | Sep 01 09:39:07 PM UTC 24 |
| Peak memory | 255736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868701102 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.868701102 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/36.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/36.kmac_entropy_refresh.243207817 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 12748755628 ps |
| CPU time | 289.21 seconds |
| Started | Sep 01 09:27:22 PM UTC 24 |
| Finished | Sep 01 09:32:16 PM UTC 24 |
| Peak memory | 466732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243207817 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.243207817 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/36.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/36.kmac_error.1753373458 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 46258614082 ps |
| CPU time | 290.8 seconds |
| Started | Sep 01 09:27:28 PM UTC 24 |
| Finished | Sep 01 09:32:24 PM UTC 24 |
| Peak memory | 485356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753373458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.1753373458 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/36.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/36.kmac_key_error.3673128042 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 4996047378 ps |
| CPU time | 11.91 seconds |
| Started | Sep 01 09:27:38 PM UTC 24 |
| Finished | Sep 01 09:27:51 PM UTC 24 |
| Peak memory | 230392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673128042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.3673128042 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/36.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/36.kmac_lc_escalation.566983436 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 45538560 ps |
| CPU time | 1.68 seconds |
| Started | Sep 01 09:27:49 PM UTC 24 |
| Finished | Sep 01 09:27:51 PM UTC 24 |
| Peak memory | 231792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566983436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.566983436 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/36.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/36.kmac_long_msg_and_output.1176474202 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 12335394033 ps |
| CPU time | 151.88 seconds |
| Started | Sep 01 09:27:01 PM UTC 24 |
| Finished | Sep 01 09:29:36 PM UTC 24 |
| Peak memory | 292640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176474202 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_and_output.1176474202 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/36.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/36.kmac_sideload.3259862256 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 4147565197 ps |
| CPU time | 376.54 seconds |
| Started | Sep 01 09:27:02 PM UTC 24 |
| Finished | Sep 01 09:33:24 PM UTC 24 |
| Peak memory | 372468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259862256 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.3259862256 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/36.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/36.kmac_smoke.1257475670 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 1899414348 ps |
| CPU time | 46.29 seconds |
| Started | Sep 01 09:27:00 PM UTC 24 |
| Finished | Sep 01 09:27:48 PM UTC 24 |
| Peak memory | 230532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257475670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.1257475670 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/36.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/36.kmac_stress_all.3298147374 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 26547443701 ps |
| CPU time | 1303.93 seconds |
| Started | Sep 01 09:27:52 PM UTC 24 |
| Finished | Sep 01 09:49:53 PM UTC 24 |
| Peak memory | 329716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298147374 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.3298147374 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/36.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/37.kmac_alert_test.3277054454 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 16841696 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 09:29:03 PM UTC 24 |
| Finished | Sep 01 09:29:06 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277054454 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.3277054454 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/37.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/37.kmac_app.2503902774 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 1815721103 ps |
| CPU time | 100.4 seconds |
| Started | Sep 01 09:28:22 PM UTC 24 |
| Finished | Sep 01 09:30:05 PM UTC 24 |
| Peak memory | 261868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503902774 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.2503902774 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/37.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/37.kmac_burst_write.1375080094 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 22573203593 ps |
| CPU time | 293.34 seconds |
| Started | Sep 01 09:28:18 PM UTC 24 |
| Finished | Sep 01 09:33:16 PM UTC 24 |
| Peak memory | 239400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375080094 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.1375080094 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/37.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/37.kmac_entropy_refresh.2227276295 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 1049702742 ps |
| CPU time | 33.05 seconds |
| Started | Sep 01 09:28:22 PM UTC 24 |
| Finished | Sep 01 09:28:57 PM UTC 24 |
| Peak memory | 251564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227276295 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.2227276295 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/37.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/37.kmac_error.2367502526 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 11598108618 ps |
| CPU time | 245.93 seconds |
| Started | Sep 01 09:28:45 PM UTC 24 |
| Finished | Sep 01 09:32:55 PM UTC 24 |
| Peak memory | 339684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367502526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.2367502526 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/37.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/37.kmac_key_error.10135151 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 614470815 ps |
| CPU time | 6.61 seconds |
| Started | Sep 01 09:28:57 PM UTC 24 |
| Finished | Sep 01 09:29:04 PM UTC 24 |
| Peak memory | 230348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10135151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.10135151 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/37.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/37.kmac_lc_escalation.2095297942 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 42805767 ps |
| CPU time | 1.79 seconds |
| Started | Sep 01 09:28:58 PM UTC 24 |
| Finished | Sep 01 09:29:01 PM UTC 24 |
| Peak memory | 229788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095297942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.2095297942 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/37.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/37.kmac_long_msg_and_output.3339633575 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 7912076401 ps |
| CPU time | 709.37 seconds |
| Started | Sep 01 09:28:06 PM UTC 24 |
| Finished | Sep 01 09:40:04 PM UTC 24 |
| Peak memory | 702192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339633575 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_and_output.3339633575 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/37.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/37.kmac_sideload.3485702464 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 9471442381 ps |
| CPU time | 52.14 seconds |
| Started | Sep 01 09:28:12 PM UTC 24 |
| Finished | Sep 01 09:29:06 PM UTC 24 |
| Peak memory | 278264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485702464 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.3485702464 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/37.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/37.kmac_smoke.2125986442 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 3786686260 ps |
| CPU time | 65.37 seconds |
| Started | Sep 01 09:27:55 PM UTC 24 |
| Finished | Sep 01 09:29:02 PM UTC 24 |
| Peak memory | 230528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125986442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.2125986442 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/37.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/37.kmac_stress_all.1587101876 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 26977818740 ps |
| CPU time | 1030.23 seconds |
| Started | Sep 01 09:28:59 PM UTC 24 |
| Finished | Sep 01 09:46:24 PM UTC 24 |
| Peak memory | 1396764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587101876 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.1587101876 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/37.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/38.kmac_alert_test.2226075915 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 26918905 ps |
| CPU time | 1.17 seconds |
| Started | Sep 01 09:29:50 PM UTC 24 |
| Finished | Sep 01 09:29:53 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226075915 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.2226075915 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/38.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/38.kmac_app.2392081348 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 94591857777 ps |
| CPU time | 429.57 seconds |
| Started | Sep 01 09:29:08 PM UTC 24 |
| Finished | Sep 01 09:36:24 PM UTC 24 |
| Peak memory | 511980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392081348 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.2392081348 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/38.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/38.kmac_burst_write.758939532 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 8046146976 ps |
| CPU time | 253.19 seconds |
| Started | Sep 01 09:29:08 PM UTC 24 |
| Finished | Sep 01 09:33:25 PM UTC 24 |
| Peak memory | 237348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758939532 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.758939532 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/38.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/38.kmac_entropy_refresh.4102609928 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 3951792926 ps |
| CPU time | 79.67 seconds |
| Started | Sep 01 09:29:14 PM UTC 24 |
| Finished | Sep 01 09:30:36 PM UTC 24 |
| Peak memory | 253808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102609928 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.4102609928 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/38.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/38.kmac_error.335201168 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 3955195680 ps |
| CPU time | 148.32 seconds |
| Started | Sep 01 09:29:20 PM UTC 24 |
| Finished | Sep 01 09:31:51 PM UTC 24 |
| Peak memory | 333600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335201168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.335201168 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/38.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/38.kmac_key_error.3458126874 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 2391898574 ps |
| CPU time | 3.83 seconds |
| Started | Sep 01 09:29:34 PM UTC 24 |
| Finished | Sep 01 09:29:39 PM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458126874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.3458126874 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/38.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/38.kmac_long_msg_and_output.4199027882 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 137506842159 ps |
| CPU time | 2626.05 seconds |
| Started | Sep 01 09:29:06 PM UTC 24 |
| Finished | Sep 01 10:13:22 PM UTC 24 |
| Peak memory | 2987712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199027882 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_and_output.4199027882 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/38.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/38.kmac_sideload.433087656 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 7258625242 ps |
| CPU time | 302.53 seconds |
| Started | Sep 01 09:29:06 PM UTC 24 |
| Finished | Sep 01 09:34:13 PM UTC 24 |
| Peak memory | 356204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433087656 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.433087656 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/38.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/38.kmac_smoke.492964356 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 1040722324 ps |
| CPU time | 60.48 seconds |
| Started | Sep 01 09:29:03 PM UTC 24 |
| Finished | Sep 01 09:30:06 PM UTC 24 |
| Peak memory | 230788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492964356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.492964356 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/38.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/38.kmac_stress_all.250261900 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 22618512804 ps |
| CPU time | 778.45 seconds |
| Started | Sep 01 09:29:40 PM UTC 24 |
| Finished | Sep 01 09:42:49 PM UTC 24 |
| Peak memory | 1071164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250261900 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.250261900 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/38.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/39.kmac_alert_test.2656126123 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 40650815 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 09:30:48 PM UTC 24 |
| Finished | Sep 01 09:30:51 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656126123 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.2656126123 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/39.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/39.kmac_app.2765659079 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 1239508454 ps |
| CPU time | 22.96 seconds |
| Started | Sep 01 09:30:08 PM UTC 24 |
| Finished | Sep 01 09:30:32 PM UTC 24 |
| Peak memory | 237488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765659079 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.2765659079 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/39.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/39.kmac_burst_write.1218602690 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 18479778395 ps |
| CPU time | 477.72 seconds |
| Started | Sep 01 09:30:07 PM UTC 24 |
| Finished | Sep 01 09:38:11 PM UTC 24 |
| Peak memory | 251692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218602690 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.1218602690 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/39.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/39.kmac_entropy_refresh.77960663 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 43916571389 ps |
| CPU time | 332.9 seconds |
| Started | Sep 01 09:30:19 PM UTC 24 |
| Finished | Sep 01 09:35:57 PM UTC 24 |
| Peak memory | 489268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77960663 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.77960663 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/39.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/39.kmac_error.1196410535 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 8582603233 ps |
| CPU time | 316.53 seconds |
| Started | Sep 01 09:30:32 PM UTC 24 |
| Finished | Sep 01 09:35:54 PM UTC 24 |
| Peak memory | 464664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196410535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.1196410535 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/39.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/39.kmac_key_error.173262271 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 16533530527 ps |
| CPU time | 13.07 seconds |
| Started | Sep 01 09:30:33 PM UTC 24 |
| Finished | Sep 01 09:30:48 PM UTC 24 |
| Peak memory | 230500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173262271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.173262271 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/39.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/39.kmac_lc_escalation.2989085518 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 959878609 ps |
| CPU time | 12.12 seconds |
| Started | Sep 01 09:30:35 PM UTC 24 |
| Finished | Sep 01 09:30:49 PM UTC 24 |
| Peak memory | 245552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989085518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.2989085518 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/39.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/39.kmac_long_msg_and_output.2003557540 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 13039634009 ps |
| CPU time | 1596.62 seconds |
| Started | Sep 01 09:30:03 PM UTC 24 |
| Finished | Sep 01 09:56:59 PM UTC 24 |
| Peak memory | 974804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003557540 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_and_output.2003557540 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/39.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/39.kmac_sideload.3098280548 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 26350818611 ps |
| CPU time | 141.3 seconds |
| Started | Sep 01 09:30:03 PM UTC 24 |
| Finished | Sep 01 09:32:27 PM UTC 24 |
| Peak memory | 354092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098280548 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.3098280548 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/39.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/39.kmac_smoke.2694152866 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 1305901125 ps |
| CPU time | 38.39 seconds |
| Started | Sep 01 09:29:54 PM UTC 24 |
| Finished | Sep 01 09:30:34 PM UTC 24 |
| Peak memory | 230592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694152866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.2694152866 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/39.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/39.kmac_stress_all.2663261541 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 87917970432 ps |
| CPU time | 696.02 seconds |
| Started | Sep 01 09:30:36 PM UTC 24 |
| Finished | Sep 01 09:42:22 PM UTC 24 |
| Peak memory | 577592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663261541 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.2663261541 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/39.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/4.kmac_alert_test.3450926265 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 25919439 ps |
| CPU time | 1.3 seconds |
| Started | Sep 01 08:53:57 PM UTC 24 |
| Finished | Sep 01 08:54:00 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450926265 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.3450926265 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/4.kmac_app.1193138861 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 7400127844 ps |
| CPU time | 142.82 seconds |
| Started | Sep 01 08:53:21 PM UTC 24 |
| Finished | Sep 01 08:55:47 PM UTC 24 |
| Peak memory | 286376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193138861 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.1193138861 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/4.kmac_app_with_partial_data.4050751741 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 16029575744 ps |
| CPU time | 395.48 seconds |
| Started | Sep 01 08:53:23 PM UTC 24 |
| Finished | Sep 01 09:00:06 PM UTC 24 |
| Peak memory | 495408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050751741 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.4050751741 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/4.kmac_burst_write.763882726 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 16787295413 ps |
| CPU time | 744.53 seconds |
| Started | Sep 01 08:52:17 PM UTC 24 |
| Finished | Sep 01 09:04:52 PM UTC 24 |
| Peak memory | 255708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763882726 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.763882726 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/4.kmac_edn_timeout_error.2187933480 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 17351631239 ps |
| CPU time | 41.27 seconds |
| Started | Sep 01 08:53:36 PM UTC 24 |
| Finished | Sep 01 08:54:19 PM UTC 24 |
| Peak memory | 247372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187933480 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.2187933480 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_mode_error.2897703737 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 541499768 ps |
| CPU time | 25.83 seconds |
| Started | Sep 01 08:53:40 PM UTC 24 |
| Finished | Sep 01 08:54:07 PM UTC 24 |
| Peak memory | 230352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897703737 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.2897703737 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_ready_error.3514040662 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 22084081099 ps |
| CPU time | 94.13 seconds |
| Started | Sep 01 08:53:43 PM UTC 24 |
| Finished | Sep 01 08:55:20 PM UTC 24 |
| Peak memory | 230772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514040662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.3514040662 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_refresh.3542189695 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 215216578 ps |
| CPU time | 4.46 seconds |
| Started | Sep 01 08:53:25 PM UTC 24 |
| Finished | Sep 01 08:53:31 PM UTC 24 |
| Peak memory | 232652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542189695 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.3542189695 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/4.kmac_error.4231414179 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 7894193185 ps |
| CPU time | 352.38 seconds |
| Started | Sep 01 08:53:31 PM UTC 24 |
| Finished | Sep 01 08:59:28 PM UTC 24 |
| Peak memory | 370496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231414179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.4231414179 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/4.kmac_key_error.1503323823 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 2289341633 ps |
| CPU time | 8.64 seconds |
| Started | Sep 01 08:53:32 PM UTC 24 |
| Finished | Sep 01 08:53:41 PM UTC 24 |
| Peak memory | 230592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503323823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.1503323823 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/4.kmac_lc_escalation.1832555678 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 158016791 ps |
| CPU time | 2.08 seconds |
| Started | Sep 01 08:53:44 PM UTC 24 |
| Finished | Sep 01 08:53:47 PM UTC 24 |
| Peak memory | 230372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832555678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.1832555678 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/4.kmac_long_msg_and_output.3151752302 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 71627177188 ps |
| CPU time | 2459.69 seconds |
| Started | Sep 01 08:52:14 PM UTC 24 |
| Finished | Sep 01 09:33:43 PM UTC 24 |
| Peak memory | 2744116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151752302 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and_output.3151752302 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/4.kmac_mubi.1584168781 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 11508042197 ps |
| CPU time | 429.23 seconds |
| Started | Sep 01 08:53:27 PM UTC 24 |
| Finished | Sep 01 09:00:43 PM UTC 24 |
| Peak memory | 512052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584168781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.1584168781 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/4.kmac_sec_cm.727072706 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 9045918813 ps |
| CPU time | 57.91 seconds |
| Started | Sep 01 08:53:54 PM UTC 24 |
| Finished | Sep 01 08:54:54 PM UTC 24 |
| Peak memory | 271196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727072706 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.727072706 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/4.kmac_sideload.620252385 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 10873663731 ps |
| CPU time | 219.4 seconds |
| Started | Sep 01 08:52:17 PM UTC 24 |
| Finished | Sep 01 08:56:00 PM UTC 24 |
| Peak memory | 327484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620252385 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.620252385 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/4.kmac_smoke.396526728 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 15272137 ps |
| CPU time | 1.66 seconds |
| Started | Sep 01 08:52:14 PM UTC 24 |
| Finished | Sep 01 08:52:17 PM UTC 24 |
| Peak memory | 229672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396526728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.396526728 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/4.kmac_stress_all.911229736 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 66573908834 ps |
| CPU time | 1878.4 seconds |
| Started | Sep 01 08:53:47 PM UTC 24 |
| Finished | Sep 01 09:25:29 PM UTC 24 |
| Peak memory | 1634484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911229736 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.911229736 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac.54780274 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 347138722 ps |
| CPU time | 3.29 seconds |
| Started | Sep 01 08:53:16 PM UTC 24 |
| Finished | Sep 01 08:53:21 PM UTC 24 |
| Peak memory | 230596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54780274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vec tors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac.54780274 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac_xof.3133708100 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 384984395 ps |
| CPU time | 3.95 seconds |
| Started | Sep 01 08:53:21 PM UTC 24 |
| Finished | Sep 01 08:53:26 PM UTC 24 |
| Peak memory | 230180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133708100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac_xof.3133708100 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_224.2699415382 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 63086474480 ps |
| CPU time | 2528.8 seconds |
| Started | Sep 01 08:52:30 PM UTC 24 |
| Finished | Sep 01 09:35:09 PM UTC 24 |
| Peak memory | 3194844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699415382 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.2699415382 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_256.4185247708 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 16286641338 ps |
| CPU time | 1613.55 seconds |
| Started | Sep 01 08:52:44 PM UTC 24 |
| Finished | Sep 01 09:19:57 PM UTC 24 |
| Peak memory | 1105876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185247708 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.4185247708 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_384.1809674525 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 14734053832 ps |
| CPU time | 1291.1 seconds |
| Started | Sep 01 08:52:46 PM UTC 24 |
| Finished | Sep 01 09:14:33 PM UTC 24 |
| Peak memory | 906900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809674525 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.1809674525 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_512.2952824265 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 50553615552 ps |
| CPU time | 1390.33 seconds |
| Started | Sep 01 08:53:06 PM UTC 24 |
| Finished | Sep 01 09:16:33 PM UTC 24 |
| Peak memory | 1726104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952824265 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.2952824265 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_128.1135242654 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 3687639732 ps |
| CPU time | 229.98 seconds |
| Started | Sep 01 08:53:07 PM UTC 24 |
| Finished | Sep 01 08:57:01 PM UTC 24 |
| Peak memory | 239396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135242654 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.1135242 654 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_256.2577932302 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 4826963786 ps |
| CPU time | 144.38 seconds |
| Started | Sep 01 08:53:15 PM UTC 24 |
| Finished | Sep 01 08:55:42 PM UTC 24 |
| Peak memory | 360356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577932302 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.2577932 302 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/4.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/40.kmac_alert_test.1983699202 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 31138144 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 09:32:25 PM UTC 24 |
| Finished | Sep 01 09:32:27 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983699202 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.1983699202 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/40.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/40.kmac_app.916507041 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 8140806645 ps |
| CPU time | 278.42 seconds |
| Started | Sep 01 09:31:38 PM UTC 24 |
| Finished | Sep 01 09:36:21 PM UTC 24 |
| Peak memory | 313192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916507041 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.916507041 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/40.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/40.kmac_burst_write.3129189430 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 16757402377 ps |
| CPU time | 601.79 seconds |
| Started | Sep 01 09:31:24 PM UTC 24 |
| Finished | Sep 01 09:41:33 PM UTC 24 |
| Peak memory | 257832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129189430 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.3129189430 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/40.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/40.kmac_entropy_refresh.2961788039 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 10165701430 ps |
| CPU time | 49.5 seconds |
| Started | Sep 01 09:31:40 PM UTC 24 |
| Finished | Sep 01 09:32:31 PM UTC 24 |
| Peak memory | 272380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961788039 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.2961788039 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/40.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/40.kmac_error.3073742654 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 12477404780 ps |
| CPU time | 329.08 seconds |
| Started | Sep 01 09:31:52 PM UTC 24 |
| Finished | Sep 01 09:37:26 PM UTC 24 |
| Peak memory | 569128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073742654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.3073742654 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/40.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/40.kmac_key_error.3379250248 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 11576469692 ps |
| CPU time | 14.61 seconds |
| Started | Sep 01 09:32:12 PM UTC 24 |
| Finished | Sep 01 09:32:28 PM UTC 24 |
| Peak memory | 232448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379250248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.3379250248 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/40.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/40.kmac_lc_escalation.2004721753 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 443303182 ps |
| CPU time | 20.97 seconds |
| Started | Sep 01 09:32:16 PM UTC 24 |
| Finished | Sep 01 09:32:39 PM UTC 24 |
| Peak memory | 232576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004721753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.2004721753 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/40.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/40.kmac_long_msg_and_output.3058537067 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 73144540757 ps |
| CPU time | 2055.15 seconds |
| Started | Sep 01 09:30:52 PM UTC 24 |
| Finished | Sep 01 10:05:32 PM UTC 24 |
| Peak memory | 1349348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058537067 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_and_output.3058537067 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/40.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/40.kmac_sideload.68066929 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 8900390723 ps |
| CPU time | 349.04 seconds |
| Started | Sep 01 09:30:52 PM UTC 24 |
| Finished | Sep 01 09:36:46 PM UTC 24 |
| Peak memory | 380652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68066929 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.68066929 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/40.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/40.kmac_smoke.2089520075 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 8220945326 ps |
| CPU time | 47.96 seconds |
| Started | Sep 01 09:30:50 PM UTC 24 |
| Finished | Sep 01 09:31:39 PM UTC 24 |
| Peak memory | 235232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089520075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.2089520075 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/40.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/40.kmac_stress_all.3419024548 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 87293875714 ps |
| CPU time | 1154.78 seconds |
| Started | Sep 01 09:32:17 PM UTC 24 |
| Finished | Sep 01 09:51:46 PM UTC 24 |
| Peak memory | 1122400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419024548 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.3419024548 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/40.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/41.kmac_alert_test.3077370182 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 56805543 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 09:33:14 PM UTC 24 |
| Finished | Sep 01 09:33:16 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077370182 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.3077370182 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/41.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/41.kmac_app.656386702 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 3939934591 ps |
| CPU time | 191.95 seconds |
| Started | Sep 01 09:32:40 PM UTC 24 |
| Finished | Sep 01 09:35:55 PM UTC 24 |
| Peak memory | 302880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656386702 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.656386702 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/41.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/41.kmac_burst_write.3033711449 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 27658477310 ps |
| CPU time | 640.27 seconds |
| Started | Sep 01 09:32:32 PM UTC 24 |
| Finished | Sep 01 09:43:21 PM UTC 24 |
| Peak memory | 253808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033711449 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.3033711449 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/41.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/41.kmac_entropy_refresh.4284838817 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 15195208251 ps |
| CPU time | 199.32 seconds |
| Started | Sep 01 09:32:55 PM UTC 24 |
| Finished | Sep 01 09:36:18 PM UTC 24 |
| Peak memory | 351996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284838817 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.4284838817 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/41.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/41.kmac_error.3305563344 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 13149271427 ps |
| CPU time | 144.43 seconds |
| Started | Sep 01 09:33:07 PM UTC 24 |
| Finished | Sep 01 09:35:35 PM UTC 24 |
| Peak memory | 333616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305563344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.3305563344 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/41.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/41.kmac_key_error.2508372108 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 891129806 ps |
| CPU time | 1.88 seconds |
| Started | Sep 01 09:33:08 PM UTC 24 |
| Finished | Sep 01 09:33:11 PM UTC 24 |
| Peak memory | 229800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508372108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.2508372108 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/41.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/41.kmac_lc_escalation.1661240292 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 149102136 ps |
| CPU time | 1.88 seconds |
| Started | Sep 01 09:33:10 PM UTC 24 |
| Finished | Sep 01 09:33:12 PM UTC 24 |
| Peak memory | 229796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661240292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.1661240292 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/41.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/41.kmac_long_msg_and_output.2545203459 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 252676194431 ps |
| CPU time | 2976.15 seconds |
| Started | Sep 01 09:32:28 PM UTC 24 |
| Finished | Sep 01 10:22:37 PM UTC 24 |
| Peak memory | 3065640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545203459 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_and_output.2545203459 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/41.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/41.kmac_sideload.3974012603 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 12138346142 ps |
| CPU time | 359.96 seconds |
| Started | Sep 01 09:32:29 PM UTC 24 |
| Finished | Sep 01 09:38:34 PM UTC 24 |
| Peak memory | 560888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974012603 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.3974012603 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/41.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/41.kmac_smoke.3321744571 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 746777914 ps |
| CPU time | 50.37 seconds |
| Started | Sep 01 09:32:28 PM UTC 24 |
| Finished | Sep 01 09:33:20 PM UTC 24 |
| Peak memory | 230588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321744571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.3321744571 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/41.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/41.kmac_stress_all.526769124 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 3015887942 ps |
| CPU time | 44.36 seconds |
| Started | Sep 01 09:33:13 PM UTC 24 |
| Finished | Sep 01 09:33:59 PM UTC 24 |
| Peak memory | 232596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526769124 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.526769124 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/41.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/42.kmac_alert_test.140413538 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 16918237 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 09:34:16 PM UTC 24 |
| Finished | Sep 01 09:34:18 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140413538 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.140413538 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/42.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/42.kmac_app.914172779 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 2889345175 ps |
| CPU time | 196.73 seconds |
| Started | Sep 01 09:33:26 PM UTC 24 |
| Finished | Sep 01 09:36:46 PM UTC 24 |
| Peak memory | 300816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914172779 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.914172779 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/42.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/42.kmac_burst_write.1412356449 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 81702019846 ps |
| CPU time | 670.23 seconds |
| Started | Sep 01 09:33:25 PM UTC 24 |
| Finished | Sep 01 09:44:44 PM UTC 24 |
| Peak memory | 257772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412356449 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.1412356449 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/42.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/42.kmac_entropy_refresh.501981246 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 13389687024 ps |
| CPU time | 116.33 seconds |
| Started | Sep 01 09:33:43 PM UTC 24 |
| Finished | Sep 01 09:35:42 PM UTC 24 |
| Peak memory | 297072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501981246 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.501981246 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/42.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/42.kmac_error.2109515480 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 25820735992 ps |
| CPU time | 238.18 seconds |
| Started | Sep 01 09:33:49 PM UTC 24 |
| Finished | Sep 01 09:37:52 PM UTC 24 |
| Peak memory | 405492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109515480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.2109515480 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/42.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/42.kmac_key_error.2527677979 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 1028152028 ps |
| CPU time | 10.17 seconds |
| Started | Sep 01 09:34:00 PM UTC 24 |
| Finished | Sep 01 09:34:11 PM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527677979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.2527677979 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/42.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/42.kmac_lc_escalation.2008591986 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 46972815 ps |
| CPU time | 1.95 seconds |
| Started | Sep 01 09:34:12 PM UTC 24 |
| Finished | Sep 01 09:34:15 PM UTC 24 |
| Peak memory | 229684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008591986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.2008591986 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/42.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/42.kmac_long_msg_and_output.4151698896 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 11627395436 ps |
| CPU time | 845.77 seconds |
| Started | Sep 01 09:33:17 PM UTC 24 |
| Finished | Sep 01 09:47:33 PM UTC 24 |
| Peak memory | 792344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151698896 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_and_output.4151698896 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/42.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/42.kmac_sideload.1616126303 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 16592056366 ps |
| CPU time | 402.53 seconds |
| Started | Sep 01 09:33:21 PM UTC 24 |
| Finished | Sep 01 09:40:09 PM UTC 24 |
| Peak memory | 597744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616126303 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.1616126303 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/42.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/42.kmac_smoke.1704737725 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 7344380966 ps |
| CPU time | 81.53 seconds |
| Started | Sep 01 09:33:17 PM UTC 24 |
| Finished | Sep 01 09:34:40 PM UTC 24 |
| Peak memory | 234740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704737725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.1704737725 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/42.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/42.kmac_stress_all.3645294876 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 11065415466 ps |
| CPU time | 969.32 seconds |
| Started | Sep 01 09:34:14 PM UTC 24 |
| Finished | Sep 01 09:50:36 PM UTC 24 |
| Peak memory | 641040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645294876 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.3645294876 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/42.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/43.kmac_alert_test.1173887597 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 21685862 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 09:36:00 PM UTC 24 |
| Finished | Sep 01 09:36:02 PM UTC 24 |
| Peak memory | 216232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173887597 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.1173887597 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/43.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/43.kmac_app.1723744810 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 12316422471 ps |
| CPU time | 152.05 seconds |
| Started | Sep 01 09:35:09 PM UTC 24 |
| Finished | Sep 01 09:37:45 PM UTC 24 |
| Peak memory | 294704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723744810 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.1723744810 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/43.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/43.kmac_burst_write.670257186 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 33043653203 ps |
| CPU time | 494.58 seconds |
| Started | Sep 01 09:34:41 PM UTC 24 |
| Finished | Sep 01 09:43:02 PM UTC 24 |
| Peak memory | 245740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670257186 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.670257186 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/43.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/43.kmac_entropy_refresh.2307773188 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 19128431504 ps |
| CPU time | 386.77 seconds |
| Started | Sep 01 09:35:36 PM UTC 24 |
| Finished | Sep 01 09:42:08 PM UTC 24 |
| Peak memory | 481400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307773188 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.2307773188 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/43.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/43.kmac_error.1594233172 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 288005238 ps |
| CPU time | 23.62 seconds |
| Started | Sep 01 09:35:43 PM UTC 24 |
| Finished | Sep 01 09:36:08 PM UTC 24 |
| Peak memory | 247856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594233172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.1594233172 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/43.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/43.kmac_key_error.1914989599 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 5929513772 ps |
| CPU time | 10.55 seconds |
| Started | Sep 01 09:35:55 PM UTC 24 |
| Finished | Sep 01 09:36:06 PM UTC 24 |
| Peak memory | 232656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914989599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.1914989599 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/43.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/43.kmac_lc_escalation.565914837 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 96141837 ps |
| CPU time | 1.93 seconds |
| Started | Sep 01 09:35:56 PM UTC 24 |
| Finished | Sep 01 09:35:59 PM UTC 24 |
| Peak memory | 231904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565914837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.565914837 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/43.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/43.kmac_long_msg_and_output.1924856908 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 38787982917 ps |
| CPU time | 1636.94 seconds |
| Started | Sep 01 09:34:27 PM UTC 24 |
| Finished | Sep 01 10:02:03 PM UTC 24 |
| Peak memory | 2072548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924856908 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_and_output.1924856908 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/43.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/43.kmac_sideload.2175730175 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 2457119130 ps |
| CPU time | 233.86 seconds |
| Started | Sep 01 09:34:39 PM UTC 24 |
| Finished | Sep 01 09:38:37 PM UTC 24 |
| Peak memory | 317232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175730175 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.2175730175 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/43.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/43.kmac_smoke.3037053280 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 385102767 ps |
| CPU time | 6.29 seconds |
| Started | Sep 01 09:34:19 PM UTC 24 |
| Finished | Sep 01 09:34:26 PM UTC 24 |
| Peak memory | 232500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037053280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.3037053280 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/43.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/43.kmac_stress_all.4019271904 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 208326445221 ps |
| CPU time | 1268.79 seconds |
| Started | Sep 01 09:35:58 PM UTC 24 |
| Finished | Sep 01 09:57:22 PM UTC 24 |
| Peak memory | 1056804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019271904 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.4019271904 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/43.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/44.kmac_alert_test.1145454179 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 30566848 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 09:36:55 PM UTC 24 |
| Finished | Sep 01 09:36:57 PM UTC 24 |
| Peak memory | 216232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145454179 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.1145454179 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/44.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/44.kmac_app.1927342486 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 11800419729 ps |
| CPU time | 426.41 seconds |
| Started | Sep 01 09:36:20 PM UTC 24 |
| Finished | Sep 01 09:43:34 PM UTC 24 |
| Peak memory | 495408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927342486 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.1927342486 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/44.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/44.kmac_burst_write.3052560627 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 8985558831 ps |
| CPU time | 421.71 seconds |
| Started | Sep 01 09:36:18 PM UTC 24 |
| Finished | Sep 01 09:43:26 PM UTC 24 |
| Peak memory | 243480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052560627 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.3052560627 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/44.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/44.kmac_entropy_refresh.798054270 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 5505502927 ps |
| CPU time | 85.17 seconds |
| Started | Sep 01 09:36:22 PM UTC 24 |
| Finished | Sep 01 09:37:49 PM UTC 24 |
| Peak memory | 280348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798054270 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.798054270 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/44.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/44.kmac_key_error.766877463 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 1863832327 ps |
| CPU time | 15.43 seconds |
| Started | Sep 01 09:36:47 PM UTC 24 |
| Finished | Sep 01 09:37:04 PM UTC 24 |
| Peak memory | 230332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766877463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.766877463 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/44.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/44.kmac_lc_escalation.1932294907 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 36368630 ps |
| CPU time | 1.85 seconds |
| Started | Sep 01 09:36:48 PM UTC 24 |
| Finished | Sep 01 09:36:51 PM UTC 24 |
| Peak memory | 229844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932294907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.1932294907 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/44.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/44.kmac_long_msg_and_output.3244288205 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 22567674212 ps |
| CPU time | 2754.36 seconds |
| Started | Sep 01 09:36:07 PM UTC 24 |
| Finished | Sep 01 10:22:34 PM UTC 24 |
| Peak memory | 1644452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244288205 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_and_output.3244288205 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/44.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/44.kmac_sideload.4094029336 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 84044130486 ps |
| CPU time | 233.38 seconds |
| Started | Sep 01 09:36:08 PM UTC 24 |
| Finished | Sep 01 09:40:06 PM UTC 24 |
| Peak memory | 392964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094029336 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.4094029336 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/44.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/44.kmac_smoke.341940853 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 2226792534 ps |
| CPU time | 15.45 seconds |
| Started | Sep 01 09:36:03 PM UTC 24 |
| Finished | Sep 01 09:36:20 PM UTC 24 |
| Peak memory | 232620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341940853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.341940853 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/44.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/44.kmac_stress_all.2857597436 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 421501698662 ps |
| CPU time | 3245.65 seconds |
| Started | Sep 01 09:36:52 PM UTC 24 |
| Finished | Sep 01 10:31:37 PM UTC 24 |
| Peak memory | 1265652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857597436 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.2857597436 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/44.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/45.kmac_alert_test.3563659747 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 12931715 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 09:38:21 PM UTC 24 |
| Finished | Sep 01 09:38:23 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563659747 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.3563659747 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/45.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/45.kmac_app.2437596562 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 59327589553 ps |
| CPU time | 350 seconds |
| Started | Sep 01 09:37:46 PM UTC 24 |
| Finished | Sep 01 09:43:41 PM UTC 24 |
| Peak memory | 522036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437596562 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.2437596562 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/45.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/45.kmac_burst_write.947343219 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 77111586058 ps |
| CPU time | 794.62 seconds |
| Started | Sep 01 09:37:42 PM UTC 24 |
| Finished | Sep 01 09:51:07 PM UTC 24 |
| Peak memory | 257840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947343219 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.947343219 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/45.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/45.kmac_entropy_refresh.2034944840 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 13293408361 ps |
| CPU time | 147.37 seconds |
| Started | Sep 01 09:37:50 PM UTC 24 |
| Finished | Sep 01 09:40:20 PM UTC 24 |
| Peak memory | 356212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034944840 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.2034944840 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/45.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/45.kmac_error.2585779121 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 6593315745 ps |
| CPU time | 194.69 seconds |
| Started | Sep 01 09:37:53 PM UTC 24 |
| Finished | Sep 01 09:41:11 PM UTC 24 |
| Peak memory | 395048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585779121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.2585779121 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/45.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/45.kmac_key_error.1349564008 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 711129085 ps |
| CPU time | 7.31 seconds |
| Started | Sep 01 09:38:12 PM UTC 24 |
| Finished | Sep 01 09:38:20 PM UTC 24 |
| Peak memory | 230588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349564008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.1349564008 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/45.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/45.kmac_lc_escalation.4001104125 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 203617524 ps |
| CPU time | 1.92 seconds |
| Started | Sep 01 09:38:14 PM UTC 24 |
| Finished | Sep 01 09:38:17 PM UTC 24 |
| Peak memory | 229796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001104125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.4001104125 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/45.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/45.kmac_long_msg_and_output.1993906637 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 17746857537 ps |
| CPU time | 1847.89 seconds |
| Started | Sep 01 09:37:04 PM UTC 24 |
| Finished | Sep 01 10:08:13 PM UTC 24 |
| Peak memory | 1339152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993906637 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_and_output.1993906637 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/45.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/45.kmac_sideload.3507984395 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 17718494689 ps |
| CPU time | 421.98 seconds |
| Started | Sep 01 09:37:26 PM UTC 24 |
| Finished | Sep 01 09:44:34 PM UTC 24 |
| Peak memory | 587568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507984395 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.3507984395 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/45.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/45.kmac_smoke.1094905909 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 5104979423 ps |
| CPU time | 40.36 seconds |
| Started | Sep 01 09:36:58 PM UTC 24 |
| Finished | Sep 01 09:37:40 PM UTC 24 |
| Peak memory | 230900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094905909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.1094905909 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/45.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/45.kmac_stress_all.4228098276 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 99442998446 ps |
| CPU time | 689.11 seconds |
| Started | Sep 01 09:38:18 PM UTC 24 |
| Finished | Sep 01 09:49:56 PM UTC 24 |
| Peak memory | 739124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228098276 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.4228098276 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/45.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/46.kmac_alert_test.4240382177 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 16011436 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 09:40:14 PM UTC 24 |
| Finished | Sep 01 09:40:16 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240382177 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.4240382177 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/46.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/46.kmac_app.3910503681 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 4801134684 ps |
| CPU time | 261.1 seconds |
| Started | Sep 01 09:39:08 PM UTC 24 |
| Finished | Sep 01 09:43:33 PM UTC 24 |
| Peak memory | 325356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910503681 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.3910503681 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/46.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/46.kmac_burst_write.626533316 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 1280828223 ps |
| CPU time | 150.28 seconds |
| Started | Sep 01 09:38:53 PM UTC 24 |
| Finished | Sep 01 09:41:26 PM UTC 24 |
| Peak memory | 234664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626533316 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.626533316 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/46.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/46.kmac_entropy_refresh.2855667905 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 29959579326 ps |
| CPU time | 327.12 seconds |
| Started | Sep 01 09:40:02 PM UTC 24 |
| Finished | Sep 01 09:45:34 PM UTC 24 |
| Peak memory | 466732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855667905 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.2855667905 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/46.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/46.kmac_error.1950619806 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 2665656474 ps |
| CPU time | 34.65 seconds |
| Started | Sep 01 09:40:05 PM UTC 24 |
| Finished | Sep 01 09:40:42 PM UTC 24 |
| Peak memory | 251632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950619806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.1950619806 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/46.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/46.kmac_key_error.3425014662 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 2258924651 ps |
| CPU time | 5.53 seconds |
| Started | Sep 01 09:40:06 PM UTC 24 |
| Finished | Sep 01 09:40:13 PM UTC 24 |
| Peak memory | 230392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425014662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.3425014662 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/46.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/46.kmac_lc_escalation.3399200094 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 34499732 ps |
| CPU time | 1.66 seconds |
| Started | Sep 01 09:40:10 PM UTC 24 |
| Finished | Sep 01 09:40:12 PM UTC 24 |
| Peak memory | 229736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399200094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.3399200094 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/46.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/46.kmac_long_msg_and_output.2558671023 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 20496511318 ps |
| CPU time | 828.08 seconds |
| Started | Sep 01 09:38:34 PM UTC 24 |
| Finished | Sep 01 09:52:33 PM UTC 24 |
| Peak memory | 1169192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558671023 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_and_output.2558671023 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/46.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/46.kmac_sideload.1999946311 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 13763825070 ps |
| CPU time | 288.06 seconds |
| Started | Sep 01 09:38:38 PM UTC 24 |
| Finished | Sep 01 09:43:30 PM UTC 24 |
| Peak memory | 321476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999946311 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.1999946311 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/46.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/46.kmac_smoke.1733266784 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 1091074716 ps |
| CPU time | 25.7 seconds |
| Started | Sep 01 09:38:24 PM UTC 24 |
| Finished | Sep 01 09:38:51 PM UTC 24 |
| Peak memory | 230464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733266784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.1733266784 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/46.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/46.kmac_stress_all.2855192431 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 3662835833 ps |
| CPU time | 49.84 seconds |
| Started | Sep 01 09:40:13 PM UTC 24 |
| Finished | Sep 01 09:41:04 PM UTC 24 |
| Peak memory | 234704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855192431 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.2855192431 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/46.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/47.kmac_alert_test.1061971860 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 56896642 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 09:41:27 PM UTC 24 |
| Finished | Sep 01 09:41:29 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061971860 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.1061971860 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/47.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/47.kmac_app.494831926 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 12533311659 ps |
| CPU time | 196.39 seconds |
| Started | Sep 01 09:41:05 PM UTC 24 |
| Finished | Sep 01 09:44:25 PM UTC 24 |
| Peak memory | 296876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494831926 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.494831926 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/47.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/47.kmac_burst_write.2205046318 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 16144462113 ps |
| CPU time | 918.96 seconds |
| Started | Sep 01 09:40:51 PM UTC 24 |
| Finished | Sep 01 09:56:22 PM UTC 24 |
| Peak memory | 253860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205046318 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.2205046318 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/47.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/47.kmac_entropy_refresh.1232914503 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 8276503657 ps |
| CPU time | 163.77 seconds |
| Started | Sep 01 09:41:11 PM UTC 24 |
| Finished | Sep 01 09:43:58 PM UTC 24 |
| Peak memory | 343864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232914503 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.1232914503 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/47.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/47.kmac_error.2793797510 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 6866593018 ps |
| CPU time | 230.29 seconds |
| Started | Sep 01 09:41:16 PM UTC 24 |
| Finished | Sep 01 09:45:11 PM UTC 24 |
| Peak memory | 419552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793797510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.2793797510 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/47.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/47.kmac_key_error.1563216511 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 5846464004 ps |
| CPU time | 17.83 seconds |
| Started | Sep 01 09:41:18 PM UTC 24 |
| Finished | Sep 01 09:41:37 PM UTC 24 |
| Peak memory | 230440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563216511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.1563216511 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/47.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/47.kmac_lc_escalation.3129574028 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 39404144 ps |
| CPU time | 1.9 seconds |
| Started | Sep 01 09:41:21 PM UTC 24 |
| Finished | Sep 01 09:41:24 PM UTC 24 |
| Peak memory | 231664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129574028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.3129574028 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/47.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/47.kmac_long_msg_and_output.2062829922 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 7085452274 ps |
| CPU time | 111.32 seconds |
| Started | Sep 01 09:40:21 PM UTC 24 |
| Finished | Sep 01 09:42:14 PM UTC 24 |
| Peak memory | 290540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062829922 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_and_output.2062829922 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/47.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/47.kmac_sideload.1775645457 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 22992237186 ps |
| CPU time | 170.79 seconds |
| Started | Sep 01 09:40:42 PM UTC 24 |
| Finished | Sep 01 09:43:36 PM UTC 24 |
| Peak memory | 329520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775645457 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.1775645457 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/47.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/47.kmac_smoke.1483920803 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 1632003066 ps |
| CPU time | 57.32 seconds |
| Started | Sep 01 09:40:17 PM UTC 24 |
| Finished | Sep 01 09:41:16 PM UTC 24 |
| Peak memory | 230452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483920803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.1483920803 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/47.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/47.kmac_stress_all.243772898 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 1145721081 ps |
| CPU time | 16.76 seconds |
| Started | Sep 01 09:41:25 PM UTC 24 |
| Finished | Sep 01 09:41:43 PM UTC 24 |
| Peak memory | 232516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243772898 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.243772898 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/47.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/48.kmac_alert_test.67040896 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 11790578 ps |
| CPU time | 1.17 seconds |
| Started | Sep 01 09:42:33 PM UTC 24 |
| Finished | Sep 01 09:42:35 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67040896 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.67040896 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/48.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/48.kmac_app.1510431791 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 3143865855 ps |
| CPU time | 40.01 seconds |
| Started | Sep 01 09:42:03 PM UTC 24 |
| Finished | Sep 01 09:42:45 PM UTC 24 |
| Peak memory | 241440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510431791 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.1510431791 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/48.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/48.kmac_burst_write.2455392810 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 19412403285 ps |
| CPU time | 108.33 seconds |
| Started | Sep 01 09:41:44 PM UTC 24 |
| Finished | Sep 01 09:43:35 PM UTC 24 |
| Peak memory | 235300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455392810 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.2455392810 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/48.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/48.kmac_entropy_refresh.123141607 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 4761425310 ps |
| CPU time | 120.82 seconds |
| Started | Sep 01 09:42:10 PM UTC 24 |
| Finished | Sep 01 09:44:13 PM UTC 24 |
| Peak memory | 329500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123141607 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.123141607 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/48.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/48.kmac_error.387715926 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 3866131663 ps |
| CPU time | 34.83 seconds |
| Started | Sep 01 09:42:16 PM UTC 24 |
| Finished | Sep 01 09:42:52 PM UTC 24 |
| Peak memory | 261928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387715926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.387715926 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/48.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/48.kmac_key_error.467556735 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 9468024290 ps |
| CPU time | 12.61 seconds |
| Started | Sep 01 09:42:19 PM UTC 24 |
| Finished | Sep 01 09:42:32 PM UTC 24 |
| Peak memory | 230668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467556735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.467556735 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/48.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/48.kmac_lc_escalation.2899790983 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 76357798 ps |
| CPU time | 1.96 seconds |
| Started | Sep 01 09:42:23 PM UTC 24 |
| Finished | Sep 01 09:42:26 PM UTC 24 |
| Peak memory | 233712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899790983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.2899790983 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/48.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/48.kmac_long_msg_and_output.2720531816 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 82947087597 ps |
| CPU time | 1937.04 seconds |
| Started | Sep 01 09:41:34 PM UTC 24 |
| Finished | Sep 01 10:14:15 PM UTC 24 |
| Peak memory | 2099176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720531816 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_and_output.2720531816 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/48.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/48.kmac_sideload.144273582 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 7422302827 ps |
| CPU time | 54.32 seconds |
| Started | Sep 01 09:41:37 PM UTC 24 |
| Finished | Sep 01 09:42:33 PM UTC 24 |
| Peak memory | 262124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144273582 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.144273582 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/48.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/48.kmac_smoke.2092522688 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 814417691 ps |
| CPU time | 46.44 seconds |
| Started | Sep 01 09:41:30 PM UTC 24 |
| Finished | Sep 01 09:42:18 PM UTC 24 |
| Peak memory | 230768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092522688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.2092522688 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/48.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/48.kmac_stress_all.87624416 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 322104111593 ps |
| CPU time | 1014.63 seconds |
| Started | Sep 01 09:42:27 PM UTC 24 |
| Finished | Sep 01 09:59:34 PM UTC 24 |
| Peak memory | 1034368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87624416 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.87624416 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/48.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/49.kmac_alert_test.3428180968 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 30733720 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 09:43:31 PM UTC 24 |
| Finished | Sep 01 09:43:33 PM UTC 24 |
| Peak memory | 216348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428180968 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.3428180968 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/49.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/49.kmac_app.264605926 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 15986553649 ps |
| CPU time | 315.38 seconds |
| Started | Sep 01 09:42:52 PM UTC 24 |
| Finished | Sep 01 09:48:13 PM UTC 24 |
| Peak memory | 505716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264605926 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.264605926 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/49.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/49.kmac_burst_write.3346892990 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 11443003054 ps |
| CPU time | 101.7 seconds |
| Started | Sep 01 09:42:49 PM UTC 24 |
| Finished | Sep 01 09:44:33 PM UTC 24 |
| Peak memory | 235304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346892990 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.3346892990 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/49.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/49.kmac_entropy_refresh.2522853482 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 6944247950 ps |
| CPU time | 248.9 seconds |
| Started | Sep 01 09:43:04 PM UTC 24 |
| Finished | Sep 01 09:47:17 PM UTC 24 |
| Peak memory | 306932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522853482 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.2522853482 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/49.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/49.kmac_error.2740378086 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 7397642361 ps |
| CPU time | 65.62 seconds |
| Started | Sep 01 09:43:15 PM UTC 24 |
| Finished | Sep 01 09:44:23 PM UTC 24 |
| Peak memory | 264240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740378086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.2740378086 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/49.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/49.kmac_key_error.3644341732 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 7977621295 ps |
| CPU time | 20 seconds |
| Started | Sep 01 09:43:22 PM UTC 24 |
| Finished | Sep 01 09:43:43 PM UTC 24 |
| Peak memory | 230452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644341732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.3644341732 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/49.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/49.kmac_lc_escalation.3118210212 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 94884276 ps |
| CPU time | 2.09 seconds |
| Started | Sep 01 09:43:27 PM UTC 24 |
| Finished | Sep 01 09:43:30 PM UTC 24 |
| Peak memory | 230312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118210212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.3118210212 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/49.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/49.kmac_long_msg_and_output.761084570 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 61623322747 ps |
| CPU time | 186.93 seconds |
| Started | Sep 01 09:42:36 PM UTC 24 |
| Finished | Sep 01 09:45:46 PM UTC 24 |
| Peak memory | 462656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761084570 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_and_output.761084570 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/49.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/49.kmac_sideload.719502164 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 6743477046 ps |
| CPU time | 212.62 seconds |
| Started | Sep 01 09:42:46 PM UTC 24 |
| Finished | Sep 01 09:46:22 PM UTC 24 |
| Peak memory | 405300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719502164 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.719502164 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/49.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/49.kmac_smoke.1314605546 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 30854740503 ps |
| CPU time | 74.28 seconds |
| Started | Sep 01 09:42:34 PM UTC 24 |
| Finished | Sep 01 09:43:50 PM UTC 24 |
| Peak memory | 232976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314605546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.1314605546 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/49.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/49.kmac_stress_all.592846884 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 13743389706 ps |
| CPU time | 1310.86 seconds |
| Started | Sep 01 09:43:31 PM UTC 24 |
| Finished | Sep 01 10:05:38 PM UTC 24 |
| Peak memory | 753468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592846884 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.592846884 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/49.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/5.kmac_alert_test.2218269634 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 71764084 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 08:54:55 PM UTC 24 |
| Finished | Sep 01 08:54:57 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218269634 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.2218269634 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/5.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/5.kmac_app.341954645 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 7927206780 ps |
| CPU time | 212.01 seconds |
| Started | Sep 01 08:54:07 PM UTC 24 |
| Finished | Sep 01 08:57:43 PM UTC 24 |
| Peak memory | 311028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341954645 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.341954645 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/5.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/5.kmac_app_with_partial_data.1371810637 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 12731275697 ps |
| CPU time | 241.39 seconds |
| Started | Sep 01 08:54:09 PM UTC 24 |
| Finished | Sep 01 08:58:14 PM UTC 24 |
| Peak memory | 452340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371810637 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.1371810637 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/5.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/5.kmac_burst_write.986144823 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 57174857027 ps |
| CPU time | 484.01 seconds |
| Started | Sep 01 08:54:07 PM UTC 24 |
| Finished | Sep 01 09:02:18 PM UTC 24 |
| Peak memory | 249652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986144823 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.986144823 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/5.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/5.kmac_edn_timeout_error.91972538 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 629039342 ps |
| CPU time | 30.9 seconds |
| Started | Sep 01 08:54:31 PM UTC 24 |
| Finished | Sep 01 08:55:04 PM UTC 24 |
| Peak memory | 235308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91972538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.91972538 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/5.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_mode_error.3264660242 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 589198338 ps |
| CPU time | 30.82 seconds |
| Started | Sep 01 08:54:38 PM UTC 24 |
| Finished | Sep 01 08:55:10 PM UTC 24 |
| Peak memory | 230476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264660242 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.3264660242 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/5.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_refresh.231234071 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 11732600588 ps |
| CPU time | 195.78 seconds |
| Started | Sep 01 08:54:09 PM UTC 24 |
| Finished | Sep 01 08:57:28 PM UTC 24 |
| Peak memory | 298720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231234071 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.231234071 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/5.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/5.kmac_error.454388895 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 4422735453 ps |
| CPU time | 116.84 seconds |
| Started | Sep 01 08:54:30 PM UTC 24 |
| Finished | Sep 01 08:56:29 PM UTC 24 |
| Peak memory | 282388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454388895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.454388895 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/5.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/5.kmac_key_error.2676909976 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 2021338103 ps |
| CPU time | 11.16 seconds |
| Started | Sep 01 08:54:31 PM UTC 24 |
| Finished | Sep 01 08:54:44 PM UTC 24 |
| Peak memory | 230464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676909976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.2676909976 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/5.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/5.kmac_lc_escalation.1836692440 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 89059287 ps |
| CPU time | 1.75 seconds |
| Started | Sep 01 08:54:49 PM UTC 24 |
| Finished | Sep 01 08:54:52 PM UTC 24 |
| Peak memory | 231724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836692440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.1836692440 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/5.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/5.kmac_long_msg_and_output.2823949048 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 279718868908 ps |
| CPU time | 1219.42 seconds |
| Started | Sep 01 08:54:01 PM UTC 24 |
| Finished | Sep 01 09:14:35 PM UTC 24 |
| Peak memory | 1593328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823949048 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and_output.2823949048 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/5.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/5.kmac_mubi.2801390638 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 4929698955 ps |
| CPU time | 91.12 seconds |
| Started | Sep 01 08:54:20 PM UTC 24 |
| Finished | Sep 01 08:55:53 PM UTC 24 |
| Peak memory | 282860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801390638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.2801390638 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/5.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/5.kmac_sideload.3994116111 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 5653248906 ps |
| CPU time | 92.49 seconds |
| Started | Sep 01 08:54:03 PM UTC 24 |
| Finished | Sep 01 08:55:37 PM UTC 24 |
| Peak memory | 284456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994116111 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.3994116111 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/5.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/5.kmac_smoke.266824250 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 5591418989 ps |
| CPU time | 35.51 seconds |
| Started | Sep 01 08:54:00 PM UTC 24 |
| Finished | Sep 01 08:54:37 PM UTC 24 |
| Peak memory | 230528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266824250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.266824250 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/5.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/6.kmac_alert_test.231623298 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 19089752 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 08:56:14 PM UTC 24 |
| Finished | Sep 01 08:56:16 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231623298 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.231623298 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/6.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/6.kmac_app.3591206518 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 36224748486 ps |
| CPU time | 180.06 seconds |
| Started | Sep 01 08:55:15 PM UTC 24 |
| Finished | Sep 01 08:58:18 PM UTC 24 |
| Peak memory | 284520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591206518 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.3591206518 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/6.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/6.kmac_app_with_partial_data.2918135152 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 8776350449 ps |
| CPU time | 206.53 seconds |
| Started | Sep 01 08:55:20 PM UTC 24 |
| Finished | Sep 01 08:58:50 PM UTC 24 |
| Peak memory | 364324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918135152 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.2918135152 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/6.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/6.kmac_burst_write.1612804829 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 25039016388 ps |
| CPU time | 675.37 seconds |
| Started | Sep 01 08:55:11 PM UTC 24 |
| Finished | Sep 01 09:06:36 PM UTC 24 |
| Peak memory | 247672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612804829 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.1612804829 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/6.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/6.kmac_edn_timeout_error.1496227392 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 6234572755 ps |
| CPU time | 42.97 seconds |
| Started | Sep 01 08:55:51 PM UTC 24 |
| Finished | Sep 01 08:56:35 PM UTC 24 |
| Peak memory | 240640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496227392 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.1496227392 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/6.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_mode_error.3856024152 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 1148203351 ps |
| CPU time | 26.32 seconds |
| Started | Sep 01 08:55:54 PM UTC 24 |
| Finished | Sep 01 08:56:21 PM UTC 24 |
| Peak memory | 234424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856024152 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.3856024152 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/6.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_ready_error.32633203 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 12354574908 ps |
| CPU time | 49.23 seconds |
| Started | Sep 01 08:55:54 PM UTC 24 |
| Finished | Sep 01 08:56:45 PM UTC 24 |
| Peak memory | 230656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32633203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_un masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.32633203 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/6.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_refresh.3930721900 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 8143697052 ps |
| CPU time | 35.15 seconds |
| Started | Sep 01 08:55:38 PM UTC 24 |
| Finished | Sep 01 08:56:15 PM UTC 24 |
| Peak memory | 255728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930721900 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.3930721900 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/6.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/6.kmac_error.2778961248 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 2610143614 ps |
| CPU time | 91.68 seconds |
| Started | Sep 01 08:55:44 PM UTC 24 |
| Finished | Sep 01 08:57:17 PM UTC 24 |
| Peak memory | 292852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778961248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.2778961248 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/6.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/6.kmac_key_error.152942390 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 623067479 ps |
| CPU time | 4.35 seconds |
| Started | Sep 01 08:55:48 PM UTC 24 |
| Finished | Sep 01 08:55:53 PM UTC 24 |
| Peak memory | 230380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152942390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.152942390 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/6.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/6.kmac_lc_escalation.1446562270 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 92958891 ps |
| CPU time | 1.91 seconds |
| Started | Sep 01 08:56:01 PM UTC 24 |
| Finished | Sep 01 08:56:04 PM UTC 24 |
| Peak memory | 229932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446562270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.1446562270 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/6.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/6.kmac_long_msg_and_output.4188944361 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 25755950566 ps |
| CPU time | 3001.03 seconds |
| Started | Sep 01 08:55:05 PM UTC 24 |
| Finished | Sep 01 09:45:40 PM UTC 24 |
| Peak memory | 1878020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188944361 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and_output.4188944361 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/6.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/6.kmac_mubi.1577608819 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 13328902678 ps |
| CPU time | 239.33 seconds |
| Started | Sep 01 08:55:38 PM UTC 24 |
| Finished | Sep 01 08:59:42 PM UTC 24 |
| Peak memory | 376864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577608819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.1577608819 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/6.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/6.kmac_sideload.4228436390 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 1215100846 ps |
| CPU time | 87.58 seconds |
| Started | Sep 01 08:55:09 PM UTC 24 |
| Finished | Sep 01 08:56:39 PM UTC 24 |
| Peak memory | 257768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228436390 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.4228436390 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/6.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/6.kmac_smoke.1845674455 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 860772330 ps |
| CPU time | 15.24 seconds |
| Started | Sep 01 08:54:58 PM UTC 24 |
| Finished | Sep 01 08:55:14 PM UTC 24 |
| Peak memory | 230716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845674455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.1845674455 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/6.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/6.kmac_stress_all.4260501724 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 3897376964 ps |
| CPU time | 121.97 seconds |
| Started | Sep 01 08:56:01 PM UTC 24 |
| Finished | Sep 01 08:58:06 PM UTC 24 |
| Peak memory | 321520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260501724 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.4260501724 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/6.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/7.kmac_alert_test.305546737 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 22172901 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 08:56:56 PM UTC 24 |
| Finished | Sep 01 08:56:58 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305546737 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.305546737 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/7.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/7.kmac_app.3463847634 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 35617730159 ps |
| CPU time | 110.66 seconds |
| Started | Sep 01 08:56:29 PM UTC 24 |
| Finished | Sep 01 08:58:22 PM UTC 24 |
| Peak memory | 272104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463847634 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.3463847634 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/7.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/7.kmac_app_with_partial_data.286469288 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 18442188936 ps |
| CPU time | 160.89 seconds |
| Started | Sep 01 08:56:30 PM UTC 24 |
| Finished | Sep 01 08:59:14 PM UTC 24 |
| Peak memory | 343764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286469288 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.286469288 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/7.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/7.kmac_burst_write.3545976280 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 17643453311 ps |
| CPU time | 400.13 seconds |
| Started | Sep 01 08:56:22 PM UTC 24 |
| Finished | Sep 01 09:03:08 PM UTC 24 |
| Peak memory | 243444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545976280 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.3545976280 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/7.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/7.kmac_edn_timeout_error.969638182 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 2323590784 ps |
| CPU time | 34.87 seconds |
| Started | Sep 01 08:56:39 PM UTC 24 |
| Finished | Sep 01 08:57:16 PM UTC 24 |
| Peak memory | 230400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969638182 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.969638182 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/7.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_mode_error.523010974 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 345759708 ps |
| CPU time | 32.8 seconds |
| Started | Sep 01 08:56:43 PM UTC 24 |
| Finished | Sep 01 08:57:17 PM UTC 24 |
| Peak memory | 234552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523010974 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.523010974 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/7.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_ready_error.910579400 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 39961332935 ps |
| CPU time | 97.49 seconds |
| Started | Sep 01 08:56:45 PM UTC 24 |
| Finished | Sep 01 08:58:25 PM UTC 24 |
| Peak memory | 230588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910579400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_u nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.910579400 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/7.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_refresh.3826678026 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 64171004 ps |
| CPU time | 2.78 seconds |
| Started | Sep 01 08:56:32 PM UTC 24 |
| Finished | Sep 01 08:56:36 PM UTC 24 |
| Peak memory | 230540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826678026 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.3826678026 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/7.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/7.kmac_error.3015678886 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 4909604298 ps |
| CPU time | 38.79 seconds |
| Started | Sep 01 08:56:37 PM UTC 24 |
| Finished | Sep 01 08:57:18 PM UTC 24 |
| Peak memory | 266028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015678886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.3015678886 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/7.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/7.kmac_key_error.3410558405 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 6022160058 ps |
| CPU time | 12.63 seconds |
| Started | Sep 01 08:56:37 PM UTC 24 |
| Finished | Sep 01 08:56:51 PM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410558405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.3410558405 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/7.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/7.kmac_lc_escalation.3668377886 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 110597333 ps |
| CPU time | 2.03 seconds |
| Started | Sep 01 08:56:52 PM UTC 24 |
| Finished | Sep 01 08:56:55 PM UTC 24 |
| Peak memory | 230324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668377886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.3668377886 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/7.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/7.kmac_long_msg_and_output.1872462835 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 78769188775 ps |
| CPU time | 404.75 seconds |
| Started | Sep 01 08:56:16 PM UTC 24 |
| Finished | Sep 01 09:03:06 PM UTC 24 |
| Peak memory | 763632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872462835 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_and_output.1872462835 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/7.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/7.kmac_mubi.2636798222 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 5752692269 ps |
| CPU time | 147.93 seconds |
| Started | Sep 01 08:56:36 PM UTC 24 |
| Finished | Sep 01 08:59:07 PM UTC 24 |
| Peak memory | 356460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636798222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.2636798222 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/7.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/7.kmac_sideload.408387061 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 70117360369 ps |
| CPU time | 467.38 seconds |
| Started | Sep 01 08:56:17 PM UTC 24 |
| Finished | Sep 01 09:04:11 PM UTC 24 |
| Peak memory | 607980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408387061 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.408387061 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/7.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/7.kmac_smoke.3713300581 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 2209416020 ps |
| CPU time | 69.05 seconds |
| Started | Sep 01 08:56:15 PM UTC 24 |
| Finished | Sep 01 08:57:26 PM UTC 24 |
| Peak memory | 232628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713300581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.3713300581 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/7.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/7.kmac_stress_all.4068700878 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 25100286840 ps |
| CPU time | 636.91 seconds |
| Started | Sep 01 08:56:53 PM UTC 24 |
| Finished | Sep 01 09:07:38 PM UTC 24 |
| Peak memory | 890884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068700878 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.4068700878 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/7.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/8.kmac_alert_test.531053444 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 80036831 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 08:57:44 PM UTC 24 |
| Finished | Sep 01 08:57:46 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531053444 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.531053444 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/8.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/8.kmac_app.1459292738 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 23085283104 ps |
| CPU time | 286.26 seconds |
| Started | Sep 01 08:57:11 PM UTC 24 |
| Finished | Sep 01 09:02:02 PM UTC 24 |
| Peak memory | 466792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459292738 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.1459292738 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/8.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/8.kmac_app_with_partial_data.2103374963 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 7739339064 ps |
| CPU time | 61.37 seconds |
| Started | Sep 01 08:57:16 PM UTC 24 |
| Finished | Sep 01 08:58:19 PM UTC 24 |
| Peak memory | 272376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103374963 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.2103374963 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/8.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/8.kmac_burst_write.2383454043 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 42120623739 ps |
| CPU time | 1110.56 seconds |
| Started | Sep 01 08:57:08 PM UTC 24 |
| Finished | Sep 01 09:15:53 PM UTC 24 |
| Peak memory | 264180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383454043 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.2383454043 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/8.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/8.kmac_edn_timeout_error.3627102107 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 1995647845 ps |
| CPU time | 26.15 seconds |
| Started | Sep 01 08:57:24 PM UTC 24 |
| Finished | Sep 01 08:57:51 PM UTC 24 |
| Peak memory | 235256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627102107 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.3627102107 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/8.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_mode_error.1335102665 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 616595554 ps |
| CPU time | 14.69 seconds |
| Started | Sep 01 08:57:27 PM UTC 24 |
| Finished | Sep 01 08:57:43 PM UTC 24 |
| Peak memory | 235044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335102665 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.1335102665 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/8.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_ready_error.1471408903 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 10166342975 ps |
| CPU time | 74.12 seconds |
| Started | Sep 01 08:57:29 PM UTC 24 |
| Finished | Sep 01 08:58:45 PM UTC 24 |
| Peak memory | 230668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471408903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.1471408903 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/8.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_refresh.1673729671 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 134205637483 ps |
| CPU time | 263.39 seconds |
| Started | Sep 01 08:57:17 PM UTC 24 |
| Finished | Sep 01 09:01:45 PM UTC 24 |
| Peak memory | 427816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673729671 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.1673729671 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/8.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/8.kmac_error.3800609101 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 28156533249 ps |
| CPU time | 278.59 seconds |
| Started | Sep 01 08:57:18 PM UTC 24 |
| Finished | Sep 01 09:02:01 PM UTC 24 |
| Peak memory | 423792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800609101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.3800609101 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/8.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/8.kmac_key_error.3874387697 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 968859760 ps |
| CPU time | 3.39 seconds |
| Started | Sep 01 08:57:18 PM UTC 24 |
| Finished | Sep 01 08:57:23 PM UTC 24 |
| Peak memory | 230576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874387697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.3874387697 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/8.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/8.kmac_lc_escalation.253898665 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 85698925 ps |
| CPU time | 2.08 seconds |
| Started | Sep 01 08:57:33 PM UTC 24 |
| Finished | Sep 01 08:57:36 PM UTC 24 |
| Peak memory | 230440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253898665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.253898665 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/8.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/8.kmac_long_msg_and_output.3147383492 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 379230272958 ps |
| CPU time | 4437.02 seconds |
| Started | Sep 01 08:57:02 PM UTC 24 |
| Finished | Sep 01 10:11:48 PM UTC 24 |
| Peak memory | 4169716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147383492 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_and_output.3147383492 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/8.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/8.kmac_mubi.1238631925 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 24422846272 ps |
| CPU time | 171.72 seconds |
| Started | Sep 01 08:57:18 PM UTC 24 |
| Finished | Sep 01 09:00:13 PM UTC 24 |
| Peak memory | 286748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238631925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.1238631925 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/8.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/8.kmac_sideload.1250453609 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 106934953 ps |
| CPU time | 5.04 seconds |
| Started | Sep 01 08:57:04 PM UTC 24 |
| Finished | Sep 01 08:57:10 PM UTC 24 |
| Peak memory | 232560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250453609 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.1250453609 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/8.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/8.kmac_smoke.3373495583 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 792274557 ps |
| CPU time | 14.47 seconds |
| Started | Sep 01 08:56:59 PM UTC 24 |
| Finished | Sep 01 08:57:16 PM UTC 24 |
| Peak memory | 230528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373495583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.3373495583 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/8.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/8.kmac_stress_all.3560317248 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 36546877717 ps |
| CPU time | 1383.1 seconds |
| Started | Sep 01 08:57:37 PM UTC 24 |
| Finished | Sep 01 09:20:57 PM UTC 24 |
| Peak memory | 694008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560317248 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.3560317248 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/8.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/9.kmac_alert_test.1843590154 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 33933340 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 08:58:33 PM UTC 24 |
| Finished | Sep 01 08:58:35 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843590154 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.1843590154 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/9.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/9.kmac_app.1964894348 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 6567998217 ps |
| CPU time | 213.79 seconds |
| Started | Sep 01 08:57:53 PM UTC 24 |
| Finished | Sep 01 09:01:31 PM UTC 24 |
| Peak memory | 321316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964894348 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.1964894348 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/9.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/9.kmac_app_with_partial_data.1929569846 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 38095247035 ps |
| CPU time | 307.27 seconds |
| Started | Sep 01 08:58:01 PM UTC 24 |
| Finished | Sep 01 09:03:13 PM UTC 24 |
| Peak memory | 323360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929569846 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.1929569846 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/9.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/9.kmac_burst_write.2259498276 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 11471746473 ps |
| CPU time | 558.97 seconds |
| Started | Sep 01 08:57:49 PM UTC 24 |
| Finished | Sep 01 09:07:16 PM UTC 24 |
| Peak memory | 251644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259498276 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.2259498276 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/9.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/9.kmac_edn_timeout_error.652154086 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 379993167 ps |
| CPU time | 6.71 seconds |
| Started | Sep 01 08:58:21 PM UTC 24 |
| Finished | Sep 01 08:58:29 PM UTC 24 |
| Peak memory | 228232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652154086 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.652154086 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/9.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_mode_error.2190777967 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 611153162 ps |
| CPU time | 7.91 seconds |
| Started | Sep 01 08:58:24 PM UTC 24 |
| Finished | Sep 01 08:58:33 PM UTC 24 |
| Peak memory | 228496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190777967 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.2190777967 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/9.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_ready_error.2772957451 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 10591944648 ps |
| CPU time | 44.12 seconds |
| Started | Sep 01 08:58:24 PM UTC 24 |
| Finished | Sep 01 08:59:09 PM UTC 24 |
| Peak memory | 230668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772957451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.2772957451 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/9.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_refresh.2868039989 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 13456398535 ps |
| CPU time | 126.43 seconds |
| Started | Sep 01 08:58:07 PM UTC 24 |
| Finished | Sep 01 09:00:16 PM UTC 24 |
| Peak memory | 343996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868039989 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.2868039989 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/9.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/9.kmac_error.2100097698 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 15129818747 ps |
| CPU time | 73.64 seconds |
| Started | Sep 01 08:58:15 PM UTC 24 |
| Finished | Sep 01 08:59:31 PM UTC 24 |
| Peak memory | 280372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100097698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.2100097698 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/9.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/9.kmac_key_error.1761745990 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 7728870272 ps |
| CPU time | 22.55 seconds |
| Started | Sep 01 08:58:19 PM UTC 24 |
| Finished | Sep 01 08:58:43 PM UTC 24 |
| Peak memory | 232768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761745990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.1761745990 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/9.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/9.kmac_long_msg_and_output.1894732464 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 131151016555 ps |
| CPU time | 1589.05 seconds |
| Started | Sep 01 08:57:47 PM UTC 24 |
| Finished | Sep 01 09:24:37 PM UTC 24 |
| Peak memory | 1050420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894732464 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and_output.1894732464 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/9.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/9.kmac_mubi.1500151609 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 11397532278 ps |
| CPU time | 287.9 seconds |
| Started | Sep 01 08:58:11 PM UTC 24 |
| Finished | Sep 01 09:03:04 PM UTC 24 |
| Peak memory | 448552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500151609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.1500151609 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/9.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/9.kmac_sideload.165876915 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 9177706161 ps |
| CPU time | 113.64 seconds |
| Started | Sep 01 08:57:47 PM UTC 24 |
| Finished | Sep 01 08:59:44 PM UTC 24 |
| Peak memory | 311032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165876915 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.165876915 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/9.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/9.kmac_smoke.1674015012 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 2540225328 ps |
| CPU time | 63.35 seconds |
| Started | Sep 01 08:57:44 PM UTC 24 |
| Finished | Sep 01 08:58:49 PM UTC 24 |
| Peak memory | 230600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674015012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.1674015012 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/9.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default/9.kmac_stress_all.3266784361 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 11275643184 ps |
| CPU time | 479.47 seconds |
| Started | Sep 01 08:58:30 PM UTC 24 |
| Finished | Sep 01 09:06:36 PM UTC 24 |
| Peak memory | 327672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266784361 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.3266784361 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/9.kmac_stress_all/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |