Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15174195	1			T1	84		T2	161		T3	2
all_values[1]	15174195	1			T1	84		T2	161		T3	2
all_values[2]	15174195	1			T1	84		T2	161		T3	2

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

480103

1

T1

12

T2

89

T3

2

auto[1]

45042482

1

T1

240

T2

394

T3

4

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45298089

1

T1

237

T2

471

T3

6

auto[1]

224496

1

T1

15

T2

12

T4

15

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	158384	1			T1	8		T2	4		T3	2
all_values[0]	auto[0]	auto[1]	1320	1			T1	4		T2	2		T4	2
all_values[0]	auto[1]	auto[0]	14940979	1			T1	71		T2	153		T4	179
all_values[0]	auto[1]	auto[1]	73512	1			T1	1		T2	2		T4	3
all_values[1]	auto[0]	auto[0]	168432	1			T2	80		T4	74		T12	19
all_values[1]	auto[0]	auto[1]	1024	1			T2	3		T4	2		T12	3
all_values[1]	auto[1]	auto[0]	14930931	1			T1	79		T2	77		T3	2
all_values[1]	auto[1]	auto[1]	73808	1			T1	5		T2	1		T4	3
all_values[2]	auto[0]	auto[0]	150015	1			T4	75		T15	11		T5	17
all_values[2]	auto[0]	auto[1]	928	1			T4	2		T15	3		T82	8
all_values[2]	auto[1]	auto[0]	14949348	1			T1	79		T2	157		T3	2
all_values[2]	auto[1]	auto[1]	73904	1			T1	5		T2	4		T4	3