Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53504 |
1 |
|
|
T1 |
6 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
59250 |
1 |
|
|
T2 |
4 |
|
T4 |
10 |
|
T14 |
18 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
27875 |
1 |
|
|
T1 |
2 |
|
T12 |
7 |
|
T14 |
10 |
lower_val |
27622 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
zero_val |
861 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
56492 |
1 |
|
|
T1 |
2 |
|
T2 |
4 |
|
T4 |
6 |
lower_val |
56260 |
1 |
|
|
T1 |
4 |
|
T2 |
2 |
|
T3 |
2 |
zero_val |
2 |
1 |
|
|
T160 |
2 |
|
- |
- |
|
- |
- |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
5 |
13 |
72.22 |
5 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[lower_val] |
[zero_val] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
6566 |
1 |
|
|
T12 |
5 |
|
T21 |
7 |
|
T32 |
4 |
higher_val |
higher_val |
auto[1] |
7371 |
1 |
|
|
T14 |
2 |
|
T80 |
14 |
|
T22 |
8 |
higher_val |
lower_val |
auto[0] |
6574 |
1 |
|
|
T1 |
2 |
|
T12 |
2 |
|
T14 |
1 |
higher_val |
lower_val |
auto[1] |
7364 |
1 |
|
|
T14 |
7 |
|
T80 |
16 |
|
T22 |
18 |
lower_val |
higher_val |
auto[0] |
6528 |
1 |
|
|
T12 |
3 |
|
T15 |
1 |
|
T16 |
2 |
lower_val |
higher_val |
auto[1] |
7429 |
1 |
|
|
T2 |
1 |
|
T4 |
2 |
|
T14 |
1 |
lower_val |
lower_val |
auto[0] |
6436 |
1 |
|
|
T3 |
1 |
|
T12 |
1 |
|
T80 |
1 |
lower_val |
lower_val |
auto[1] |
7228 |
1 |
|
|
T4 |
1 |
|
T14 |
3 |
|
T80 |
25 |
lower_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T160 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
324 |
1 |
|
|
T12 |
1 |
|
T22 |
1 |
|
T83 |
1 |
zero_val |
higher_val |
auto[1] |
97 |
1 |
|
|
T96 |
2 |
|
T161 |
1 |
|
T93 |
3 |
zero_val |
lower_val |
auto[0] |
357 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
lower_val |
auto[1] |
83 |
1 |
|
|
T32 |
1 |
|
T96 |
1 |
|
T31 |
1 |