Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	166	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	2751	1			T96	7		T54	9		T191	5
len_5001_7500	6696	1			T96	14		T54	44		T191	13
len_2501_5000	1458	1			T96	5		T54	9		T191	4
len_1025_2500	900	1			T96	3		T54	4		T191	2
len_769_1024	5271	1			T32	1		T39	2		T52	1
len_513_768	5709	1			T32	3		T39	1		T52	6
len_257_512	6030	1			T4	2		T32	2		T52	6
len_0_256	20723	1			T1	3		T2	3		T4	1
len_keccak_block_sizes[72]	42	1			T80	1		T82	1		T85	1
len_keccak_block_sizes[104]	37	1			T82	1		T86	1		T87	1
len_keccak_block_sizes[136]	29	1			T87	1		T102	1		T107	1
len_keccak_block_sizes[144]	36	1			T87	1		T102	1		T192	1
len_keccak_block_sizes[168]	28	1			T99	1		T193	1		T194	1
len_1	83	1			T12	1		T80	1		T82	1
len_0	493	1			T80	1		T82	1		T85	1