Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	15174195	1			T1	84		T2	161		T3	2
all_pins[1]	15174195	1			T1	84		T2	161		T3	2
all_pins[2]	15174195	1			T1	84		T2	161		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	45168250	1			T1	251		T2	481		T3	6
values[0x1]	354335	1			T1	1		T2	2		T4	3
transitions[0x0=>0x1]	352599	1			T1	1		T2	2		T4	3
transitions[0x1=>0x0]	352624	1			T1	1		T2	2		T4	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	15100683	1			T1	83		T2	159		T3	2
all_pins[0]	values[0x1]	73512	1			T1	1		T2	2		T4	3
all_pins[0]	transitions[0x0=>0x1]	73495	1			T1	1		T2	2		T4	3
all_pins[0]	transitions[0x1=>0x0]	69	1			T149	2		T178	7		T179	3
all_pins[1]	values[0x0]	15174109	1			T1	84		T2	161		T3	2
all_pins[1]	values[0x1]	86	1			T149	2		T178	7		T179	3
all_pins[1]	transitions[0x0=>0x1]	72	1			T149	2		T178	7		T179	3
all_pins[1]	transitions[0x1=>0x0]	280723	1			T52	51		T36	6916		T60	238
all_pins[2]	values[0x0]	14893458	1			T1	84		T2	161		T3	2
all_pins[2]	values[0x1]	280737	1			T52	51		T36	6916		T60	238
all_pins[2]	transitions[0x0=>0x1]	279032	1			T52	50		T36	6868		T60	238
all_pins[2]	transitions[0x1=>0x0]	71832	1			T1	1		T2	2		T4	3