Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6359629 |
1 |
|
|
T1 |
24 |
|
T2 |
48 |
|
T4 |
559 |
auto[1] |
9751320 |
1 |
|
|
T1 |
150 |
|
T2 |
150 |
|
T4 |
918 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
16077627 |
1 |
|
|
T1 |
174 |
|
T2 |
198 |
|
T4 |
1474 |
triple_byte_access |
10935 |
1 |
|
|
T4 |
2 |
|
T12 |
2 |
|
T14 |
6 |
halfword_access |
11203 |
1 |
|
|
T12 |
2 |
|
T14 |
2 |
|
T32 |
1 |
byte_access |
11184 |
1 |
|
|
T4 |
1 |
|
T12 |
4 |
|
T14 |
1 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
6326307 |
1 |
|
|
T1 |
24 |
|
T2 |
48 |
|
T4 |
556 |
auto[0] |
triple_byte_access |
10935 |
1 |
|
|
T4 |
2 |
|
T12 |
2 |
|
T14 |
6 |
auto[0] |
halfword_access |
11203 |
1 |
|
|
T12 |
2 |
|
T14 |
2 |
|
T32 |
1 |
auto[0] |
byte_access |
11184 |
1 |
|
|
T4 |
1 |
|
T12 |
4 |
|
T14 |
1 |
auto[1] |
word_access |
9751320 |
1 |
|
|
T1 |
150 |
|
T2 |
150 |
|
T4 |
918 |