| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 92.40 | 95.89 | 92.27 | 100.00 | 69.42 | 94.11 | 98.84 | 96.29 |
| T761 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.824730034 | Sep 04 01:38:41 PM UTC 24 | Sep 04 01:38:44 PM UTC 24 | 84402517 ps | ||
| T762 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3945389646 | Sep 04 01:38:41 PM UTC 24 | Sep 04 01:38:44 PM UTC 24 | 27454391 ps | ||
| T763 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3618148391 | Sep 04 01:38:41 PM UTC 24 | Sep 04 01:38:44 PM UTC 24 | 77637216 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.3144962562 | Sep 04 01:38:42 PM UTC 24 | Sep 04 01:38:45 PM UTC 24 | 13589170 ps | ||
| T764 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.2297884100 | Sep 04 01:38:43 PM UTC 24 | Sep 04 01:38:45 PM UTC 24 | 13288488 ps | ||
| T765 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.577828587 | Sep 04 01:38:40 PM UTC 24 | Sep 04 01:38:45 PM UTC 24 | 658900140 ps | ||
| T766 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.64844073 | Sep 04 01:38:41 PM UTC 24 | Sep 04 01:38:45 PM UTC 24 | 395009890 ps | ||
| T767 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.483032592 | Sep 04 01:38:44 PM UTC 24 | Sep 04 01:38:46 PM UTC 24 | 31117570 ps | ||
| T768 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.456857043 | Sep 04 01:38:42 PM UTC 24 | Sep 04 01:38:47 PM UTC 24 | 475349230 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.3728024561 | Sep 04 01:38:44 PM UTC 24 | Sep 04 01:38:47 PM UTC 24 | 55124227 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.298033704 | Sep 04 01:38:41 PM UTC 24 | Sep 04 01:38:47 PM UTC 24 | 423219166 ps | ||
| T769 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1183242130 | Sep 04 01:38:44 PM UTC 24 | Sep 04 01:38:47 PM UTC 24 | 412810999 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.708590533 | Sep 04 01:38:45 PM UTC 24 | Sep 04 01:38:47 PM UTC 24 | 50166319 ps | ||
| T770 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.215415767 | Sep 04 01:38:43 PM UTC 24 | Sep 04 01:38:47 PM UTC 24 | 99185071 ps | ||
| T771 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.3954820981 | Sep 04 01:38:45 PM UTC 24 | Sep 04 01:38:48 PM UTC 24 | 14900662 ps | ||
| T772 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.311318604 | Sep 04 01:38:45 PM UTC 24 | Sep 04 01:38:48 PM UTC 24 | 48235145 ps | ||
| T773 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.1672534601 | Sep 04 01:38:45 PM UTC 24 | Sep 04 01:38:49 PM UTC 24 | 247102082 ps | ||
| T774 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.4273387167 | Sep 04 01:38:45 PM UTC 24 | Sep 04 01:38:49 PM UTC 24 | 178758830 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.4001966843 | Sep 04 01:38:42 PM UTC 24 | Sep 04 01:38:50 PM UTC 24 | 967857841 ps | ||
| T775 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.3553614077 | Sep 04 01:38:45 PM UTC 24 | Sep 04 01:38:50 PM UTC 24 | 288498435 ps | ||
| T776 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.1990190214 | Sep 04 01:38:47 PM UTC 24 | Sep 04 01:38:50 PM UTC 24 | 45046176 ps | ||
| T777 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.2798695057 | Sep 04 01:38:48 PM UTC 24 | Sep 04 01:38:50 PM UTC 24 | 30734462 ps | ||
| T778 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.3504053350 | Sep 04 01:38:47 PM UTC 24 | Sep 04 01:38:50 PM UTC 24 | 86345228 ps | ||
| T779 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.713966278 | Sep 04 01:38:48 PM UTC 24 | Sep 04 01:38:50 PM UTC 24 | 34007889 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.1783109078 | Sep 04 01:38:45 PM UTC 24 | Sep 04 01:38:51 PM UTC 24 | 128415706 ps | ||
| T780 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.1591518688 | Sep 04 01:38:48 PM UTC 24 | Sep 04 01:38:51 PM UTC 24 | 27541242 ps | ||
| T781 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1452170880 | Sep 04 01:38:48 PM UTC 24 | Sep 04 01:38:51 PM UTC 24 | 139821164 ps | ||
| T782 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.3576757815 | Sep 04 01:38:48 PM UTC 24 | Sep 04 01:38:52 PM UTC 24 | 33847365 ps | ||
| T783 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.357251263 | Sep 04 01:38:50 PM UTC 24 | Sep 04 01:38:52 PM UTC 24 | 65074054 ps | ||
| T784 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.675586383 | Sep 04 01:38:50 PM UTC 24 | Sep 04 01:38:52 PM UTC 24 | 12987067 ps | ||
| T785 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.2391221477 | Sep 04 01:38:48 PM UTC 24 | Sep 04 01:38:52 PM UTC 24 | 103865131 ps | ||
| T786 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.289013567 | Sep 04 01:39:00 PM UTC 24 | Sep 04 01:39:03 PM UTC 24 | 85450886 ps | ||
| T787 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.3758287628 | Sep 04 01:38:30 PM UTC 24 | Sep 04 01:38:53 PM UTC 24 | 1484041772 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.1345749420 | Sep 04 01:38:48 PM UTC 24 | Sep 04 01:38:53 PM UTC 24 | 223777634 ps | ||
| T788 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1880085892 | Sep 04 01:38:50 PM UTC 24 | Sep 04 01:38:53 PM UTC 24 | 445939141 ps | ||
| T789 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.2965704834 | Sep 04 01:38:51 PM UTC 24 | Sep 04 01:38:53 PM UTC 24 | 15086490 ps | ||
| T790 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.1887917820 | Sep 04 01:38:49 PM UTC 24 | Sep 04 01:38:53 PM UTC 24 | 90518995 ps | ||
| T791 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.4167925186 | Sep 04 01:38:51 PM UTC 24 | Sep 04 01:38:54 PM UTC 24 | 58502296 ps | ||
| T792 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.239153814 | Sep 04 01:38:51 PM UTC 24 | Sep 04 01:38:54 PM UTC 24 | 37919519 ps | ||
| T793 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.3443479685 | Sep 04 01:38:49 PM UTC 24 | Sep 04 01:38:54 PM UTC 24 | 126953352 ps | ||
| T794 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.1104121099 | Sep 04 01:38:51 PM UTC 24 | Sep 04 01:38:54 PM UTC 24 | 108358509 ps | ||
| T795 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.163841257 | Sep 04 01:38:51 PM UTC 24 | Sep 04 01:38:55 PM UTC 24 | 117204397 ps | ||
| T796 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.1397592109 | Sep 04 01:38:52 PM UTC 24 | Sep 04 01:38:55 PM UTC 24 | 42837275 ps | ||
| T797 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.2947214352 | Sep 04 01:38:52 PM UTC 24 | Sep 04 01:38:55 PM UTC 24 | 106377919 ps | ||
| T798 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.1752792737 | Sep 04 01:38:53 PM UTC 24 | Sep 04 01:38:55 PM UTC 24 | 49005711 ps | ||
| T799 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2396721368 | Sep 04 01:38:52 PM UTC 24 | Sep 04 01:38:55 PM UTC 24 | 145829086 ps | ||
| T800 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.4097331536 | Sep 04 01:38:52 PM UTC 24 | Sep 04 01:38:55 PM UTC 24 | 57105882 ps | ||
| T801 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.2883179456 | Sep 04 01:38:52 PM UTC 24 | Sep 04 01:38:55 PM UTC 24 | 27008882 ps | ||
| T802 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.3046759687 | Sep 04 01:38:54 PM UTC 24 | Sep 04 01:38:56 PM UTC 24 | 42226868 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.1541679066 | Sep 04 01:38:51 PM UTC 24 | Sep 04 01:38:56 PM UTC 24 | 575757872 ps | ||
| T803 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.4255085305 | Sep 04 01:38:54 PM UTC 24 | Sep 04 01:38:56 PM UTC 24 | 45587260 ps | ||
| T804 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.4086734855 | Sep 04 01:38:52 PM UTC 24 | Sep 04 01:38:56 PM UTC 24 | 98627898 ps | ||
| T805 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3484367891 | Sep 04 01:38:54 PM UTC 24 | Sep 04 01:38:57 PM UTC 24 | 37157401 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.2533774224 | Sep 04 01:38:53 PM UTC 24 | Sep 04 01:38:57 PM UTC 24 | 116545070 ps | ||
| T806 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.1550351945 | Sep 04 01:38:54 PM UTC 24 | Sep 04 01:38:57 PM UTC 24 | 85535668 ps | ||
| T807 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.1888380210 | Sep 04 01:38:55 PM UTC 24 | Sep 04 01:38:57 PM UTC 24 | 39480069 ps | ||
| T808 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2891336374 | Sep 04 01:38:55 PM UTC 24 | Sep 04 01:38:57 PM UTC 24 | 102375310 ps | ||
| T809 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.1120509534 | Sep 04 01:38:55 PM UTC 24 | Sep 04 01:38:58 PM UTC 24 | 29764658 ps | ||
| T810 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.3837403769 | Sep 04 01:38:55 PM UTC 24 | Sep 04 01:38:58 PM UTC 24 | 44436113 ps | ||
| T811 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.1331735001 | Sep 04 01:38:55 PM UTC 24 | Sep 04 01:38:58 PM UTC 24 | 75150554 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.2097421718 | Sep 04 01:38:55 PM UTC 24 | Sep 04 01:38:59 PM UTC 24 | 82470807 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.4049158171 | Sep 04 01:38:57 PM UTC 24 | Sep 04 01:38:59 PM UTC 24 | 30636465 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.1710967383 | Sep 04 01:38:55 PM UTC 24 | Sep 04 01:38:59 PM UTC 24 | 109372837 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.3014196415 | Sep 04 01:38:57 PM UTC 24 | Sep 04 01:38:59 PM UTC 24 | 110174457 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.3128410971 | Sep 04 01:38:57 PM UTC 24 | Sep 04 01:38:59 PM UTC 24 | 50725715 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.3037584378 | Sep 04 01:38:55 PM UTC 24 | Sep 04 01:38:59 PM UTC 24 | 223122397 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.4255138803 | Sep 04 01:38:55 PM UTC 24 | Sep 04 01:38:59 PM UTC 24 | 429894916 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.2680122067 | Sep 04 01:38:57 PM UTC 24 | Sep 04 01:39:00 PM UTC 24 | 75507700 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2038964520 | Sep 04 01:38:57 PM UTC 24 | Sep 04 01:39:00 PM UTC 24 | 27111481 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.4141090564 | Sep 04 01:38:58 PM UTC 24 | Sep 04 01:39:00 PM UTC 24 | 32956986 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1183061658 | Sep 04 01:38:57 PM UTC 24 | Sep 04 01:39:00 PM UTC 24 | 82681419 ps | ||
| T823 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.2101497874 | Sep 04 01:38:58 PM UTC 24 | Sep 04 01:39:01 PM UTC 24 | 51234778 ps | ||
| T824 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.412865272 | Sep 04 01:38:59 PM UTC 24 | Sep 04 01:39:01 PM UTC 24 | 27237762 ps | ||
| T825 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.4092469619 | Sep 04 01:38:57 PM UTC 24 | Sep 04 01:39:01 PM UTC 24 | 161371043 ps | ||
| T826 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.929009040 | Sep 04 01:38:59 PM UTC 24 | Sep 04 01:39:01 PM UTC 24 | 43705845 ps | ||
| T827 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2546322368 | Sep 04 01:38:59 PM UTC 24 | Sep 04 01:39:01 PM UTC 24 | 189022670 ps | ||
| T828 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.2772066248 | Sep 04 01:38:58 PM UTC 24 | Sep 04 01:39:02 PM UTC 24 | 156869879 ps | ||
| T829 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.2340448905 | Sep 04 01:39:00 PM UTC 24 | Sep 04 01:39:02 PM UTC 24 | 12627932 ps | ||
| T830 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.1644395365 | Sep 04 01:39:00 PM UTC 24 | Sep 04 01:39:02 PM UTC 24 | 28137217 ps | ||
| T831 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2354574217 | Sep 04 01:38:58 PM UTC 24 | Sep 04 01:39:02 PM UTC 24 | 177428573 ps | ||
| T832 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.3261739696 | Sep 04 01:39:01 PM UTC 24 | Sep 04 01:39:04 PM UTC 24 | 11006332 ps | ||
| T833 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.2292032888 | Sep 04 01:39:00 PM UTC 24 | Sep 04 01:39:03 PM UTC 24 | 22919138 ps | ||
| T834 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2367665182 | Sep 04 01:39:00 PM UTC 24 | Sep 04 01:39:03 PM UTC 24 | 43901003 ps | ||
| T835 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.3310952585 | Sep 04 01:39:00 PM UTC 24 | Sep 04 01:39:03 PM UTC 24 | 96403718 ps | ||
| T836 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.2003096893 | Sep 04 01:39:01 PM UTC 24 | Sep 04 01:39:04 PM UTC 24 | 61109220 ps | ||
| T837 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.1568605733 | Sep 04 01:39:01 PM UTC 24 | Sep 04 01:39:04 PM UTC 24 | 41014741 ps | ||
| T838 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.3574306306 | Sep 04 01:39:01 PM UTC 24 | Sep 04 01:39:04 PM UTC 24 | 27801260 ps | ||
| T839 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.100450225 | Sep 04 01:39:02 PM UTC 24 | Sep 04 01:39:04 PM UTC 24 | 145109500 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.3449560065 | Sep 04 01:38:58 PM UTC 24 | Sep 04 01:39:05 PM UTC 24 | 219930911 ps | ||
| T840 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.3123681493 | Sep 04 01:39:00 PM UTC 24 | Sep 04 01:39:05 PM UTC 24 | 156912257 ps | ||
| T841 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.1947666563 | Sep 04 01:39:01 PM UTC 24 | Sep 04 01:39:05 PM UTC 24 | 40406281 ps | ||
| T842 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.1431203304 | Sep 04 01:39:03 PM UTC 24 | Sep 04 01:39:05 PM UTC 24 | 18392532 ps | ||
| T843 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.667883282 | Sep 04 01:39:02 PM UTC 24 | Sep 04 01:39:05 PM UTC 24 | 132459977 ps | ||
| T844 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.1334148854 | Sep 04 01:39:03 PM UTC 24 | Sep 04 01:39:05 PM UTC 24 | 34124926 ps | ||
| T845 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.2518219587 | Sep 04 01:39:00 PM UTC 24 | Sep 04 01:39:06 PM UTC 24 | 237623077 ps | ||
| T846 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.3511557163 | Sep 04 01:39:03 PM UTC 24 | Sep 04 01:39:06 PM UTC 24 | 21581294 ps | ||
| T847 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1394980890 | Sep 04 01:39:03 PM UTC 24 | Sep 04 01:39:06 PM UTC 24 | 40050453 ps | ||
| T848 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.2934778099 | Sep 04 01:39:04 PM UTC 24 | Sep 04 01:39:06 PM UTC 24 | 12806208 ps | ||
| T849 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.273784012 | Sep 04 01:39:04 PM UTC 24 | Sep 04 01:39:06 PM UTC 24 | 20809654 ps | ||
| T850 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.1313392922 | Sep 04 01:39:04 PM UTC 24 | Sep 04 01:39:06 PM UTC 24 | 29285201 ps | ||
| T851 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.3745479521 | Sep 04 01:39:05 PM UTC 24 | Sep 04 01:39:06 PM UTC 24 | 27850788 ps | ||
| T852 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.204953096 | Sep 04 01:39:03 PM UTC 24 | Sep 04 01:39:06 PM UTC 24 | 102386084 ps | ||
| T853 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.790152731 | Sep 04 01:39:05 PM UTC 24 | Sep 04 01:39:07 PM UTC 24 | 36212488 ps | ||
| T854 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.4001328701 | Sep 04 01:39:04 PM UTC 24 | Sep 04 01:39:07 PM UTC 24 | 37660771 ps | ||
| T855 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.3871056473 | Sep 04 01:39:01 PM UTC 24 | Sep 04 01:39:07 PM UTC 24 | 147353119 ps | ||
| T856 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.554112043 | Sep 04 01:39:03 PM UTC 24 | Sep 04 01:39:07 PM UTC 24 | 449119488 ps | ||
| T857 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.909584411 | Sep 04 01:39:04 PM UTC 24 | Sep 04 01:39:08 PM UTC 24 | 185682043 ps | ||
| T858 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.2188607742 | Sep 04 01:39:06 PM UTC 24 | Sep 04 01:39:08 PM UTC 24 | 46588361 ps | ||
| T859 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.3784322926 | Sep 04 01:39:06 PM UTC 24 | Sep 04 01:39:08 PM UTC 24 | 22324032 ps | ||
| T860 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.371249766 | Sep 04 01:39:06 PM UTC 24 | Sep 04 01:39:08 PM UTC 24 | 78004001 ps | ||
| T861 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.1777777547 | Sep 04 01:39:06 PM UTC 24 | Sep 04 01:39:08 PM UTC 24 | 39772146 ps | ||
| T862 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.2931214554 | Sep 04 01:39:06 PM UTC 24 | Sep 04 01:39:08 PM UTC 24 | 53805157 ps | ||
| T863 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.1411142692 | Sep 04 01:39:06 PM UTC 24 | Sep 04 01:39:08 PM UTC 24 | 53596871 ps | ||
| T864 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.1102383964 | Sep 04 01:39:06 PM UTC 24 | Sep 04 01:39:08 PM UTC 24 | 14572776 ps | ||
| T865 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.2451185918 | Sep 04 01:39:06 PM UTC 24 | Sep 04 01:39:08 PM UTC 24 | 14203933 ps | ||
| T866 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.587266782 | Sep 04 01:39:06 PM UTC 24 | Sep 04 01:39:08 PM UTC 24 | 25540351 ps | ||
| T867 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.760745086 | Sep 04 01:39:08 PM UTC 24 | Sep 04 01:39:09 PM UTC 24 | 62014995 ps | ||
| T868 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.355029531 | Sep 04 01:39:08 PM UTC 24 | Sep 04 01:39:09 PM UTC 24 | 13803965 ps | ||
| T869 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.3376767494 | Sep 04 01:39:08 PM UTC 24 | Sep 04 01:39:10 PM UTC 24 | 28953844 ps | ||
| T870 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.3217309206 | Sep 04 01:39:08 PM UTC 24 | Sep 04 01:39:10 PM UTC 24 | 28122440 ps | ||
| T871 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.2543946216 | Sep 04 01:39:08 PM UTC 24 | Sep 04 01:39:10 PM UTC 24 | 18423525 ps | ||
| T872 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.1369493293 | Sep 04 01:39:08 PM UTC 24 | Sep 04 01:39:10 PM UTC 24 | 27082414 ps | ||
| T873 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.290307286 | Sep 04 01:39:08 PM UTC 24 | Sep 04 01:39:10 PM UTC 24 | 26790509 ps | ||
| T874 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.4210758214 | Sep 04 01:39:08 PM UTC 24 | Sep 04 01:39:10 PM UTC 24 | 70166545 ps | ||
| T875 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.923699863 | Sep 04 01:39:08 PM UTC 24 | Sep 04 01:39:10 PM UTC 24 | 51779969 ps | ||
| T876 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.814561933 | Sep 04 01:39:08 PM UTC 24 | Sep 04 01:39:10 PM UTC 24 | 17003667 ps | ||
| T877 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.3644766190 | Sep 04 01:39:08 PM UTC 24 | Sep 04 01:39:10 PM UTC 24 | 30091757 ps | ||
| T878 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.4013214798 | Sep 04 01:39:08 PM UTC 24 | Sep 04 01:39:10 PM UTC 24 | 13110233 ps | ||
| T879 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.646809468 | Sep 04 01:39:09 PM UTC 24 | Sep 04 01:39:11 PM UTC 24 | 54848935 ps | ||
| T880 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.2710668327 | Sep 04 01:39:09 PM UTC 24 | Sep 04 01:39:11 PM UTC 24 | 45180642 ps | ||
| T881 | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.928234454 | Sep 04 01:39:09 PM UTC 24 | Sep 04 01:39:12 PM UTC 24 | 85173816 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/0.kmac_app_with_partial_data.3045094097 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1886958424 ps |
| CPU time | 6.86 seconds |
| Started | Sep 04 12:42:01 PM UTC 24 |
| Finished | Sep 04 12:42:09 PM UTC 24 |
| Peak memory | 235436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045094097 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.3045094097 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/0.kmac_stress_all_with_rand_reset.3508103101 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1404295295 ps |
| CPU time | 40.04 seconds |
| Started | Sep 04 12:42:06 PM UTC 24 |
| Finished | Sep 04 12:42:47 PM UTC 24 |
| Peak memory | 251700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3508103101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all_ with_rand_reset.3508103101 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_ready_error.3823716179 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 1214827546 ps |
| CPU time | 7.44 seconds |
| Started | Sep 04 12:42:10 PM UTC 24 |
| Finished | Sep 04 12:42:19 PM UTC 24 |
| Peak memory | 230720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823716179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.3823716179 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/1.kmac_sec_cm.1456078843 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 21636757470 ps |
| CPU time | 65.53 seconds |
| Started | Sep 04 12:42:11 PM UTC 24 |
| Finished | Sep 04 12:43:19 PM UTC 24 |
| Peak memory | 281564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456078843 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.1456078843 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_intg_err.310678277 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 530966349 ps |
| CPU time | 5.31 seconds |
| Started | Sep 04 01:38:04 PM UTC 24 |
| Finished | Sep 04 01:38:10 PM UTC 24 |
| Peak memory | 229388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310678277 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.310678277 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/0.kmac_key_error.1331272845 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 6134091927 ps |
| CPU time | 5.62 seconds |
| Started | Sep 04 12:42:04 PM UTC 24 |
| Finished | Sep 04 12:42:10 PM UTC 24 |
| Peak memory | 230768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331272845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.1331272845 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.220970322 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 159634660 ps |
| CPU time | 3.94 seconds |
| Started | Sep 04 01:38:21 PM UTC 24 |
| Finished | Sep 04 01:38:26 PM UTC 24 |
| Peak memory | 229804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220970322 -asse rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors_with_csr_rw.2 20970322 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/1.kmac_lc_escalation.2400626914 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 203455571 ps |
| CPU time | 1.88 seconds |
| Started | Sep 04 12:42:10 PM UTC 24 |
| Finished | Sep 04 12:42:13 PM UTC 24 |
| Peak memory | 229680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400626914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.2400626914 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/1.kmac_error.2569871934 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 2569451970 ps |
| CPU time | 189.77 seconds |
| Started | Sep 04 12:42:09 PM UTC 24 |
| Finished | Sep 04 12:45:22 PM UTC 24 |
| Peak memory | 317216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569871934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.2569871934 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/15.kmac_lc_escalation.3921360685 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 461137834 ps |
| CPU time | 27.15 seconds |
| Started | Sep 04 12:55:09 PM UTC 24 |
| Finished | Sep 04 12:55:38 PM UTC 24 |
| Peak memory | 245492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921360685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.3921360685 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/15.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/16.kmac_lc_escalation.3275812849 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 47918463 ps |
| CPU time | 2.13 seconds |
| Started | Sep 04 12:55:56 PM UTC 24 |
| Finished | Sep 04 12:55:59 PM UTC 24 |
| Peak memory | 232364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275812849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.3275812849 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/16.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_intr_test.174506531 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 14644087 ps |
| CPU time | 1.13 seconds |
| Started | Sep 04 01:38:11 PM UTC 24 |
| Finished | Sep 04 01:38:13 PM UTC 24 |
| Peak memory | 218868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174506531 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.174506531 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/5.kmac_stress_all.2981818077 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 57873456217 ps |
| CPU time | 410.35 seconds |
| Started | Sep 04 12:47:00 PM UTC 24 |
| Finished | Sep 04 12:53:57 PM UTC 24 |
| Peak memory | 376968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981818077 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.2981818077 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/5.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_refresh.666512927 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 58519139756 ps |
| CPU time | 190.73 seconds |
| Started | Sep 04 12:42:45 PM UTC 24 |
| Finished | Sep 04 12:46:00 PM UTC 24 |
| Peak memory | 362292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666512927 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.666512927 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/9.kmac_stress_all_with_rand_reset.1117730338 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 5429171224 ps |
| CPU time | 317.56 seconds |
| Started | Sep 04 12:50:35 PM UTC 24 |
| Finished | Sep 04 12:55:57 PM UTC 24 |
| Peak memory | 311152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1117730338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all_ with_rand_reset.1117730338 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_512.3193254363 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1113284296 ps |
| CPU time | 13.61 seconds |
| Started | Sep 04 12:42:00 PM UTC 24 |
| Finished | Sep 04 12:42:17 PM UTC 24 |
| Peak memory | 228732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193254363 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.3193254363 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/13.kmac_lc_escalation.923166761 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 154464862 ps |
| CPU time | 1.95 seconds |
| Started | Sep 04 12:53:58 PM UTC 24 |
| Finished | Sep 04 12:54:01 PM UTC 24 |
| Peak memory | 234488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923166761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.923166761 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/13.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors.658659998 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 385350470 ps |
| CPU time | 1.89 seconds |
| Started | Sep 04 01:38:00 PM UTC 24 |
| Finished | Sep 04 01:38:03 PM UTC 24 |
| Peak memory | 229356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658659998 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors.658659998 +enable_masking =0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_256.3615880670 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 22501343146 ps |
| CPU time | 399.53 seconds |
| Started | Sep 04 12:42:00 PM UTC 24 |
| Finished | Sep 04 12:48:48 PM UTC 24 |
| Peak memory | 364188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615880670 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.3615880 670 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_partial_access.1557515605 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 45243274 ps |
| CPU time | 1.88 seconds |
| Started | Sep 04 01:38:08 PM UTC 24 |
| Finished | Sep 04 01:38:11 PM UTC 24 |
| Peak memory | 228872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557515605 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial_access.1557515605 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/31.kmac_lc_escalation.397286455 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 261391505 ps |
| CPU time | 2.13 seconds |
| Started | Sep 04 01:09:41 PM UTC 24 |
| Finished | Sep 04 01:09:44 PM UTC 24 |
| Peak memory | 230324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397286455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.397286455 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/31.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/37.kmac_lc_escalation.3032246148 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 101135967 ps |
| CPU time | 1.85 seconds |
| Started | Sep 04 01:16:23 PM UTC 24 |
| Finished | Sep 04 01:16:26 PM UTC 24 |
| Peak memory | 229680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032246148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.3032246148 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/37.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/40.kmac_lc_escalation.3151925025 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 63726255 ps |
| CPU time | 2.02 seconds |
| Started | Sep 04 01:19:31 PM UTC 24 |
| Finished | Sep 04 01:19:34 PM UTC 24 |
| Peak memory | 230576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151925025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.3151925025 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/40.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/12.kmac_error.439310490 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 3310956543 ps |
| CPU time | 240.45 seconds |
| Started | Sep 04 12:52:28 PM UTC 24 |
| Finished | Sep 04 12:56:33 PM UTC 24 |
| Peak memory | 344112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439310490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.439310490 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/12.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/0.kmac_alert_test.1794209694 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 15195878 ps |
| CPU time | 0.96 seconds |
| Started | Sep 04 12:42:06 PM UTC 24 |
| Finished | Sep 04 12:42:08 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794209694 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.1794209694 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.3449560065 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 219930911 ps |
| CPU time | 5.21 seconds |
| Started | Sep 04 01:38:58 PM UTC 24 |
| Finished | Sep 04 01:39:05 PM UTC 24 |
| Peak memory | 231248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449560065 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.3449560065 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/16.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_intr_test.1720357839 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 36716255 ps |
| CPU time | 1.14 seconds |
| Started | Sep 04 01:38:04 PM UTC 24 |
| Finished | Sep 04 01:38:06 PM UTC 24 |
| Peak memory | 219052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720357839 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.1720357839 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_ready_error.2586642808 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 13794606253 ps |
| CPU time | 41.58 seconds |
| Started | Sep 04 12:42:55 PM UTC 24 |
| Finished | Sep 04 12:43:38 PM UTC 24 |
| Peak memory | 230540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586642808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.2586642808 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_224.4115346447 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 5744639075 ps |
| CPU time | 51.08 seconds |
| Started | Sep 04 12:41:58 PM UTC 24 |
| Finished | Sep 04 12:42:54 PM UTC 24 |
| Peak memory | 260064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115346447 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.4115346447 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.2965704834 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 15086490 ps |
| CPU time | 1.06 seconds |
| Started | Sep 04 01:38:51 PM UTC 24 |
| Finished | Sep 04 01:38:53 PM UTC 24 |
| Peak memory | 219056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965704834 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.2965704834 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/12.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.1990190214 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 45046176 ps |
| CPU time | 2.32 seconds |
| Started | Sep 04 01:38:47 PM UTC 24 |
| Finished | Sep 04 01:38:50 PM UTC 24 |
| Peak memory | 236680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990190214 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors_with_csr_rw .1990190214 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/0.kmac_mubi.3675584399 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 4825070649 ps |
| CPU time | 250.14 seconds |
| Started | Sep 04 12:42:02 PM UTC 24 |
| Finished | Sep 04 12:46:17 PM UTC 24 |
| Peak memory | 331824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675584399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.3675584399 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.1345749420 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 223777634 ps |
| CPU time | 4.13 seconds |
| Started | Sep 04 01:38:48 PM UTC 24 |
| Finished | Sep 04 01:38:53 PM UTC 24 |
| Peak memory | 229460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345749420 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.1345749420 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/10.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/0.kmac_burst_write.3637463729 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 49521898110 ps |
| CPU time | 820.97 seconds |
| Started | Sep 04 12:41:58 PM UTC 24 |
| Finished | Sep 04 12:55:53 PM UTC 24 |
| Peak memory | 253808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637463729 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.3637463729 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/0.kmac_error.4213972651 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 12088844510 ps |
| CPU time | 281.08 seconds |
| Started | Sep 04 12:42:02 PM UTC 24 |
| Finished | Sep 04 12:46:48 PM UTC 24 |
| Peak memory | 474912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213972651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.4213972651 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_aliasing.59358580 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 1527086058 ps |
| CPU time | 13.65 seconds |
| Started | Sep 04 01:38:05 PM UTC 24 |
| Finished | Sep 04 01:38:20 PM UTC 24 |
| Peak memory | 219124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59358580 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.59358580 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.2723871159 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 1036858362 ps |
| CPU time | 16.95 seconds |
| Started | Sep 04 01:38:04 PM UTC 24 |
| Finished | Sep 04 01:38:22 PM UTC 24 |
| Peak memory | 219416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723871159 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.2723871159 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_hw_reset.1501980545 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 111881161 ps |
| CPU time | 1.13 seconds |
| Started | Sep 04 01:38:04 PM UTC 24 |
| Finished | Sep 04 01:38:06 PM UTC 24 |
| Peak memory | 219052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501980545 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1501980545 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.2881292992 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 111407518 ps |
| CPU time | 2.99 seconds |
| Started | Sep 04 01:38:06 PM UTC 24 |
| Finished | Sep 04 01:38:10 PM UTC 24 |
| Peak memory | 231508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2881292992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_ mem_rw_with_rand_reset.2881292992 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_rw.3374674570 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 53712596 ps |
| CPU time | 1.71 seconds |
| Started | Sep 04 01:38:04 PM UTC 24 |
| Finished | Sep 04 01:38:07 PM UTC 24 |
| Peak memory | 228932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374674570 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.3374674570 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_partial_access.924284785 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 63356622 ps |
| CPU time | 1.56 seconds |
| Started | Sep 04 01:38:02 PM UTC 24 |
| Finished | Sep 04 01:38:04 PM UTC 24 |
| Peak memory | 228868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924284785 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial_access.924284785 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_walk.259881365 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 13598170 ps |
| CPU time | 0.93 seconds |
| Started | Sep 04 01:38:02 PM UTC 24 |
| Finished | Sep 04 01:38:03 PM UTC 24 |
| Peak memory | 218992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259881365 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.259881365 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_same_csr_outstanding.1243294718 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 164144046 ps |
| CPU time | 3.39 seconds |
| Started | Sep 04 01:38:05 PM UTC 24 |
| Finished | Sep 04 01:38:10 PM UTC 24 |
| Peak memory | 229420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243294718 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_outstanding.1243294718 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.63904586 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 244131626 ps |
| CPU time | 2.72 seconds |
| Started | Sep 04 01:38:01 PM UTC 24 |
| Finished | Sep 04 01:38:05 PM UTC 24 |
| Peak memory | 230056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63904586 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors_with_csr_rw.63 904586 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_errors.4011773203 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 197492013 ps |
| CPU time | 3.22 seconds |
| Started | Sep 04 01:38:04 PM UTC 24 |
| Finished | Sep 04 01:38:08 PM UTC 24 |
| Peak memory | 229620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011773203 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.4011773203 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_aliasing.253878860 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 519676769 ps |
| CPU time | 11.08 seconds |
| Started | Sep 04 01:38:12 PM UTC 24 |
| Finished | Sep 04 01:38:24 PM UTC 24 |
| Peak memory | 219152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253878860 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.253878860 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.3023251985 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 551900669 ps |
| CPU time | 16.78 seconds |
| Started | Sep 04 01:38:12 PM UTC 24 |
| Finished | Sep 04 01:38:30 PM UTC 24 |
| Peak memory | 219352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023251985 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.3023251985 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_hw_reset.207074276 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 84742240 ps |
| CPU time | 1.73 seconds |
| Started | Sep 04 01:38:11 PM UTC 24 |
| Finished | Sep 04 01:38:13 PM UTC 24 |
| Peak memory | 228932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207074276 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.207074276 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.4254522807 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 154996519 ps |
| CPU time | 3.66 seconds |
| Started | Sep 04 01:38:13 PM UTC 24 |
| Finished | Sep 04 01:38:18 PM UTC 24 |
| Peak memory | 236540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4254522807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_ mem_rw_with_rand_reset.4254522807 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_rw.2622858713 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 38067541 ps |
| CPU time | 1.68 seconds |
| Started | Sep 04 01:38:12 PM UTC 24 |
| Finished | Sep 04 01:38:14 PM UTC 24 |
| Peak memory | 218956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622858713 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.2622858713 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_walk.2269290139 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 15865071 ps |
| CPU time | 1.1 seconds |
| Started | Sep 04 01:38:07 PM UTC 24 |
| Finished | Sep 04 01:38:10 PM UTC 24 |
| Peak memory | 218992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269290139 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.2269290139 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_same_csr_outstanding.3519776267 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 130064345 ps |
| CPU time | 2.36 seconds |
| Started | Sep 04 01:38:12 PM UTC 24 |
| Finished | Sep 04 01:38:15 PM UTC 24 |
| Peak memory | 229396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519776267 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_outstanding.3519776267 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors.1233742900 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 64360133 ps |
| CPU time | 1.59 seconds |
| Started | Sep 04 01:38:07 PM UTC 24 |
| Finished | Sep 04 01:38:10 PM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233742900 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors.1233742900 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.2078553943 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 117394156 ps |
| CPU time | 4.05 seconds |
| Started | Sep 04 01:38:07 PM UTC 24 |
| Finished | Sep 04 01:38:12 PM UTC 24 |
| Peak memory | 229548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078553943 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors_with_csr_rw. 2078553943 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_errors.2743898151 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 119475366 ps |
| CPU time | 4.24 seconds |
| Started | Sep 04 01:38:09 PM UTC 24 |
| Finished | Sep 04 01:38:15 PM UTC 24 |
| Peak memory | 229576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743898151 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.2743898151 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_intg_err.85634551 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 120488402 ps |
| CPU time | 4.3 seconds |
| Started | Sep 04 01:38:11 PM UTC 24 |
| Finished | Sep 04 01:38:16 PM UTC 24 |
| Peak memory | 229496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85634551 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.85634551 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.3576757815 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 33847365 ps |
| CPU time | 2.4 seconds |
| Started | Sep 04 01:38:48 PM UTC 24 |
| Finished | Sep 04 01:38:52 PM UTC 24 |
| Peak memory | 229716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3576757815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr _mem_rw_with_rand_reset.3576757815 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/10.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.713966278 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 34007889 ps |
| CPU time | 1.46 seconds |
| Started | Sep 04 01:38:48 PM UTC 24 |
| Finished | Sep 04 01:38:50 PM UTC 24 |
| Peak memory | 228928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713966278 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.713966278 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/10.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.2798695057 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 30734462 ps |
| CPU time | 1.14 seconds |
| Started | Sep 04 01:38:48 PM UTC 24 |
| Finished | Sep 04 01:38:50 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798695057 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.2798695057 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/10.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1452170880 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 139821164 ps |
| CPU time | 2.27 seconds |
| Started | Sep 04 01:38:48 PM UTC 24 |
| Finished | Sep 04 01:38:51 PM UTC 24 |
| Peak memory | 229364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452170880 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr_outstanding.1452170880 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/10.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.311318604 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 48235145 ps |
| CPU time | 1.66 seconds |
| Started | Sep 04 01:38:45 PM UTC 24 |
| Finished | Sep 04 01:38:48 PM UTC 24 |
| Peak memory | 228744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311318604 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors.311318604 +enable_maskin g=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.3504053350 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 86345228 ps |
| CPU time | 2.55 seconds |
| Started | Sep 04 01:38:47 PM UTC 24 |
| Finished | Sep 04 01:38:50 PM UTC 24 |
| Peak memory | 229520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504053350 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.3504053350 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/10.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.239153814 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 37919519 ps |
| CPU time | 1.7 seconds |
| Started | Sep 04 01:38:51 PM UTC 24 |
| Finished | Sep 04 01:38:54 PM UTC 24 |
| Peak memory | 228936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=239153814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_ mem_rw_with_rand_reset.239153814 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/11.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.357251263 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 65074054 ps |
| CPU time | 1.19 seconds |
| Started | Sep 04 01:38:50 PM UTC 24 |
| Finished | Sep 04 01:38:52 PM UTC 24 |
| Peak memory | 218992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357251263 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.357251263 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/11.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.675586383 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 12987067 ps |
| CPU time | 1.21 seconds |
| Started | Sep 04 01:38:50 PM UTC 24 |
| Finished | Sep 04 01:38:52 PM UTC 24 |
| Peak memory | 218936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675586383 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.675586383 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/11.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1880085892 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 445939141 ps |
| CPU time | 2.52 seconds |
| Started | Sep 04 01:38:50 PM UTC 24 |
| Finished | Sep 04 01:38:53 PM UTC 24 |
| Peak memory | 229388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880085892 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr_outstanding.1880085892 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/11.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.1591518688 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 27541242 ps |
| CPU time | 1.56 seconds |
| Started | Sep 04 01:38:48 PM UTC 24 |
| Finished | Sep 04 01:38:51 PM UTC 24 |
| Peak memory | 228808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591518688 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors.1591518688 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/11.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.2391221477 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 103865131 ps |
| CPU time | 2.72 seconds |
| Started | Sep 04 01:38:48 PM UTC 24 |
| Finished | Sep 04 01:38:52 PM UTC 24 |
| Peak memory | 229604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391221477 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors_with_csr_rw .2391221477 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.1887917820 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 90518995 ps |
| CPU time | 2.91 seconds |
| Started | Sep 04 01:38:49 PM UTC 24 |
| Finished | Sep 04 01:38:53 PM UTC 24 |
| Peak memory | 229712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887917820 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.1887917820 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/11.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.3443479685 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 126953352 ps |
| CPU time | 3.07 seconds |
| Started | Sep 04 01:38:49 PM UTC 24 |
| Finished | Sep 04 01:38:54 PM UTC 24 |
| Peak memory | 229608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443479685 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.3443479685 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/11.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2396721368 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 145829086 ps |
| CPU time | 1.59 seconds |
| Started | Sep 04 01:38:52 PM UTC 24 |
| Finished | Sep 04 01:38:55 PM UTC 24 |
| Peak memory | 228876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2396721368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr _mem_rw_with_rand_reset.2396721368 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/12.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.1397592109 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 42837275 ps |
| CPU time | 1.34 seconds |
| Started | Sep 04 01:38:52 PM UTC 24 |
| Finished | Sep 04 01:38:55 PM UTC 24 |
| Peak memory | 218992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397592109 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.1397592109 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/12.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.2883179456 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 27008882 ps |
| CPU time | 1.88 seconds |
| Started | Sep 04 01:38:52 PM UTC 24 |
| Finished | Sep 04 01:38:55 PM UTC 24 |
| Peak memory | 228932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883179456 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr_outstanding.2883179456 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/12.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.4167925186 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 58502296 ps |
| CPU time | 1.61 seconds |
| Started | Sep 04 01:38:51 PM UTC 24 |
| Finished | Sep 04 01:38:54 PM UTC 24 |
| Peak memory | 228808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167925186 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors.4167925186 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/12.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.1104121099 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 108358509 ps |
| CPU time | 2.23 seconds |
| Started | Sep 04 01:38:51 PM UTC 24 |
| Finished | Sep 04 01:38:54 PM UTC 24 |
| Peak memory | 229808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104121099 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors_with_csr_rw .1104121099 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.163841257 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 117204397 ps |
| CPU time | 2.45 seconds |
| Started | Sep 04 01:38:51 PM UTC 24 |
| Finished | Sep 04 01:38:55 PM UTC 24 |
| Peak memory | 229560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163841257 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.163841257 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/12.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.1541679066 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 575757872 ps |
| CPU time | 3.86 seconds |
| Started | Sep 04 01:38:51 PM UTC 24 |
| Finished | Sep 04 01:38:56 PM UTC 24 |
| Peak memory | 231612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541679066 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.1541679066 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/12.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3484367891 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 37157401 ps |
| CPU time | 1.8 seconds |
| Started | Sep 04 01:38:54 PM UTC 24 |
| Finished | Sep 04 01:38:57 PM UTC 24 |
| Peak memory | 228876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3484367891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr _mem_rw_with_rand_reset.3484367891 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/13.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.3046759687 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 42226868 ps |
| CPU time | 1.1 seconds |
| Started | Sep 04 01:38:54 PM UTC 24 |
| Finished | Sep 04 01:38:56 PM UTC 24 |
| Peak memory | 218940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046759687 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.3046759687 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/13.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.1752792737 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 49005711 ps |
| CPU time | 1.13 seconds |
| Started | Sep 04 01:38:53 PM UTC 24 |
| Finished | Sep 04 01:38:55 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752792737 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.1752792737 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/13.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.1550351945 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 85535668 ps |
| CPU time | 2.07 seconds |
| Started | Sep 04 01:38:54 PM UTC 24 |
| Finished | Sep 04 01:38:57 PM UTC 24 |
| Peak memory | 229448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550351945 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr_outstanding.1550351945 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/13.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.2947214352 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 106377919 ps |
| CPU time | 1.21 seconds |
| Started | Sep 04 01:38:52 PM UTC 24 |
| Finished | Sep 04 01:38:55 PM UTC 24 |
| Peak memory | 228740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947214352 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors.2947214352 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/13.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.4097331536 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 57105882 ps |
| CPU time | 1.8 seconds |
| Started | Sep 04 01:38:52 PM UTC 24 |
| Finished | Sep 04 01:38:55 PM UTC 24 |
| Peak memory | 218652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097331536 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors_with_csr_rw .4097331536 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.4086734855 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 98627898 ps |
| CPU time | 2.98 seconds |
| Started | Sep 04 01:38:52 PM UTC 24 |
| Finished | Sep 04 01:38:56 PM UTC 24 |
| Peak memory | 229648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086734855 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.4086734855 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/13.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.2533774224 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 116545070 ps |
| CPU time | 3.01 seconds |
| Started | Sep 04 01:38:53 PM UTC 24 |
| Finished | Sep 04 01:38:57 PM UTC 24 |
| Peak memory | 229588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533774224 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.2533774224 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/13.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.2097421718 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 82470807 ps |
| CPU time | 2.53 seconds |
| Started | Sep 04 01:38:55 PM UTC 24 |
| Finished | Sep 04 01:38:59 PM UTC 24 |
| Peak memory | 231508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2097421718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr _mem_rw_with_rand_reset.2097421718 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/14.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.1120509534 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 29764658 ps |
| CPU time | 1.26 seconds |
| Started | Sep 04 01:38:55 PM UTC 24 |
| Finished | Sep 04 01:38:58 PM UTC 24 |
| Peak memory | 218956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120509534 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.1120509534 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/14.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.1888380210 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 39480069 ps |
| CPU time | 1.21 seconds |
| Started | Sep 04 01:38:55 PM UTC 24 |
| Finished | Sep 04 01:38:57 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888380210 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.1888380210 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/14.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.3837403769 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 44436113 ps |
| CPU time | 2 seconds |
| Started | Sep 04 01:38:55 PM UTC 24 |
| Finished | Sep 04 01:38:58 PM UTC 24 |
| Peak memory | 228932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837403769 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr_outstanding.3837403769 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/14.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.4255085305 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 45587260 ps |
| CPU time | 1.18 seconds |
| Started | Sep 04 01:38:54 PM UTC 24 |
| Finished | Sep 04 01:38:56 PM UTC 24 |
| Peak memory | 218628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255085305 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors.4255085305 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/14.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.1710967383 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 109372837 ps |
| CPU time | 3.18 seconds |
| Started | Sep 04 01:38:55 PM UTC 24 |
| Finished | Sep 04 01:38:59 PM UTC 24 |
| Peak memory | 229864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710967383 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors_with_csr_rw .1710967383 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/14.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.1331735001 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 75150554 ps |
| CPU time | 2.41 seconds |
| Started | Sep 04 01:38:55 PM UTC 24 |
| Finished | Sep 04 01:38:58 PM UTC 24 |
| Peak memory | 229520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331735001 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.1331735001 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/14.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.3037584378 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 223122397 ps |
| CPU time | 3.3 seconds |
| Started | Sep 04 01:38:55 PM UTC 24 |
| Finished | Sep 04 01:38:59 PM UTC 24 |
| Peak memory | 231636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037584378 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.3037584378 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/14.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1183061658 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 82681419 ps |
| CPU time | 2.61 seconds |
| Started | Sep 04 01:38:57 PM UTC 24 |
| Finished | Sep 04 01:39:00 PM UTC 24 |
| Peak memory | 236540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1183061658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr _mem_rw_with_rand_reset.1183061658 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/15.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.3014196415 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 110174457 ps |
| CPU time | 1.48 seconds |
| Started | Sep 04 01:38:57 PM UTC 24 |
| Finished | Sep 04 01:38:59 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014196415 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.3014196415 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/15.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.4049158171 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 30636465 ps |
| CPU time | 1.22 seconds |
| Started | Sep 04 01:38:57 PM UTC 24 |
| Finished | Sep 04 01:38:59 PM UTC 24 |
| Peak memory | 219056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049158171 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.4049158171 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/15.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2038964520 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 27111481 ps |
| CPU time | 1.76 seconds |
| Started | Sep 04 01:38:57 PM UTC 24 |
| Finished | Sep 04 01:39:00 PM UTC 24 |
| Peak memory | 228972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038964520 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr_outstanding.2038964520 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/15.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2891336374 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 102375310 ps |
| CPU time | 1.15 seconds |
| Started | Sep 04 01:38:55 PM UTC 24 |
| Finished | Sep 04 01:38:57 PM UTC 24 |
| Peak memory | 228736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891336374 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors.2891336374 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/15.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.4255138803 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 429894916 ps |
| CPU time | 3.02 seconds |
| Started | Sep 04 01:38:55 PM UTC 24 |
| Finished | Sep 04 01:38:59 PM UTC 24 |
| Peak memory | 229808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255138803 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors_with_csr_rw .4255138803 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.2680122067 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 75507700 ps |
| CPU time | 1.87 seconds |
| Started | Sep 04 01:38:57 PM UTC 24 |
| Finished | Sep 04 01:39:00 PM UTC 24 |
| Peak memory | 228936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680122067 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.2680122067 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/15.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.4092469619 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 161371043 ps |
| CPU time | 3.09 seconds |
| Started | Sep 04 01:38:57 PM UTC 24 |
| Finished | Sep 04 01:39:01 PM UTC 24 |
| Peak memory | 229504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092469619 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.4092469619 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/15.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2546322368 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 189022670 ps |
| CPU time | 1.9 seconds |
| Started | Sep 04 01:38:59 PM UTC 24 |
| Finished | Sep 04 01:39:01 PM UTC 24 |
| Peak memory | 228876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2546322368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr _mem_rw_with_rand_reset.2546322368 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/16.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.2101497874 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 51234778 ps |
| CPU time | 1.19 seconds |
| Started | Sep 04 01:38:58 PM UTC 24 |
| Finished | Sep 04 01:39:01 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101497874 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.2101497874 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/16.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.4141090564 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 32956986 ps |
| CPU time | 1.08 seconds |
| Started | Sep 04 01:38:58 PM UTC 24 |
| Finished | Sep 04 01:39:00 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141090564 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.4141090564 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/16.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.929009040 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 43705845 ps |
| CPU time | 1.55 seconds |
| Started | Sep 04 01:38:59 PM UTC 24 |
| Finished | Sep 04 01:39:01 PM UTC 24 |
| Peak memory | 228928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929009040 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr_outstanding.929009040 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/16.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.3128410971 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 50725715 ps |
| CPU time | 1.54 seconds |
| Started | Sep 04 01:38:57 PM UTC 24 |
| Finished | Sep 04 01:38:59 PM UTC 24 |
| Peak memory | 228676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128410971 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors.3128410971 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/16.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2354574217 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 177428573 ps |
| CPU time | 3.15 seconds |
| Started | Sep 04 01:38:58 PM UTC 24 |
| Finished | Sep 04 01:39:02 PM UTC 24 |
| Peak memory | 229808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354574217 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors_with_csr_rw .2354574217 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.2772066248 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 156869879 ps |
| CPU time | 2.54 seconds |
| Started | Sep 04 01:38:58 PM UTC 24 |
| Finished | Sep 04 01:39:02 PM UTC 24 |
| Peak memory | 229812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772066248 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.2772066248 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/16.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.2292032888 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 22919138 ps |
| CPU time | 1.6 seconds |
| Started | Sep 04 01:39:00 PM UTC 24 |
| Finished | Sep 04 01:39:03 PM UTC 24 |
| Peak memory | 228876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2292032888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr _mem_rw_with_rand_reset.2292032888 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/17.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.1644395365 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 28137217 ps |
| CPU time | 1.18 seconds |
| Started | Sep 04 01:39:00 PM UTC 24 |
| Finished | Sep 04 01:39:02 PM UTC 24 |
| Peak memory | 218900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644395365 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.1644395365 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/17.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.2340448905 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 12627932 ps |
| CPU time | 0.88 seconds |
| Started | Sep 04 01:39:00 PM UTC 24 |
| Finished | Sep 04 01:39:02 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340448905 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.2340448905 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/17.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2367665182 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 43901003 ps |
| CPU time | 1.99 seconds |
| Started | Sep 04 01:39:00 PM UTC 24 |
| Finished | Sep 04 01:39:03 PM UTC 24 |
| Peak memory | 228928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367665182 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr_outstanding.2367665182 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/17.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.412865272 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 27237762 ps |
| CPU time | 1.16 seconds |
| Started | Sep 04 01:38:59 PM UTC 24 |
| Finished | Sep 04 01:39:01 PM UTC 24 |
| Peak memory | 218628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412865272 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors.412865272 +enable_maskin g=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/17.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.3310952585 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 96403718 ps |
| CPU time | 2.61 seconds |
| Started | Sep 04 01:39:00 PM UTC 24 |
| Finished | Sep 04 01:39:03 PM UTC 24 |
| Peak memory | 229808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310952585 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors_with_csr_rw .3310952585 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.3123681493 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 156912257 ps |
| CPU time | 3.79 seconds |
| Started | Sep 04 01:39:00 PM UTC 24 |
| Finished | Sep 04 01:39:05 PM UTC 24 |
| Peak memory | 229708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123681493 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.3123681493 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/17.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.2518219587 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 237623077 ps |
| CPU time | 4.68 seconds |
| Started | Sep 04 01:39:00 PM UTC 24 |
| Finished | Sep 04 01:39:06 PM UTC 24 |
| Peak memory | 229400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518219587 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.2518219587 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/17.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.667883282 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 132459977 ps |
| CPU time | 2.49 seconds |
| Started | Sep 04 01:39:02 PM UTC 24 |
| Finished | Sep 04 01:39:05 PM UTC 24 |
| Peak memory | 231500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=667883282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_ mem_rw_with_rand_reset.667883282 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/18.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.2003096893 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 61109220 ps |
| CPU time | 1.27 seconds |
| Started | Sep 04 01:39:01 PM UTC 24 |
| Finished | Sep 04 01:39:04 PM UTC 24 |
| Peak memory | 218940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003096893 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.2003096893 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/18.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.3261739696 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 11006332 ps |
| CPU time | 1.08 seconds |
| Started | Sep 04 01:39:01 PM UTC 24 |
| Finished | Sep 04 01:39:04 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261739696 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.3261739696 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/18.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.3574306306 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 27801260 ps |
| CPU time | 1.75 seconds |
| Started | Sep 04 01:39:01 PM UTC 24 |
| Finished | Sep 04 01:39:04 PM UTC 24 |
| Peak memory | 228928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574306306 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr_outstanding.3574306306 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/18.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.289013567 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 85450886 ps |
| CPU time | 1.47 seconds |
| Started | Sep 04 01:39:00 PM UTC 24 |
| Finished | Sep 04 01:39:03 PM UTC 24 |
| Peak memory | 228744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289013567 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors.289013567 +enable_maskin g=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/18.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.1568605733 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 41014741 ps |
| CPU time | 1.7 seconds |
| Started | Sep 04 01:39:01 PM UTC 24 |
| Finished | Sep 04 01:39:04 PM UTC 24 |
| Peak memory | 228804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568605733 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors_with_csr_rw .1568605733 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.1947666563 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 40406281 ps |
| CPU time | 2.64 seconds |
| Started | Sep 04 01:39:01 PM UTC 24 |
| Finished | Sep 04 01:39:05 PM UTC 24 |
| Peak memory | 229648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947666563 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.1947666563 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/18.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.3871056473 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 147353119 ps |
| CPU time | 4.29 seconds |
| Started | Sep 04 01:39:01 PM UTC 24 |
| Finished | Sep 04 01:39:07 PM UTC 24 |
| Peak memory | 219220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871056473 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.3871056473 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/18.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.909584411 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 185682043 ps |
| CPU time | 2.39 seconds |
| Started | Sep 04 01:39:04 PM UTC 24 |
| Finished | Sep 04 01:39:08 PM UTC 24 |
| Peak memory | 231368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=909584411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_ mem_rw_with_rand_reset.909584411 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/19.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.1334148854 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 34124926 ps |
| CPU time | 1.11 seconds |
| Started | Sep 04 01:39:03 PM UTC 24 |
| Finished | Sep 04 01:39:05 PM UTC 24 |
| Peak memory | 218984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334148854 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.1334148854 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/19.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.1431203304 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 18392532 ps |
| CPU time | 1.18 seconds |
| Started | Sep 04 01:39:03 PM UTC 24 |
| Finished | Sep 04 01:39:05 PM UTC 24 |
| Peak memory | 219056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431203304 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.1431203304 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/19.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1394980890 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 40050453 ps |
| CPU time | 1.7 seconds |
| Started | Sep 04 01:39:03 PM UTC 24 |
| Finished | Sep 04 01:39:06 PM UTC 24 |
| Peak memory | 228932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394980890 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr_outstanding.1394980890 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/19.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.100450225 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 145109500 ps |
| CPU time | 1.6 seconds |
| Started | Sep 04 01:39:02 PM UTC 24 |
| Finished | Sep 04 01:39:04 PM UTC 24 |
| Peak memory | 228828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100450225 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors.100450225 +enable_maskin g=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/19.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.554112043 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 449119488 ps |
| CPU time | 3.05 seconds |
| Started | Sep 04 01:39:03 PM UTC 24 |
| Finished | Sep 04 01:39:07 PM UTC 24 |
| Peak memory | 229864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554112043 -asse rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors_with_csr_rw. 554112043 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.3511557163 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 21581294 ps |
| CPU time | 1.92 seconds |
| Started | Sep 04 01:39:03 PM UTC 24 |
| Finished | Sep 04 01:39:06 PM UTC 24 |
| Peak memory | 228972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511557163 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.3511557163 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/19.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.204953096 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 102386084 ps |
| CPU time | 2.5 seconds |
| Started | Sep 04 01:39:03 PM UTC 24 |
| Finished | Sep 04 01:39:06 PM UTC 24 |
| Peak memory | 229520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204953096 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.204953096 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/19.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.1861364821 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1266019304 ps |
| CPU time | 6.11 seconds |
| Started | Sep 04 01:38:19 PM UTC 24 |
| Finished | Sep 04 01:38:26 PM UTC 24 |
| Peak memory | 219272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861364821 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.1861364821 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.1153760794 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 3726466090 ps |
| CPU time | 21.48 seconds |
| Started | Sep 04 01:38:19 PM UTC 24 |
| Finished | Sep 04 01:38:41 PM UTC 24 |
| Peak memory | 219064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153760794 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.1153760794 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_hw_reset.2298092065 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 25940248 ps |
| CPU time | 1.42 seconds |
| Started | Sep 04 01:38:19 PM UTC 24 |
| Finished | Sep 04 01:38:21 PM UTC 24 |
| Peak memory | 218992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298092065 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.2298092065 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.596605200 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 142453103 ps |
| CPU time | 3.71 seconds |
| Started | Sep 04 01:38:19 PM UTC 24 |
| Finished | Sep 04 01:38:24 PM UTC 24 |
| Peak memory | 231580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=596605200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_m em_rw_with_rand_reset.596605200 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_rw.4024820093 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 112364316 ps |
| CPU time | 1.45 seconds |
| Started | Sep 04 01:38:19 PM UTC 24 |
| Finished | Sep 04 01:38:21 PM UTC 24 |
| Peak memory | 218660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024820093 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.4024820093 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_intr_test.633373621 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 31817969 ps |
| CPU time | 0.86 seconds |
| Started | Sep 04 01:38:17 PM UTC 24 |
| Finished | Sep 04 01:38:18 PM UTC 24 |
| Peak memory | 219060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633373621 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.633373621 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_partial_access.3410007096 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 18766877 ps |
| CPU time | 1.66 seconds |
| Started | Sep 04 01:38:15 PM UTC 24 |
| Finished | Sep 04 01:38:18 PM UTC 24 |
| Peak memory | 228872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410007096 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial_access.3410007096 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_walk.3805814279 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 17552681 ps |
| CPU time | 1.11 seconds |
| Started | Sep 04 01:38:15 PM UTC 24 |
| Finished | Sep 04 01:38:17 PM UTC 24 |
| Peak memory | 219052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805814279 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.3805814279 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_same_csr_outstanding.1958246004 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 144125902 ps |
| CPU time | 2.97 seconds |
| Started | Sep 04 01:38:19 PM UTC 24 |
| Finished | Sep 04 01:38:23 PM UTC 24 |
| Peak memory | 229448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958246004 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_outstanding.1958246004 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors.1743631477 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 40164525 ps |
| CPU time | 1.72 seconds |
| Started | Sep 04 01:38:13 PM UTC 24 |
| Finished | Sep 04 01:38:16 PM UTC 24 |
| Peak memory | 228668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743631477 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors.1743631477 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.667550468 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 167766055 ps |
| CPU time | 2.43 seconds |
| Started | Sep 04 01:38:14 PM UTC 24 |
| Finished | Sep 04 01:38:18 PM UTC 24 |
| Peak memory | 229864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667550468 -asse rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors_with_csr_rw.6 67550468 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_errors.3773388914 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 89859131 ps |
| CPU time | 2.54 seconds |
| Started | Sep 04 01:38:16 PM UTC 24 |
| Finished | Sep 04 01:38:20 PM UTC 24 |
| Peak memory | 229516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773388914 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.3773388914 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_intg_err.148029926 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 300377780 ps |
| CPU time | 4.65 seconds |
| Started | Sep 04 01:38:16 PM UTC 24 |
| Finished | Sep 04 01:38:22 PM UTC 24 |
| Peak memory | 219340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148029926 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.148029926 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.1313392922 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 29285201 ps |
| CPU time | 1.02 seconds |
| Started | Sep 04 01:39:04 PM UTC 24 |
| Finished | Sep 04 01:39:06 PM UTC 24 |
| Peak memory | 218992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313392922 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.1313392922 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/20.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.273784012 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 20809654 ps |
| CPU time | 0.9 seconds |
| Started | Sep 04 01:39:04 PM UTC 24 |
| Finished | Sep 04 01:39:06 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273784012 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.273784012 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/21.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.2934778099 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 12806208 ps |
| CPU time | 0.84 seconds |
| Started | Sep 04 01:39:04 PM UTC 24 |
| Finished | Sep 04 01:39:06 PM UTC 24 |
| Peak memory | 218932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934778099 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.2934778099 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/22.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.4001328701 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 37660771 ps |
| CPU time | 1.17 seconds |
| Started | Sep 04 01:39:04 PM UTC 24 |
| Finished | Sep 04 01:39:07 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001328701 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.4001328701 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/23.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.3745479521 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 27850788 ps |
| CPU time | 0.85 seconds |
| Started | Sep 04 01:39:05 PM UTC 24 |
| Finished | Sep 04 01:39:06 PM UTC 24 |
| Peak memory | 218936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745479521 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.3745479521 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/24.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.790152731 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 36212488 ps |
| CPU time | 1.03 seconds |
| Started | Sep 04 01:39:05 PM UTC 24 |
| Finished | Sep 04 01:39:07 PM UTC 24 |
| Peak memory | 218852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790152731 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.790152731 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/25.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.2188607742 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 46588361 ps |
| CPU time | 0.98 seconds |
| Started | Sep 04 01:39:06 PM UTC 24 |
| Finished | Sep 04 01:39:08 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188607742 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.2188607742 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/26.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.3784322926 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 22324032 ps |
| CPU time | 0.91 seconds |
| Started | Sep 04 01:39:06 PM UTC 24 |
| Finished | Sep 04 01:39:08 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784322926 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.3784322926 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/27.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.1102383964 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 14572776 ps |
| CPU time | 1.22 seconds |
| Started | Sep 04 01:39:06 PM UTC 24 |
| Finished | Sep 04 01:39:08 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102383964 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.1102383964 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/28.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.1411142692 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 53596871 ps |
| CPU time | 1.17 seconds |
| Started | Sep 04 01:39:06 PM UTC 24 |
| Finished | Sep 04 01:39:08 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411142692 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.1411142692 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/29.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.1210111685 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 516237659 ps |
| CPU time | 10.7 seconds |
| Started | Sep 04 01:38:25 PM UTC 24 |
| Finished | Sep 04 01:38:37 PM UTC 24 |
| Peak memory | 219144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210111685 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.1210111685 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.3904378893 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 2525769454 ps |
| CPU time | 13.78 seconds |
| Started | Sep 04 01:38:25 PM UTC 24 |
| Finished | Sep 04 01:38:40 PM UTC 24 |
| Peak memory | 219208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904378893 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.3904378893 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_hw_reset.2985417822 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 32786089 ps |
| CPU time | 1.48 seconds |
| Started | Sep 04 01:38:24 PM UTC 24 |
| Finished | Sep 04 01:38:26 PM UTC 24 |
| Peak memory | 218952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985417822 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.2985417822 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.1256258243 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 599903422 ps |
| CPU time | 3.34 seconds |
| Started | Sep 04 01:38:26 PM UTC 24 |
| Finished | Sep 04 01:38:30 PM UTC 24 |
| Peak memory | 231508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1256258243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_ mem_rw_with_rand_reset.1256258243 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_rw.4261798296 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 15523611 ps |
| CPU time | 1.38 seconds |
| Started | Sep 04 01:38:24 PM UTC 24 |
| Finished | Sep 04 01:38:26 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261798296 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.4261798296 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_intr_test.667856806 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 35886723 ps |
| CPU time | 0.94 seconds |
| Started | Sep 04 01:38:23 PM UTC 24 |
| Finished | Sep 04 01:38:25 PM UTC 24 |
| Peak memory | 219000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667856806 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.667856806 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_partial_access.3677895775 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 159072725 ps |
| CPU time | 2.18 seconds |
| Started | Sep 04 01:38:22 PM UTC 24 |
| Finished | Sep 04 01:38:25 PM UTC 24 |
| Peak memory | 229368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677895775 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial_access.3677895775 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_walk.988678071 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 22933496 ps |
| CPU time | 1.19 seconds |
| Started | Sep 04 01:38:21 PM UTC 24 |
| Finished | Sep 04 01:38:23 PM UTC 24 |
| Peak memory | 219052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988678071 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.988678071 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_same_csr_outstanding.3532029234 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 249276701 ps |
| CPU time | 2.01 seconds |
| Started | Sep 04 01:38:25 PM UTC 24 |
| Finished | Sep 04 01:38:28 PM UTC 24 |
| Peak memory | 229524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532029234 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_outstanding.3532029234 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors.101206892 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 69561112 ps |
| CPU time | 1.51 seconds |
| Started | Sep 04 01:38:20 PM UTC 24 |
| Finished | Sep 04 01:38:23 PM UTC 24 |
| Peak memory | 228744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101206892 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors.101206892 +enable_masking =0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_errors.1555741236 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 332569982 ps |
| CPU time | 5.55 seconds |
| Started | Sep 04 01:38:22 PM UTC 24 |
| Finished | Sep 04 01:38:29 PM UTC 24 |
| Peak memory | 233740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555741236 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.1555741236 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_intg_err.951498321 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 57453045 ps |
| CPU time | 3.53 seconds |
| Started | Sep 04 01:38:23 PM UTC 24 |
| Finished | Sep 04 01:38:28 PM UTC 24 |
| Peak memory | 229576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951498321 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.951498321 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.587266782 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 25540351 ps |
| CPU time | 1.11 seconds |
| Started | Sep 04 01:39:06 PM UTC 24 |
| Finished | Sep 04 01:39:08 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587266782 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.587266782 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/30.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.1777777547 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 39772146 ps |
| CPU time | 1.05 seconds |
| Started | Sep 04 01:39:06 PM UTC 24 |
| Finished | Sep 04 01:39:08 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777777547 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.1777777547 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/31.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.2931214554 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 53805157 ps |
| CPU time | 0.98 seconds |
| Started | Sep 04 01:39:06 PM UTC 24 |
| Finished | Sep 04 01:39:08 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931214554 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.2931214554 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/32.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.371249766 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 78004001 ps |
| CPU time | 0.89 seconds |
| Started | Sep 04 01:39:06 PM UTC 24 |
| Finished | Sep 04 01:39:08 PM UTC 24 |
| Peak memory | 218936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371249766 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.371249766 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/33.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.2451185918 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 14203933 ps |
| CPU time | 0.87 seconds |
| Started | Sep 04 01:39:06 PM UTC 24 |
| Finished | Sep 04 01:39:08 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451185918 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.2451185918 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/34.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.3376767494 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 28953844 ps |
| CPU time | 0.95 seconds |
| Started | Sep 04 01:39:08 PM UTC 24 |
| Finished | Sep 04 01:39:10 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376767494 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.3376767494 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/35.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.355029531 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 13803965 ps |
| CPU time | 0.81 seconds |
| Started | Sep 04 01:39:08 PM UTC 24 |
| Finished | Sep 04 01:39:09 PM UTC 24 |
| Peak memory | 218936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355029531 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.355029531 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/36.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.760745086 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 62014995 ps |
| CPU time | 0.77 seconds |
| Started | Sep 04 01:39:08 PM UTC 24 |
| Finished | Sep 04 01:39:09 PM UTC 24 |
| Peak memory | 218936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760745086 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.760745086 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/37.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.290307286 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 26790509 ps |
| CPU time | 1.15 seconds |
| Started | Sep 04 01:39:08 PM UTC 24 |
| Finished | Sep 04 01:39:10 PM UTC 24 |
| Peak memory | 218936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290307286 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.290307286 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/38.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.3217309206 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 28122440 ps |
| CPU time | 0.92 seconds |
| Started | Sep 04 01:39:08 PM UTC 24 |
| Finished | Sep 04 01:39:10 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217309206 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.3217309206 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/39.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.3068928426 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 760323944 ps |
| CPU time | 9.63 seconds |
| Started | Sep 04 01:38:31 PM UTC 24 |
| Finished | Sep 04 01:38:42 PM UTC 24 |
| Peak memory | 229384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068928426 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.3068928426 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.3758287628 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 1484041772 ps |
| CPU time | 21.56 seconds |
| Started | Sep 04 01:38:30 PM UTC 24 |
| Finished | Sep 04 01:38:53 PM UTC 24 |
| Peak memory | 219272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758287628 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.3758287628 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_hw_reset.2162592136 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 52119838 ps |
| CPU time | 1.43 seconds |
| Started | Sep 04 01:38:30 PM UTC 24 |
| Finished | Sep 04 01:38:32 PM UTC 24 |
| Peak memory | 219052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162592136 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.2162592136 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.3869357772 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 258690026 ps |
| CPU time | 2.82 seconds |
| Started | Sep 04 01:38:31 PM UTC 24 |
| Finished | Sep 04 01:38:35 PM UTC 24 |
| Peak memory | 231508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3869357772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_ mem_rw_with_rand_reset.3869357772 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.3552804843 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 26933970 ps |
| CPU time | 1.23 seconds |
| Started | Sep 04 01:38:30 PM UTC 24 |
| Finished | Sep 04 01:38:32 PM UTC 24 |
| Peak memory | 218956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552804843 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.3552804843 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_intr_test.2925575430 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 15884822 ps |
| CPU time | 1.24 seconds |
| Started | Sep 04 01:38:28 PM UTC 24 |
| Finished | Sep 04 01:38:31 PM UTC 24 |
| Peak memory | 218992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925575430 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.2925575430 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_partial_access.1934550689 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 35240648 ps |
| CPU time | 2 seconds |
| Started | Sep 04 01:38:27 PM UTC 24 |
| Finished | Sep 04 01:38:30 PM UTC 24 |
| Peak memory | 228908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934550689 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial_access.1934550689 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_walk.4161942461 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 15580145 ps |
| CPU time | 1.12 seconds |
| Started | Sep 04 01:38:27 PM UTC 24 |
| Finished | Sep 04 01:38:29 PM UTC 24 |
| Peak memory | 218992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161942461 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.4161942461 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.228847255 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 353757983 ps |
| CPU time | 3 seconds |
| Started | Sep 04 01:38:31 PM UTC 24 |
| Finished | Sep 04 01:38:35 PM UTC 24 |
| Peak memory | 229388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228847255 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_outstanding.228847255 +enable_m asking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors.1734077809 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 37064693 ps |
| CPU time | 1.85 seconds |
| Started | Sep 04 01:38:26 PM UTC 24 |
| Finished | Sep 04 01:38:29 PM UTC 24 |
| Peak memory | 228800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734077809 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors.1734077809 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2533822194 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 409726896 ps |
| CPU time | 4.38 seconds |
| Started | Sep 04 01:38:27 PM UTC 24 |
| Finished | Sep 04 01:38:32 PM UTC 24 |
| Peak memory | 236876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533822194 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors_with_csr_rw. 2533822194 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.99126924 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 168091114 ps |
| CPU time | 2.98 seconds |
| Started | Sep 04 01:38:27 PM UTC 24 |
| Finished | Sep 04 01:38:31 PM UTC 24 |
| Peak memory | 229708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99126924 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.99126924 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.2772714278 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 99789355 ps |
| CPU time | 3.43 seconds |
| Started | Sep 04 01:38:28 PM UTC 24 |
| Finished | Sep 04 01:38:33 PM UTC 24 |
| Peak memory | 229380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772714278 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.2772714278 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.1369493293 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 27082414 ps |
| CPU time | 1.08 seconds |
| Started | Sep 04 01:39:08 PM UTC 24 |
| Finished | Sep 04 01:39:10 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369493293 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.1369493293 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/40.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.923699863 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 51779969 ps |
| CPU time | 1.06 seconds |
| Started | Sep 04 01:39:08 PM UTC 24 |
| Finished | Sep 04 01:39:10 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923699863 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.923699863 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/41.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.3644766190 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 30091757 ps |
| CPU time | 1.12 seconds |
| Started | Sep 04 01:39:08 PM UTC 24 |
| Finished | Sep 04 01:39:10 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644766190 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.3644766190 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/42.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.4210758214 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 70166545 ps |
| CPU time | 0.92 seconds |
| Started | Sep 04 01:39:08 PM UTC 24 |
| Finished | Sep 04 01:39:10 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210758214 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.4210758214 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/43.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.2543946216 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 18423525 ps |
| CPU time | 0.88 seconds |
| Started | Sep 04 01:39:08 PM UTC 24 |
| Finished | Sep 04 01:39:10 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543946216 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.2543946216 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/44.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.4013214798 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 13110233 ps |
| CPU time | 1.05 seconds |
| Started | Sep 04 01:39:08 PM UTC 24 |
| Finished | Sep 04 01:39:10 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013214798 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.4013214798 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/45.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.814561933 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 17003667 ps |
| CPU time | 0.92 seconds |
| Started | Sep 04 01:39:08 PM UTC 24 |
| Finished | Sep 04 01:39:10 PM UTC 24 |
| Peak memory | 218936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814561933 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.814561933 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/46.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.646809468 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 54848935 ps |
| CPU time | 0.83 seconds |
| Started | Sep 04 01:39:09 PM UTC 24 |
| Finished | Sep 04 01:39:11 PM UTC 24 |
| Peak memory | 218936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646809468 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.646809468 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/47.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.928234454 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 85173816 ps |
| CPU time | 1.01 seconds |
| Started | Sep 04 01:39:09 PM UTC 24 |
| Finished | Sep 04 01:39:12 PM UTC 24 |
| Peak memory | 218936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928234454 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.928234454 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/48.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.2710668327 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 45180642 ps |
| CPU time | 0.86 seconds |
| Started | Sep 04 01:39:09 PM UTC 24 |
| Finished | Sep 04 01:39:11 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710668327 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.2710668327 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/49.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.1723345654 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 68841847 ps |
| CPU time | 2.56 seconds |
| Started | Sep 04 01:38:36 PM UTC 24 |
| Finished | Sep 04 01:38:39 PM UTC 24 |
| Peak memory | 229460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1723345654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_ mem_rw_with_rand_reset.1723345654 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/5.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_rw.763038969 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 187566575 ps |
| CPU time | 1.37 seconds |
| Started | Sep 04 01:38:33 PM UTC 24 |
| Finished | Sep 04 01:38:36 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763038969 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.763038969 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/5.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.1224590855 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 37114869 ps |
| CPU time | 1.15 seconds |
| Started | Sep 04 01:38:33 PM UTC 24 |
| Finished | Sep 04 01:38:35 PM UTC 24 |
| Peak memory | 218992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224590855 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.1224590855 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/5.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_same_csr_outstanding.1679128369 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 77403423 ps |
| CPU time | 2.02 seconds |
| Started | Sep 04 01:38:35 PM UTC 24 |
| Finished | Sep 04 01:38:38 PM UTC 24 |
| Peak memory | 229752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679128369 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_outstanding.1679128369 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/5.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.1722639404 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 24098443 ps |
| CPU time | 1.57 seconds |
| Started | Sep 04 01:38:32 PM UTC 24 |
| Finished | Sep 04 01:38:35 PM UTC 24 |
| Peak memory | 228668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722639404 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors.1722639404 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.522689984 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 124338326 ps |
| CPU time | 4.17 seconds |
| Started | Sep 04 01:38:32 PM UTC 24 |
| Finished | Sep 04 01:38:37 PM UTC 24 |
| Peak memory | 229804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522689984 -asse rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors_with_csr_rw.5 22689984 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.4273294733 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 107196788 ps |
| CPU time | 1.75 seconds |
| Started | Sep 04 01:38:33 PM UTC 24 |
| Finished | Sep 04 01:38:36 PM UTC 24 |
| Peak memory | 228968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273294733 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.4273294733 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/5.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.1096302593 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 383753221 ps |
| CPU time | 5.77 seconds |
| Started | Sep 04 01:38:33 PM UTC 24 |
| Finished | Sep 04 01:38:40 PM UTC 24 |
| Peak memory | 229440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096302593 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.1096302593 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/5.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3885129811 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 40364145 ps |
| CPU time | 2.19 seconds |
| Started | Sep 04 01:38:38 PM UTC 24 |
| Finished | Sep 04 01:38:42 PM UTC 24 |
| Peak memory | 229588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3885129811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_ mem_rw_with_rand_reset.3885129811 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/6.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_rw.2320769662 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 48376029 ps |
| CPU time | 1.4 seconds |
| Started | Sep 04 01:38:37 PM UTC 24 |
| Finished | Sep 04 01:38:40 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320769662 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.2320769662 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/6.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_intr_test.3525785131 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 18747335 ps |
| CPU time | 1.11 seconds |
| Started | Sep 04 01:38:37 PM UTC 24 |
| Finished | Sep 04 01:38:39 PM UTC 24 |
| Peak memory | 218992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525785131 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.3525785131 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/6.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.198707704 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 210738849 ps |
| CPU time | 2.6 seconds |
| Started | Sep 04 01:38:38 PM UTC 24 |
| Finished | Sep 04 01:38:42 PM UTC 24 |
| Peak memory | 229424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198707704 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_outstanding.198707704 +enable_m asking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/6.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.2823904172 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 53933302 ps |
| CPU time | 1.96 seconds |
| Started | Sep 04 01:38:36 PM UTC 24 |
| Finished | Sep 04 01:38:39 PM UTC 24 |
| Peak memory | 228676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823904172 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors.2823904172 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3764522915 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 131730887 ps |
| CPU time | 2.91 seconds |
| Started | Sep 04 01:38:36 PM UTC 24 |
| Finished | Sep 04 01:38:40 PM UTC 24 |
| Peak memory | 229860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764522915 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors_with_csr_rw. 3764522915 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.167696723 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 210188525 ps |
| CPU time | 2.42 seconds |
| Started | Sep 04 01:38:37 PM UTC 24 |
| Finished | Sep 04 01:38:40 PM UTC 24 |
| Peak memory | 229520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167696723 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.167696723 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/6.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.1102417372 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 203059717 ps |
| CPU time | 4.02 seconds |
| Started | Sep 04 01:38:37 PM UTC 24 |
| Finished | Sep 04 01:38:42 PM UTC 24 |
| Peak memory | 219140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102417372 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.1102417372 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/6.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3945389646 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 27454391 ps |
| CPU time | 2.14 seconds |
| Started | Sep 04 01:38:41 PM UTC 24 |
| Finished | Sep 04 01:38:44 PM UTC 24 |
| Peak memory | 229456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3945389646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_ mem_rw_with_rand_reset.3945389646 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/7.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.1519811802 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 17325077 ps |
| CPU time | 1.3 seconds |
| Started | Sep 04 01:38:41 PM UTC 24 |
| Finished | Sep 04 01:38:43 PM UTC 24 |
| Peak memory | 218956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519811802 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.1519811802 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/7.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.1805896894 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 13017613 ps |
| CPU time | 1.18 seconds |
| Started | Sep 04 01:38:41 PM UTC 24 |
| Finished | Sep 04 01:38:43 PM UTC 24 |
| Peak memory | 219052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805896894 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.1805896894 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/7.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3618148391 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 77637216 ps |
| CPU time | 2.33 seconds |
| Started | Sep 04 01:38:41 PM UTC 24 |
| Finished | Sep 04 01:38:44 PM UTC 24 |
| Peak memory | 229396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618148391 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_outstanding.3618148391 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/7.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors.3538730734 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 42204577 ps |
| CPU time | 1.87 seconds |
| Started | Sep 04 01:38:38 PM UTC 24 |
| Finished | Sep 04 01:38:41 PM UTC 24 |
| Peak memory | 228800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538730734 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors.3538730734 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.577828587 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 658900140 ps |
| CPU time | 4.24 seconds |
| Started | Sep 04 01:38:40 PM UTC 24 |
| Finished | Sep 04 01:38:45 PM UTC 24 |
| Peak memory | 229932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577828587 -asse rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors_with_csr_rw.5 77828587 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.2389688270 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 45085632 ps |
| CPU time | 3.33 seconds |
| Started | Sep 04 01:38:40 PM UTC 24 |
| Finished | Sep 04 01:38:44 PM UTC 24 |
| Peak memory | 229520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389688270 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.2389688270 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/7.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.298033704 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 423219166 ps |
| CPU time | 4.97 seconds |
| Started | Sep 04 01:38:41 PM UTC 24 |
| Finished | Sep 04 01:38:47 PM UTC 24 |
| Peak memory | 229408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298033704 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.298033704 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/7.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.3728024561 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 55124227 ps |
| CPU time | 1.99 seconds |
| Started | Sep 04 01:38:44 PM UTC 24 |
| Finished | Sep 04 01:38:47 PM UTC 24 |
| Peak memory | 230924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3728024561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_ mem_rw_with_rand_reset.3728024561 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/8.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.2297884100 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 13288488 ps |
| CPU time | 1.2 seconds |
| Started | Sep 04 01:38:43 PM UTC 24 |
| Finished | Sep 04 01:38:45 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297884100 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.2297884100 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/8.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.3144962562 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 13589170 ps |
| CPU time | 1.12 seconds |
| Started | Sep 04 01:38:42 PM UTC 24 |
| Finished | Sep 04 01:38:45 PM UTC 24 |
| Peak memory | 219052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144962562 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.3144962562 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/8.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.215415767 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 99185071 ps |
| CPU time | 3.74 seconds |
| Started | Sep 04 01:38:43 PM UTC 24 |
| Finished | Sep 04 01:38:47 PM UTC 24 |
| Peak memory | 229576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215415767 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_outstanding.215415767 +enable_m asking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/8.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.824730034 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 84402517 ps |
| CPU time | 1.46 seconds |
| Started | Sep 04 01:38:41 PM UTC 24 |
| Finished | Sep 04 01:38:44 PM UTC 24 |
| Peak memory | 228676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824730034 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors.824730034 +enable_masking =0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.64844073 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 395009890 ps |
| CPU time | 3 seconds |
| Started | Sep 04 01:38:41 PM UTC 24 |
| Finished | Sep 04 01:38:45 PM UTC 24 |
| Peak memory | 229524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64844073 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors_with_csr_rw.64 844073 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.456857043 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 475349230 ps |
| CPU time | 3.3 seconds |
| Started | Sep 04 01:38:42 PM UTC 24 |
| Finished | Sep 04 01:38:47 PM UTC 24 |
| Peak memory | 229556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456857043 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.456857043 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/8.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.4001966843 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 967857841 ps |
| CPU time | 6.06 seconds |
| Started | Sep 04 01:38:42 PM UTC 24 |
| Finished | Sep 04 01:38:50 PM UTC 24 |
| Peak memory | 229440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001966843 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.4001966843 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/8.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.4273387167 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 178758830 ps |
| CPU time | 2.43 seconds |
| Started | Sep 04 01:38:45 PM UTC 24 |
| Finished | Sep 04 01:38:49 PM UTC 24 |
| Peak memory | 229460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4273387167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_ mem_rw_with_rand_reset.4273387167 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/9.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.3954820981 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 14900662 ps |
| CPU time | 1.6 seconds |
| Started | Sep 04 01:38:45 PM UTC 24 |
| Finished | Sep 04 01:38:48 PM UTC 24 |
| Peak memory | 218956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954820981 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.3954820981 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/9.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.708590533 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 50166319 ps |
| CPU time | 0.9 seconds |
| Started | Sep 04 01:38:45 PM UTC 24 |
| Finished | Sep 04 01:38:47 PM UTC 24 |
| Peak memory | 219000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708590533 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.708590533 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/9.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.1672534601 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 247102082 ps |
| CPU time | 2.45 seconds |
| Started | Sep 04 01:38:45 PM UTC 24 |
| Finished | Sep 04 01:38:49 PM UTC 24 |
| Peak memory | 229396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672534601 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_outstanding.1672534601 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/9.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.483032592 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 31117570 ps |
| CPU time | 1.71 seconds |
| Started | Sep 04 01:38:44 PM UTC 24 |
| Finished | Sep 04 01:38:46 PM UTC 24 |
| Peak memory | 228804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483032592 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors.483032592 +enable_masking =0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1183242130 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 412810999 ps |
| CPU time | 2.26 seconds |
| Started | Sep 04 01:38:44 PM UTC 24 |
| Finished | Sep 04 01:38:47 PM UTC 24 |
| Peak memory | 229836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183242130 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors_with_csr_rw. 1183242130 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.3553614077 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 288498435 ps |
| CPU time | 3.57 seconds |
| Started | Sep 04 01:38:45 PM UTC 24 |
| Finished | Sep 04 01:38:50 PM UTC 24 |
| Peak memory | 229644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553614077 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.3553614077 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/9.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.1783109078 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 128415706 ps |
| CPU time | 4.36 seconds |
| Started | Sep 04 01:38:45 PM UTC 24 |
| Finished | Sep 04 01:38:51 PM UTC 24 |
| Peak memory | 229508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783109078 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.1783109078 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/9.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/0.kmac_app.198244251 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 115524086452 ps |
| CPU time | 324.55 seconds |
| Started | Sep 04 12:42:00 PM UTC 24 |
| Finished | Sep 04 12:47:32 PM UTC 24 |
| Peak memory | 507612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198244251 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.198244251 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/0.kmac_edn_timeout_error.3072329680 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 4501570133 ps |
| CPU time | 33.88 seconds |
| Started | Sep 04 12:42:04 PM UTC 24 |
| Finished | Sep 04 12:42:39 PM UTC 24 |
| Peak memory | 232516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072329680 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.3072329680 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_mode_error.628248956 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 215743205 ps |
| CPU time | 11.8 seconds |
| Started | Sep 04 12:42:04 PM UTC 24 |
| Finished | Sep 04 12:42:17 PM UTC 24 |
| Peak memory | 232320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628248956 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.628248956 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_ready_error.4253154344 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3908237158 ps |
| CPU time | 17.67 seconds |
| Started | Sep 04 12:42:05 PM UTC 24 |
| Finished | Sep 04 12:42:24 PM UTC 24 |
| Peak memory | 230524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253154344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.4253154344 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_refresh.2969621080 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 11788327867 ps |
| CPU time | 293.5 seconds |
| Started | Sep 04 12:42:02 PM UTC 24 |
| Finished | Sep 04 12:47:00 PM UTC 24 |
| Peak memory | 501668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969621080 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.2969621080 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/0.kmac_lc_escalation.3045758657 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 64070281 ps |
| CPU time | 1.15 seconds |
| Started | Sep 04 12:42:05 PM UTC 24 |
| Finished | Sep 04 12:42:08 PM UTC 24 |
| Peak memory | 229800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045758657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.3045758657 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/0.kmac_long_msg_and_output.3944746398 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 46215264951 ps |
| CPU time | 1244.06 seconds |
| Started | Sep 04 12:41:58 PM UTC 24 |
| Finished | Sep 04 01:03:01 PM UTC 24 |
| Peak memory | 1844980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944746398 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_and_output.3944746398 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/0.kmac_sec_cm.3206265800 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 6367942872 ps |
| CPU time | 29.97 seconds |
| Started | Sep 04 12:42:06 PM UTC 24 |
| Finished | Sep 04 12:42:37 PM UTC 24 |
| Peak memory | 267180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206265800 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.3206265800 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/0.kmac_sideload.1442019111 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 28634523621 ps |
| CPU time | 457.5 seconds |
| Started | Sep 04 12:41:58 PM UTC 24 |
| Finished | Sep 04 12:49:47 PM UTC 24 |
| Peak memory | 618280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442019111 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.1442019111 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/0.kmac_smoke.3565388672 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 296031805 ps |
| CPU time | 6.75 seconds |
| Started | Sep 04 12:41:58 PM UTC 24 |
| Finished | Sep 04 12:42:09 PM UTC 24 |
| Peak memory | 230608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565388672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.3565388672 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/0.kmac_stress_all.673334664 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 14509608112 ps |
| CPU time | 202.07 seconds |
| Started | Sep 04 12:42:06 PM UTC 24 |
| Finished | Sep 04 12:45:31 PM UTC 24 |
| Peak memory | 264052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673334664 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.673334664 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac.506313784 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 164040114 ps |
| CPU time | 2.43 seconds |
| Started | Sep 04 12:42:00 PM UTC 24 |
| Finished | Sep 04 12:42:06 PM UTC 24 |
| Peak memory | 230780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506313784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_ve ctors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac.506313784 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac_xof.188172862 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 320025016 ps |
| CPU time | 1.7 seconds |
| Started | Sep 04 12:42:00 PM UTC 24 |
| Finished | Sep 04 12:42:05 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188172862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_ve ctors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.188172862 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_256.2745279395 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 76522575148 ps |
| CPU time | 2216.02 seconds |
| Started | Sep 04 12:41:59 PM UTC 24 |
| Finished | Sep 04 01:19:29 PM UTC 24 |
| Peak memory | 2993912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745279395 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.2745279395 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_384.1386134400 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 2341869421 ps |
| CPU time | 35.49 seconds |
| Started | Sep 04 12:41:59 PM UTC 24 |
| Finished | Sep 04 12:42:40 PM UTC 24 |
| Peak memory | 239396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386134400 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.1386134400 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_128.2925283663 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 256418263020 ps |
| CPU time | 1993.37 seconds |
| Started | Sep 04 12:42:00 PM UTC 24 |
| Finished | Sep 04 01:15:41 PM UTC 24 |
| Peak memory | 1343124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925283663 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.2925283 663 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/1.kmac_alert_test.2546184509 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 28666972 ps |
| CPU time | 0.98 seconds |
| Started | Sep 04 12:42:14 PM UTC 24 |
| Finished | Sep 04 12:42:16 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546184509 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.2546184509 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/1.kmac_app.2330796879 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 4429674045 ps |
| CPU time | 237.61 seconds |
| Started | Sep 04 12:42:08 PM UTC 24 |
| Finished | Sep 04 12:46:11 PM UTC 24 |
| Peak memory | 321532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330796879 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.2330796879 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/1.kmac_app_with_partial_data.944833064 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 94468516762 ps |
| CPU time | 361.18 seconds |
| Started | Sep 04 12:42:08 PM UTC 24 |
| Finished | Sep 04 12:48:16 PM UTC 24 |
| Peak memory | 466720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944833064 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.944833064 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/1.kmac_burst_write.1438055582 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 3329654899 ps |
| CPU time | 305.82 seconds |
| Started | Sep 04 12:42:08 PM UTC 24 |
| Finished | Sep 04 12:47:19 PM UTC 24 |
| Peak memory | 241460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438055582 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.1438055582 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/1.kmac_edn_timeout_error.2326132413 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 495679052 ps |
| CPU time | 34.12 seconds |
| Started | Sep 04 12:42:10 PM UTC 24 |
| Finished | Sep 04 12:42:46 PM UTC 24 |
| Peak memory | 235032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326132413 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.2326132413 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_mode_error.937164341 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 6366351997 ps |
| CPU time | 48.93 seconds |
| Started | Sep 04 12:42:10 PM UTC 24 |
| Finished | Sep 04 12:43:01 PM UTC 24 |
| Peak memory | 235120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937164341 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.937164341 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_refresh.2567707596 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 75437498407 ps |
| CPU time | 348.35 seconds |
| Started | Sep 04 12:42:08 PM UTC 24 |
| Finished | Sep 04 12:48:03 PM UTC 24 |
| Peak memory | 509664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567707596 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.2567707596 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/1.kmac_key_error.2461340568 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 3885780587 ps |
| CPU time | 7.14 seconds |
| Started | Sep 04 12:42:09 PM UTC 24 |
| Finished | Sep 04 12:42:17 PM UTC 24 |
| Peak memory | 230400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461340568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.2461340568 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/1.kmac_long_msg_and_output.2836361487 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 14060056316 ps |
| CPU time | 314.4 seconds |
| Started | Sep 04 12:42:06 PM UTC 24 |
| Finished | Sep 04 12:47:25 PM UTC 24 |
| Peak memory | 450416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836361487 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_and_output.2836361487 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/1.kmac_mubi.3786865812 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9235967501 ps |
| CPU time | 229.55 seconds |
| Started | Sep 04 12:42:08 PM UTC 24 |
| Finished | Sep 04 12:46:03 PM UTC 24 |
| Peak memory | 329768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786865812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.3786865812 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/1.kmac_sideload.849785094 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 7882342035 ps |
| CPU time | 330.03 seconds |
| Started | Sep 04 12:42:08 PM UTC 24 |
| Finished | Sep 04 12:47:44 PM UTC 24 |
| Peak memory | 383020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849785094 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.849785094 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/1.kmac_smoke.1742293587 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 828755504 ps |
| CPU time | 4.67 seconds |
| Started | Sep 04 12:42:06 PM UTC 24 |
| Finished | Sep 04 12:42:12 PM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742293587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.1742293587 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/1.kmac_stress_all.803217004 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 101385796501 ps |
| CPU time | 937.08 seconds |
| Started | Sep 04 12:42:11 PM UTC 24 |
| Finished | Sep 04 12:58:01 PM UTC 24 |
| Peak memory | 569064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803217004 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.803217004 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac.3740819595 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 289393843 ps |
| CPU time | 2.48 seconds |
| Started | Sep 04 12:42:08 PM UTC 24 |
| Finished | Sep 04 12:42:12 PM UTC 24 |
| Peak memory | 230540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740819595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac.3740819595 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac_xof.4277548748 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 111287447 ps |
| CPU time | 3.08 seconds |
| Started | Sep 04 12:42:08 PM UTC 24 |
| Finished | Sep 04 12:42:13 PM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277548748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.4277548748 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_224.2767251340 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 4906326446 ps |
| CPU time | 46.3 seconds |
| Started | Sep 04 12:42:08 PM UTC 24 |
| Finished | Sep 04 12:42:56 PM UTC 24 |
| Peak memory | 257764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767251340 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.2767251340 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_256.424123830 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 228854216532 ps |
| CPU time | 2171.79 seconds |
| Started | Sep 04 12:42:08 PM UTC 24 |
| Finished | Sep 04 01:18:46 PM UTC 24 |
| Peak memory | 2963088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424123830 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.424123830 + enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_384.3886479534 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 47232775511 ps |
| CPU time | 1583.3 seconds |
| Started | Sep 04 12:42:08 PM UTC 24 |
| Finished | Sep 04 01:08:52 PM UTC 24 |
| Peak memory | 2350748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886479534 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.3886479534 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_512.553882759 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 515482380967 ps |
| CPU time | 1105.87 seconds |
| Started | Sep 04 12:42:08 PM UTC 24 |
| Finished | Sep 04 01:00:49 PM UTC 24 |
| Peak memory | 1701524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553882759 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.553882759 + enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_128.951678548 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 34330322720 ps |
| CPU time | 222.51 seconds |
| Started | Sep 04 12:42:08 PM UTC 24 |
| Finished | Sep 04 12:45:55 PM UTC 24 |
| Peak memory | 444256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951678548 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.95167854 8 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_256.1216365432 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 23480682790 ps |
| CPU time | 285.62 seconds |
| Started | Sep 04 12:42:08 PM UTC 24 |
| Finished | Sep 04 12:46:59 PM UTC 24 |
| Peak memory | 263832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216365432 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.1216365 432 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/10.kmac_alert_test.1270098396 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 78016894 ps |
| CPU time | 1.28 seconds |
| Started | Sep 04 12:51:25 PM UTC 24 |
| Finished | Sep 04 12:51:27 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270098396 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.1270098396 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/10.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/10.kmac_app.2840166845 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 2675637787 ps |
| CPU time | 133.5 seconds |
| Started | Sep 04 12:50:50 PM UTC 24 |
| Finished | Sep 04 12:53:06 PM UTC 24 |
| Peak memory | 286448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840166845 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.2840166845 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/10.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/10.kmac_burst_write.1038308635 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 17851505155 ps |
| CPU time | 709.17 seconds |
| Started | Sep 04 12:50:47 PM UTC 24 |
| Finished | Sep 04 01:02:45 PM UTC 24 |
| Peak memory | 259820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038308635 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.1038308635 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/10.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/10.kmac_edn_timeout_error.1368617039 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 2371426306 ps |
| CPU time | 18.45 seconds |
| Started | Sep 04 12:51:15 PM UTC 24 |
| Finished | Sep 04 12:51:35 PM UTC 24 |
| Peak memory | 245420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368617039 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.1368617039 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/10.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/10.kmac_entropy_mode_error.2098881744 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 88479744 ps |
| CPU time | 3.89 seconds |
| Started | Sep 04 12:51:18 PM UTC 24 |
| Finished | Sep 04 12:51:23 PM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098881744 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.2098881744 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/10.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/10.kmac_entropy_refresh.1520493943 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 19771480627 ps |
| CPU time | 406.36 seconds |
| Started | Sep 04 12:51:03 PM UTC 24 |
| Finished | Sep 04 12:57:55 PM UTC 24 |
| Peak memory | 579568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520493943 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.1520493943 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/10.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/10.kmac_error.2135462536 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 781736497 ps |
| CPU time | 19.27 seconds |
| Started | Sep 04 12:51:04 PM UTC 24 |
| Finished | Sep 04 12:51:25 PM UTC 24 |
| Peak memory | 245680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135462536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.2135462536 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/10.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/10.kmac_key_error.3093742351 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 1321469607 ps |
| CPU time | 6.26 seconds |
| Started | Sep 04 12:51:07 PM UTC 24 |
| Finished | Sep 04 12:51:15 PM UTC 24 |
| Peak memory | 232460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093742351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.3093742351 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/10.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/10.kmac_lc_escalation.4098910771 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 39663710 ps |
| CPU time | 2.02 seconds |
| Started | Sep 04 12:51:21 PM UTC 24 |
| Finished | Sep 04 12:51:24 PM UTC 24 |
| Peak memory | 230392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098910771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.4098910771 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/10.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/10.kmac_long_msg_and_output.2013125237 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 65166784643 ps |
| CPU time | 1192.46 seconds |
| Started | Sep 04 12:50:46 PM UTC 24 |
| Finished | Sep 04 01:10:53 PM UTC 24 |
| Peak memory | 1705828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013125237 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_and_output.2013125237 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/10.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/10.kmac_sideload.3334442657 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 4155044183 ps |
| CPU time | 45.74 seconds |
| Started | Sep 04 12:50:46 PM UTC 24 |
| Finished | Sep 04 12:51:33 PM UTC 24 |
| Peak memory | 267996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334442657 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.3334442657 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/10.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/10.kmac_smoke.3017573142 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 1342452621 ps |
| CPU time | 17.99 seconds |
| Started | Sep 04 12:50:43 PM UTC 24 |
| Finished | Sep 04 12:51:02 PM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017573142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.3017573142 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/10.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/10.kmac_stress_all.1784574447 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 9619631699 ps |
| CPU time | 624.86 seconds |
| Started | Sep 04 12:51:22 PM UTC 24 |
| Finished | Sep 04 01:01:54 PM UTC 24 |
| Peak memory | 626796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784574447 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.1784574447 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/10.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/11.kmac_alert_test.1130254033 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 27186109 ps |
| CPU time | 0.98 seconds |
| Started | Sep 04 12:52:07 PM UTC 24 |
| Finished | Sep 04 12:52:09 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130254033 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.1130254033 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/11.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/11.kmac_app.1817795383 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 13664258325 ps |
| CPU time | 64.59 seconds |
| Started | Sep 04 12:51:34 PM UTC 24 |
| Finished | Sep 04 12:52:40 PM UTC 24 |
| Peak memory | 272376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817795383 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.1817795383 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/11.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/11.kmac_burst_write.3988081278 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 95219302366 ps |
| CPU time | 371.59 seconds |
| Started | Sep 04 12:51:34 PM UTC 24 |
| Finished | Sep 04 12:57:51 PM UTC 24 |
| Peak memory | 245544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988081278 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.3988081278 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/11.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/11.kmac_edn_timeout_error.4106648224 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 2567449259 ps |
| CPU time | 14.68 seconds |
| Started | Sep 04 12:51:50 PM UTC 24 |
| Finished | Sep 04 12:52:06 PM UTC 24 |
| Peak memory | 228344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106648224 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.4106648224 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/11.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/11.kmac_entropy_mode_error.3907807952 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 809179658 ps |
| CPU time | 9.82 seconds |
| Started | Sep 04 12:51:51 PM UTC 24 |
| Finished | Sep 04 12:52:02 PM UTC 24 |
| Peak memory | 228212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907807952 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.3907807952 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/11.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/11.kmac_entropy_refresh.1201681829 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 31051068844 ps |
| CPU time | 224.72 seconds |
| Started | Sep 04 12:51:35 PM UTC 24 |
| Finished | Sep 04 12:55:24 PM UTC 24 |
| Peak memory | 378660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201681829 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.1201681829 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/11.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/11.kmac_error.2405200830 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 199359691729 ps |
| CPU time | 421.14 seconds |
| Started | Sep 04 12:51:36 PM UTC 24 |
| Finished | Sep 04 12:58:43 PM UTC 24 |
| Peak memory | 659252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405200830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.2405200830 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/11.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/11.kmac_key_error.2716238205 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 731305529 ps |
| CPU time | 8.24 seconds |
| Started | Sep 04 12:51:46 PM UTC 24 |
| Finished | Sep 04 12:51:56 PM UTC 24 |
| Peak memory | 230664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716238205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.2716238205 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/11.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/11.kmac_lc_escalation.1978146191 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 77870937 ps |
| CPU time | 1.47 seconds |
| Started | Sep 04 12:51:56 PM UTC 24 |
| Finished | Sep 04 12:51:59 PM UTC 24 |
| Peak memory | 229680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978146191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.1978146191 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/11.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/11.kmac_long_msg_and_output.2272289065 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 134256327197 ps |
| CPU time | 1357.17 seconds |
| Started | Sep 04 12:51:26 PM UTC 24 |
| Finished | Sep 04 01:14:20 PM UTC 24 |
| Peak memory | 1683304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272289065 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_and_output.2272289065 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/11.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/11.kmac_sideload.3309616733 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 74145908372 ps |
| CPU time | 481.61 seconds |
| Started | Sep 04 12:51:28 PM UTC 24 |
| Finished | Sep 04 12:59:36 PM UTC 24 |
| Peak memory | 646964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309616733 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.3309616733 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/11.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/11.kmac_smoke.3548114761 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 289866337 ps |
| CPU time | 18.67 seconds |
| Started | Sep 04 12:51:26 PM UTC 24 |
| Finished | Sep 04 12:51:46 PM UTC 24 |
| Peak memory | 230612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548114761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.3548114761 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/11.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/11.kmac_stress_all.759329327 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 8659476430 ps |
| CPU time | 489.38 seconds |
| Started | Sep 04 12:51:58 PM UTC 24 |
| Finished | Sep 04 01:00:13 PM UTC 24 |
| Peak memory | 360616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759329327 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.759329327 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/11.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/12.kmac_alert_test.639911693 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 199272359 ps |
| CPU time | 1.36 seconds |
| Started | Sep 04 12:52:46 PM UTC 24 |
| Finished | Sep 04 12:52:48 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639911693 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.639911693 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/12.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/12.kmac_app.2237623567 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 24086122330 ps |
| CPU time | 342.16 seconds |
| Started | Sep 04 12:52:09 PM UTC 24 |
| Finished | Sep 04 12:57:57 PM UTC 24 |
| Peak memory | 362468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237623567 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.2237623567 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/12.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/12.kmac_burst_write.401955917 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 6506964016 ps |
| CPU time | 63.74 seconds |
| Started | Sep 04 12:52:08 PM UTC 24 |
| Finished | Sep 04 12:53:14 PM UTC 24 |
| Peak memory | 230592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401955917 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.401955917 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/12.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/12.kmac_edn_timeout_error.2362199812 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 847551299 ps |
| CPU time | 15.99 seconds |
| Started | Sep 04 12:52:29 PM UTC 24 |
| Finished | Sep 04 12:52:47 PM UTC 24 |
| Peak memory | 234984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362199812 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.2362199812 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/12.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/12.kmac_entropy_mode_error.1316712836 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 74670054 ps |
| CPU time | 3.09 seconds |
| Started | Sep 04 12:52:33 PM UTC 24 |
| Finished | Sep 04 12:52:38 PM UTC 24 |
| Peak memory | 228428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316712836 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.1316712836 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/12.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/12.kmac_entropy_refresh.3753924111 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 29679373789 ps |
| CPU time | 262.65 seconds |
| Started | Sep 04 12:52:27 PM UTC 24 |
| Finished | Sep 04 12:56:54 PM UTC 24 |
| Peak memory | 331516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753924111 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.3753924111 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/12.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/12.kmac_key_error.3424011777 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 74704906 ps |
| CPU time | 1.58 seconds |
| Started | Sep 04 12:52:29 PM UTC 24 |
| Finished | Sep 04 12:52:32 PM UTC 24 |
| Peak memory | 229800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424011777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.3424011777 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/12.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/12.kmac_lc_escalation.3232584846 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 334431019 ps |
| CPU time | 6.51 seconds |
| Started | Sep 04 12:52:38 PM UTC 24 |
| Finished | Sep 04 12:52:46 PM UTC 24 |
| Peak memory | 234824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232584846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.3232584846 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/12.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/12.kmac_long_msg_and_output.2116358437 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 77596810901 ps |
| CPU time | 2876.79 seconds |
| Started | Sep 04 12:52:08 PM UTC 24 |
| Finished | Sep 04 01:40:38 PM UTC 24 |
| Peak memory | 3395364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116358437 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_and_output.2116358437 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/12.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/12.kmac_sideload.2457423507 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 10415513270 ps |
| CPU time | 292.33 seconds |
| Started | Sep 04 12:52:08 PM UTC 24 |
| Finished | Sep 04 12:57:06 PM UTC 24 |
| Peak memory | 499696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457423507 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.2457423507 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/12.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/12.kmac_smoke.3463123221 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 588756039 ps |
| CPU time | 10.32 seconds |
| Started | Sep 04 12:52:08 PM UTC 24 |
| Finished | Sep 04 12:52:20 PM UTC 24 |
| Peak memory | 230612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463123221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.3463123221 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/12.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/12.kmac_stress_all.3622636838 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 368430332258 ps |
| CPU time | 2323.75 seconds |
| Started | Sep 04 12:52:42 PM UTC 24 |
| Finished | Sep 04 01:31:53 PM UTC 24 |
| Peak memory | 1120464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622636838 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.3622636838 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/12.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/13.kmac_alert_test.1673914648 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 12803911 ps |
| CPU time | 1.14 seconds |
| Started | Sep 04 12:54:05 PM UTC 24 |
| Finished | Sep 04 12:54:07 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673914648 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.1673914648 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/13.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/13.kmac_app.1654991038 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 2787214659 ps |
| CPU time | 62.91 seconds |
| Started | Sep 04 12:53:07 PM UTC 24 |
| Finished | Sep 04 12:54:12 PM UTC 24 |
| Peak memory | 276536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654991038 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.1654991038 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/13.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/13.kmac_burst_write.177680057 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 10390665033 ps |
| CPU time | 432.8 seconds |
| Started | Sep 04 12:53:07 PM UTC 24 |
| Finished | Sep 04 01:00:26 PM UTC 24 |
| Peak memory | 249604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177680057 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.177680057 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/13.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/13.kmac_edn_timeout_error.2067869675 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 4757395485 ps |
| CPU time | 39.4 seconds |
| Started | Sep 04 12:53:36 PM UTC 24 |
| Finished | Sep 04 12:54:17 PM UTC 24 |
| Peak memory | 235040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067869675 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.2067869675 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/13.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/13.kmac_entropy_mode_error.682670461 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 753273940 ps |
| CPU time | 37.26 seconds |
| Started | Sep 04 12:53:36 PM UTC 24 |
| Finished | Sep 04 12:54:15 PM UTC 24 |
| Peak memory | 235068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682670461 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.682670461 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/13.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/13.kmac_entropy_refresh.1080885633 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 3441501514 ps |
| CPU time | 46.94 seconds |
| Started | Sep 04 12:53:15 PM UTC 24 |
| Finished | Sep 04 12:54:04 PM UTC 24 |
| Peak memory | 247596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080885633 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.1080885633 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/13.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/13.kmac_error.2844101389 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 1448924863 ps |
| CPU time | 92.75 seconds |
| Started | Sep 04 12:53:18 PM UTC 24 |
| Finished | Sep 04 12:54:53 PM UTC 24 |
| Peak memory | 284324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844101389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.2844101389 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/13.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/13.kmac_key_error.3185187251 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 596153605 ps |
| CPU time | 6.98 seconds |
| Started | Sep 04 12:53:27 PM UTC 24 |
| Finished | Sep 04 12:53:35 PM UTC 24 |
| Peak memory | 230652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185187251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.3185187251 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/13.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/13.kmac_long_msg_and_output.1346146365 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 3517766876 ps |
| CPU time | 110.12 seconds |
| Started | Sep 04 12:52:48 PM UTC 24 |
| Finished | Sep 04 12:54:40 PM UTC 24 |
| Peak memory | 341804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346146365 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_and_output.1346146365 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/13.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/13.kmac_sideload.2839340387 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 83365026217 ps |
| CPU time | 456.78 seconds |
| Started | Sep 04 12:52:49 PM UTC 24 |
| Finished | Sep 04 01:00:34 PM UTC 24 |
| Peak memory | 599856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839340387 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.2839340387 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/13.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/13.kmac_smoke.3428756383 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 11445002367 ps |
| CPU time | 38.82 seconds |
| Started | Sep 04 12:52:47 PM UTC 24 |
| Finished | Sep 04 12:53:27 PM UTC 24 |
| Peak memory | 230776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428756383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.3428756383 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/13.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/13.kmac_stress_all.1061021997 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 8460574928 ps |
| CPU time | 62.37 seconds |
| Started | Sep 04 12:54:02 PM UTC 24 |
| Finished | Sep 04 12:55:06 PM UTC 24 |
| Peak memory | 268404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061021997 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.1061021997 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/13.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/14.kmac_alert_test.2595488762 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 55828577 ps |
| CPU time | 1.21 seconds |
| Started | Sep 04 12:54:41 PM UTC 24 |
| Finished | Sep 04 12:54:43 PM UTC 24 |
| Peak memory | 216232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595488762 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.2595488762 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/14.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/14.kmac_app.2659591160 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 30384590698 ps |
| CPU time | 316.34 seconds |
| Started | Sep 04 12:54:14 PM UTC 24 |
| Finished | Sep 04 12:59:35 PM UTC 24 |
| Peak memory | 514096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659591160 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.2659591160 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/14.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/14.kmac_burst_write.4171456310 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 2950919939 ps |
| CPU time | 124.54 seconds |
| Started | Sep 04 12:54:14 PM UTC 24 |
| Finished | Sep 04 12:56:21 PM UTC 24 |
| Peak memory | 235364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171456310 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.4171456310 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/14.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/14.kmac_edn_timeout_error.3374465430 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 478381178 ps |
| CPU time | 21.61 seconds |
| Started | Sep 04 12:54:28 PM UTC 24 |
| Finished | Sep 04 12:54:51 PM UTC 24 |
| Peak memory | 232440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374465430 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.3374465430 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/14.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/14.kmac_entropy_mode_error.3151038142 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 6021859859 ps |
| CPU time | 44.27 seconds |
| Started | Sep 04 12:54:30 PM UTC 24 |
| Finished | Sep 04 12:55:15 PM UTC 24 |
| Peak memory | 232632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151038142 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.3151038142 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/14.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/14.kmac_entropy_refresh.1738133349 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 24244839283 ps |
| CPU time | 261.48 seconds |
| Started | Sep 04 12:54:16 PM UTC 24 |
| Finished | Sep 04 12:58:43 PM UTC 24 |
| Peak memory | 323372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738133349 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.1738133349 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/14.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/14.kmac_error.550692148 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 406505827 ps |
| CPU time | 9.43 seconds |
| Started | Sep 04 12:54:17 PM UTC 24 |
| Finished | Sep 04 12:54:28 PM UTC 24 |
| Peak memory | 232696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550692148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.550692148 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/14.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/14.kmac_key_error.1848478764 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 3301490825 ps |
| CPU time | 8.85 seconds |
| Started | Sep 04 12:54:18 PM UTC 24 |
| Finished | Sep 04 12:54:28 PM UTC 24 |
| Peak memory | 230476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848478764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.1848478764 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/14.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/14.kmac_lc_escalation.171667989 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 109926322 ps |
| CPU time | 2 seconds |
| Started | Sep 04 12:54:33 PM UTC 24 |
| Finished | Sep 04 12:54:36 PM UTC 24 |
| Peak memory | 229820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171667989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.171667989 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/14.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/14.kmac_long_msg_and_output.3837170938 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 42425031562 ps |
| CPU time | 1075.38 seconds |
| Started | Sep 04 12:54:12 PM UTC 24 |
| Finished | Sep 04 01:12:20 PM UTC 24 |
| Peak memory | 851748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837170938 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_and_output.3837170938 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/14.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/14.kmac_sideload.942253848 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 24815845913 ps |
| CPU time | 396.15 seconds |
| Started | Sep 04 12:54:13 PM UTC 24 |
| Finished | Sep 04 01:00:55 PM UTC 24 |
| Peak memory | 554808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942253848 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.942253848 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/14.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/14.kmac_smoke.71905372 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 192834425 ps |
| CPU time | 2.55 seconds |
| Started | Sep 04 12:54:08 PM UTC 24 |
| Finished | Sep 04 12:54:11 PM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71905372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.71905372 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/14.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/14.kmac_stress_all.969119075 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 14604173108 ps |
| CPU time | 379.85 seconds |
| Started | Sep 04 12:54:37 PM UTC 24 |
| Finished | Sep 04 01:01:02 PM UTC 24 |
| Peak memory | 493356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969119075 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.969119075 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/14.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/15.kmac_alert_test.2908525125 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 19230930 ps |
| CPU time | 1.24 seconds |
| Started | Sep 04 12:55:32 PM UTC 24 |
| Finished | Sep 04 12:55:34 PM UTC 24 |
| Peak memory | 216348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908525125 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.2908525125 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/15.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/15.kmac_app.4116667970 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 1290702981 ps |
| CPU time | 52.6 seconds |
| Started | Sep 04 12:54:47 PM UTC 24 |
| Finished | Sep 04 12:55:41 PM UTC 24 |
| Peak memory | 253672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116667970 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.4116667970 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/15.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/15.kmac_burst_write.1866518938 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 16664461949 ps |
| CPU time | 152.47 seconds |
| Started | Sep 04 12:54:44 PM UTC 24 |
| Finished | Sep 04 12:57:19 PM UTC 24 |
| Peak memory | 237468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866518938 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.1866518938 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/15.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/15.kmac_edn_timeout_error.2793243938 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 2152324402 ps |
| CPU time | 38.43 seconds |
| Started | Sep 04 12:55:06 PM UTC 24 |
| Finished | Sep 04 12:55:46 PM UTC 24 |
| Peak memory | 235300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793243938 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.2793243938 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/15.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/15.kmac_entropy_mode_error.2316795618 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 13112893804 ps |
| CPU time | 43.3 seconds |
| Started | Sep 04 12:55:09 PM UTC 24 |
| Finished | Sep 04 12:55:54 PM UTC 24 |
| Peak memory | 235040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316795618 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.2316795618 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/15.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/15.kmac_entropy_refresh.3301246972 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 828841674 ps |
| CPU time | 45.25 seconds |
| Started | Sep 04 12:54:52 PM UTC 24 |
| Finished | Sep 04 12:55:39 PM UTC 24 |
| Peak memory | 251568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301246972 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.3301246972 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/15.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/15.kmac_error.394380612 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 17079843464 ps |
| CPU time | 366.12 seconds |
| Started | Sep 04 12:54:54 PM UTC 24 |
| Finished | Sep 04 01:01:06 PM UTC 24 |
| Peak memory | 368436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394380612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.394380612 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/15.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/15.kmac_key_error.2050567436 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 1313732611 ps |
| CPU time | 11.72 seconds |
| Started | Sep 04 12:54:55 PM UTC 24 |
| Finished | Sep 04 12:55:08 PM UTC 24 |
| Peak memory | 230460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050567436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.2050567436 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/15.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/15.kmac_long_msg_and_output.820649202 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 379926164315 ps |
| CPU time | 2968.75 seconds |
| Started | Sep 04 12:54:44 PM UTC 24 |
| Finished | Sep 04 01:44:46 PM UTC 24 |
| Peak memory | 3311408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820649202 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_and_output.820649202 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/15.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/15.kmac_sideload.2815896007 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 2224076436 ps |
| CPU time | 213.47 seconds |
| Started | Sep 04 12:54:44 PM UTC 24 |
| Finished | Sep 04 12:58:21 PM UTC 24 |
| Peak memory | 304944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815896007 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.2815896007 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/15.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/15.kmac_smoke.730804586 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 1594907819 ps |
| CPU time | 25.54 seconds |
| Started | Sep 04 12:54:41 PM UTC 24 |
| Finished | Sep 04 12:55:08 PM UTC 24 |
| Peak memory | 230460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730804586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.730804586 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/15.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/15.kmac_stress_all.2628461663 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 43433082220 ps |
| CPU time | 337.56 seconds |
| Started | Sep 04 12:55:17 PM UTC 24 |
| Finished | Sep 04 01:00:59 PM UTC 24 |
| Peak memory | 710452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628461663 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.2628461663 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/15.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/16.kmac_alert_test.589451047 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 136887380 ps |
| CPU time | 1.2 seconds |
| Started | Sep 04 12:56:00 PM UTC 24 |
| Finished | Sep 04 12:56:02 PM UTC 24 |
| Peak memory | 216348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589451047 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.589451047 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/16.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/16.kmac_app.3725522771 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 15536636101 ps |
| CPU time | 115.27 seconds |
| Started | Sep 04 12:55:42 PM UTC 24 |
| Finished | Sep 04 12:57:40 PM UTC 24 |
| Peak memory | 341872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725522771 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.3725522771 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/16.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/16.kmac_burst_write.2828584691 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 21775482505 ps |
| CPU time | 551.91 seconds |
| Started | Sep 04 12:55:40 PM UTC 24 |
| Finished | Sep 04 01:04:59 PM UTC 24 |
| Peak memory | 245604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828584691 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.2828584691 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/16.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/16.kmac_edn_timeout_error.2358745556 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 598978454 ps |
| CPU time | 14.63 seconds |
| Started | Sep 04 12:55:55 PM UTC 24 |
| Finished | Sep 04 12:56:10 PM UTC 24 |
| Peak memory | 232300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358745556 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.2358745556 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/16.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/16.kmac_entropy_mode_error.4047339284 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 2315884047 ps |
| CPU time | 22.96 seconds |
| Started | Sep 04 12:55:55 PM UTC 24 |
| Finished | Sep 04 12:56:19 PM UTC 24 |
| Peak memory | 235232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047339284 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.4047339284 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/16.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/16.kmac_entropy_refresh.4203575517 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 13057261414 ps |
| CPU time | 51.79 seconds |
| Started | Sep 04 12:55:46 PM UTC 24 |
| Finished | Sep 04 12:56:40 PM UTC 24 |
| Peak memory | 262184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203575517 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.4203575517 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/16.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/16.kmac_error.3273216171 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 20821241007 ps |
| CPU time | 499.38 seconds |
| Started | Sep 04 12:55:47 PM UTC 24 |
| Finished | Sep 04 01:04:13 PM UTC 24 |
| Peak memory | 675612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273216171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.3273216171 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/16.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/16.kmac_key_error.2155190286 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 701177935 ps |
| CPU time | 7.43 seconds |
| Started | Sep 04 12:55:51 PM UTC 24 |
| Finished | Sep 04 12:56:00 PM UTC 24 |
| Peak memory | 230340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155190286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.2155190286 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/16.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/16.kmac_long_msg_and_output.4113049653 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 51913558381 ps |
| CPU time | 1455.98 seconds |
| Started | Sep 04 12:55:35 PM UTC 24 |
| Finished | Sep 04 01:20:08 PM UTC 24 |
| Peak memory | 2011116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113049653 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_and_output.4113049653 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/16.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/16.kmac_sideload.2468070900 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 4289646873 ps |
| CPU time | 382.73 seconds |
| Started | Sep 04 12:55:38 PM UTC 24 |
| Finished | Sep 04 01:02:06 PM UTC 24 |
| Peak memory | 372452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468070900 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.2468070900 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/16.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/16.kmac_smoke.710061800 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 1283446941 ps |
| CPU time | 35.99 seconds |
| Started | Sep 04 12:55:33 PM UTC 24 |
| Finished | Sep 04 12:56:10 PM UTC 24 |
| Peak memory | 230548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710061800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.710061800 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/16.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/16.kmac_stress_all.2877642766 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 3978393075 ps |
| CPU time | 95.78 seconds |
| Started | Sep 04 12:55:58 PM UTC 24 |
| Finished | Sep 04 12:57:35 PM UTC 24 |
| Peak memory | 323504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877642766 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.2877642766 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/16.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/17.kmac_alert_test.3122814758 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 25849922 ps |
| CPU time | 1.21 seconds |
| Started | Sep 04 12:57:07 PM UTC 24 |
| Finished | Sep 04 12:57:09 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122814758 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.3122814758 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/17.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/17.kmac_app.1121955965 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 4949020830 ps |
| CPU time | 280.48 seconds |
| Started | Sep 04 12:56:11 PM UTC 24 |
| Finished | Sep 04 01:00:56 PM UTC 24 |
| Peak memory | 354100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121955965 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.1121955965 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/17.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/17.kmac_burst_write.1786042409 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 227729571811 ps |
| CPU time | 999.4 seconds |
| Started | Sep 04 12:56:11 PM UTC 24 |
| Finished | Sep 04 01:13:02 PM UTC 24 |
| Peak memory | 270120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786042409 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.1786042409 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/17.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/17.kmac_edn_timeout_error.3357046630 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 2601982236 ps |
| CPU time | 26.74 seconds |
| Started | Sep 04 12:56:41 PM UTC 24 |
| Finished | Sep 04 12:57:09 PM UTC 24 |
| Peak memory | 235044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357046630 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.3357046630 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/17.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/17.kmac_entropy_mode_error.517289673 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 1347251865 ps |
| CPU time | 11.25 seconds |
| Started | Sep 04 12:56:43 PM UTC 24 |
| Finished | Sep 04 12:56:55 PM UTC 24 |
| Peak memory | 235232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517289673 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.517289673 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/17.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/17.kmac_entropy_refresh.548173884 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 17585834869 ps |
| CPU time | 257.62 seconds |
| Started | Sep 04 12:56:19 PM UTC 24 |
| Finished | Sep 04 01:00:41 PM UTC 24 |
| Peak memory | 341736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548173884 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.548173884 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/17.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/17.kmac_error.127340376 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1577461410 ps |
| CPU time | 53.3 seconds |
| Started | Sep 04 12:56:22 PM UTC 24 |
| Finished | Sep 04 12:57:17 PM UTC 24 |
| Peak memory | 268076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127340376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.127340376 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/17.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/17.kmac_key_error.671061767 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 637286646 ps |
| CPU time | 7.61 seconds |
| Started | Sep 04 12:56:33 PM UTC 24 |
| Finished | Sep 04 12:56:42 PM UTC 24 |
| Peak memory | 230332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671061767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.671061767 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/17.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/17.kmac_lc_escalation.2178312542 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 853574395 ps |
| CPU time | 17.42 seconds |
| Started | Sep 04 12:56:56 PM UTC 24 |
| Finished | Sep 04 12:57:15 PM UTC 24 |
| Peak memory | 244860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178312542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.2178312542 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/17.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/17.kmac_long_msg_and_output.3097384875 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 97532942911 ps |
| CPU time | 1480.51 seconds |
| Started | Sep 04 12:56:03 PM UTC 24 |
| Finished | Sep 04 01:21:01 PM UTC 24 |
| Peak memory | 1949480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097384875 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_and_output.3097384875 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/17.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/17.kmac_sideload.4032017235 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 24057541493 ps |
| CPU time | 395.32 seconds |
| Started | Sep 04 12:56:11 PM UTC 24 |
| Finished | Sep 04 01:02:52 PM UTC 24 |
| Peak memory | 562276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032017235 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.4032017235 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/17.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/17.kmac_smoke.3018901931 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 495152933 ps |
| CPU time | 8.7 seconds |
| Started | Sep 04 12:56:01 PM UTC 24 |
| Finished | Sep 04 12:56:11 PM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018901931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.3018901931 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/17.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/17.kmac_stress_all.2659544462 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 130567377959 ps |
| CPU time | 805.25 seconds |
| Started | Sep 04 12:56:56 PM UTC 24 |
| Finished | Sep 04 01:10:31 PM UTC 24 |
| Peak memory | 858204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659544462 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.2659544462 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/17.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/18.kmac_alert_test.736092831 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 51472722 ps |
| CPU time | 1.19 seconds |
| Started | Sep 04 12:57:52 PM UTC 24 |
| Finished | Sep 04 12:57:54 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736092831 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.736092831 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/18.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/18.kmac_app.4259842022 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 11281544112 ps |
| CPU time | 103.87 seconds |
| Started | Sep 04 12:57:18 PM UTC 24 |
| Finished | Sep 04 12:59:04 PM UTC 24 |
| Peak memory | 329500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259842022 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.4259842022 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/18.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/18.kmac_burst_write.2826740912 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 23607138967 ps |
| CPU time | 889.08 seconds |
| Started | Sep 04 12:57:15 PM UTC 24 |
| Finished | Sep 04 01:12:16 PM UTC 24 |
| Peak memory | 264028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826740912 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.2826740912 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/18.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/18.kmac_edn_timeout_error.2939160302 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 319502135 ps |
| CPU time | 16.16 seconds |
| Started | Sep 04 12:57:41 PM UTC 24 |
| Finished | Sep 04 12:57:58 PM UTC 24 |
| Peak memory | 232708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939160302 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.2939160302 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/18.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/18.kmac_entropy_mode_error.1702886699 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 204024885 ps |
| CPU time | 4.18 seconds |
| Started | Sep 04 12:57:42 PM UTC 24 |
| Finished | Sep 04 12:57:47 PM UTC 24 |
| Peak memory | 228340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702886699 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.1702886699 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/18.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/18.kmac_entropy_refresh.1558783185 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 2812986396 ps |
| CPU time | 53.82 seconds |
| Started | Sep 04 12:57:20 PM UTC 24 |
| Finished | Sep 04 12:58:16 PM UTC 24 |
| Peak memory | 261868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558783185 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.1558783185 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/18.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/18.kmac_error.812624156 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 14218533288 ps |
| CPU time | 290.8 seconds |
| Started | Sep 04 12:57:36 PM UTC 24 |
| Finished | Sep 04 01:02:32 PM UTC 24 |
| Peak memory | 345848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812624156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.812624156 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/18.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/18.kmac_key_error.352589488 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 2081278973 ps |
| CPU time | 11.22 seconds |
| Started | Sep 04 12:57:38 PM UTC 24 |
| Finished | Sep 04 12:57:50 PM UTC 24 |
| Peak memory | 230380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352589488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.352589488 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/18.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/18.kmac_lc_escalation.3333032861 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 58331052 ps |
| CPU time | 2.11 seconds |
| Started | Sep 04 12:57:48 PM UTC 24 |
| Finished | Sep 04 12:57:51 PM UTC 24 |
| Peak memory | 235148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333032861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.3333032861 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/18.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/18.kmac_long_msg_and_output.2111291372 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 110381997706 ps |
| CPU time | 2774.76 seconds |
| Started | Sep 04 12:57:10 PM UTC 24 |
| Finished | Sep 04 01:43:57 PM UTC 24 |
| Peak memory | 1873896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111291372 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_and_output.2111291372 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/18.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/18.kmac_sideload.1365009179 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 2674273209 ps |
| CPU time | 76.7 seconds |
| Started | Sep 04 12:57:10 PM UTC 24 |
| Finished | Sep 04 12:58:29 PM UTC 24 |
| Peak memory | 282412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365009179 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.1365009179 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/18.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/18.kmac_smoke.1370666956 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 622849737 ps |
| CPU time | 27.88 seconds |
| Started | Sep 04 12:57:08 PM UTC 24 |
| Finished | Sep 04 12:57:37 PM UTC 24 |
| Peak memory | 234612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370666956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.1370666956 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/18.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/18.kmac_stress_all.1260370357 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 10414922131 ps |
| CPU time | 1053.47 seconds |
| Started | Sep 04 12:57:51 PM UTC 24 |
| Finished | Sep 04 01:15:38 PM UTC 24 |
| Peak memory | 545072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260370357 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.1260370357 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/18.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/19.kmac_alert_test.1350055327 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 23589495 ps |
| CPU time | 1.22 seconds |
| Started | Sep 04 12:58:29 PM UTC 24 |
| Finished | Sep 04 12:58:31 PM UTC 24 |
| Peak memory | 216232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350055327 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.1350055327 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/19.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/19.kmac_app.2911611520 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 294624553 ps |
| CPU time | 19.23 seconds |
| Started | Sep 04 12:57:58 PM UTC 24 |
| Finished | Sep 04 12:58:19 PM UTC 24 |
| Peak memory | 232580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911611520 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.2911611520 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/19.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/19.kmac_burst_write.3464748243 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 9476586610 ps |
| CPU time | 380.73 seconds |
| Started | Sep 04 12:57:57 PM UTC 24 |
| Finished | Sep 04 01:04:23 PM UTC 24 |
| Peak memory | 243472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464748243 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.3464748243 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/19.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/19.kmac_edn_timeout_error.1690536427 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 1686870128 ps |
| CPU time | 12.04 seconds |
| Started | Sep 04 12:58:20 PM UTC 24 |
| Finished | Sep 04 12:58:33 PM UTC 24 |
| Peak memory | 228216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690536427 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.1690536427 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/19.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/19.kmac_entropy_mode_error.2646983706 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 251338581 ps |
| CPU time | 5.14 seconds |
| Started | Sep 04 12:58:22 PM UTC 24 |
| Finished | Sep 04 12:58:28 PM UTC 24 |
| Peak memory | 230340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646983706 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.2646983706 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/19.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/19.kmac_entropy_refresh.4241266640 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 11678876056 ps |
| CPU time | 254.67 seconds |
| Started | Sep 04 12:58:01 PM UTC 24 |
| Finished | Sep 04 01:02:20 PM UTC 24 |
| Peak memory | 374552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241266640 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.4241266640 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/19.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/19.kmac_error.3770853838 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 5908848388 ps |
| CPU time | 205.63 seconds |
| Started | Sep 04 12:58:12 PM UTC 24 |
| Finished | Sep 04 01:01:41 PM UTC 24 |
| Peak memory | 415528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770853838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.3770853838 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/19.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/19.kmac_key_error.3536821262 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 8488649970 ps |
| CPU time | 6.88 seconds |
| Started | Sep 04 12:58:17 PM UTC 24 |
| Finished | Sep 04 12:58:25 PM UTC 24 |
| Peak memory | 230588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536821262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.3536821262 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/19.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/19.kmac_lc_escalation.3681418812 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 1573913666 ps |
| CPU time | 21.09 seconds |
| Started | Sep 04 12:58:26 PM UTC 24 |
| Finished | Sep 04 12:58:49 PM UTC 24 |
| Peak memory | 247468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681418812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.3681418812 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/19.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/19.kmac_long_msg_and_output.19209968 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 106945724981 ps |
| CPU time | 2553.05 seconds |
| Started | Sep 04 12:57:55 PM UTC 24 |
| Finished | Sep 04 01:40:56 PM UTC 24 |
| Peak memory | 1855416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19209968 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_and_output.19209968 +enable_maskin g=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/19.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/19.kmac_sideload.3691149081 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 2915340744 ps |
| CPU time | 273.34 seconds |
| Started | Sep 04 12:57:56 PM UTC 24 |
| Finished | Sep 04 01:02:34 PM UTC 24 |
| Peak memory | 327448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691149081 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.3691149081 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/19.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/19.kmac_smoke.2109895877 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 286776749 ps |
| CPU time | 17.5 seconds |
| Started | Sep 04 12:57:52 PM UTC 24 |
| Finished | Sep 04 12:58:11 PM UTC 24 |
| Peak memory | 230672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109895877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.2109895877 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/19.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/19.kmac_stress_all.402642902 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 11828449778 ps |
| CPU time | 457.9 seconds |
| Started | Sep 04 12:58:29 PM UTC 24 |
| Finished | Sep 04 01:06:13 PM UTC 24 |
| Peak memory | 530240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402642902 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.402642902 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/19.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/2.kmac_alert_test.1420409463 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 50820053 ps |
| CPU time | 1.21 seconds |
| Started | Sep 04 12:43:04 PM UTC 24 |
| Finished | Sep 04 12:43:06 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420409463 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.1420409463 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/2.kmac_app.1332790158 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 26141777325 ps |
| CPU time | 115.3 seconds |
| Started | Sep 04 12:42:41 PM UTC 24 |
| Finished | Sep 04 12:44:39 PM UTC 24 |
| Peak memory | 280368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332790158 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.1332790158 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/2.kmac_app_with_partial_data.4106184191 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 25090491062 ps |
| CPU time | 196.5 seconds |
| Started | Sep 04 12:42:43 PM UTC 24 |
| Finished | Sep 04 12:46:04 PM UTC 24 |
| Peak memory | 378860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106184191 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.4106184191 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/2.kmac_burst_write.3132294838 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 15229493028 ps |
| CPU time | 532.27 seconds |
| Started | Sep 04 12:42:17 PM UTC 24 |
| Finished | Sep 04 12:51:17 PM UTC 24 |
| Peak memory | 249848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132294838 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.3132294838 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/2.kmac_edn_timeout_error.1144090458 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 964780497 ps |
| CPU time | 19.2 seconds |
| Started | Sep 04 12:42:55 PM UTC 24 |
| Finished | Sep 04 12:43:15 PM UTC 24 |
| Peak memory | 235276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144090458 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.1144090458 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_mode_error.4216633549 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 3736256096 ps |
| CPU time | 34.64 seconds |
| Started | Sep 04 12:42:55 PM UTC 24 |
| Finished | Sep 04 12:43:31 PM UTC 24 |
| Peak memory | 232572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216633549 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.4216633549 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/2.kmac_error.3203571711 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 4864286816 ps |
| CPU time | 37.48 seconds |
| Started | Sep 04 12:42:48 PM UTC 24 |
| Finished | Sep 04 12:43:27 PM UTC 24 |
| Peak memory | 268080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203571711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.3203571711 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/2.kmac_key_error.2477935893 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 1958914715 ps |
| CPU time | 5.52 seconds |
| Started | Sep 04 12:42:48 PM UTC 24 |
| Finished | Sep 04 12:42:54 PM UTC 24 |
| Peak memory | 230384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477935893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.2477935893 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/2.kmac_lc_escalation.107743755 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 470048183 ps |
| CPU time | 15.69 seconds |
| Started | Sep 04 12:42:57 PM UTC 24 |
| Finished | Sep 04 12:43:14 PM UTC 24 |
| Peak memory | 234824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107743755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.107743755 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/2.kmac_long_msg_and_output.921928868 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 29510756940 ps |
| CPU time | 798.55 seconds |
| Started | Sep 04 12:42:15 PM UTC 24 |
| Finished | Sep 04 12:55:44 PM UTC 24 |
| Peak memory | 1355536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921928868 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and_output.921928868 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/2.kmac_mubi.971178215 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 13038913796 ps |
| CPU time | 118.59 seconds |
| Started | Sep 04 12:42:48 PM UTC 24 |
| Finished | Sep 04 12:44:49 PM UTC 24 |
| Peak memory | 340208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971178215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.971178215 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/2.kmac_sec_cm.3637237750 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4628304607 ps |
| CPU time | 67.08 seconds |
| Started | Sep 04 12:43:03 PM UTC 24 |
| Finished | Sep 04 12:44:12 PM UTC 24 |
| Peak memory | 289784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637237750 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.3637237750 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/2.kmac_sideload.1789644082 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 2910505380 ps |
| CPU time | 107.25 seconds |
| Started | Sep 04 12:42:15 PM UTC 24 |
| Finished | Sep 04 12:44:05 PM UTC 24 |
| Peak memory | 276224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789644082 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.1789644082 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/2.kmac_smoke.3044743459 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 4737243646 ps |
| CPU time | 46.72 seconds |
| Started | Sep 04 12:42:15 PM UTC 24 |
| Finished | Sep 04 12:43:03 PM UTC 24 |
| Peak memory | 230524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044743459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.3044743459 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/2.kmac_stress_all.3755068994 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 12432800009 ps |
| CPU time | 179.06 seconds |
| Started | Sep 04 12:43:00 PM UTC 24 |
| Finished | Sep 04 12:46:02 PM UTC 24 |
| Peak memory | 388896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755068994 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.3755068994 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac.3577934494 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 73551518 ps |
| CPU time | 2.68 seconds |
| Started | Sep 04 12:42:39 PM UTC 24 |
| Finished | Sep 04 12:42:43 PM UTC 24 |
| Peak memory | 230532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577934494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac.3577934494 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac_xof.1193713364 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 35559337 ps |
| CPU time | 2.53 seconds |
| Started | Sep 04 12:42:41 PM UTC 24 |
| Finished | Sep 04 12:42:45 PM UTC 24 |
| Peak memory | 230544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193713364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.1193713364 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_224.4055222676 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 9363090209 ps |
| CPU time | 58.01 seconds |
| Started | Sep 04 12:42:19 PM UTC 24 |
| Finished | Sep 04 12:43:19 PM UTC 24 |
| Peak memory | 257800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055222676 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.4055222676 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_256.2126047447 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 9458932170 ps |
| CPU time | 41.99 seconds |
| Started | Sep 04 12:42:19 PM UTC 24 |
| Finished | Sep 04 12:43:03 PM UTC 24 |
| Peak memory | 232492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126047447 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.2126047447 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_384.3064099679 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 1676041739 ps |
| CPU time | 33.5 seconds |
| Started | Sep 04 12:42:19 PM UTC 24 |
| Finished | Sep 04 12:42:54 PM UTC 24 |
| Peak memory | 239248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064099679 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.3064099679 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_512.394055220 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 4397024600 ps |
| CPU time | 24.22 seconds |
| Started | Sep 04 12:42:21 PM UTC 24 |
| Finished | Sep 04 12:42:47 PM UTC 24 |
| Peak memory | 230580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394055220 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.394055220 + enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_128.3672143146 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 38993359719 ps |
| CPU time | 228.33 seconds |
| Started | Sep 04 12:42:25 PM UTC 24 |
| Finished | Sep 04 12:46:17 PM UTC 24 |
| Peak memory | 439952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672143146 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.3672143 146 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_256.4141983328 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 17235469646 ps |
| CPU time | 1559.39 seconds |
| Started | Sep 04 12:42:33 PM UTC 24 |
| Finished | Sep 04 01:08:52 PM UTC 24 |
| Peak memory | 1154712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141983328 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.4141983 328 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/20.kmac_alert_test.2758470130 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 25729192 ps |
| CPU time | 1.19 seconds |
| Started | Sep 04 12:59:36 PM UTC 24 |
| Finished | Sep 04 12:59:38 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758470130 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.2758470130 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/20.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/20.kmac_app.3382888863 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 17072203173 ps |
| CPU time | 334.71 seconds |
| Started | Sep 04 12:58:44 PM UTC 24 |
| Finished | Sep 04 01:04:24 PM UTC 24 |
| Peak memory | 517916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382888863 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.3382888863 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/20.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/20.kmac_burst_write.3025469830 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 80606848907 ps |
| CPU time | 462.73 seconds |
| Started | Sep 04 12:58:43 PM UTC 24 |
| Finished | Sep 04 01:06:32 PM UTC 24 |
| Peak memory | 253676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025469830 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.3025469830 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/20.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/20.kmac_entropy_refresh.1430205660 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 12523965337 ps |
| CPU time | 164.9 seconds |
| Started | Sep 04 12:58:50 PM UTC 24 |
| Finished | Sep 04 01:01:37 PM UTC 24 |
| Peak memory | 368628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430205660 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.1430205660 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/20.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/20.kmac_error.1858980852 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 57171015272 ps |
| CPU time | 333.81 seconds |
| Started | Sep 04 12:59:05 PM UTC 24 |
| Finished | Sep 04 01:04:43 PM UTC 24 |
| Peak memory | 470892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858980852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.1858980852 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/20.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/20.kmac_key_error.3509001094 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 1267040261 ps |
| CPU time | 6.52 seconds |
| Started | Sep 04 12:59:06 PM UTC 24 |
| Finished | Sep 04 12:59:13 PM UTC 24 |
| Peak memory | 230656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509001094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.3509001094 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/20.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/20.kmac_lc_escalation.3331036351 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 754342447 ps |
| CPU time | 22.12 seconds |
| Started | Sep 04 12:59:14 PM UTC 24 |
| Finished | Sep 04 12:59:37 PM UTC 24 |
| Peak memory | 245452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331036351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.3331036351 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/20.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/20.kmac_long_msg_and_output.102546406 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 160370567392 ps |
| CPU time | 2350.55 seconds |
| Started | Sep 04 12:58:32 PM UTC 24 |
| Finished | Sep 04 01:38:07 PM UTC 24 |
| Peak memory | 3346232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102546406 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_and_output.102546406 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/20.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/20.kmac_sideload.3400957726 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 59152108669 ps |
| CPU time | 418.66 seconds |
| Started | Sep 04 12:58:34 PM UTC 24 |
| Finished | Sep 04 01:05:39 PM UTC 24 |
| Peak memory | 573232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400957726 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.3400957726 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/20.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/20.kmac_smoke.4080329380 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 583843360 ps |
| CPU time | 33.22 seconds |
| Started | Sep 04 12:58:30 PM UTC 24 |
| Finished | Sep 04 12:59:05 PM UTC 24 |
| Peak memory | 230540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080329380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.4080329380 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/20.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/20.kmac_stress_all.1009624796 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 51516360277 ps |
| CPU time | 871.75 seconds |
| Started | Sep 04 12:59:27 PM UTC 24 |
| Finished | Sep 04 01:14:09 PM UTC 24 |
| Peak memory | 712740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009624796 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.1009624796 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/20.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/21.kmac_alert_test.252070788 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 99178009 ps |
| CPU time | 1.27 seconds |
| Started | Sep 04 01:00:40 PM UTC 24 |
| Finished | Sep 04 01:00:43 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252070788 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.252070788 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/21.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/21.kmac_app.3790993308 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 1741960326 ps |
| CPU time | 13.39 seconds |
| Started | Sep 04 01:00:08 PM UTC 24 |
| Finished | Sep 04 01:00:23 PM UTC 24 |
| Peak memory | 245492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790993308 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.3790993308 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/21.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/21.kmac_burst_write.243050452 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 5266060757 ps |
| CPU time | 23.71 seconds |
| Started | Sep 04 01:00:06 PM UTC 24 |
| Finished | Sep 04 01:00:32 PM UTC 24 |
| Peak memory | 235268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243050452 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.243050452 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/21.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/21.kmac_entropy_refresh.2863538288 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 22021372730 ps |
| CPU time | 242.37 seconds |
| Started | Sep 04 01:00:15 PM UTC 24 |
| Finished | Sep 04 01:04:21 PM UTC 24 |
| Peak memory | 442092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863538288 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.2863538288 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/21.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/21.kmac_error.2659775597 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 2189737170 ps |
| CPU time | 67.76 seconds |
| Started | Sep 04 01:00:24 PM UTC 24 |
| Finished | Sep 04 01:01:33 PM UTC 24 |
| Peak memory | 284668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659775597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.2659775597 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/21.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/21.kmac_key_error.1811076431 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 4183433555 ps |
| CPU time | 10.51 seconds |
| Started | Sep 04 01:00:27 PM UTC 24 |
| Finished | Sep 04 01:00:39 PM UTC 24 |
| Peak memory | 230396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811076431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.1811076431 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/21.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/21.kmac_lc_escalation.372754807 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 971805900 ps |
| CPU time | 33.62 seconds |
| Started | Sep 04 01:00:33 PM UTC 24 |
| Finished | Sep 04 01:01:08 PM UTC 24 |
| Peak memory | 247464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372754807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.372754807 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/21.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/21.kmac_long_msg_and_output.240157167 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 7089822441 ps |
| CPU time | 574.2 seconds |
| Started | Sep 04 12:59:38 PM UTC 24 |
| Finished | Sep 04 01:09:19 PM UTC 24 |
| Peak memory | 675816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240157167 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_and_output.240157167 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/21.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/21.kmac_sideload.2503247553 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 1660752858 ps |
| CPU time | 22.14 seconds |
| Started | Sep 04 12:59:39 PM UTC 24 |
| Finished | Sep 04 01:00:03 PM UTC 24 |
| Peak memory | 232588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503247553 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.2503247553 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/21.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/21.kmac_smoke.3681361664 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 1242667963 ps |
| CPU time | 29.15 seconds |
| Started | Sep 04 12:59:37 PM UTC 24 |
| Finished | Sep 04 01:00:08 PM UTC 24 |
| Peak memory | 234564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681361664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.3681361664 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/21.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/21.kmac_stress_all.2058114471 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 126951452556 ps |
| CPU time | 1956.07 seconds |
| Started | Sep 04 01:00:35 PM UTC 24 |
| Finished | Sep 04 01:33:34 PM UTC 24 |
| Peak memory | 1163252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058114471 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.2058114471 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/21.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/22.kmac_alert_test.828014747 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 19794461 ps |
| CPU time | 1.22 seconds |
| Started | Sep 04 01:01:07 PM UTC 24 |
| Finished | Sep 04 01:01:09 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828014747 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.828014747 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/22.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/22.kmac_app.4173615935 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 93259358502 ps |
| CPU time | 297.72 seconds |
| Started | Sep 04 01:00:55 PM UTC 24 |
| Finished | Sep 04 01:05:57 PM UTC 24 |
| Peak memory | 516012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173615935 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.4173615935 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/22.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/22.kmac_burst_write.914089742 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 857802476 ps |
| CPU time | 80.28 seconds |
| Started | Sep 04 01:00:49 PM UTC 24 |
| Finished | Sep 04 01:02:12 PM UTC 24 |
| Peak memory | 251572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914089742 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.914089742 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/22.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/22.kmac_entropy_refresh.3617144445 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 38268910207 ps |
| CPU time | 164.19 seconds |
| Started | Sep 04 01:00:56 PM UTC 24 |
| Finished | Sep 04 01:03:43 PM UTC 24 |
| Peak memory | 356344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617144445 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.3617144445 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/22.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/22.kmac_error.598798229 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 6698637443 ps |
| CPU time | 287.46 seconds |
| Started | Sep 04 01:00:57 PM UTC 24 |
| Finished | Sep 04 01:05:48 PM UTC 24 |
| Peak memory | 354088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598798229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.598798229 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/22.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/22.kmac_key_error.1791029019 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 819570782 ps |
| CPU time | 8.13 seconds |
| Started | Sep 04 01:01:00 PM UTC 24 |
| Finished | Sep 04 01:01:09 PM UTC 24 |
| Peak memory | 230460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791029019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.1791029019 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/22.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/22.kmac_lc_escalation.1714339663 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 408198225 ps |
| CPU time | 1.99 seconds |
| Started | Sep 04 01:01:03 PM UTC 24 |
| Finished | Sep 04 01:01:06 PM UTC 24 |
| Peak memory | 229804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714339663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.1714339663 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/22.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/22.kmac_long_msg_and_output.3774103852 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 356499043283 ps |
| CPU time | 3562.26 seconds |
| Started | Sep 04 01:00:41 PM UTC 24 |
| Finished | Sep 04 02:00:41 PM UTC 24 |
| Peak memory | 4163372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774103852 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_and_output.3774103852 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/22.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/22.kmac_sideload.2362319725 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 4448963816 ps |
| CPU time | 297.69 seconds |
| Started | Sep 04 01:00:43 PM UTC 24 |
| Finished | Sep 04 01:05:45 PM UTC 24 |
| Peak memory | 376884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362319725 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.2362319725 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/22.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/22.kmac_smoke.1488935904 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 413179319 ps |
| CPU time | 12.07 seconds |
| Started | Sep 04 01:00:41 PM UTC 24 |
| Finished | Sep 04 01:00:55 PM UTC 24 |
| Peak memory | 230732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488935904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.1488935904 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/22.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/22.kmac_stress_all.3741050724 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 278549456693 ps |
| CPU time | 1791.69 seconds |
| Started | Sep 04 01:01:07 PM UTC 24 |
| Finished | Sep 04 01:31:19 PM UTC 24 |
| Peak memory | 1022008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741050724 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.3741050724 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/22.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/23.kmac_alert_test.2748197203 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 27267705 ps |
| CPU time | 1.17 seconds |
| Started | Sep 04 01:01:53 PM UTC 24 |
| Finished | Sep 04 01:01:55 PM UTC 24 |
| Peak memory | 216232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748197203 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.2748197203 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/23.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/23.kmac_app.3699199366 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 12698179391 ps |
| CPU time | 278.62 seconds |
| Started | Sep 04 01:01:34 PM UTC 24 |
| Finished | Sep 04 01:06:17 PM UTC 24 |
| Peak memory | 452596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699199366 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.3699199366 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/23.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/23.kmac_burst_write.177520794 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 269199174 ps |
| CPU time | 14.29 seconds |
| Started | Sep 04 01:01:22 PM UTC 24 |
| Finished | Sep 04 01:01:38 PM UTC 24 |
| Peak memory | 230524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177520794 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.177520794 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/23.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/23.kmac_entropy_refresh.551451071 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 5544001370 ps |
| CPU time | 158.33 seconds |
| Started | Sep 04 01:01:39 PM UTC 24 |
| Finished | Sep 04 01:04:20 PM UTC 24 |
| Peak memory | 319280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551451071 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.551451071 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/23.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/23.kmac_error.2621061348 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 15866582931 ps |
| CPU time | 223.91 seconds |
| Started | Sep 04 01:01:39 PM UTC 24 |
| Finished | Sep 04 01:05:26 PM UTC 24 |
| Peak memory | 417908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621061348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.2621061348 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/23.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/23.kmac_key_error.1146673013 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 755730013 ps |
| CPU time | 7.62 seconds |
| Started | Sep 04 01:01:39 PM UTC 24 |
| Finished | Sep 04 01:01:48 PM UTC 24 |
| Peak memory | 230388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146673013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.1146673013 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/23.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/23.kmac_lc_escalation.1636199776 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 529570867 ps |
| CPU time | 8.91 seconds |
| Started | Sep 04 01:01:42 PM UTC 24 |
| Finished | Sep 04 01:01:52 PM UTC 24 |
| Peak memory | 235428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636199776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.1636199776 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/23.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/23.kmac_long_msg_and_output.3630196231 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 81843704731 ps |
| CPU time | 3570.67 seconds |
| Started | Sep 04 01:01:10 PM UTC 24 |
| Finished | Sep 04 02:01:19 PM UTC 24 |
| Peak memory | 3931948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630196231 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_and_output.3630196231 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/23.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/23.kmac_sideload.3551642634 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 931046652 ps |
| CPU time | 10.02 seconds |
| Started | Sep 04 01:01:10 PM UTC 24 |
| Finished | Sep 04 01:01:21 PM UTC 24 |
| Peak memory | 235516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551642634 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.3551642634 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/23.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/23.kmac_smoke.2656846298 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 804019989 ps |
| CPU time | 27 seconds |
| Started | Sep 04 01:01:09 PM UTC 24 |
| Finished | Sep 04 01:01:37 PM UTC 24 |
| Peak memory | 232500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656846298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.2656846298 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/23.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/23.kmac_stress_all.2339546060 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 43060879529 ps |
| CPU time | 1004.58 seconds |
| Started | Sep 04 01:01:49 PM UTC 24 |
| Finished | Sep 04 01:18:45 PM UTC 24 |
| Peak memory | 1257204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339546060 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.2339546060 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/23.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/24.kmac_alert_test.722808776 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 22409152 ps |
| CPU time | 1.19 seconds |
| Started | Sep 04 01:02:51 PM UTC 24 |
| Finished | Sep 04 01:02:53 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722808776 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.722808776 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/24.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/24.kmac_app.275460883 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 64875778 ps |
| CPU time | 2.98 seconds |
| Started | Sep 04 01:02:21 PM UTC 24 |
| Finished | Sep 04 01:02:25 PM UTC 24 |
| Peak memory | 230536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275460883 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.275460883 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/24.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/24.kmac_burst_write.374074349 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 18895320723 ps |
| CPU time | 352.68 seconds |
| Started | Sep 04 01:02:12 PM UTC 24 |
| Finished | Sep 04 01:08:10 PM UTC 24 |
| Peak memory | 249644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374074349 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.374074349 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/24.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/24.kmac_entropy_refresh.4021758684 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 25063249666 ps |
| CPU time | 354.11 seconds |
| Started | Sep 04 01:02:26 PM UTC 24 |
| Finished | Sep 04 01:08:26 PM UTC 24 |
| Peak memory | 454704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021758684 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.4021758684 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/24.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/24.kmac_error.2774974255 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 37331285896 ps |
| CPU time | 278.05 seconds |
| Started | Sep 04 01:02:32 PM UTC 24 |
| Finished | Sep 04 01:07:15 PM UTC 24 |
| Peak memory | 452332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774974255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.2774974255 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/24.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/24.kmac_key_error.3050140028 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 1479206299 ps |
| CPU time | 12.46 seconds |
| Started | Sep 04 01:02:35 PM UTC 24 |
| Finished | Sep 04 01:02:48 PM UTC 24 |
| Peak memory | 230328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050140028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.3050140028 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/24.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/24.kmac_lc_escalation.954220432 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 145144401 ps |
| CPU time | 2.27 seconds |
| Started | Sep 04 01:02:47 PM UTC 24 |
| Finished | Sep 04 01:02:50 PM UTC 24 |
| Peak memory | 230376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954220432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.954220432 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/24.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/24.kmac_long_msg_and_output.1419043417 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 185855119197 ps |
| CPU time | 2804.11 seconds |
| Started | Sep 04 01:01:56 PM UTC 24 |
| Finished | Sep 04 01:49:12 PM UTC 24 |
| Peak memory | 1744632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419043417 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_and_output.1419043417 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/24.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/24.kmac_sideload.2700847416 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 2100029019 ps |
| CPU time | 161.74 seconds |
| Started | Sep 04 01:02:07 PM UTC 24 |
| Finished | Sep 04 01:04:52 PM UTC 24 |
| Peak memory | 300848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700847416 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.2700847416 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/24.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/24.kmac_smoke.3926233454 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 5050273609 ps |
| CPU time | 69.7 seconds |
| Started | Sep 04 01:01:55 PM UTC 24 |
| Finished | Sep 04 01:03:07 PM UTC 24 |
| Peak memory | 232580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926233454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.3926233454 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/24.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/24.kmac_stress_all.874769779 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 15199839377 ps |
| CPU time | 85.52 seconds |
| Started | Sep 04 01:02:49 PM UTC 24 |
| Finished | Sep 04 01:04:16 PM UTC 24 |
| Peak memory | 268016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874769779 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.874769779 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/24.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/25.kmac_alert_test.519904636 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 12670229 ps |
| CPU time | 1.17 seconds |
| Started | Sep 04 01:04:14 PM UTC 24 |
| Finished | Sep 04 01:04:16 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519904636 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.519904636 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/25.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/25.kmac_app.1636335577 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 15158168655 ps |
| CPU time | 351.63 seconds |
| Started | Sep 04 01:03:25 PM UTC 24 |
| Finished | Sep 04 01:09:22 PM UTC 24 |
| Peak memory | 460836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636335577 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.1636335577 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/25.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/25.kmac_burst_write.3847856602 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 87134333964 ps |
| CPU time | 828.7 seconds |
| Started | Sep 04 01:03:07 PM UTC 24 |
| Finished | Sep 04 01:17:06 PM UTC 24 |
| Peak memory | 263928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847856602 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.3847856602 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/25.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/25.kmac_entropy_refresh.4057686806 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 14331651876 ps |
| CPU time | 260 seconds |
| Started | Sep 04 01:03:29 PM UTC 24 |
| Finished | Sep 04 01:07:53 PM UTC 24 |
| Peak memory | 421620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057686806 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.4057686806 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/25.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/25.kmac_error.2677933253 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 10726315372 ps |
| CPU time | 316.14 seconds |
| Started | Sep 04 01:03:42 PM UTC 24 |
| Finished | Sep 04 01:09:02 PM UTC 24 |
| Peak memory | 530156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677933253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.2677933253 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/25.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/25.kmac_key_error.419783635 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 6933703620 ps |
| CPU time | 15.93 seconds |
| Started | Sep 04 01:03:44 PM UTC 24 |
| Finished | Sep 04 01:04:01 PM UTC 24 |
| Peak memory | 232764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419783635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.419783635 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/25.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/25.kmac_lc_escalation.2479117074 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 57374769 ps |
| CPU time | 1.98 seconds |
| Started | Sep 04 01:04:02 PM UTC 24 |
| Finished | Sep 04 01:04:05 PM UTC 24 |
| Peak memory | 231712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479117074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.2479117074 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/25.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/25.kmac_long_msg_and_output.3272281102 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 36368599118 ps |
| CPU time | 1784 seconds |
| Started | Sep 04 01:02:54 PM UTC 24 |
| Finished | Sep 04 01:32:58 PM UTC 24 |
| Peak memory | 1325028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272281102 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_and_output.3272281102 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/25.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/25.kmac_sideload.3548120853 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 45380698201 ps |
| CPU time | 275.93 seconds |
| Started | Sep 04 01:03:01 PM UTC 24 |
| Finished | Sep 04 01:07:41 PM UTC 24 |
| Peak memory | 448304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548120853 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.3548120853 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/25.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/25.kmac_smoke.790954567 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 216165441 ps |
| CPU time | 14.56 seconds |
| Started | Sep 04 01:02:53 PM UTC 24 |
| Finished | Sep 04 01:03:09 PM UTC 24 |
| Peak memory | 230740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790954567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.790954567 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/25.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/25.kmac_stress_all.2213687180 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 48297141396 ps |
| CPU time | 1129.96 seconds |
| Started | Sep 04 01:04:06 PM UTC 24 |
| Finished | Sep 04 01:23:09 PM UTC 24 |
| Peak memory | 911408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213687180 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.2213687180 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/25.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/26.kmac_alert_test.4212520518 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 17629998 ps |
| CPU time | 1.26 seconds |
| Started | Sep 04 01:05:04 PM UTC 24 |
| Finished | Sep 04 01:05:06 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212520518 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.4212520518 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/26.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/26.kmac_app.473940597 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 31818017192 ps |
| CPU time | 120.51 seconds |
| Started | Sep 04 01:04:23 PM UTC 24 |
| Finished | Sep 04 01:06:26 PM UTC 24 |
| Peak memory | 333612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473940597 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.473940597 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/26.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/26.kmac_burst_write.1924699065 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 17895167576 ps |
| CPU time | 238.71 seconds |
| Started | Sep 04 01:04:21 PM UTC 24 |
| Finished | Sep 04 01:08:24 PM UTC 24 |
| Peak memory | 237332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924699065 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.1924699065 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/26.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/26.kmac_entropy_refresh.3330398232 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 19821476955 ps |
| CPU time | 251.8 seconds |
| Started | Sep 04 01:04:24 PM UTC 24 |
| Finished | Sep 04 01:08:40 PM UTC 24 |
| Peak memory | 435948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330398232 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.3330398232 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/26.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/26.kmac_error.1681979814 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 8080794121 ps |
| CPU time | 194.78 seconds |
| Started | Sep 04 01:04:45 PM UTC 24 |
| Finished | Sep 04 01:08:03 PM UTC 24 |
| Peak memory | 419576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681979814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.1681979814 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/26.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/26.kmac_key_error.3686448602 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 1088424048 ps |
| CPU time | 10.07 seconds |
| Started | Sep 04 01:04:53 PM UTC 24 |
| Finished | Sep 04 01:05:04 PM UTC 24 |
| Peak memory | 230328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686448602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.3686448602 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/26.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/26.kmac_lc_escalation.414167820 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 97055137 ps |
| CPU time | 1.88 seconds |
| Started | Sep 04 01:05:00 PM UTC 24 |
| Finished | Sep 04 01:05:03 PM UTC 24 |
| Peak memory | 229812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414167820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.414167820 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/26.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/26.kmac_long_msg_and_output.3620015481 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 57781229108 ps |
| CPU time | 2221.12 seconds |
| Started | Sep 04 01:04:17 PM UTC 24 |
| Finished | Sep 04 01:41:43 PM UTC 24 |
| Peak memory | 2852636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620015481 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_and_output.3620015481 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/26.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/26.kmac_sideload.3845406540 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 11814048677 ps |
| CPU time | 336.24 seconds |
| Started | Sep 04 01:04:21 PM UTC 24 |
| Finished | Sep 04 01:10:02 PM UTC 24 |
| Peak memory | 569392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845406540 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.3845406540 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/26.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/26.kmac_smoke.2152874068 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 1817198700 ps |
| CPU time | 40.25 seconds |
| Started | Sep 04 01:04:17 PM UTC 24 |
| Finished | Sep 04 01:04:59 PM UTC 24 |
| Peak memory | 230512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152874068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.2152874068 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/26.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/26.kmac_stress_all.3997200042 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 11198575712 ps |
| CPU time | 875.87 seconds |
| Started | Sep 04 01:05:00 PM UTC 24 |
| Finished | Sep 04 01:19:46 PM UTC 24 |
| Peak memory | 589876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997200042 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.3997200042 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/26.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/27.kmac_alert_test.4079549312 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 16753234 ps |
| CPU time | 1.09 seconds |
| Started | Sep 04 01:05:59 PM UTC 24 |
| Finished | Sep 04 01:06:01 PM UTC 24 |
| Peak memory | 216232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079549312 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.4079549312 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/27.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/27.kmac_app.670593407 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 1746653739 ps |
| CPU time | 87.26 seconds |
| Started | Sep 04 01:05:34 PM UTC 24 |
| Finished | Sep 04 01:07:04 PM UTC 24 |
| Peak memory | 259756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670593407 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.670593407 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/27.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/27.kmac_burst_write.3220949004 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 29939066008 ps |
| CPU time | 668.9 seconds |
| Started | Sep 04 01:05:27 PM UTC 24 |
| Finished | Sep 04 01:16:45 PM UTC 24 |
| Peak memory | 251612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220949004 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.3220949004 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/27.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/27.kmac_entropy_refresh.4249932394 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 10086038853 ps |
| CPU time | 237.79 seconds |
| Started | Sep 04 01:05:40 PM UTC 24 |
| Finished | Sep 04 01:09:41 PM UTC 24 |
| Peak memory | 448220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249932394 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.4249932394 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/27.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/27.kmac_error.282548004 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 62284298498 ps |
| CPU time | 439.84 seconds |
| Started | Sep 04 01:05:46 PM UTC 24 |
| Finished | Sep 04 01:13:11 PM UTC 24 |
| Peak memory | 581396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282548004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.282548004 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/27.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/27.kmac_key_error.4272367492 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 448152441 ps |
| CPU time | 5 seconds |
| Started | Sep 04 01:05:49 PM UTC 24 |
| Finished | Sep 04 01:05:55 PM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272367492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.4272367492 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/27.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/27.kmac_lc_escalation.2097458651 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 97467542 ps |
| CPU time | 1.87 seconds |
| Started | Sep 04 01:05:56 PM UTC 24 |
| Finished | Sep 04 01:05:59 PM UTC 24 |
| Peak memory | 229684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097458651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.2097458651 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/27.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/27.kmac_long_msg_and_output.1881798858 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 10813314994 ps |
| CPU time | 472.37 seconds |
| Started | Sep 04 01:05:07 PM UTC 24 |
| Finished | Sep 04 01:13:05 PM UTC 24 |
| Peak memory | 565032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881798858 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_and_output.1881798858 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/27.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/27.kmac_sideload.1561488154 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 2410668329 ps |
| CPU time | 93.58 seconds |
| Started | Sep 04 01:05:08 PM UTC 24 |
| Finished | Sep 04 01:06:44 PM UTC 24 |
| Peak memory | 276396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561488154 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.1561488154 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/27.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/27.kmac_smoke.986105715 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 414846487 ps |
| CPU time | 1.81 seconds |
| Started | Sep 04 01:05:05 PM UTC 24 |
| Finished | Sep 04 01:05:08 PM UTC 24 |
| Peak memory | 229732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986105715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.986105715 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/27.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/27.kmac_stress_all.586725239 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 22868099844 ps |
| CPU time | 155.18 seconds |
| Started | Sep 04 01:05:58 PM UTC 24 |
| Finished | Sep 04 01:08:36 PM UTC 24 |
| Peak memory | 313400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586725239 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.586725239 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/27.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/28.kmac_alert_test.3675590558 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 13590501 ps |
| CPU time | 1.18 seconds |
| Started | Sep 04 01:07:16 PM UTC 24 |
| Finished | Sep 04 01:07:18 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675590558 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.3675590558 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/28.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/28.kmac_app.2415648032 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 26304674533 ps |
| CPU time | 114.43 seconds |
| Started | Sep 04 01:06:27 PM UTC 24 |
| Finished | Sep 04 01:08:24 PM UTC 24 |
| Peak memory | 296684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415648032 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.2415648032 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/28.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/28.kmac_burst_write.3286917272 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 10177273928 ps |
| CPU time | 240.28 seconds |
| Started | Sep 04 01:06:18 PM UTC 24 |
| Finished | Sep 04 01:10:23 PM UTC 24 |
| Peak memory | 237332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286917272 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.3286917272 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/28.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/28.kmac_entropy_refresh.949029217 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 2734745556 ps |
| CPU time | 40.73 seconds |
| Started | Sep 04 01:06:33 PM UTC 24 |
| Finished | Sep 04 01:07:15 PM UTC 24 |
| Peak memory | 259804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949029217 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.949029217 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/28.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/28.kmac_error.3540866746 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 2915130834 ps |
| CPU time | 112.83 seconds |
| Started | Sep 04 01:06:45 PM UTC 24 |
| Finished | Sep 04 01:08:40 PM UTC 24 |
| Peak memory | 284380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540866746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.3540866746 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/28.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/28.kmac_key_error.4145453631 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 18070735933 ps |
| CPU time | 12.89 seconds |
| Started | Sep 04 01:07:05 PM UTC 24 |
| Finished | Sep 04 01:07:19 PM UTC 24 |
| Peak memory | 232492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145453631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.4145453631 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/28.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/28.kmac_lc_escalation.3949341005 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 124703369 ps |
| CPU time | 1.82 seconds |
| Started | Sep 04 01:07:10 PM UTC 24 |
| Finished | Sep 04 01:07:13 PM UTC 24 |
| Peak memory | 231772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949341005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.3949341005 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/28.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/28.kmac_long_msg_and_output.4114296581 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 21910768665 ps |
| CPU time | 2222.46 seconds |
| Started | Sep 04 01:06:13 PM UTC 24 |
| Finished | Sep 04 01:43:41 PM UTC 24 |
| Peak memory | 1591208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114296581 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_and_output.4114296581 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/28.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/28.kmac_sideload.514582527 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 539922600 ps |
| CPU time | 50.24 seconds |
| Started | Sep 04 01:06:17 PM UTC 24 |
| Finished | Sep 04 01:07:09 PM UTC 24 |
| Peak memory | 245556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514582527 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.514582527 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/28.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/28.kmac_smoke.1489727807 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 778157339 ps |
| CPU time | 12.97 seconds |
| Started | Sep 04 01:06:02 PM UTC 24 |
| Finished | Sep 04 01:06:16 PM UTC 24 |
| Peak memory | 230548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489727807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.1489727807 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/28.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/28.kmac_stress_all.1009696211 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 12433597610 ps |
| CPU time | 240.29 seconds |
| Started | Sep 04 01:07:14 PM UTC 24 |
| Finished | Sep 04 01:11:18 PM UTC 24 |
| Peak memory | 317236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009696211 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.1009696211 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/28.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/29.kmac_alert_test.1141280395 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 20549075 ps |
| CPU time | 1.34 seconds |
| Started | Sep 04 01:08:25 PM UTC 24 |
| Finished | Sep 04 01:08:27 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141280395 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.1141280395 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/29.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/29.kmac_app.1890805903 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 1090344240 ps |
| CPU time | 35.11 seconds |
| Started | Sep 04 01:07:54 PM UTC 24 |
| Finished | Sep 04 01:08:31 PM UTC 24 |
| Peak memory | 239344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890805903 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.1890805903 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/29.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/29.kmac_burst_write.2495840545 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 5590791494 ps |
| CPU time | 243.04 seconds |
| Started | Sep 04 01:07:42 PM UTC 24 |
| Finished | Sep 04 01:11:49 PM UTC 24 |
| Peak memory | 239464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495840545 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.2495840545 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/29.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/29.kmac_entropy_refresh.2173573487 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 4074862868 ps |
| CPU time | 41.47 seconds |
| Started | Sep 04 01:08:00 PM UTC 24 |
| Finished | Sep 04 01:08:43 PM UTC 24 |
| Peak memory | 266244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173573487 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.2173573487 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/29.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/29.kmac_error.390866000 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 7881510923 ps |
| CPU time | 155.16 seconds |
| Started | Sep 04 01:08:04 PM UTC 24 |
| Finished | Sep 04 01:10:42 PM UTC 24 |
| Peak memory | 313140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390866000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.390866000 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/29.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/29.kmac_key_error.3393106264 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 107259269 ps |
| CPU time | 2.31 seconds |
| Started | Sep 04 01:08:11 PM UTC 24 |
| Finished | Sep 04 01:08:14 PM UTC 24 |
| Peak memory | 230332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393106264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.3393106264 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/29.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/29.kmac_lc_escalation.2931258232 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 93676702 ps |
| CPU time | 1.71 seconds |
| Started | Sep 04 01:08:15 PM UTC 24 |
| Finished | Sep 04 01:08:18 PM UTC 24 |
| Peak memory | 229856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931258232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.2931258232 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/29.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/29.kmac_long_msg_and_output.988027652 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 61114944096 ps |
| CPU time | 1194.09 seconds |
| Started | Sep 04 01:07:19 PM UTC 24 |
| Finished | Sep 04 01:27:28 PM UTC 24 |
| Peak memory | 1630060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988027652 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_and_output.988027652 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/29.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/29.kmac_sideload.3909954072 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 26067730341 ps |
| CPU time | 406.96 seconds |
| Started | Sep 04 01:07:20 PM UTC 24 |
| Finished | Sep 04 01:14:13 PM UTC 24 |
| Peak memory | 575272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909954072 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.3909954072 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/29.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/29.kmac_smoke.1675035398 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 934582179 ps |
| CPU time | 41.69 seconds |
| Started | Sep 04 01:07:16 PM UTC 24 |
| Finished | Sep 04 01:07:59 PM UTC 24 |
| Peak memory | 234952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675035398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.1675035398 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/29.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/29.kmac_stress_all.351827403 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 32318837034 ps |
| CPU time | 409.92 seconds |
| Started | Sep 04 01:08:18 PM UTC 24 |
| Finished | Sep 04 01:15:13 PM UTC 24 |
| Peak memory | 334132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351827403 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.351827403 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/29.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/3.kmac_alert_test.4027853327 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 53069170 ps |
| CPU time | 1.2 seconds |
| Started | Sep 04 12:44:40 PM UTC 24 |
| Finished | Sep 04 12:44:42 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027853327 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.4027853327 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/3.kmac_app.2282011565 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 12457805458 ps |
| CPU time | 90.64 seconds |
| Started | Sep 04 12:43:44 PM UTC 24 |
| Finished | Sep 04 12:45:17 PM UTC 24 |
| Peak memory | 286700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282011565 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.2282011565 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/3.kmac_app_with_partial_data.3062512749 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 7197825488 ps |
| CPU time | 192.61 seconds |
| Started | Sep 04 12:43:44 PM UTC 24 |
| Finished | Sep 04 12:47:00 PM UTC 24 |
| Peak memory | 313120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062512749 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.3062512749 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/3.kmac_burst_write.3349059704 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 14340376846 ps |
| CPU time | 682.34 seconds |
| Started | Sep 04 12:43:12 PM UTC 24 |
| Finished | Sep 04 12:54:43 PM UTC 24 |
| Peak memory | 249640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349059704 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.3349059704 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/3.kmac_edn_timeout_error.3214376652 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 41070809 ps |
| CPU time | 1.48 seconds |
| Started | Sep 04 12:44:11 PM UTC 24 |
| Finished | Sep 04 12:44:13 PM UTC 24 |
| Peak memory | 216976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214376652 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.3214376652 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_mode_error.722014530 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 84925939 ps |
| CPU time | 7.27 seconds |
| Started | Sep 04 12:44:13 PM UTC 24 |
| Finished | Sep 04 12:44:21 PM UTC 24 |
| Peak memory | 234440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722014530 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.722014530 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_ready_error.1212395013 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1326434237 ps |
| CPU time | 18.83 seconds |
| Started | Sep 04 12:44:14 PM UTC 24 |
| Finished | Sep 04 12:44:34 PM UTC 24 |
| Peak memory | 230708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212395013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.1212395013 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_refresh.4076357280 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 106064505288 ps |
| CPU time | 289.61 seconds |
| Started | Sep 04 12:43:44 PM UTC 24 |
| Finished | Sep 04 12:48:45 PM UTC 24 |
| Peak memory | 472880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076357280 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.4076357280 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/3.kmac_error.2978847716 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 3149755912 ps |
| CPU time | 49.02 seconds |
| Started | Sep 04 12:43:58 PM UTC 24 |
| Finished | Sep 04 12:44:50 PM UTC 24 |
| Peak memory | 282340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978847716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.2978847716 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/3.kmac_key_error.1830187550 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1343854558 ps |
| CPU time | 2.78 seconds |
| Started | Sep 04 12:44:06 PM UTC 24 |
| Finished | Sep 04 12:44:10 PM UTC 24 |
| Peak memory | 230324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830187550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.1830187550 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/3.kmac_lc_escalation.3882577103 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 129695012 ps |
| CPU time | 1.52 seconds |
| Started | Sep 04 12:44:22 PM UTC 24 |
| Finished | Sep 04 12:44:24 PM UTC 24 |
| Peak memory | 231720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882577103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.3882577103 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/3.kmac_long_msg_and_output.2204586439 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 211033351020 ps |
| CPU time | 3553 seconds |
| Started | Sep 04 12:43:07 PM UTC 24 |
| Finished | Sep 04 01:42:59 PM UTC 24 |
| Peak memory | 4405456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204586439 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_and_output.2204586439 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/3.kmac_mubi.1906251634 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 6318531418 ps |
| CPU time | 196.39 seconds |
| Started | Sep 04 12:43:45 PM UTC 24 |
| Finished | Sep 04 12:47:06 PM UTC 24 |
| Peak memory | 319804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906251634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.1906251634 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/3.kmac_sec_cm.969040939 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 2381267876 ps |
| CPU time | 31.66 seconds |
| Started | Sep 04 12:44:35 PM UTC 24 |
| Finished | Sep 04 12:45:08 PM UTC 24 |
| Peak memory | 267184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969040939 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.969040939 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/3.kmac_sideload.1263016887 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1537741409 ps |
| CPU time | 32.28 seconds |
| Started | Sep 04 12:43:10 PM UTC 24 |
| Finished | Sep 04 12:43:44 PM UTC 24 |
| Peak memory | 241316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263016887 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.1263016887 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/3.kmac_smoke.1706328502 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 100946160 ps |
| CPU time | 3.62 seconds |
| Started | Sep 04 12:43:05 PM UTC 24 |
| Finished | Sep 04 12:43:10 PM UTC 24 |
| Peak memory | 232812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706328502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.1706328502 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/3.kmac_stress_all.465471176 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 11766608446 ps |
| CPU time | 963.12 seconds |
| Started | Sep 04 12:44:24 PM UTC 24 |
| Finished | Sep 04 01:00:40 PM UTC 24 |
| Peak memory | 681976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465471176 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.465471176 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac.3833472269 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 34918487 ps |
| CPU time | 3.43 seconds |
| Started | Sep 04 12:43:39 PM UTC 24 |
| Finished | Sep 04 12:43:44 PM UTC 24 |
| Peak memory | 230444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833472269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac.3833472269 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac_xof.642253161 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 124789161 ps |
| CPU time | 2.67 seconds |
| Started | Sep 04 12:43:40 PM UTC 24 |
| Finished | Sep 04 12:43:44 PM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642253161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_ve ctors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.642253161 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_224.351802389 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 2440879669 ps |
| CPU time | 41.94 seconds |
| Started | Sep 04 12:43:15 PM UTC 24 |
| Finished | Sep 04 12:43:58 PM UTC 24 |
| Peak memory | 232496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351802389 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.351802389 + enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_256.3813774761 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 34232247919 ps |
| CPU time | 65.25 seconds |
| Started | Sep 04 12:43:16 PM UTC 24 |
| Finished | Sep 04 12:44:23 PM UTC 24 |
| Peak memory | 253712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813774761 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.3813774761 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_384.2903215463 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 13389249592 ps |
| CPU time | 1317.76 seconds |
| Started | Sep 04 12:43:20 PM UTC 24 |
| Finished | Sep 04 01:05:34 PM UTC 24 |
| Peak memory | 937628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903215463 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.2903215463 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_512.774159845 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 1906876004 ps |
| CPU time | 22.59 seconds |
| Started | Sep 04 12:43:20 PM UTC 24 |
| Finished | Sep 04 12:43:44 PM UTC 24 |
| Peak memory | 230464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774159845 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.774159845 + enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_128.4064898033 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 3601391437 ps |
| CPU time | 183.32 seconds |
| Started | Sep 04 12:43:28 PM UTC 24 |
| Finished | Sep 04 12:46:35 PM UTC 24 |
| Peak memory | 239328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064898033 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.4064898 033 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_256.982005545 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 314253083623 ps |
| CPU time | 2373.24 seconds |
| Started | Sep 04 12:43:32 PM UTC 24 |
| Finished | Sep 04 01:23:33 PM UTC 24 |
| Peak memory | 3004056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982005545 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.98200554 5 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/3.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/30.kmac_alert_test.704042547 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 50991906 ps |
| CPU time | 1.18 seconds |
| Started | Sep 04 01:08:53 PM UTC 24 |
| Finished | Sep 04 01:08:55 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704042547 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.704042547 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/30.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/30.kmac_app.2717262728 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 13026398625 ps |
| CPU time | 336.81 seconds |
| Started | Sep 04 01:08:36 PM UTC 24 |
| Finished | Sep 04 01:14:18 PM UTC 24 |
| Peak memory | 518124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717262728 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.2717262728 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/30.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/30.kmac_burst_write.2450252818 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 3405264390 ps |
| CPU time | 40.28 seconds |
| Started | Sep 04 01:08:32 PM UTC 24 |
| Finished | Sep 04 01:09:14 PM UTC 24 |
| Peak memory | 230540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450252818 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.2450252818 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/30.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/30.kmac_entropy_refresh.4113780858 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 2686798624 ps |
| CPU time | 23.83 seconds |
| Started | Sep 04 01:08:40 PM UTC 24 |
| Finished | Sep 04 01:09:05 PM UTC 24 |
| Peak memory | 239340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113780858 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.4113780858 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/30.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/30.kmac_error.2463793100 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 58658212379 ps |
| CPU time | 396.66 seconds |
| Started | Sep 04 01:08:42 PM UTC 24 |
| Finished | Sep 04 01:15:24 PM UTC 24 |
| Peak memory | 550708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463793100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.2463793100 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/30.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/30.kmac_key_error.2532203406 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 1326297452 ps |
| CPU time | 7.38 seconds |
| Started | Sep 04 01:08:44 PM UTC 24 |
| Finished | Sep 04 01:08:52 PM UTC 24 |
| Peak memory | 230332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532203406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.2532203406 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/30.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/30.kmac_lc_escalation.74975689 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 42020964 ps |
| CPU time | 2.18 seconds |
| Started | Sep 04 01:08:53 PM UTC 24 |
| Finished | Sep 04 01:08:56 PM UTC 24 |
| Peak memory | 230320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74975689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.74975689 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/30.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/30.kmac_long_msg_and_output.2247230312 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 31928645389 ps |
| CPU time | 773.02 seconds |
| Started | Sep 04 01:08:26 PM UTC 24 |
| Finished | Sep 04 01:21:28 PM UTC 24 |
| Peak memory | 727092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247230312 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_and_output.2247230312 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/30.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/30.kmac_sideload.1433490434 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 14716079146 ps |
| CPU time | 110.73 seconds |
| Started | Sep 04 01:08:28 PM UTC 24 |
| Finished | Sep 04 01:10:21 PM UTC 24 |
| Peak memory | 331496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433490434 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.1433490434 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/30.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/30.kmac_smoke.1529011596 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 4002882729 ps |
| CPU time | 53.97 seconds |
| Started | Sep 04 01:08:25 PM UTC 24 |
| Finished | Sep 04 01:09:21 PM UTC 24 |
| Peak memory | 230592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529011596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.1529011596 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/30.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/30.kmac_stress_all.2169991425 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 3375679306 ps |
| CPU time | 210.76 seconds |
| Started | Sep 04 01:08:53 PM UTC 24 |
| Finished | Sep 04 01:12:27 PM UTC 24 |
| Peak memory | 284936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169991425 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.2169991425 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/30.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/31.kmac_alert_test.1821860688 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 53966442 ps |
| CPU time | 1.22 seconds |
| Started | Sep 04 01:09:45 PM UTC 24 |
| Finished | Sep 04 01:09:47 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821860688 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.1821860688 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/31.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/31.kmac_app.2617755352 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 7805254124 ps |
| CPU time | 39.82 seconds |
| Started | Sep 04 01:09:15 PM UTC 24 |
| Finished | Sep 04 01:09:56 PM UTC 24 |
| Peak memory | 252016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617755352 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.2617755352 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/31.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/31.kmac_burst_write.3060134532 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 17312261399 ps |
| CPU time | 572.68 seconds |
| Started | Sep 04 01:09:06 PM UTC 24 |
| Finished | Sep 04 01:18:46 PM UTC 24 |
| Peak memory | 253736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060134532 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.3060134532 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/31.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/31.kmac_entropy_refresh.4151793235 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 7076290749 ps |
| CPU time | 182.54 seconds |
| Started | Sep 04 01:09:20 PM UTC 24 |
| Finished | Sep 04 01:12:26 PM UTC 24 |
| Peak memory | 311320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151793235 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.4151793235 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/31.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/31.kmac_error.322178068 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 15165580349 ps |
| CPU time | 67.64 seconds |
| Started | Sep 04 01:09:21 PM UTC 24 |
| Finished | Sep 04 01:10:31 PM UTC 24 |
| Peak memory | 266080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322178068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.322178068 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/31.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/31.kmac_key_error.1207430619 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 1530603252 ps |
| CPU time | 14.92 seconds |
| Started | Sep 04 01:09:24 PM UTC 24 |
| Finished | Sep 04 01:09:40 PM UTC 24 |
| Peak memory | 230328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207430619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.1207430619 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/31.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/31.kmac_long_msg_and_output.2290117933 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 15495564317 ps |
| CPU time | 1425.7 seconds |
| Started | Sep 04 01:08:57 PM UTC 24 |
| Finished | Sep 04 01:32:59 PM UTC 24 |
| Peak memory | 1175288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290117933 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_and_output.2290117933 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/31.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/31.kmac_sideload.4028228775 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 733089648 ps |
| CPU time | 44.48 seconds |
| Started | Sep 04 01:09:03 PM UTC 24 |
| Finished | Sep 04 01:09:49 PM UTC 24 |
| Peak memory | 241456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028228775 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.4028228775 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/31.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/31.kmac_smoke.2812188150 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 11203485354 ps |
| CPU time | 54.7 seconds |
| Started | Sep 04 01:08:56 PM UTC 24 |
| Finished | Sep 04 01:09:52 PM UTC 24 |
| Peak memory | 230604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812188150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.2812188150 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/31.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/31.kmac_stress_all.3837761123 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 117963990160 ps |
| CPU time | 992.34 seconds |
| Started | Sep 04 01:09:42 PM UTC 24 |
| Finished | Sep 04 01:26:26 PM UTC 24 |
| Peak memory | 694388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837761123 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.3837761123 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/31.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/32.kmac_alert_test.2206041636 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 38295132 ps |
| CPU time | 1.13 seconds |
| Started | Sep 04 01:10:43 PM UTC 24 |
| Finished | Sep 04 01:10:45 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206041636 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.2206041636 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/32.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/32.kmac_app.4085728151 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 9868622350 ps |
| CPU time | 263.94 seconds |
| Started | Sep 04 01:10:03 PM UTC 24 |
| Finished | Sep 04 01:14:31 PM UTC 24 |
| Peak memory | 435944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085728151 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.4085728151 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/32.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/32.kmac_burst_write.1910607493 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 7444915475 ps |
| CPU time | 740.17 seconds |
| Started | Sep 04 01:09:57 PM UTC 24 |
| Finished | Sep 04 01:22:27 PM UTC 24 |
| Peak memory | 251624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910607493 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.1910607493 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/32.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/32.kmac_entropy_refresh.3591422683 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 12903811946 ps |
| CPU time | 132.13 seconds |
| Started | Sep 04 01:10:22 PM UTC 24 |
| Finished | Sep 04 01:12:37 PM UTC 24 |
| Peak memory | 276196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591422683 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.3591422683 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/32.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/32.kmac_error.1483706076 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 29791093727 ps |
| CPU time | 162.52 seconds |
| Started | Sep 04 01:10:23 PM UTC 24 |
| Finished | Sep 04 01:13:09 PM UTC 24 |
| Peak memory | 386992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483706076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.1483706076 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/32.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/32.kmac_key_error.2294080420 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 5810094391 ps |
| CPU time | 5.78 seconds |
| Started | Sep 04 01:10:31 PM UTC 24 |
| Finished | Sep 04 01:10:38 PM UTC 24 |
| Peak memory | 230672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294080420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.2294080420 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/32.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/32.kmac_lc_escalation.1340808072 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 1169375586 ps |
| CPU time | 72.3 seconds |
| Started | Sep 04 01:10:32 PM UTC 24 |
| Finished | Sep 04 01:11:46 PM UTC 24 |
| Peak memory | 261920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340808072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.1340808072 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/32.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/32.kmac_long_msg_and_output.3957597545 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 105281721971 ps |
| CPU time | 1652.81 seconds |
| Started | Sep 04 01:09:50 PM UTC 24 |
| Finished | Sep 04 01:37:41 PM UTC 24 |
| Peak memory | 2371360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957597545 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_and_output.3957597545 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/32.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/32.kmac_sideload.785006254 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 17660133109 ps |
| CPU time | 100.09 seconds |
| Started | Sep 04 01:09:53 PM UTC 24 |
| Finished | Sep 04 01:11:35 PM UTC 24 |
| Peak memory | 319532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785006254 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.785006254 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/32.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/32.kmac_smoke.3148017225 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 28065741104 ps |
| CPU time | 85.74 seconds |
| Started | Sep 04 01:09:48 PM UTC 24 |
| Finished | Sep 04 01:11:16 PM UTC 24 |
| Peak memory | 235496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148017225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.3148017225 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/32.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/32.kmac_stress_all.358938649 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 129830430575 ps |
| CPU time | 866.13 seconds |
| Started | Sep 04 01:10:40 PM UTC 24 |
| Finished | Sep 04 01:25:16 PM UTC 24 |
| Peak memory | 397556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358938649 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.358938649 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/32.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/33.kmac_alert_test.3112754585 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 18122175 ps |
| CPU time | 1.21 seconds |
| Started | Sep 04 01:12:17 PM UTC 24 |
| Finished | Sep 04 01:12:19 PM UTC 24 |
| Peak memory | 215228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112754585 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.3112754585 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/33.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/33.kmac_app.1843512073 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 5427968168 ps |
| CPU time | 133.99 seconds |
| Started | Sep 04 01:11:19 PM UTC 24 |
| Finished | Sep 04 01:13:36 PM UTC 24 |
| Peak memory | 337904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843512073 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.1843512073 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/33.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/33.kmac_burst_write.2504443921 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 42907405588 ps |
| CPU time | 366.55 seconds |
| Started | Sep 04 01:11:17 PM UTC 24 |
| Finished | Sep 04 01:17:29 PM UTC 24 |
| Peak memory | 243452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504443921 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.2504443921 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/33.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/33.kmac_entropy_refresh.1165165469 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 20027221546 ps |
| CPU time | 292.63 seconds |
| Started | Sep 04 01:11:24 PM UTC 24 |
| Finished | Sep 04 01:16:21 PM UTC 24 |
| Peak memory | 415660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165165469 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.1165165469 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/33.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/33.kmac_error.3050306086 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 39891293061 ps |
| CPU time | 411.62 seconds |
| Started | Sep 04 01:11:36 PM UTC 24 |
| Finished | Sep 04 01:18:34 PM UTC 24 |
| Peak memory | 569260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050306086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.3050306086 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/33.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/33.kmac_key_error.3529180690 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 1641107565 ps |
| CPU time | 11.76 seconds |
| Started | Sep 04 01:11:46 PM UTC 24 |
| Finished | Sep 04 01:11:59 PM UTC 24 |
| Peak memory | 230592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529180690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.3529180690 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/33.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/33.kmac_lc_escalation.2329171076 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 935816513 ps |
| CPU time | 24.14 seconds |
| Started | Sep 04 01:11:50 PM UTC 24 |
| Finished | Sep 04 01:12:15 PM UTC 24 |
| Peak memory | 247604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329171076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.2329171076 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/33.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/33.kmac_long_msg_and_output.3630474451 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 6606505972 ps |
| CPU time | 290.58 seconds |
| Started | Sep 04 01:10:53 PM UTC 24 |
| Finished | Sep 04 01:15:48 PM UTC 24 |
| Peak memory | 429820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630474451 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_and_output.3630474451 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/33.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/33.kmac_sideload.889552543 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 11540027137 ps |
| CPU time | 311.42 seconds |
| Started | Sep 04 01:10:54 PM UTC 24 |
| Finished | Sep 04 01:16:10 PM UTC 24 |
| Peak memory | 331624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889552543 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.889552543 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/33.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/33.kmac_smoke.2183648638 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 593451956 ps |
| CPU time | 36.01 seconds |
| Started | Sep 04 01:10:46 PM UTC 24 |
| Finished | Sep 04 01:11:23 PM UTC 24 |
| Peak memory | 230528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183648638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.2183648638 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/33.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/33.kmac_stress_all.1108981196 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 74641117437 ps |
| CPU time | 1335.24 seconds |
| Started | Sep 04 01:12:01 PM UTC 24 |
| Finished | Sep 04 01:34:31 PM UTC 24 |
| Peak memory | 1667112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108981196 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.1108981196 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/33.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/34.kmac_alert_test.2842589182 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 23518194 ps |
| CPU time | 1.16 seconds |
| Started | Sep 04 01:13:10 PM UTC 24 |
| Finished | Sep 04 01:13:12 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842589182 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.2842589182 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/34.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/34.kmac_app.181285749 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 16187692600 ps |
| CPU time | 360.99 seconds |
| Started | Sep 04 01:12:28 PM UTC 24 |
| Finished | Sep 04 01:18:34 PM UTC 24 |
| Peak memory | 536364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181285749 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.181285749 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/34.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/34.kmac_burst_write.988827026 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 415309289 ps |
| CPU time | 37.21 seconds |
| Started | Sep 04 01:12:27 PM UTC 24 |
| Finished | Sep 04 01:13:06 PM UTC 24 |
| Peak memory | 232756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988827026 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.988827026 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/34.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/34.kmac_entropy_refresh.3298665911 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 27914432588 ps |
| CPU time | 290.94 seconds |
| Started | Sep 04 01:12:37 PM UTC 24 |
| Finished | Sep 04 01:17:32 PM UTC 24 |
| Peak memory | 342064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298665911 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.3298665911 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/34.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/34.kmac_error.3617977003 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 14286205500 ps |
| CPU time | 433.99 seconds |
| Started | Sep 04 01:12:51 PM UTC 24 |
| Finished | Sep 04 01:20:11 PM UTC 24 |
| Peak memory | 538672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617977003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.3617977003 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/34.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/34.kmac_key_error.124889657 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 631463886 ps |
| CPU time | 7.44 seconds |
| Started | Sep 04 01:13:03 PM UTC 24 |
| Finished | Sep 04 01:13:11 PM UTC 24 |
| Peak memory | 230388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124889657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.124889657 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/34.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/34.kmac_lc_escalation.3245390852 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 63366171 ps |
| CPU time | 1.9 seconds |
| Started | Sep 04 01:13:07 PM UTC 24 |
| Finished | Sep 04 01:13:10 PM UTC 24 |
| Peak memory | 234428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245390852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.3245390852 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/34.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/34.kmac_long_msg_and_output.1849643572 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 243977133373 ps |
| CPU time | 2622.32 seconds |
| Started | Sep 04 01:12:20 PM UTC 24 |
| Finished | Sep 04 01:56:31 PM UTC 24 |
| Peak memory | 3082024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849643572 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_and_output.1849643572 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/34.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/34.kmac_sideload.2084695865 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 3497334419 ps |
| CPU time | 27.33 seconds |
| Started | Sep 04 01:12:21 PM UTC 24 |
| Finished | Sep 04 01:12:50 PM UTC 24 |
| Peak memory | 251756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084695865 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.2084695865 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/34.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/34.kmac_smoke.3131883958 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 2081588312 ps |
| CPU time | 61.62 seconds |
| Started | Sep 04 01:12:17 PM UTC 24 |
| Finished | Sep 04 01:13:20 PM UTC 24 |
| Peak memory | 230572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131883958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.3131883958 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/34.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/34.kmac_stress_all.1457906349 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 10768018031 ps |
| CPU time | 78.16 seconds |
| Started | Sep 04 01:13:07 PM UTC 24 |
| Finished | Sep 04 01:14:27 PM UTC 24 |
| Peak memory | 296752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457906349 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.1457906349 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/34.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/35.kmac_alert_test.1689414262 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 13259161 ps |
| CPU time | 1.14 seconds |
| Started | Sep 04 01:14:18 PM UTC 24 |
| Finished | Sep 04 01:14:20 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689414262 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.1689414262 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/35.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/35.kmac_app.2932273046 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 5679744916 ps |
| CPU time | 170.8 seconds |
| Started | Sep 04 01:13:21 PM UTC 24 |
| Finished | Sep 04 01:16:15 PM UTC 24 |
| Peak memory | 358128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932273046 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.2932273046 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/35.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/35.kmac_burst_write.4200699476 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 22294903675 ps |
| CPU time | 934.25 seconds |
| Started | Sep 04 01:13:13 PM UTC 24 |
| Finished | Sep 04 01:28:59 PM UTC 24 |
| Peak memory | 251688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200699476 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.4200699476 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/35.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/35.kmac_entropy_refresh.64580834 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 10460492400 ps |
| CPU time | 139.42 seconds |
| Started | Sep 04 01:13:36 PM UTC 24 |
| Finished | Sep 04 01:15:58 PM UTC 24 |
| Peak memory | 356344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64580834 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.64580834 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/35.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/35.kmac_error.2820509764 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 7185274582 ps |
| CPU time | 157.54 seconds |
| Started | Sep 04 01:13:40 PM UTC 24 |
| Finished | Sep 04 01:16:20 PM UTC 24 |
| Peak memory | 376868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820509764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.2820509764 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/35.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/35.kmac_lc_escalation.3468667755 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 51379058 ps |
| CPU time | 1.83 seconds |
| Started | Sep 04 01:14:14 PM UTC 24 |
| Finished | Sep 04 01:14:17 PM UTC 24 |
| Peak memory | 229676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468667755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.3468667755 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/35.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/35.kmac_long_msg_and_output.883447461 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 64232170503 ps |
| CPU time | 2706.4 seconds |
| Started | Sep 04 01:13:12 PM UTC 24 |
| Finished | Sep 04 01:58:52 PM UTC 24 |
| Peak memory | 1742660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883447461 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_and_output.883447461 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/35.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/35.kmac_sideload.2419785159 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 5587161817 ps |
| CPU time | 241.85 seconds |
| Started | Sep 04 01:13:12 PM UTC 24 |
| Finished | Sep 04 01:17:18 PM UTC 24 |
| Peak memory | 323388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419785159 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.2419785159 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/35.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/35.kmac_smoke.1298285816 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 2345433893 ps |
| CPU time | 26.36 seconds |
| Started | Sep 04 01:13:11 PM UTC 24 |
| Finished | Sep 04 01:13:39 PM UTC 24 |
| Peak memory | 230852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298285816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.1298285816 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/35.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/35.kmac_stress_all.959944016 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 52332403819 ps |
| CPU time | 215.23 seconds |
| Started | Sep 04 01:14:16 PM UTC 24 |
| Finished | Sep 04 01:17:54 PM UTC 24 |
| Peak memory | 522028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959944016 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.959944016 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/35.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/36.kmac_alert_test.121357805 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 19307999 ps |
| CPU time | 0.99 seconds |
| Started | Sep 04 01:15:42 PM UTC 24 |
| Finished | Sep 04 01:15:44 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121357805 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.121357805 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/36.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/36.kmac_app.1880319868 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 176243218854 ps |
| CPU time | 281.56 seconds |
| Started | Sep 04 01:14:32 PM UTC 24 |
| Finished | Sep 04 01:19:18 PM UTC 24 |
| Peak memory | 454524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880319868 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.1880319868 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/36.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/36.kmac_burst_write.2017665496 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 33599582443 ps |
| CPU time | 1028.51 seconds |
| Started | Sep 04 01:14:27 PM UTC 24 |
| Finished | Sep 04 01:31:48 PM UTC 24 |
| Peak memory | 266024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017665496 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.2017665496 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/36.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/36.kmac_entropy_refresh.272137004 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 14672035083 ps |
| CPU time | 193.16 seconds |
| Started | Sep 04 01:14:35 PM UTC 24 |
| Finished | Sep 04 01:17:52 PM UTC 24 |
| Peak memory | 378672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272137004 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.272137004 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/36.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/36.kmac_error.2356906947 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 65584949223 ps |
| CPU time | 336.58 seconds |
| Started | Sep 04 01:15:14 PM UTC 24 |
| Finished | Sep 04 01:20:55 PM UTC 24 |
| Peak memory | 569132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356906947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.2356906947 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/36.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/36.kmac_key_error.3596037462 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 4980952915 ps |
| CPU time | 14.28 seconds |
| Started | Sep 04 01:15:25 PM UTC 24 |
| Finished | Sep 04 01:15:40 PM UTC 24 |
| Peak memory | 230648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596037462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.3596037462 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/36.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/36.kmac_lc_escalation.2020757639 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 3712476713 ps |
| CPU time | 25.49 seconds |
| Started | Sep 04 01:15:39 PM UTC 24 |
| Finished | Sep 04 01:16:06 PM UTC 24 |
| Peak memory | 251620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020757639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.2020757639 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/36.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/36.kmac_long_msg_and_output.2772411438 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 870536332862 ps |
| CPU time | 2098.69 seconds |
| Started | Sep 04 01:14:21 PM UTC 24 |
| Finished | Sep 04 01:49:43 PM UTC 24 |
| Peak memory | 2967232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772411438 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_and_output.2772411438 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/36.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/36.kmac_sideload.3009380274 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 53384069909 ps |
| CPU time | 333.79 seconds |
| Started | Sep 04 01:14:21 PM UTC 24 |
| Finished | Sep 04 01:20:00 PM UTC 24 |
| Peak memory | 517892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009380274 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.3009380274 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/36.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/36.kmac_smoke.1667009006 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 2997915375 ps |
| CPU time | 14.02 seconds |
| Started | Sep 04 01:14:19 PM UTC 24 |
| Finished | Sep 04 01:14:34 PM UTC 24 |
| Peak memory | 232584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667009006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.1667009006 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/36.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/36.kmac_stress_all.2038377522 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 93211494162 ps |
| CPU time | 797.49 seconds |
| Started | Sep 04 01:15:41 PM UTC 24 |
| Finished | Sep 04 01:29:09 PM UTC 24 |
| Peak memory | 677968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038377522 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.2038377522 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/36.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/37.kmac_alert_test.3281940549 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 18248274 ps |
| CPU time | 1.22 seconds |
| Started | Sep 04 01:16:36 PM UTC 24 |
| Finished | Sep 04 01:16:38 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281940549 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.3281940549 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/37.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/37.kmac_app.493289943 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 3071934958 ps |
| CPU time | 197.22 seconds |
| Started | Sep 04 01:16:09 PM UTC 24 |
| Finished | Sep 04 01:19:30 PM UTC 24 |
| Peak memory | 296992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493289943 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.493289943 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/37.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/37.kmac_burst_write.409091837 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 17192696280 ps |
| CPU time | 448.88 seconds |
| Started | Sep 04 01:16:07 PM UTC 24 |
| Finished | Sep 04 01:23:42 PM UTC 24 |
| Peak memory | 243508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409091837 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.409091837 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/37.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/37.kmac_entropy_refresh.2309773311 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 4061309448 ps |
| CPU time | 273.72 seconds |
| Started | Sep 04 01:16:11 PM UTC 24 |
| Finished | Sep 04 01:20:49 PM UTC 24 |
| Peak memory | 333548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309773311 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.2309773311 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/37.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/37.kmac_error.2247607237 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 470772509 ps |
| CPU time | 18.73 seconds |
| Started | Sep 04 01:16:16 PM UTC 24 |
| Finished | Sep 04 01:16:35 PM UTC 24 |
| Peak memory | 245476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247607237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.2247607237 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/37.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/37.kmac_key_error.1012523590 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 2910435873 ps |
| CPU time | 14.71 seconds |
| Started | Sep 04 01:16:21 PM UTC 24 |
| Finished | Sep 04 01:16:37 PM UTC 24 |
| Peak memory | 232840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012523590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.1012523590 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/37.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/37.kmac_long_msg_and_output.4023330721 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 16734194816 ps |
| CPU time | 1596.7 seconds |
| Started | Sep 04 01:15:48 PM UTC 24 |
| Finished | Sep 04 01:42:44 PM UTC 24 |
| Peak memory | 1230760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023330721 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_and_output.4023330721 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/37.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/37.kmac_sideload.53984899 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 6504842636 ps |
| CPU time | 188.5 seconds |
| Started | Sep 04 01:15:59 PM UTC 24 |
| Finished | Sep 04 01:19:11 PM UTC 24 |
| Peak memory | 356052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53984899 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.53984899 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/37.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/37.kmac_smoke.3094861735 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 817171295 ps |
| CPU time | 22.19 seconds |
| Started | Sep 04 01:15:45 PM UTC 24 |
| Finished | Sep 04 01:16:09 PM UTC 24 |
| Peak memory | 234608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094861735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.3094861735 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/37.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/37.kmac_stress_all.2272346248 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 12782331545 ps |
| CPU time | 270.37 seconds |
| Started | Sep 04 01:16:27 PM UTC 24 |
| Finished | Sep 04 01:21:01 PM UTC 24 |
| Peak memory | 393332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272346248 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.2272346248 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/37.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/38.kmac_alert_test.970090270 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 55302441 ps |
| CPU time | 1.23 seconds |
| Started | Sep 04 01:18:02 PM UTC 24 |
| Finished | Sep 04 01:18:04 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970090270 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.970090270 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/38.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/38.kmac_app.4024935799 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 35708670985 ps |
| CPU time | 257.17 seconds |
| Started | Sep 04 01:17:18 PM UTC 24 |
| Finished | Sep 04 01:21:40 PM UTC 24 |
| Peak memory | 390956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024935799 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.4024935799 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/38.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/38.kmac_burst_write.644989764 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 230170184146 ps |
| CPU time | 614.6 seconds |
| Started | Sep 04 01:17:07 PM UTC 24 |
| Finished | Sep 04 01:27:30 PM UTC 24 |
| Peak memory | 251688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644989764 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.644989764 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/38.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/38.kmac_entropy_refresh.1256305171 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 9335050349 ps |
| CPU time | 29.93 seconds |
| Started | Sep 04 01:17:30 PM UTC 24 |
| Finished | Sep 04 01:18:01 PM UTC 24 |
| Peak memory | 243444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256305171 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.1256305171 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/38.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/38.kmac_error.4270598714 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 800677092 ps |
| CPU time | 72.42 seconds |
| Started | Sep 04 01:17:34 PM UTC 24 |
| Finished | Sep 04 01:18:48 PM UTC 24 |
| Peak memory | 263912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270598714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.4270598714 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/38.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/38.kmac_key_error.3936697315 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 4606632242 ps |
| CPU time | 15.31 seconds |
| Started | Sep 04 01:17:53 PM UTC 24 |
| Finished | Sep 04 01:18:09 PM UTC 24 |
| Peak memory | 230400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936697315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.3936697315 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/38.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/38.kmac_lc_escalation.1603120152 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 264308219 ps |
| CPU time | 1.84 seconds |
| Started | Sep 04 01:17:55 PM UTC 24 |
| Finished | Sep 04 01:17:58 PM UTC 24 |
| Peak memory | 231724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603120152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.1603120152 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/38.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/38.kmac_long_msg_and_output.1077634907 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 2701932722 ps |
| CPU time | 166.82 seconds |
| Started | Sep 04 01:16:39 PM UTC 24 |
| Finished | Sep 04 01:19:29 PM UTC 24 |
| Peak memory | 309148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077634907 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_and_output.1077634907 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/38.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/38.kmac_sideload.1628850928 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 1519655724 ps |
| CPU time | 74.59 seconds |
| Started | Sep 04 01:16:45 PM UTC 24 |
| Finished | Sep 04 01:18:02 PM UTC 24 |
| Peak memory | 253680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628850928 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.1628850928 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/38.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/38.kmac_smoke.3104004039 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 8161328988 ps |
| CPU time | 89.21 seconds |
| Started | Sep 04 01:16:38 PM UTC 24 |
| Finished | Sep 04 01:18:09 PM UTC 24 |
| Peak memory | 234680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104004039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.3104004039 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/38.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/38.kmac_stress_all.624236078 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 44154659073 ps |
| CPU time | 1154.67 seconds |
| Started | Sep 04 01:17:59 PM UTC 24 |
| Finished | Sep 04 01:37:27 PM UTC 24 |
| Peak memory | 973052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624236078 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.624236078 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/38.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/39.kmac_alert_test.840755468 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 19140690 ps |
| CPU time | 1.22 seconds |
| Started | Sep 04 01:18:50 PM UTC 24 |
| Finished | Sep 04 01:18:52 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840755468 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.840755468 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/39.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/39.kmac_app.3635476476 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 12440652808 ps |
| CPU time | 139.5 seconds |
| Started | Sep 04 01:18:34 PM UTC 24 |
| Finished | Sep 04 01:20:57 PM UTC 24 |
| Peak memory | 286444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635476476 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.3635476476 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/39.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/39.kmac_burst_write.1090617601 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 34831415004 ps |
| CPU time | 617.63 seconds |
| Started | Sep 04 01:18:10 PM UTC 24 |
| Finished | Sep 04 01:28:35 PM UTC 24 |
| Peak memory | 255984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090617601 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.1090617601 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/39.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/39.kmac_entropy_refresh.1375798623 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 2376381445 ps |
| CPU time | 62.83 seconds |
| Started | Sep 04 01:18:36 PM UTC 24 |
| Finished | Sep 04 01:19:40 PM UTC 24 |
| Peak memory | 266016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375798623 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.1375798623 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/39.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/39.kmac_error.1444363571 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 9839473823 ps |
| CPU time | 196.92 seconds |
| Started | Sep 04 01:18:46 PM UTC 24 |
| Finished | Sep 04 01:22:06 PM UTC 24 |
| Peak memory | 317484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444363571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.1444363571 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/39.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/39.kmac_key_error.2244530045 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 1415664853 ps |
| CPU time | 7.46 seconds |
| Started | Sep 04 01:18:47 PM UTC 24 |
| Finished | Sep 04 01:18:55 PM UTC 24 |
| Peak memory | 230532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244530045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.2244530045 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/39.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/39.kmac_lc_escalation.2177695492 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 433764755 ps |
| CPU time | 10.95 seconds |
| Started | Sep 04 01:18:47 PM UTC 24 |
| Finished | Sep 04 01:18:59 PM UTC 24 |
| Peak memory | 242888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177695492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.2177695492 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/39.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/39.kmac_long_msg_and_output.3578982346 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 62665268977 ps |
| CPU time | 2446.01 seconds |
| Started | Sep 04 01:18:05 PM UTC 24 |
| Finished | Sep 04 01:59:18 PM UTC 24 |
| Peak memory | 3043116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578982346 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_and_output.3578982346 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/39.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/39.kmac_sideload.4067580540 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 16908638897 ps |
| CPU time | 190.79 seconds |
| Started | Sep 04 01:18:10 PM UTC 24 |
| Finished | Sep 04 01:21:24 PM UTC 24 |
| Peak memory | 429888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067580540 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.4067580540 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/39.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/39.kmac_smoke.602386628 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 3852982129 ps |
| CPU time | 44.01 seconds |
| Started | Sep 04 01:18:03 PM UTC 24 |
| Finished | Sep 04 01:18:49 PM UTC 24 |
| Peak memory | 230724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602386628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.602386628 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/39.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/39.kmac_stress_all.3438210862 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 91516173578 ps |
| CPU time | 661.74 seconds |
| Started | Sep 04 01:18:49 PM UTC 24 |
| Finished | Sep 04 01:29:59 PM UTC 24 |
| Peak memory | 952372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438210862 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.3438210862 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/39.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/4.kmac_alert_test.1675853052 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 28188249 ps |
| CPU time | 1 seconds |
| Started | Sep 04 12:46:17 PM UTC 24 |
| Finished | Sep 04 12:46:19 PM UTC 24 |
| Peak memory | 216348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675853052 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.1675853052 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/4.kmac_app.2581785254 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 1604483620 ps |
| CPU time | 37.8 seconds |
| Started | Sep 04 12:46:00 PM UTC 24 |
| Finished | Sep 04 12:46:40 PM UTC 24 |
| Peak memory | 262060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581785254 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.2581785254 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/4.kmac_app_with_partial_data.578020304 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 69935927041 ps |
| CPU time | 278.81 seconds |
| Started | Sep 04 12:46:02 PM UTC 24 |
| Finished | Sep 04 12:50:46 PM UTC 24 |
| Peak memory | 491368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578020304 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.578020304 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/4.kmac_burst_write.724298854 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 4374448015 ps |
| CPU time | 433.46 seconds |
| Started | Sep 04 12:45:09 PM UTC 24 |
| Finished | Sep 04 12:52:29 PM UTC 24 |
| Peak memory | 243428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724298854 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.724298854 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/4.kmac_edn_timeout_error.2829034659 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 161121209 ps |
| CPU time | 15.42 seconds |
| Started | Sep 04 12:46:05 PM UTC 24 |
| Finished | Sep 04 12:46:21 PM UTC 24 |
| Peak memory | 230316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829034659 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.2829034659 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_mode_error.2697576193 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 123091233 ps |
| CPU time | 4.77 seconds |
| Started | Sep 04 12:46:13 PM UTC 24 |
| Finished | Sep 04 12:46:19 PM UTC 24 |
| Peak memory | 228296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697576193 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.2697576193 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_ready_error.1400519152 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 4599474375 ps |
| CPU time | 40.51 seconds |
| Started | Sep 04 12:46:13 PM UTC 24 |
| Finished | Sep 04 12:46:55 PM UTC 24 |
| Peak memory | 230532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400519152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.1400519152 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_refresh.1117249547 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 105354887662 ps |
| CPU time | 339.99 seconds |
| Started | Sep 04 12:46:05 PM UTC 24 |
| Finished | Sep 04 12:51:50 PM UTC 24 |
| Peak memory | 499496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117249547 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.1117249547 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/4.kmac_error.2046922993 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 59677246993 ps |
| CPU time | 182.75 seconds |
| Started | Sep 04 12:46:05 PM UTC 24 |
| Finished | Sep 04 12:49:11 PM UTC 24 |
| Peak memory | 378864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046922993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.2046922993 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/4.kmac_key_error.925250576 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 7005025735 ps |
| CPU time | 14.18 seconds |
| Started | Sep 04 12:46:05 PM UTC 24 |
| Finished | Sep 04 12:46:20 PM UTC 24 |
| Peak memory | 230452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925250576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.925250576 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/4.kmac_lc_escalation.3705559998 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 556747120 ps |
| CPU time | 17.16 seconds |
| Started | Sep 04 12:46:13 PM UTC 24 |
| Finished | Sep 04 12:46:32 PM UTC 24 |
| Peak memory | 247596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705559998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.3705559998 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/4.kmac_long_msg_and_output.2883931545 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 23154064801 ps |
| CPU time | 2483.02 seconds |
| Started | Sep 04 12:44:51 PM UTC 24 |
| Finished | Sep 04 01:26:52 PM UTC 24 |
| Peak memory | 1674748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883931545 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and_output.2883931545 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/4.kmac_mubi.3662564692 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 3509850977 ps |
| CPU time | 65.52 seconds |
| Started | Sep 04 12:46:05 PM UTC 24 |
| Finished | Sep 04 12:47:12 PM UTC 24 |
| Peak memory | 286828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662564692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.3662564692 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/4.kmac_sec_cm.3338602822 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 58422151769 ps |
| CPU time | 105.33 seconds |
| Started | Sep 04 12:46:16 PM UTC 24 |
| Finished | Sep 04 12:48:05 PM UTC 24 |
| Peak memory | 295784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338602822 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.3338602822 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/4.kmac_sideload.1817811298 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 560004775 ps |
| CPU time | 53.82 seconds |
| Started | Sep 04 12:44:52 PM UTC 24 |
| Finished | Sep 04 12:45:47 PM UTC 24 |
| Peak memory | 245196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817811298 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.1817811298 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/4.kmac_smoke.2764574475 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 5221384076 ps |
| CPU time | 52.91 seconds |
| Started | Sep 04 12:44:43 PM UTC 24 |
| Finished | Sep 04 12:45:38 PM UTC 24 |
| Peak memory | 230772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764574475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.2764574475 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/4.kmac_stress_all.1357917634 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 381070984359 ps |
| CPU time | 2934.74 seconds |
| Started | Sep 04 12:46:13 PM UTC 24 |
| Finished | Sep 04 01:35:41 PM UTC 24 |
| Peak memory | 2115832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357917634 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.1357917634 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac.2184454802 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 106891390 ps |
| CPU time | 2.64 seconds |
| Started | Sep 04 12:45:58 PM UTC 24 |
| Finished | Sep 04 12:46:02 PM UTC 24 |
| Peak memory | 230540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184454802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac.2184454802 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac_xof.4052336212 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 79466371 ps |
| CPU time | 2.79 seconds |
| Started | Sep 04 12:46:00 PM UTC 24 |
| Finished | Sep 04 12:46:04 PM UTC 24 |
| Peak memory | 230476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052336212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac_xof.4052336212 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_224.4104446719 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 646777776 ps |
| CPU time | 38.66 seconds |
| Started | Sep 04 12:45:19 PM UTC 24 |
| Finished | Sep 04 12:45:59 PM UTC 24 |
| Peak memory | 232696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104446719 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.4104446719 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_256.3212985873 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 4619418856 ps |
| CPU time | 43.86 seconds |
| Started | Sep 04 12:45:23 PM UTC 24 |
| Finished | Sep 04 12:46:08 PM UTC 24 |
| Peak memory | 253596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212985873 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.3212985873 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_384.3553325566 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 2286447285 ps |
| CPU time | 28.15 seconds |
| Started | Sep 04 12:45:32 PM UTC 24 |
| Finished | Sep 04 12:46:02 PM UTC 24 |
| Peak memory | 237276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553325566 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.3553325566 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_512.3459035502 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 995972392 ps |
| CPU time | 15.3 seconds |
| Started | Sep 04 12:45:40 PM UTC 24 |
| Finished | Sep 04 12:45:57 PM UTC 24 |
| Peak memory | 228668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459035502 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.3459035502 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_128.530865008 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 10028588152 ps |
| CPU time | 245.59 seconds |
| Started | Sep 04 12:45:48 PM UTC 24 |
| Finished | Sep 04 12:49:58 PM UTC 24 |
| Peak memory | 437900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530865008 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.53086500 8 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_256.1878437573 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 20437140438 ps |
| CPU time | 355.57 seconds |
| Started | Sep 04 12:45:56 PM UTC 24 |
| Finished | Sep 04 12:51:57 PM UTC 24 |
| Peak memory | 362332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878437573 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.1878437 573 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/4.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/40.kmac_alert_test.919574432 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 56016442 ps |
| CPU time | 1.24 seconds |
| Started | Sep 04 01:19:38 PM UTC 24 |
| Finished | Sep 04 01:19:41 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919574432 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.919574432 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/40.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/40.kmac_app.1097300531 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 759169316 ps |
| CPU time | 17.41 seconds |
| Started | Sep 04 01:19:18 PM UTC 24 |
| Finished | Sep 04 01:19:37 PM UTC 24 |
| Peak memory | 230660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097300531 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.1097300531 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/40.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/40.kmac_burst_write.3866389790 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 106925489206 ps |
| CPU time | 1048.02 seconds |
| Started | Sep 04 01:19:11 PM UTC 24 |
| Finished | Sep 04 01:36:51 PM UTC 24 |
| Peak memory | 268200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866389790 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.3866389790 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/40.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/40.kmac_entropy_refresh.276573400 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 24293491294 ps |
| CPU time | 343.06 seconds |
| Started | Sep 04 01:19:20 PM UTC 24 |
| Finished | Sep 04 01:25:08 PM UTC 24 |
| Peak memory | 466864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276573400 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.276573400 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/40.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/40.kmac_error.524567546 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 3002487812 ps |
| CPU time | 261.88 seconds |
| Started | Sep 04 01:19:30 PM UTC 24 |
| Finished | Sep 04 01:23:56 PM UTC 24 |
| Peak memory | 335732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524567546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.524567546 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/40.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/40.kmac_key_error.4257445389 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 1707402334 ps |
| CPU time | 14.92 seconds |
| Started | Sep 04 01:19:30 PM UTC 24 |
| Finished | Sep 04 01:19:46 PM UTC 24 |
| Peak memory | 230392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257445389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.4257445389 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/40.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/40.kmac_long_msg_and_output.4248351812 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 146052973398 ps |
| CPU time | 3141.57 seconds |
| Started | Sep 04 01:18:56 PM UTC 24 |
| Finished | Sep 04 02:11:52 PM UTC 24 |
| Peak memory | 3602300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248351812 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_and_output.4248351812 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/40.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/40.kmac_sideload.1505618619 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 68561048072 ps |
| CPU time | 288.57 seconds |
| Started | Sep 04 01:18:59 PM UTC 24 |
| Finished | Sep 04 01:23:52 PM UTC 24 |
| Peak memory | 415664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505618619 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.1505618619 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/40.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/40.kmac_smoke.2116896584 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 1673927122 ps |
| CPU time | 24.06 seconds |
| Started | Sep 04 01:18:53 PM UTC 24 |
| Finished | Sep 04 01:19:18 PM UTC 24 |
| Peak memory | 230528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116896584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.2116896584 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/40.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/40.kmac_stress_all.1189192441 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 59379987191 ps |
| CPU time | 650.29 seconds |
| Started | Sep 04 01:19:35 PM UTC 24 |
| Finished | Sep 04 01:30:33 PM UTC 24 |
| Peak memory | 897012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189192441 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.1189192441 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/40.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/41.kmac_alert_test.2486378458 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 70612747 ps |
| CPU time | 0.96 seconds |
| Started | Sep 04 01:20:50 PM UTC 24 |
| Finished | Sep 04 01:20:52 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486378458 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.2486378458 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/41.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/41.kmac_app.1167452852 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 145275259843 ps |
| CPU time | 241.81 seconds |
| Started | Sep 04 01:19:54 PM UTC 24 |
| Finished | Sep 04 01:24:00 PM UTC 24 |
| Peak memory | 448308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167452852 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.1167452852 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/41.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/41.kmac_burst_write.3178016401 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 16659669486 ps |
| CPU time | 520.48 seconds |
| Started | Sep 04 01:19:47 PM UTC 24 |
| Finished | Sep 04 01:28:34 PM UTC 24 |
| Peak memory | 251624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178016401 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.3178016401 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/41.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/41.kmac_entropy_refresh.4043753531 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 47221927365 ps |
| CPU time | 197.22 seconds |
| Started | Sep 04 01:20:00 PM UTC 24 |
| Finished | Sep 04 01:23:21 PM UTC 24 |
| Peak memory | 415476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043753531 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.4043753531 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/41.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/41.kmac_error.1597144974 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 75933266128 ps |
| CPU time | 320.13 seconds |
| Started | Sep 04 01:20:09 PM UTC 24 |
| Finished | Sep 04 01:25:33 PM UTC 24 |
| Peak memory | 546588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597144974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.1597144974 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/41.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/41.kmac_key_error.3962541642 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 1068151483 ps |
| CPU time | 10.51 seconds |
| Started | Sep 04 01:20:12 PM UTC 24 |
| Finished | Sep 04 01:20:23 PM UTC 24 |
| Peak memory | 230380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962541642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.3962541642 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/41.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/41.kmac_lc_escalation.3475328182 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 393997769 ps |
| CPU time | 14.53 seconds |
| Started | Sep 04 01:20:24 PM UTC 24 |
| Finished | Sep 04 01:20:39 PM UTC 24 |
| Peak memory | 245672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475328182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.3475328182 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/41.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/41.kmac_long_msg_and_output.3887485870 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 337560758753 ps |
| CPU time | 3695.45 seconds |
| Started | Sep 04 01:19:41 PM UTC 24 |
| Finished | Sep 04 02:21:58 PM UTC 24 |
| Peak memory | 3999616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887485870 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_and_output.3887485870 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/41.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/41.kmac_sideload.4107913612 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 3198650559 ps |
| CPU time | 147.71 seconds |
| Started | Sep 04 01:19:47 PM UTC 24 |
| Finished | Sep 04 01:22:18 PM UTC 24 |
| Peak memory | 284460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107913612 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.4107913612 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/41.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/41.kmac_smoke.1103608993 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 713536065 ps |
| CPU time | 11.76 seconds |
| Started | Sep 04 01:19:41 PM UTC 24 |
| Finished | Sep 04 01:19:54 PM UTC 24 |
| Peak memory | 230924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103608993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.1103608993 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/41.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/41.kmac_stress_all.908267168 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 9684620454 ps |
| CPU time | 201.14 seconds |
| Started | Sep 04 01:20:40 PM UTC 24 |
| Finished | Sep 04 01:24:04 PM UTC 24 |
| Peak memory | 383024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908267168 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.908267168 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/41.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/42.kmac_alert_test.4000900347 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 41783436 ps |
| CPU time | 1.17 seconds |
| Started | Sep 04 01:22:06 PM UTC 24 |
| Finished | Sep 04 01:22:08 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000900347 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.4000900347 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/42.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/42.kmac_app.80375197 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 1240782149 ps |
| CPU time | 89.59 seconds |
| Started | Sep 04 01:21:02 PM UTC 24 |
| Finished | Sep 04 01:22:33 PM UTC 24 |
| Peak memory | 259948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80375197 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.80375197 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/42.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/42.kmac_burst_write.4222491919 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 34856426961 ps |
| CPU time | 1268.28 seconds |
| Started | Sep 04 01:21:02 PM UTC 24 |
| Finished | Sep 04 01:42:26 PM UTC 24 |
| Peak memory | 272108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222491919 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.4222491919 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/42.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/42.kmac_entropy_refresh.437993020 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 5732506854 ps |
| CPU time | 154.96 seconds |
| Started | Sep 04 01:21:25 PM UTC 24 |
| Finished | Sep 04 01:24:03 PM UTC 24 |
| Peak memory | 278388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437993020 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.437993020 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/42.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/42.kmac_error.2621579372 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 833296290 ps |
| CPU time | 51.8 seconds |
| Started | Sep 04 01:21:29 PM UTC 24 |
| Finished | Sep 04 01:22:23 PM UTC 24 |
| Peak memory | 268088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621579372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.2621579372 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/42.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/42.kmac_key_error.30805381 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 1742798919 ps |
| CPU time | 9.5 seconds |
| Started | Sep 04 01:21:41 PM UTC 24 |
| Finished | Sep 04 01:21:52 PM UTC 24 |
| Peak memory | 230632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30805381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.30805381 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/42.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/42.kmac_lc_escalation.433279357 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 43016780 ps |
| CPU time | 1.9 seconds |
| Started | Sep 04 01:21:52 PM UTC 24 |
| Finished | Sep 04 01:21:55 PM UTC 24 |
| Peak memory | 229868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433279357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.433279357 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/42.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/42.kmac_long_msg_and_output.667958699 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 113414185762 ps |
| CPU time | 1457.39 seconds |
| Started | Sep 04 01:20:55 PM UTC 24 |
| Finished | Sep 04 01:45:30 PM UTC 24 |
| Peak memory | 1939244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667958699 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_and_output.667958699 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/42.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/42.kmac_sideload.1426247364 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 13922791944 ps |
| CPU time | 407.35 seconds |
| Started | Sep 04 01:20:57 PM UTC 24 |
| Finished | Sep 04 01:27:50 PM UTC 24 |
| Peak memory | 585508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426247364 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.1426247364 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/42.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/42.kmac_smoke.3703427272 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 2751950529 ps |
| CPU time | 78.95 seconds |
| Started | Sep 04 01:20:53 PM UTC 24 |
| Finished | Sep 04 01:22:14 PM UTC 24 |
| Peak memory | 232624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703427272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.3703427272 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/42.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/42.kmac_stress_all.276199709 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 31146479471 ps |
| CPU time | 367.85 seconds |
| Started | Sep 04 01:21:56 PM UTC 24 |
| Finished | Sep 04 01:28:09 PM UTC 24 |
| Peak memory | 241448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276199709 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.276199709 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/42.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/43.kmac_alert_test.3917486074 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 36815774 ps |
| CPU time | 1.12 seconds |
| Started | Sep 04 01:23:24 PM UTC 24 |
| Finished | Sep 04 01:23:27 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917486074 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.3917486074 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/43.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/43.kmac_app.4171080521 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 3433387340 ps |
| CPU time | 112.34 seconds |
| Started | Sep 04 01:22:28 PM UTC 24 |
| Finished | Sep 04 01:24:23 PM UTC 24 |
| Peak memory | 300856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171080521 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.4171080521 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/43.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/43.kmac_burst_write.3643629067 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 35288168900 ps |
| CPU time | 964.02 seconds |
| Started | Sep 04 01:22:24 PM UTC 24 |
| Finished | Sep 04 01:38:40 PM UTC 24 |
| Peak memory | 251692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643629067 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.3643629067 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/43.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/43.kmac_entropy_refresh.668957369 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 11446316261 ps |
| CPU time | 56.98 seconds |
| Started | Sep 04 01:22:32 PM UTC 24 |
| Finished | Sep 04 01:23:31 PM UTC 24 |
| Peak memory | 259868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668957369 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.668957369 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/43.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/43.kmac_error.4169094766 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 979659565 ps |
| CPU time | 48.92 seconds |
| Started | Sep 04 01:22:34 PM UTC 24 |
| Finished | Sep 04 01:23:24 PM UTC 24 |
| Peak memory | 251880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169094766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.4169094766 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/43.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/43.kmac_key_error.325091215 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 2527227908 ps |
| CPU time | 6.78 seconds |
| Started | Sep 04 01:23:10 PM UTC 24 |
| Finished | Sep 04 01:23:18 PM UTC 24 |
| Peak memory | 230524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325091215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.325091215 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/43.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/43.kmac_lc_escalation.2985539569 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 60762508 ps |
| CPU time | 3.03 seconds |
| Started | Sep 04 01:23:19 PM UTC 24 |
| Finished | Sep 04 01:23:23 PM UTC 24 |
| Peak memory | 235300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985539569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.2985539569 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/43.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/43.kmac_long_msg_and_output.4285497467 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 4686329285 ps |
| CPU time | 410.69 seconds |
| Started | Sep 04 01:22:15 PM UTC 24 |
| Finished | Sep 04 01:29:11 PM UTC 24 |
| Peak memory | 524072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285497467 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_and_output.4285497467 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/43.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/43.kmac_sideload.3700702900 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 3673290365 ps |
| CPU time | 106.07 seconds |
| Started | Sep 04 01:22:19 PM UTC 24 |
| Finished | Sep 04 01:24:07 PM UTC 24 |
| Peak memory | 327476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700702900 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.3700702900 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/43.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/43.kmac_smoke.1667315031 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 3361687174 ps |
| CPU time | 20.45 seconds |
| Started | Sep 04 01:22:09 PM UTC 24 |
| Finished | Sep 04 01:22:31 PM UTC 24 |
| Peak memory | 230872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667315031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.1667315031 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/43.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/43.kmac_stress_all.1612094411 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 35439741594 ps |
| CPU time | 366.64 seconds |
| Started | Sep 04 01:23:21 PM UTC 24 |
| Finished | Sep 04 01:29:33 PM UTC 24 |
| Peak memory | 344116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612094411 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.1612094411 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/43.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/44.kmac_alert_test.1865503956 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 79874900 ps |
| CPU time | 1.26 seconds |
| Started | Sep 04 01:24:07 PM UTC 24 |
| Finished | Sep 04 01:24:10 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865503956 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.1865503956 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/44.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/44.kmac_app.2447221252 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 42081248244 ps |
| CPU time | 291.33 seconds |
| Started | Sep 04 01:23:43 PM UTC 24 |
| Finished | Sep 04 01:28:39 PM UTC 24 |
| Peak memory | 440240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447221252 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.2447221252 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/44.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/44.kmac_burst_write.4126028806 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 38224863015 ps |
| CPU time | 757.31 seconds |
| Started | Sep 04 01:23:34 PM UTC 24 |
| Finished | Sep 04 01:36:20 PM UTC 24 |
| Peak memory | 260076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126028806 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.4126028806 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/44.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/44.kmac_entropy_refresh.1125947763 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 17947825543 ps |
| CPU time | 145.39 seconds |
| Started | Sep 04 01:23:53 PM UTC 24 |
| Finished | Sep 04 01:26:21 PM UTC 24 |
| Peak memory | 372728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125947763 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.1125947763 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/44.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/44.kmac_error.1297819942 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 2667880220 ps |
| CPU time | 233.99 seconds |
| Started | Sep 04 01:23:56 PM UTC 24 |
| Finished | Sep 04 01:27:54 PM UTC 24 |
| Peak memory | 321472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297819942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.1297819942 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/44.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/44.kmac_key_error.3519110445 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 12668805480 ps |
| CPU time | 15.63 seconds |
| Started | Sep 04 01:24:00 PM UTC 24 |
| Finished | Sep 04 01:24:17 PM UTC 24 |
| Peak memory | 232428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519110445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.3519110445 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/44.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/44.kmac_lc_escalation.3503388182 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 2312645438 ps |
| CPU time | 6.91 seconds |
| Started | Sep 04 01:24:03 PM UTC 24 |
| Finished | Sep 04 01:24:11 PM UTC 24 |
| Peak memory | 240896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503388182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.3503388182 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/44.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/44.kmac_long_msg_and_output.323111143 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 121268675031 ps |
| CPU time | 2757.57 seconds |
| Started | Sep 04 01:23:28 PM UTC 24 |
| Finished | Sep 04 02:09:57 PM UTC 24 |
| Peak memory | 3137328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323111143 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_and_output.323111143 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/44.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/44.kmac_sideload.857112482 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 18112819078 ps |
| CPU time | 308.18 seconds |
| Started | Sep 04 01:23:32 PM UTC 24 |
| Finished | Sep 04 01:28:44 PM UTC 24 |
| Peak memory | 376620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857112482 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.857112482 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/44.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/44.kmac_smoke.2515389099 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 2199679100 ps |
| CPU time | 63.28 seconds |
| Started | Sep 04 01:23:25 PM UTC 24 |
| Finished | Sep 04 01:24:31 PM UTC 24 |
| Peak memory | 230576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515389099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.2515389099 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/44.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/44.kmac_stress_all.1302298954 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 37834673887 ps |
| CPU time | 468.18 seconds |
| Started | Sep 04 01:24:05 PM UTC 24 |
| Finished | Sep 04 01:32:00 PM UTC 24 |
| Peak memory | 344140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302298954 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.1302298954 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/44.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/45.kmac_alert_test.3780041947 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 15150218 ps |
| CPU time | 1.19 seconds |
| Started | Sep 04 01:25:28 PM UTC 24 |
| Finished | Sep 04 01:25:30 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780041947 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.3780041947 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/45.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/45.kmac_app.3183993389 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 5124737899 ps |
| CPU time | 399.84 seconds |
| Started | Sep 04 01:24:32 PM UTC 24 |
| Finished | Sep 04 01:31:18 PM UTC 24 |
| Peak memory | 364512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183993389 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.3183993389 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/45.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/45.kmac_burst_write.3053277387 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 4054447935 ps |
| CPU time | 172.38 seconds |
| Started | Sep 04 01:24:24 PM UTC 24 |
| Finished | Sep 04 01:27:19 PM UTC 24 |
| Peak memory | 237352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053277387 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.3053277387 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/45.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/45.kmac_entropy_refresh.1235457458 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 29767703282 ps |
| CPU time | 115.73 seconds |
| Started | Sep 04 01:25:08 PM UTC 24 |
| Finished | Sep 04 01:27:07 PM UTC 24 |
| Peak memory | 290676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235457458 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.1235457458 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/45.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/45.kmac_error.1245474561 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 15179856792 ps |
| CPU time | 196.86 seconds |
| Started | Sep 04 01:25:10 PM UTC 24 |
| Finished | Sep 04 01:28:31 PM UTC 24 |
| Peak memory | 378676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245474561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.1245474561 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/45.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/45.kmac_key_error.1270629247 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 1910124280 ps |
| CPU time | 12.4 seconds |
| Started | Sep 04 01:25:13 PM UTC 24 |
| Finished | Sep 04 01:25:27 PM UTC 24 |
| Peak memory | 230388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270629247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.1270629247 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/45.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/45.kmac_lc_escalation.1591002768 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 57022589 ps |
| CPU time | 2.29 seconds |
| Started | Sep 04 01:25:16 PM UTC 24 |
| Finished | Sep 04 01:25:20 PM UTC 24 |
| Peak memory | 230380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591002768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.1591002768 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/45.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/45.kmac_long_msg_and_output.2871004181 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 7634665489 ps |
| CPU time | 676.77 seconds |
| Started | Sep 04 01:24:12 PM UTC 24 |
| Finished | Sep 04 01:35:37 PM UTC 24 |
| Peak memory | 716768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871004181 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_and_output.2871004181 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/45.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/45.kmac_sideload.2907565106 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 24537305476 ps |
| CPU time | 317.92 seconds |
| Started | Sep 04 01:24:18 PM UTC 24 |
| Finished | Sep 04 01:29:40 PM UTC 24 |
| Peak memory | 505592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907565106 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.2907565106 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/45.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/45.kmac_smoke.464874897 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 8731021589 ps |
| CPU time | 60.46 seconds |
| Started | Sep 04 01:24:11 PM UTC 24 |
| Finished | Sep 04 01:25:13 PM UTC 24 |
| Peak memory | 235168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464874897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.464874897 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/45.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/45.kmac_stress_all.2208586933 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 63690750112 ps |
| CPU time | 1129.34 seconds |
| Started | Sep 04 01:25:20 PM UTC 24 |
| Finished | Sep 04 01:44:23 PM UTC 24 |
| Peak memory | 802880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208586933 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.2208586933 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/45.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/46.kmac_alert_test.3600957636 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 11761890 ps |
| CPU time | 1.11 seconds |
| Started | Sep 04 01:27:29 PM UTC 24 |
| Finished | Sep 04 01:27:31 PM UTC 24 |
| Peak memory | 216232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600957636 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.3600957636 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/46.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/46.kmac_app.813505076 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 6356116816 ps |
| CPU time | 108.07 seconds |
| Started | Sep 04 01:26:49 PM UTC 24 |
| Finished | Sep 04 01:28:40 PM UTC 24 |
| Peak memory | 307176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813505076 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.813505076 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/46.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/46.kmac_burst_write.721473973 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 127290908887 ps |
| CPU time | 1153.9 seconds |
| Started | Sep 04 01:26:27 PM UTC 24 |
| Finished | Sep 04 01:45:56 PM UTC 24 |
| Peak memory | 274216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721473973 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.721473973 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/46.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/46.kmac_entropy_refresh.2715191663 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 3575068713 ps |
| CPU time | 40.71 seconds |
| Started | Sep 04 01:26:53 PM UTC 24 |
| Finished | Sep 04 01:27:35 PM UTC 24 |
| Peak memory | 249632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715191663 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.2715191663 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/46.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/46.kmac_error.65648870 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 4844433818 ps |
| CPU time | 79.84 seconds |
| Started | Sep 04 01:27:08 PM UTC 24 |
| Finished | Sep 04 01:28:29 PM UTC 24 |
| Peak memory | 278316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65648870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.65648870 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/46.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/46.kmac_key_error.2930366438 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 991700549 ps |
| CPU time | 3.44 seconds |
| Started | Sep 04 01:27:20 PM UTC 24 |
| Finished | Sep 04 01:27:24 PM UTC 24 |
| Peak memory | 230604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930366438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.2930366438 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/46.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/46.kmac_lc_escalation.3010116072 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 207496030 ps |
| CPU time | 2.05 seconds |
| Started | Sep 04 01:27:25 PM UTC 24 |
| Finished | Sep 04 01:27:28 PM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010116072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.3010116072 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/46.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/46.kmac_long_msg_and_output.280207023 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 402016853026 ps |
| CPU time | 3448.06 seconds |
| Started | Sep 04 01:25:34 PM UTC 24 |
| Finished | Sep 04 02:23:39 PM UTC 24 |
| Peak memory | 3983580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280207023 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_and_output.280207023 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/46.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/46.kmac_sideload.1606770120 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 4199520293 ps |
| CPU time | 193.8 seconds |
| Started | Sep 04 01:26:22 PM UTC 24 |
| Finished | Sep 04 01:29:39 PM UTC 24 |
| Peak memory | 311084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606770120 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.1606770120 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/46.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/46.kmac_smoke.3807930024 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 6129804891 ps |
| CPU time | 74.56 seconds |
| Started | Sep 04 01:25:32 PM UTC 24 |
| Finished | Sep 04 01:26:48 PM UTC 24 |
| Peak memory | 235248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807930024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.3807930024 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/46.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/46.kmac_stress_all.734578064 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 16220984335 ps |
| CPU time | 105.39 seconds |
| Started | Sep 04 01:27:29 PM UTC 24 |
| Finished | Sep 04 01:29:17 PM UTC 24 |
| Peak memory | 298844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734578064 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.734578064 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/46.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/47.kmac_alert_test.309385852 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 104209827 ps |
| CPU time | 1.26 seconds |
| Started | Sep 04 01:28:39 PM UTC 24 |
| Finished | Sep 04 01:28:42 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309385852 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.309385852 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/47.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/47.kmac_app.3746504592 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 10310221774 ps |
| CPU time | 272.33 seconds |
| Started | Sep 04 01:27:54 PM UTC 24 |
| Finished | Sep 04 01:32:31 PM UTC 24 |
| Peak memory | 477048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746504592 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.3746504592 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/47.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/47.kmac_burst_write.3093768232 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 36341871187 ps |
| CPU time | 308.36 seconds |
| Started | Sep 04 01:27:51 PM UTC 24 |
| Finished | Sep 04 01:33:04 PM UTC 24 |
| Peak memory | 241400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093768232 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.3093768232 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/47.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/47.kmac_entropy_refresh.1200117292 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 26606221406 ps |
| CPU time | 152.57 seconds |
| Started | Sep 04 01:28:11 PM UTC 24 |
| Finished | Sep 04 01:30:46 PM UTC 24 |
| Peak memory | 315360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200117292 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.1200117292 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/47.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/47.kmac_error.2491934776 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 4549694314 ps |
| CPU time | 381.87 seconds |
| Started | Sep 04 01:28:30 PM UTC 24 |
| Finished | Sep 04 01:34:57 PM UTC 24 |
| Peak memory | 380716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491934776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.2491934776 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/47.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/47.kmac_key_error.2289252703 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 1176756578 ps |
| CPU time | 7.33 seconds |
| Started | Sep 04 01:28:32 PM UTC 24 |
| Finished | Sep 04 01:28:40 PM UTC 24 |
| Peak memory | 230652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289252703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.2289252703 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/47.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/47.kmac_lc_escalation.1654444363 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 139092928 ps |
| CPU time | 1.62 seconds |
| Started | Sep 04 01:28:35 PM UTC 24 |
| Finished | Sep 04 01:28:38 PM UTC 24 |
| Peak memory | 231724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654444363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.1654444363 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/47.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/47.kmac_long_msg_and_output.2478785168 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 25763484304 ps |
| CPU time | 2929.29 seconds |
| Started | Sep 04 01:27:32 PM UTC 24 |
| Finished | Sep 04 02:16:57 PM UTC 24 |
| Peak memory | 1789984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478785168 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_and_output.2478785168 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/47.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/47.kmac_sideload.2291522478 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 16702319927 ps |
| CPU time | 370.8 seconds |
| Started | Sep 04 01:27:36 PM UTC 24 |
| Finished | Sep 04 01:33:52 PM UTC 24 |
| Peak memory | 392932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291522478 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.2291522478 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/47.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/47.kmac_smoke.3269670169 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 35178949219 ps |
| CPU time | 74.51 seconds |
| Started | Sep 04 01:27:31 PM UTC 24 |
| Finished | Sep 04 01:28:47 PM UTC 24 |
| Peak memory | 234692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269670169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.3269670169 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/47.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/47.kmac_stress_all.3475759616 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 194528033693 ps |
| CPU time | 1044.57 seconds |
| Started | Sep 04 01:28:36 PM UTC 24 |
| Finished | Sep 04 01:46:14 PM UTC 24 |
| Peak memory | 1126192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475759616 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.3475759616 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/47.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/48.kmac_alert_test.959606910 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 17241321 ps |
| CPU time | 1.23 seconds |
| Started | Sep 04 01:29:16 PM UTC 24 |
| Finished | Sep 04 01:29:18 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959606910 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.959606910 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/48.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/48.kmac_app.3633714760 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 3204395374 ps |
| CPU time | 171.89 seconds |
| Started | Sep 04 01:28:45 PM UTC 24 |
| Finished | Sep 04 01:31:40 PM UTC 24 |
| Peak memory | 311336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633714760 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.3633714760 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/48.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/48.kmac_burst_write.3948198909 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 32442578317 ps |
| CPU time | 597.97 seconds |
| Started | Sep 04 01:28:42 PM UTC 24 |
| Finished | Sep 04 01:38:48 PM UTC 24 |
| Peak memory | 249632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948198909 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.3948198909 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/48.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/48.kmac_entropy_refresh.1113331994 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 17206246553 ps |
| CPU time | 184.56 seconds |
| Started | Sep 04 01:28:49 PM UTC 24 |
| Finished | Sep 04 01:31:56 PM UTC 24 |
| Peak memory | 290532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113331994 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.1113331994 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/48.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/48.kmac_error.3466829205 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 7827477037 ps |
| CPU time | 82.8 seconds |
| Started | Sep 04 01:29:00 PM UTC 24 |
| Finished | Sep 04 01:30:24 PM UTC 24 |
| Peak memory | 278304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466829205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.3466829205 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/48.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/48.kmac_key_error.126559700 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 1223115071 ps |
| CPU time | 3.63 seconds |
| Started | Sep 04 01:29:10 PM UTC 24 |
| Finished | Sep 04 01:29:15 PM UTC 24 |
| Peak memory | 230392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126559700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.126559700 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/48.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/48.kmac_lc_escalation.156414505 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 48420807 ps |
| CPU time | 1.86 seconds |
| Started | Sep 04 01:29:12 PM UTC 24 |
| Finished | Sep 04 01:29:15 PM UTC 24 |
| Peak memory | 229872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156414505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.156414505 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/48.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/48.kmac_long_msg_and_output.2119054474 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 2659668352 ps |
| CPU time | 248.1 seconds |
| Started | Sep 04 01:28:41 PM UTC 24 |
| Finished | Sep 04 01:32:53 PM UTC 24 |
| Peak memory | 393184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119054474 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_and_output.2119054474 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/48.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/48.kmac_sideload.3028112581 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 59350081575 ps |
| CPU time | 268.18 seconds |
| Started | Sep 04 01:28:41 PM UTC 24 |
| Finished | Sep 04 01:33:14 PM UTC 24 |
| Peak memory | 444136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028112581 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.3028112581 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/48.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/48.kmac_smoke.1137370822 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 3380885834 ps |
| CPU time | 46.33 seconds |
| Started | Sep 04 01:28:40 PM UTC 24 |
| Finished | Sep 04 01:29:28 PM UTC 24 |
| Peak memory | 230768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137370822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.1137370822 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/48.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/48.kmac_stress_all.2009378895 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 63264733795 ps |
| CPU time | 1757.4 seconds |
| Started | Sep 04 01:29:15 PM UTC 24 |
| Finished | Sep 04 01:58:53 PM UTC 24 |
| Peak memory | 1400820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009378895 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.2009378895 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/48.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/49.kmac_alert_test.2708270823 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 36693226 ps |
| CPU time | 1.17 seconds |
| Started | Sep 04 01:30:25 PM UTC 24 |
| Finished | Sep 04 01:30:27 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708270823 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.2708270823 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/49.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/49.kmac_app.2815446257 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 7912538745 ps |
| CPU time | 137.29 seconds |
| Started | Sep 04 01:29:35 PM UTC 24 |
| Finished | Sep 04 01:31:54 PM UTC 24 |
| Peak memory | 356396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815446257 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.2815446257 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/49.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/49.kmac_burst_write.2334000839 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 146735073353 ps |
| CPU time | 1211.19 seconds |
| Started | Sep 04 01:29:30 PM UTC 24 |
| Finished | Sep 04 01:49:56 PM UTC 24 |
| Peak memory | 274228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334000839 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.2334000839 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/49.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/49.kmac_entropy_refresh.701092351 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 2154494588 ps |
| CPU time | 91.87 seconds |
| Started | Sep 04 01:29:41 PM UTC 24 |
| Finished | Sep 04 01:31:15 PM UTC 24 |
| Peak memory | 264148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701092351 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.701092351 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/49.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/49.kmac_error.4046677384 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 3728544004 ps |
| CPU time | 285.26 seconds |
| Started | Sep 04 01:29:41 PM UTC 24 |
| Finished | Sep 04 01:34:30 PM UTC 24 |
| Peak memory | 366328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046677384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.4046677384 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/49.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/49.kmac_key_error.1275269437 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 2471579718 ps |
| CPU time | 2.55 seconds |
| Started | Sep 04 01:30:00 PM UTC 24 |
| Finished | Sep 04 01:30:04 PM UTC 24 |
| Peak memory | 230444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275269437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.1275269437 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/49.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/49.kmac_lc_escalation.1496588101 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 143267119 ps |
| CPU time | 1.76 seconds |
| Started | Sep 04 01:30:05 PM UTC 24 |
| Finished | Sep 04 01:30:08 PM UTC 24 |
| Peak memory | 233760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496588101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.1496588101 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/49.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/49.kmac_long_msg_and_output.108173462 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 39309734474 ps |
| CPU time | 511.65 seconds |
| Started | Sep 04 01:29:19 PM UTC 24 |
| Finished | Sep 04 01:37:57 PM UTC 24 |
| Peak memory | 935688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108173462 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_and_output.108173462 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/49.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/49.kmac_sideload.1928220129 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 12499981315 ps |
| CPU time | 112.02 seconds |
| Started | Sep 04 01:29:29 PM UTC 24 |
| Finished | Sep 04 01:31:24 PM UTC 24 |
| Peak memory | 304944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928220129 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.1928220129 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/49.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/49.kmac_smoke.2708883867 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 171315136 ps |
| CPU time | 11.18 seconds |
| Started | Sep 04 01:29:17 PM UTC 24 |
| Finished | Sep 04 01:29:29 PM UTC 24 |
| Peak memory | 230716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708883867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.2708883867 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/49.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/49.kmac_stress_all.3131535780 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 12420229350 ps |
| CPU time | 63.6 seconds |
| Started | Sep 04 01:30:09 PM UTC 24 |
| Finished | Sep 04 01:31:15 PM UTC 24 |
| Peak memory | 280604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131535780 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.3131535780 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/49.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/5.kmac_alert_test.3774596854 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 47434693 ps |
| CPU time | 1.15 seconds |
| Started | Sep 04 12:47:00 PM UTC 24 |
| Finished | Sep 04 12:47:03 PM UTC 24 |
| Peak memory | 216284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774596854 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.3774596854 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/5.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/5.kmac_app.2002142013 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 2942516517 ps |
| CPU time | 141.23 seconds |
| Started | Sep 04 12:46:22 PM UTC 24 |
| Finished | Sep 04 12:48:46 PM UTC 24 |
| Peak memory | 282484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002142013 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.2002142013 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/5.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/5.kmac_app_with_partial_data.1266290068 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 163913602737 ps |
| CPU time | 396.67 seconds |
| Started | Sep 04 12:46:23 PM UTC 24 |
| Finished | Sep 04 12:53:06 PM UTC 24 |
| Peak memory | 515828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266290068 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.1266290068 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/5.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/5.kmac_burst_write.4229202099 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 7995074903 ps |
| CPU time | 774.69 seconds |
| Started | Sep 04 12:46:21 PM UTC 24 |
| Finished | Sep 04 12:59:26 PM UTC 24 |
| Peak memory | 251700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229202099 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.4229202099 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/5.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/5.kmac_edn_timeout_error.4126093001 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 2022777642 ps |
| CPU time | 13.73 seconds |
| Started | Sep 04 12:46:49 PM UTC 24 |
| Finished | Sep 04 12:47:04 PM UTC 24 |
| Peak memory | 232364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126093001 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.4126093001 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/5.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_mode_error.302363692 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 253316195 ps |
| CPU time | 20.08 seconds |
| Started | Sep 04 12:46:51 PM UTC 24 |
| Finished | Sep 04 12:47:13 PM UTC 24 |
| Peak memory | 235248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302363692 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.302363692 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/5.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_ready_error.2549964469 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 9324929644 ps |
| CPU time | 14.64 seconds |
| Started | Sep 04 12:46:53 PM UTC 24 |
| Finished | Sep 04 12:47:09 PM UTC 24 |
| Peak memory | 230592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549964469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.2549964469 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/5.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_refresh.4069629303 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1036814489 ps |
| CPU time | 16.08 seconds |
| Started | Sep 04 12:46:33 PM UTC 24 |
| Finished | Sep 04 12:46:50 PM UTC 24 |
| Peak memory | 235316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069629303 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.4069629303 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/5.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/5.kmac_error.1626158015 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 8865473990 ps |
| CPU time | 313.39 seconds |
| Started | Sep 04 12:46:40 PM UTC 24 |
| Finished | Sep 04 12:51:58 PM UTC 24 |
| Peak memory | 469040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626158015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.1626158015 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/5.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/5.kmac_key_error.3672229235 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 743875679 ps |
| CPU time | 7.72 seconds |
| Started | Sep 04 12:46:44 PM UTC 24 |
| Finished | Sep 04 12:46:53 PM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672229235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.3672229235 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/5.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/5.kmac_lc_escalation.3585356127 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 31603966 ps |
| CPU time | 1.74 seconds |
| Started | Sep 04 12:46:55 PM UTC 24 |
| Finished | Sep 04 12:46:59 PM UTC 24 |
| Peak memory | 229752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585356127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.3585356127 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/5.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/5.kmac_long_msg_and_output.4185991546 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 29315676174 ps |
| CPU time | 672.44 seconds |
| Started | Sep 04 12:46:20 PM UTC 24 |
| Finished | Sep 04 12:57:41 PM UTC 24 |
| Peak memory | 685868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185991546 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and_output.4185991546 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/5.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/5.kmac_mubi.3571414096 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1353444212 ps |
| CPU time | 32.71 seconds |
| Started | Sep 04 12:46:36 PM UTC 24 |
| Finished | Sep 04 12:47:10 PM UTC 24 |
| Peak memory | 241580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571414096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.3571414096 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/5.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/5.kmac_sideload.4102887421 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 12353916271 ps |
| CPU time | 226.67 seconds |
| Started | Sep 04 12:46:21 PM UTC 24 |
| Finished | Sep 04 12:50:11 PM UTC 24 |
| Peak memory | 335656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102887421 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.4102887421 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/5.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/5.kmac_smoke.1293052956 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 14220394050 ps |
| CPU time | 41.43 seconds |
| Started | Sep 04 12:46:18 PM UTC 24 |
| Finished | Sep 04 12:47:01 PM UTC 24 |
| Peak memory | 230632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293052956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.1293052956 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/5.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/6.kmac_alert_test.574581380 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 93737798 ps |
| CPU time | 1.12 seconds |
| Started | Sep 04 12:47:26 PM UTC 24 |
| Finished | Sep 04 12:47:28 PM UTC 24 |
| Peak memory | 216284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574581380 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.574581380 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/6.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/6.kmac_app.2534768870 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 9131680216 ps |
| CPU time | 71.87 seconds |
| Started | Sep 04 12:47:05 PM UTC 24 |
| Finished | Sep 04 12:48:19 PM UTC 24 |
| Peak memory | 259812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534768870 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.2534768870 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/6.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/6.kmac_app_with_partial_data.1285490105 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 17284594189 ps |
| CPU time | 201.53 seconds |
| Started | Sep 04 12:47:05 PM UTC 24 |
| Finished | Sep 04 12:50:30 PM UTC 24 |
| Peak memory | 306992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285490105 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.1285490105 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/6.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/6.kmac_burst_write.960287666 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 6481614968 ps |
| CPU time | 595.11 seconds |
| Started | Sep 04 12:47:04 PM UTC 24 |
| Finished | Sep 04 12:57:07 PM UTC 24 |
| Peak memory | 249652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960287666 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.960287666 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/6.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/6.kmac_edn_timeout_error.2503940897 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 58435974 ps |
| CPU time | 2.33 seconds |
| Started | Sep 04 12:47:13 PM UTC 24 |
| Finished | Sep 04 12:47:17 PM UTC 24 |
| Peak memory | 230520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503940897 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.2503940897 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/6.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_mode_error.2992705993 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 1528429946 ps |
| CPU time | 49.19 seconds |
| Started | Sep 04 12:47:18 PM UTC 24 |
| Finished | Sep 04 12:48:09 PM UTC 24 |
| Peak memory | 234928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992705993 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.2992705993 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/6.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_ready_error.1813582380 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 80050679972 ps |
| CPU time | 53.13 seconds |
| Started | Sep 04 12:47:19 PM UTC 24 |
| Finished | Sep 04 12:48:14 PM UTC 24 |
| Peak memory | 230728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813582380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.1813582380 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/6.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_refresh.3504358373 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 195621096319 ps |
| CPU time | 461.18 seconds |
| Started | Sep 04 12:47:06 PM UTC 24 |
| Finished | Sep 04 12:54:54 PM UTC 24 |
| Peak memory | 507636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504358373 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.3504358373 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/6.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/6.kmac_error.3272118682 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 51569981519 ps |
| CPU time | 257.72 seconds |
| Started | Sep 04 12:47:11 PM UTC 24 |
| Finished | Sep 04 12:51:33 PM UTC 24 |
| Peak memory | 493340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272118682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.3272118682 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/6.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/6.kmac_key_error.1719175931 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 494300826 ps |
| CPU time | 3.78 seconds |
| Started | Sep 04 12:47:12 PM UTC 24 |
| Finished | Sep 04 12:47:18 PM UTC 24 |
| Peak memory | 230540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719175931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.1719175931 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/6.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/6.kmac_lc_escalation.1219080319 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 28397840 ps |
| CPU time | 2.16 seconds |
| Started | Sep 04 12:47:19 PM UTC 24 |
| Finished | Sep 04 12:47:22 PM UTC 24 |
| Peak memory | 230324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219080319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.1219080319 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/6.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/6.kmac_long_msg_and_output.4058986328 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 3609639392 ps |
| CPU time | 49.72 seconds |
| Started | Sep 04 12:47:01 PM UTC 24 |
| Finished | Sep 04 12:47:53 PM UTC 24 |
| Peak memory | 280368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058986328 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and_output.4058986328 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/6.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/6.kmac_mubi.2168692139 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 2309995054 ps |
| CPU time | 22.25 seconds |
| Started | Sep 04 12:47:10 PM UTC 24 |
| Finished | Sep 04 12:47:34 PM UTC 24 |
| Peak memory | 237572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168692139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.2168692139 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/6.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/6.kmac_sideload.3045413883 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 5517451854 ps |
| CPU time | 112.91 seconds |
| Started | Sep 04 12:47:03 PM UTC 24 |
| Finished | Sep 04 12:48:58 PM UTC 24 |
| Peak memory | 278496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045413883 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.3045413883 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/6.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/6.kmac_smoke.236480249 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 2196483052 ps |
| CPU time | 35.77 seconds |
| Started | Sep 04 12:47:01 PM UTC 24 |
| Finished | Sep 04 12:47:39 PM UTC 24 |
| Peak memory | 234688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236480249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.236480249 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/6.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/6.kmac_stress_all.2149214979 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 36428960296 ps |
| CPU time | 507.37 seconds |
| Started | Sep 04 12:47:20 PM UTC 24 |
| Finished | Sep 04 12:55:54 PM UTC 24 |
| Peak memory | 440344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149214979 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.2149214979 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/6.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/7.kmac_alert_test.1947512765 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 188369545 ps |
| CPU time | 1.23 seconds |
| Started | Sep 04 12:48:20 PM UTC 24 |
| Finished | Sep 04 12:48:22 PM UTC 24 |
| Peak memory | 216284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947512765 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.1947512765 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/7.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/7.kmac_app.4169154529 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 16195778597 ps |
| CPU time | 63.47 seconds |
| Started | Sep 04 12:47:52 PM UTC 24 |
| Finished | Sep 04 12:48:57 PM UTC 24 |
| Peak memory | 286568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169154529 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.4169154529 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/7.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/7.kmac_app_with_partial_data.70840911 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 27563907444 ps |
| CPU time | 111.53 seconds |
| Started | Sep 04 12:47:52 PM UTC 24 |
| Finished | Sep 04 12:49:46 PM UTC 24 |
| Peak memory | 321272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70840911 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.70840911 +enable_maskin g=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/7.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/7.kmac_burst_write.1028356317 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 24476700435 ps |
| CPU time | 640.9 seconds |
| Started | Sep 04 12:47:39 PM UTC 24 |
| Finished | Sep 04 12:58:28 PM UTC 24 |
| Peak memory | 258052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028356317 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.1028356317 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/7.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/7.kmac_edn_timeout_error.2127596617 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 3214083428 ps |
| CPU time | 17.31 seconds |
| Started | Sep 04 12:48:05 PM UTC 24 |
| Finished | Sep 04 12:48:24 PM UTC 24 |
| Peak memory | 232428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127596617 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.2127596617 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/7.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_mode_error.277076321 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 16840990226 ps |
| CPU time | 49.37 seconds |
| Started | Sep 04 12:48:06 PM UTC 24 |
| Finished | Sep 04 12:48:58 PM UTC 24 |
| Peak memory | 235032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277076321 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.277076321 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/7.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_ready_error.3852454991 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 24858409273 ps |
| CPU time | 82.87 seconds |
| Started | Sep 04 12:48:10 PM UTC 24 |
| Finished | Sep 04 12:49:34 PM UTC 24 |
| Peak memory | 230788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852454991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.3852454991 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/7.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_refresh.1297986092 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 2140539484 ps |
| CPU time | 133.2 seconds |
| Started | Sep 04 12:47:54 PM UTC 24 |
| Finished | Sep 04 12:50:10 PM UTC 24 |
| Peak memory | 272044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297986092 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.1297986092 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/7.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/7.kmac_error.3328904096 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 14286036460 ps |
| CPU time | 108.99 seconds |
| Started | Sep 04 12:48:04 PM UTC 24 |
| Finished | Sep 04 12:49:56 PM UTC 24 |
| Peak memory | 317232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328904096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.3328904096 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/7.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/7.kmac_key_error.221949442 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1523196937 ps |
| CPU time | 15.26 seconds |
| Started | Sep 04 12:48:04 PM UTC 24 |
| Finished | Sep 04 12:48:21 PM UTC 24 |
| Peak memory | 230464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221949442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.221949442 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/7.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/7.kmac_lc_escalation.3659047510 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 112951189 ps |
| CPU time | 1.77 seconds |
| Started | Sep 04 12:48:15 PM UTC 24 |
| Finished | Sep 04 12:48:17 PM UTC 24 |
| Peak memory | 231736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659047510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.3659047510 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/7.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/7.kmac_long_msg_and_output.2980815476 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 462548582355 ps |
| CPU time | 4658.22 seconds |
| Started | Sep 04 12:47:33 PM UTC 24 |
| Finished | Sep 04 02:06:03 PM UTC 24 |
| Peak memory | 4730728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980815476 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_and_output.2980815476 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/7.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/7.kmac_mubi.974799570 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 49982988001 ps |
| CPU time | 327.85 seconds |
| Started | Sep 04 12:48:03 PM UTC 24 |
| Finished | Sep 04 12:53:36 PM UTC 24 |
| Peak memory | 495596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974799570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.974799570 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/7.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/7.kmac_sideload.1697354855 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 2417865295 ps |
| CPU time | 222.26 seconds |
| Started | Sep 04 12:47:34 PM UTC 24 |
| Finished | Sep 04 12:51:20 PM UTC 24 |
| Peak memory | 315160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697354855 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.1697354855 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/7.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/7.kmac_smoke.4195015326 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 1109648766 ps |
| CPU time | 32.44 seconds |
| Started | Sep 04 12:47:29 PM UTC 24 |
| Finished | Sep 04 12:48:04 PM UTC 24 |
| Peak memory | 230508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195015326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.4195015326 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/7.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/7.kmac_stress_all.1053898954 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 382045272695 ps |
| CPU time | 2187.17 seconds |
| Started | Sep 04 12:48:17 PM UTC 24 |
| Finished | Sep 04 01:25:09 PM UTC 24 |
| Peak memory | 1926888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053898954 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.1053898954 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/7.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/8.kmac_alert_test.4010051521 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 68426527 ps |
| CPU time | 1.33 seconds |
| Started | Sep 04 12:49:35 PM UTC 24 |
| Finished | Sep 04 12:49:38 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010051521 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.4010051521 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/8.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/8.kmac_app.3762142735 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 7867840407 ps |
| CPU time | 57.81 seconds |
| Started | Sep 04 12:48:45 PM UTC 24 |
| Finished | Sep 04 12:49:45 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762142735 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.3762142735 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/8.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/8.kmac_app_with_partial_data.1706730988 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 7796954141 ps |
| CPU time | 62.66 seconds |
| Started | Sep 04 12:48:46 PM UTC 24 |
| Finished | Sep 04 12:49:51 PM UTC 24 |
| Peak memory | 255772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706730988 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.1706730988 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/8.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/8.kmac_burst_write.254458003 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 9287686681 ps |
| CPU time | 344.62 seconds |
| Started | Sep 04 12:48:27 PM UTC 24 |
| Finished | Sep 04 12:54:17 PM UTC 24 |
| Peak memory | 243888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254458003 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.254458003 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/8.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/8.kmac_edn_timeout_error.2050101574 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 474866939 ps |
| CPU time | 13.22 seconds |
| Started | Sep 04 12:49:03 PM UTC 24 |
| Finished | Sep 04 12:49:17 PM UTC 24 |
| Peak memory | 235312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050101574 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.2050101574 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/8.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_mode_error.1653802931 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 1499242746 ps |
| CPU time | 33.86 seconds |
| Started | Sep 04 12:49:10 PM UTC 24 |
| Finished | Sep 04 12:49:45 PM UTC 24 |
| Peak memory | 237168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653802931 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.1653802931 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/8.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_ready_error.179497469 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 15553033671 ps |
| CPU time | 39.47 seconds |
| Started | Sep 04 12:49:12 PM UTC 24 |
| Finished | Sep 04 12:49:53 PM UTC 24 |
| Peak memory | 230532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179497469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_u nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.179497469 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/8.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_refresh.3831835341 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 64892255680 ps |
| CPU time | 149.58 seconds |
| Started | Sep 04 12:48:49 PM UTC 24 |
| Finished | Sep 04 12:51:21 PM UTC 24 |
| Peak memory | 325540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831835341 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.3831835341 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/8.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/8.kmac_error.1223235526 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 4898229267 ps |
| CPU time | 338.84 seconds |
| Started | Sep 04 12:48:59 PM UTC 24 |
| Finished | Sep 04 12:54:43 PM UTC 24 |
| Peak memory | 378672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223235526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.1223235526 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/8.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/8.kmac_key_error.2409046454 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1531554531 ps |
| CPU time | 14.71 seconds |
| Started | Sep 04 12:48:59 PM UTC 24 |
| Finished | Sep 04 12:49:15 PM UTC 24 |
| Peak memory | 230592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409046454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.2409046454 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/8.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/8.kmac_lc_escalation.2257121863 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 118804811 ps |
| CPU time | 2.12 seconds |
| Started | Sep 04 12:49:15 PM UTC 24 |
| Finished | Sep 04 12:49:18 PM UTC 24 |
| Peak memory | 230316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257121863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.2257121863 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/8.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/8.kmac_long_msg_and_output.2311403141 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 1067832702 ps |
| CPU time | 44.1 seconds |
| Started | Sep 04 12:48:23 PM UTC 24 |
| Finished | Sep 04 12:49:09 PM UTC 24 |
| Peak memory | 265968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311403141 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_and_output.2311403141 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/8.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/8.kmac_mubi.989035166 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 12464415331 ps |
| CPU time | 343.2 seconds |
| Started | Sep 04 12:48:58 PM UTC 24 |
| Finished | Sep 04 12:54:46 PM UTC 24 |
| Peak memory | 526328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989035166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.989035166 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/8.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/8.kmac_sideload.2439961408 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 17315830716 ps |
| CPU time | 238.82 seconds |
| Started | Sep 04 12:48:25 PM UTC 24 |
| Finished | Sep 04 12:52:28 PM UTC 24 |
| Peak memory | 431928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439961408 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.2439961408 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/8.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/8.kmac_smoke.2735401128 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 51907912 ps |
| CPU time | 3.7 seconds |
| Started | Sep 04 12:48:22 PM UTC 24 |
| Finished | Sep 04 12:48:27 PM UTC 24 |
| Peak memory | 230536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735401128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.2735401128 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/8.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/8.kmac_stress_all.3020690534 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 28824169497 ps |
| CPU time | 839.13 seconds |
| Started | Sep 04 12:49:18 PM UTC 24 |
| Finished | Sep 04 01:03:28 PM UTC 24 |
| Peak memory | 1206240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020690534 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.3020690534 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/8.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/9.kmac_alert_test.1066667118 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 50008585 ps |
| CPU time | 1.17 seconds |
| Started | Sep 04 12:50:40 PM UTC 24 |
| Finished | Sep 04 12:50:42 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066667118 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.1066667118 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/9.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/9.kmac_app.2565478597 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 1920306306 ps |
| CPU time | 120.64 seconds |
| Started | Sep 04 12:49:48 PM UTC 24 |
| Finished | Sep 04 12:51:51 PM UTC 24 |
| Peak memory | 276136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565478597 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.2565478597 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/9.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/9.kmac_app_with_partial_data.3833888406 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 52206358683 ps |
| CPU time | 283.54 seconds |
| Started | Sep 04 12:49:52 PM UTC 24 |
| Finished | Sep 04 12:54:39 PM UTC 24 |
| Peak memory | 470832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833888406 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.3833888406 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/9.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/9.kmac_burst_write.252994389 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 246068093248 ps |
| CPU time | 1248.94 seconds |
| Started | Sep 04 12:49:47 PM UTC 24 |
| Finished | Sep 04 01:10:52 PM UTC 24 |
| Peak memory | 274228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252994389 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.252994389 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/9.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/9.kmac_edn_timeout_error.3974224922 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 1576337319 ps |
| CPU time | 31.5 seconds |
| Started | Sep 04 12:50:12 PM UTC 24 |
| Finished | Sep 04 12:50:45 PM UTC 24 |
| Peak memory | 235044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974224922 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.3974224922 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/9.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_mode_error.673317641 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 356588517 ps |
| CPU time | 32.54 seconds |
| Started | Sep 04 12:50:15 PM UTC 24 |
| Finished | Sep 04 12:50:49 PM UTC 24 |
| Peak memory | 235136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673317641 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.673317641 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/9.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_ready_error.1850675008 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 2536847777 ps |
| CPU time | 10.11 seconds |
| Started | Sep 04 12:50:17 PM UTC 24 |
| Finished | Sep 04 12:50:28 PM UTC 24 |
| Peak memory | 230596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850675008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.1850675008 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/9.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_refresh.662721592 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 43879256476 ps |
| CPU time | 255.74 seconds |
| Started | Sep 04 12:49:54 PM UTC 24 |
| Finished | Sep 04 12:54:14 PM UTC 24 |
| Peak memory | 380696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662721592 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.662721592 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/9.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/9.kmac_error.2488615627 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 2097617285 ps |
| CPU time | 65.76 seconds |
| Started | Sep 04 12:49:59 PM UTC 24 |
| Finished | Sep 04 12:51:06 PM UTC 24 |
| Peak memory | 294640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488615627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.2488615627 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/9.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/9.kmac_key_error.2069711697 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 730321166 ps |
| CPU time | 4.7 seconds |
| Started | Sep 04 12:50:11 PM UTC 24 |
| Finished | Sep 04 12:50:17 PM UTC 24 |
| Peak memory | 230336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069711697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.2069711697 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/9.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/9.kmac_lc_escalation.2101295794 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 289890928 ps |
| CPU time | 8.22 seconds |
| Started | Sep 04 12:50:29 PM UTC 24 |
| Finished | Sep 04 12:50:39 PM UTC 24 |
| Peak memory | 235560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101295794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.2101295794 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/9.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/9.kmac_long_msg_and_output.3052227021 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 257974223538 ps |
| CPU time | 2673.63 seconds |
| Started | Sep 04 12:49:45 PM UTC 24 |
| Finished | Sep 04 01:34:48 PM UTC 24 |
| Peak memory | 3262264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052227021 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and_output.3052227021 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/9.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/9.kmac_mubi.2628750862 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 69142597728 ps |
| CPU time | 270.69 seconds |
| Started | Sep 04 12:49:57 PM UTC 24 |
| Finished | Sep 04 12:54:32 PM UTC 24 |
| Peak memory | 333932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628750862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.2628750862 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/9.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/9.kmac_sideload.1696674134 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 10437984681 ps |
| CPU time | 262.73 seconds |
| Started | Sep 04 12:49:47 PM UTC 24 |
| Finished | Sep 04 12:54:14 PM UTC 24 |
| Peak memory | 317552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696674134 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.1696674134 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/9.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/9.kmac_smoke.3592436690 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 1864579227 ps |
| CPU time | 53.56 seconds |
| Started | Sep 04 12:49:38 PM UTC 24 |
| Finished | Sep 04 12:50:34 PM UTC 24 |
| Peak memory | 230512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592436690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.3592436690 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/9.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default/9.kmac_stress_all.3459472908 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 586599144 ps |
| CPU time | 11.85 seconds |
| Started | Sep 04 12:50:31 PM UTC 24 |
| Finished | Sep 04 12:50:45 PM UTC 24 |
| Peak memory | 232512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459472908 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.3459472908 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/9.kmac_stress_all/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |