Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	16689298	1			T1	21		T2	152		T3	91
all_values[1]	16689298	1			T1	21		T2	152		T3	91
all_values[2]	16689298	1			T1	21		T2	152		T3	91

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

523543

1

T1

12

T2

159

T3

12

auto[1]

49544351

1

T1

51

T2

297

T3

261

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49849827

1

T1

54

T2

438

T3

258

auto[1]

218067

1

T1

9

T2

18

T3

15

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	169670	1			T1	10		T2	146		T3	4
all_values[0]	auto[0]	auto[1]	1352	1			T1	2		T2	6		T3	2
all_values[0]	auto[1]	auto[0]	16446939	1			T1	8		T3	82		T13	1948
all_values[0]	auto[1]	auto[1]	71337	1			T1	1		T3	3		T13	18
all_values[1]	auto[0]	auto[0]	197103	1			T13	222		T21	592		T70	6
all_values[1]	auto[0]	auto[1]	970	1			T13	1		T21	5		T70	1
all_values[1]	auto[1]	auto[0]	16419506	1			T1	18		T2	146		T3	86
all_values[1]	auto[1]	auto[1]	71719	1			T1	3		T2	6		T3	5
all_values[2]	auto[0]	auto[0]	153447	1			T2	5		T3	4		T4	1
all_values[2]	auto[0]	auto[1]	1001	1			T2	2		T3	2		T17	5
all_values[2]	auto[1]	auto[0]	16463162	1			T1	18		T2	141		T3	82
all_values[2]	auto[1]	auto[1]	71688	1			T1	3		T2	4		T3	3