Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56934 |
1 |
|
|
T1 |
2 |
|
T2 |
6 |
|
T3 |
6 |
auto[1] |
54328 |
1 |
|
|
T1 |
2 |
|
T39 |
118 |
|
T68 |
26 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
27644 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T13 |
2 |
lower_val |
27221 |
1 |
|
|
T13 |
15 |
|
T4 |
4 |
|
T15 |
26 |
zero_val |
912 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
1 |
2 |
66.67 |
User Defined Bins for wait_timer_val
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
zero_val |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
55490 |
1 |
|
|
T1 |
2 |
|
T2 |
4 |
|
T3 |
4 |
lower_val |
55772 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
6 |
12 |
66.67 |
6 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
* |
[zero_val] |
* |
-- |
-- |
6 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
7173 |
1 |
|
|
T2 |
2 |
|
T13 |
2 |
|
T15 |
8 |
higher_val |
higher_val |
auto[1] |
6714 |
1 |
|
|
T1 |
1 |
|
T39 |
13 |
|
T68 |
1 |
higher_val |
lower_val |
auto[0] |
7060 |
1 |
|
|
T2 |
1 |
|
T4 |
2 |
|
T15 |
7 |
higher_val |
lower_val |
auto[1] |
6697 |
1 |
|
|
T39 |
12 |
|
T68 |
5 |
|
T21 |
29 |
lower_val |
higher_val |
auto[0] |
6903 |
1 |
|
|
T13 |
11 |
|
T15 |
11 |
|
T17 |
18 |
lower_val |
higher_val |
auto[1] |
6690 |
1 |
|
|
T39 |
14 |
|
T68 |
1 |
|
T21 |
32 |
lower_val |
lower_val |
auto[0] |
7023 |
1 |
|
|
T13 |
4 |
|
T4 |
4 |
|
T15 |
15 |
lower_val |
lower_val |
auto[1] |
6605 |
1 |
|
|
T39 |
16 |
|
T68 |
4 |
|
T21 |
22 |
zero_val |
higher_val |
auto[0] |
333 |
1 |
|
|
T13 |
1 |
|
T17 |
1 |
|
T68 |
1 |
zero_val |
higher_val |
auto[1] |
110 |
1 |
|
|
T23 |
1 |
|
T24 |
1 |
|
T27 |
2 |
zero_val |
lower_val |
auto[0] |
364 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
lower_val |
auto[1] |
105 |
1 |
|
|
T23 |
1 |
|
T32 |
2 |
|
T24 |
1 |