SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 20 | 0 | 20 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
hash_mode | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 | |
kmac_mode | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
msgfifo_depth | 11 | 0 | 11 | 100.00 | 100 | 1 | 1 | 0 | |
msgfifo_empty | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
msgfifo_full | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
cshake | 11008264 | 1 | T1 | 16 | T2 | 145 | T3 | 84 | ||||
shake | 5168535 | 1 | T13 | 1375 | T4 | 189 | T15 | 12 | ||||
sha3 | 2367321 | 1 | T13 | 2 | T4 | 2 | T15 | 17 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7534646 | 1 | T13 | 1375 | T4 | 189 | T15 | 21 | ||||
auto[1] | 11009474 | 1 | T1 | 16 | T2 | 145 | T3 | 84 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 11 | 0 | 11 | 100.00 |
NAME | COUNT | STATUS |
invalid | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
depth[0x00] | 17793173 | 1 | T1 | 6 | T2 | 145 | T3 | 84 | ||||
depth[0x01] | 295332 | 1 | T1 | 5 | T13 | 55 | T17 | 19 | ||||
depth[0x02] | 148400 | 1 | T1 | 4 | T13 | 15 | T68 | 28 | ||||
depth[0x03] | 120779 | 1 | T1 | 1 | T13 | 14 | T68 | 17 | ||||
depth[0x04] | 76488 | 1 | T13 | 5 | T68 | 8 | T70 | 3 | ||||
depth[0x05] | 45929 | 1 | T13 | 2 | T68 | 3 | T70 | 1 | ||||
depth[0x06] | 18262 | 1 | T42 | 457 | T27 | 88 | T43 | 113 | ||||
depth[0x07] | 365 | 1 | T27 | 2 | T43 | 2 | T44 | 5 | ||||
depth[0x08] | 1481 | 1 | T42 | 33 | T27 | 8 | T43 | 10 | ||||
depth[0x09] | 1284 | 1 | T42 | 17 | T27 | 6 | T43 | 8 | ||||
depth[0x0a] | 42627 | 1 | T42 | 773 | T27 | 199 | T43 | 236 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 750947 | 1 | T1 | 10 | T13 | 91 | T17 | 19 | ||||
auto[1] | 17793173 | 1 | T1 | 6 | T2 | 145 | T3 | 84 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 18501493 | 1 | T1 | 16 | T2 | 145 | T3 | 84 | ||||
auto[1] | 42627 | 1 | T42 | 773 | T27 | 199 | T43 | 236 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |