Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	16689298	1			T1	21		T2	152		T3	91
all_pins[1]	16689298	1			T1	21		T2	152		T3	91
all_pins[2]	16689298	1			T1	21		T2	152		T3	91

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	49705640	1			T1	62		T2	456		T3	270
values[0x1]	362254	1			T1	1		T3	3		T13	18
transitions[0x0=>0x1]	360447	1			T1	1		T3	3		T13	18
transitions[0x1=>0x0]	360474	1			T1	1		T3	3		T13	18

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	16617961	1			T1	20		T2	152		T3	88
all_pins[0]	values[0x1]	71337	1			T1	1		T3	3		T13	18
all_pins[0]	transitions[0x0=>0x1]	71325	1			T1	1		T3	3		T13	18
all_pins[0]	transitions[0x1=>0x0]	71	1			T44	4		T132	3		T46	3
all_pins[1]	values[0x0]	16689215	1			T1	21		T2	152		T3	91
all_pins[1]	values[0x1]	83	1			T44	4		T132	3		T46	3
all_pins[1]	transitions[0x0=>0x1]	62	1			T44	4		T132	3		T46	3
all_pins[1]	transitions[0x1=>0x0]	290813	1			T32	7756		T24	668		T25	306
all_pins[2]	values[0x0]	16398464	1			T1	21		T2	152		T3	91
all_pins[2]	values[0x1]	290834	1			T32	7756		T24	668		T25	306
all_pins[2]	transitions[0x0=>0x1]	289060	1			T32	7706		T24	668		T25	305
all_pins[2]	transitions[0x1=>0x0]	69590	1			T1	1		T3	3		T13	18