Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.25	95.89	92.30	100.00	68.60	94.11	98.84	96.01

Total test records in report: 885

T765	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.831292532	Sep 09 07:50:49 PM UTC 24	Sep 09 07:50:52 PM UTC 24	97315460 ps
T766	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.1412104252	Sep 09 07:50:46 PM UTC 24	Sep 09 07:50:52 PM UTC 24	341091879 ps
T158	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.4122948387	Sep 09 07:50:45 PM UTC 24	Sep 09 07:50:52 PM UTC 24	120173882 ps
T767	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.3689453467	Sep 09 07:50:47 PM UTC 24	Sep 09 07:50:53 PM UTC 24	38173622 ps
T768	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.1320763014	Sep 09 07:50:49 PM UTC 24	Sep 09 07:50:52 PM UTC 24	77950226 ps
T769	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.4004450755	Sep 09 07:50:48 PM UTC 24	Sep 09 07:50:53 PM UTC 24	590399804 ps
T770	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.3182676139	Sep 09 07:50:52 PM UTC 24	Sep 09 07:50:54 PM UTC 24	26170622 ps
T771	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.974675	Sep 09 07:50:52 PM UTC 24	Sep 09 07:50:55 PM UTC 24	173200682 ps
T772	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.3900906635	Sep 09 07:50:53 PM UTC 24	Sep 09 07:50:55 PM UTC 24	14826568 ps
T773	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.3626866902	Sep 09 07:50:53 PM UTC 24	Sep 09 07:50:56 PM UTC 24	81322997 ps
T102	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1046034157	Sep 09 07:50:53 PM UTC 24	Sep 09 07:50:56 PM UTC 24	45067871 ps
T103	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.640960292	Sep 09 07:50:52 PM UTC 24	Sep 09 07:50:56 PM UTC 24	255150624 ps
T774	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2499419579	Sep 09 07:50:53 PM UTC 24	Sep 09 07:50:56 PM UTC 24	189306064 ps
T775	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.2421653276	Sep 09 07:50:53 PM UTC 24	Sep 09 07:50:57 PM UTC 24	103098053 ps
T776	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.3389095080	Sep 09 07:50:53 PM UTC 24	Sep 09 07:50:57 PM UTC 24	39876677 ps
T152	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.937553877	Sep 09 07:50:56 PM UTC 24	Sep 09 07:50:58 PM UTC 24	15045077 ps
T167	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.985939175	Sep 09 07:50:53 PM UTC 24	Sep 09 07:50:58 PM UTC 24	341788567 ps
T157	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.273975644	Sep 09 07:50:53 PM UTC 24	Sep 09 07:50:59 PM UTC 24	445520619 ps
T777	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.3981840034	Sep 09 07:50:54 PM UTC 24	Sep 09 07:50:59 PM UTC 24	122703078 ps
T97	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.4070258845	Sep 09 07:50:57 PM UTC 24	Sep 09 07:50:59 PM UTC 24	102865117 ps
T778	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.2996888550	Sep 09 07:50:57 PM UTC 24	Sep 09 07:51:00 PM UTC 24	61455324 ps
T98	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.2934181437	Sep 09 07:50:57 PM UTC 24	Sep 09 07:51:00 PM UTC 24	54016345 ps
T153	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.2982966950	Sep 09 07:50:58 PM UTC 24	Sep 09 07:51:00 PM UTC 24	13199257 ps
T779	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.2272438788	Sep 09 07:50:32 PM UTC 24	Sep 09 07:51:00 PM UTC 24	20466664889 ps
T780	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.2742848075	Sep 09 07:50:54 PM UTC 24	Sep 09 07:51:01 PM UTC 24	1419832341 ps
T781	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3833937997	Sep 09 07:50:57 PM UTC 24	Sep 09 07:51:01 PM UTC 24	359405163 ps
T782	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.4283180779	Sep 09 07:50:57 PM UTC 24	Sep 09 07:51:01 PM UTC 24	252194937 ps
T783	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.715230212	Sep 09 07:50:59 PM UTC 24	Sep 09 07:51:02 PM UTC 24	22154606 ps
T784	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3146517045	Sep 09 07:50:59 PM UTC 24	Sep 09 07:51:02 PM UTC 24	77283443 ps
T785	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.3252791968	Sep 09 07:50:58 PM UTC 24	Sep 09 07:51:02 PM UTC 24	123995931 ps
T786	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.4108762777	Sep 09 07:50:59 PM UTC 24	Sep 09 07:51:03 PM UTC 24	46192420 ps
T787	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.447027977	Sep 09 07:50:58 PM UTC 24	Sep 09 07:51:03 PM UTC 24	326566456 ps
T788	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2508615446	Sep 09 07:51:00 PM UTC 24	Sep 09 07:51:03 PM UTC 24	47897383 ps
T789	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.382546236	Sep 09 07:51:00 PM UTC 24	Sep 09 07:51:04 PM UTC 24	106629911 ps
T790	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.1434269341	Sep 09 07:51:02 PM UTC 24	Sep 09 07:51:04 PM UTC 24	25079110 ps
T791	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.2341195429	Sep 09 07:51:00 PM UTC 24	Sep 09 07:51:04 PM UTC 24	321615097 ps
T792	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.952723815	Sep 09 07:51:02 PM UTC 24	Sep 09 07:51:04 PM UTC 24	49880867 ps
T793	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.3632375136	Sep 09 07:50:38 PM UTC 24	Sep 09 07:51:04 PM UTC 24	5980059110 ps
T794	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1705903937	Sep 09 07:51:02 PM UTC 24	Sep 09 07:51:05 PM UTC 24	93823014 ps
T795	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.2381198613	Sep 09 07:51:00 PM UTC 24	Sep 09 07:51:05 PM UTC 24	217606019 ps
T796	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3283277415	Sep 09 07:51:02 PM UTC 24	Sep 09 07:51:05 PM UTC 24	236562740 ps
T797	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.3042739599	Sep 09 07:51:03 PM UTC 24	Sep 09 07:51:06 PM UTC 24	89955278 ps
T798	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.502921203	Sep 09 07:51:03 PM UTC 24	Sep 09 07:51:06 PM UTC 24	47896413 ps
T799	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.3252598238	Sep 09 07:51:03 PM UTC 24	Sep 09 07:51:06 PM UTC 24	58592576 ps
T800	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.48727562	Sep 09 07:51:04 PM UTC 24	Sep 09 07:51:06 PM UTC 24	77477778 ps
T801	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.3230809995	Sep 09 07:51:04 PM UTC 24	Sep 09 07:51:07 PM UTC 24	26168044 ps
T802	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1953635986	Sep 09 07:51:04 PM UTC 24	Sep 09 07:51:07 PM UTC 24	175623431 ps
T803	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.2733153016	Sep 09 07:51:04 PM UTC 24	Sep 09 07:51:07 PM UTC 24	47779444 ps
T162	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.4275993197	Sep 09 07:51:03 PM UTC 24	Sep 09 07:51:08 PM UTC 24	492531720 ps
T804	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.796899742	Sep 09 07:51:06 PM UTC 24	Sep 09 07:51:08 PM UTC 24	168959837 ps
T805	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1786150010	Sep 09 07:51:05 PM UTC 24	Sep 09 07:51:08 PM UTC 24	43935731 ps
T806	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.2542220201	Sep 09 07:51:06 PM UTC 24	Sep 09 07:51:08 PM UTC 24	47657682 ps
T807	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.4034966065	Sep 09 07:51:05 PM UTC 24	Sep 09 07:51:09 PM UTC 24	202784951 ps
T808	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2975683195	Sep 09 07:51:05 PM UTC 24	Sep 09 07:51:09 PM UTC 24	454973089 ps
T809	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.1668079174	Sep 09 07:51:05 PM UTC 24	Sep 09 07:51:10 PM UTC 24	57958460 ps
T810	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.3144922344	Sep 09 07:51:07 PM UTC 24	Sep 09 07:51:10 PM UTC 24	92023305 ps
T811	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.725248760	Sep 09 07:51:08 PM UTC 24	Sep 09 07:51:10 PM UTC 24	14871609 ps
T812	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.2844602899	Sep 09 07:51:08 PM UTC 24	Sep 09 07:51:10 PM UTC 24	179471549 ps
T813	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.801999918	Sep 09 07:51:07 PM UTC 24	Sep 09 07:51:11 PM UTC 24	212340774 ps
T814	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.4281876559	Sep 09 07:51:08 PM UTC 24	Sep 09 07:51:11 PM UTC 24	84385369 ps
T815	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1852476260	Sep 09 07:51:07 PM UTC 24	Sep 09 07:51:11 PM UTC 24	253013618 ps
T816	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1075467243	Sep 09 07:51:09 PM UTC 24	Sep 09 07:51:12 PM UTC 24	100619702 ps
T817	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.341015443	Sep 09 07:51:08 PM UTC 24	Sep 09 07:51:12 PM UTC 24	126391763 ps
T818	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.3292614512	Sep 09 07:51:09 PM UTC 24	Sep 09 07:51:12 PM UTC 24	132715259 ps
T819	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.277102237	Sep 09 07:51:11 PM UTC 24	Sep 09 07:51:13 PM UTC 24	29020300 ps
T820	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.3018051313	Sep 09 07:51:11 PM UTC 24	Sep 09 07:51:13 PM UTC 24	26961672 ps
T821	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.3194514759	Sep 09 07:51:09 PM UTC 24	Sep 09 07:51:13 PM UTC 24	265142205 ps
T161	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.2230422620	Sep 09 07:51:08 PM UTC 24	Sep 09 07:51:13 PM UTC 24	164602181 ps
T822	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.3875799341	Sep 09 07:51:09 PM UTC 24	Sep 09 07:51:14 PM UTC 24	112845413 ps
T823	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.778681857	Sep 09 07:51:10 PM UTC 24	Sep 09 07:51:14 PM UTC 24	242297352 ps
T164	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.4103829395	Sep 09 07:51:10 PM UTC 24	Sep 09 07:51:15 PM UTC 24	406882007 ps
T824	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2217796378	Sep 09 07:51:11 PM UTC 24	Sep 09 07:51:15 PM UTC 24	109357901 ps
T825	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.3359519126	Sep 09 07:51:14 PM UTC 24	Sep 09 07:51:19 PM UTC 24	229857871 ps
T826	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.2577322586	Sep 09 07:51:12 PM UTC 24	Sep 09 07:51:15 PM UTC 24	22732879 ps
T827	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.780657369	Sep 09 07:51:12 PM UTC 24	Sep 09 07:51:15 PM UTC 24	483286265 ps
T828	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.3889774803	Sep 09 07:51:12 PM UTC 24	Sep 09 07:51:15 PM UTC 24	121851957 ps
T829	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.1423493346	Sep 09 07:51:13 PM UTC 24	Sep 09 07:51:15 PM UTC 24	32944102 ps
T830	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.3025579835	Sep 09 07:51:13 PM UTC 24	Sep 09 07:51:15 PM UTC 24	22662829 ps
T831	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.1179520185	Sep 09 07:51:14 PM UTC 24	Sep 09 07:51:17 PM UTC 24	112145351 ps
T832	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.3983042508	Sep 09 07:51:16 PM UTC 24	Sep 09 07:51:17 PM UTC 24	31960497 ps
T833	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2298705199	Sep 09 07:51:14 PM UTC 24	Sep 09 07:51:18 PM UTC 24	83066907 ps
T834	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.3465950567	Sep 09 07:51:16 PM UTC 24	Sep 09 07:51:18 PM UTC 24	19874403 ps
T835	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.1639890619	Sep 09 07:51:16 PM UTC 24	Sep 09 07:51:18 PM UTC 24	24854880 ps
T836	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.3683554062	Sep 09 07:51:13 PM UTC 24	Sep 09 07:51:18 PM UTC 24	97838878 ps
T837	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1089216429	Sep 09 07:51:14 PM UTC 24	Sep 09 07:51:18 PM UTC 24	38726152 ps
T838	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2129188531	Sep 09 07:51:14 PM UTC 24	Sep 09 07:51:19 PM UTC 24	67903241 ps
T839	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1550345708	Sep 09 07:51:16 PM UTC 24	Sep 09 07:51:19 PM UTC 24	67176166 ps
T159	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.3675688085	Sep 09 07:51:13 PM UTC 24	Sep 09 07:51:19 PM UTC 24	196269470 ps
T840	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.367421901	Sep 09 07:51:16 PM UTC 24	Sep 09 07:51:19 PM UTC 24	57619604 ps
T841	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.4264346491	Sep 09 07:51:16 PM UTC 24	Sep 09 07:51:20 PM UTC 24	191419275 ps
T842	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.3697590482	Sep 09 07:51:18 PM UTC 24	Sep 09 07:51:20 PM UTC 24	28961766 ps
T843	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3601363117	Sep 09 07:51:17 PM UTC 24	Sep 09 07:51:20 PM UTC 24	76539146 ps
T844	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.3961880533	Sep 09 07:51:18 PM UTC 24	Sep 09 07:51:21 PM UTC 24	31086940 ps
T845	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.1749622559	Sep 09 07:51:17 PM UTC 24	Sep 09 07:51:21 PM UTC 24	80639077 ps
T846	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.1188465087	Sep 09 07:51:20 PM UTC 24	Sep 09 07:51:22 PM UTC 24	14243271 ps
T847	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.2704741920	Sep 09 07:51:19 PM UTC 24	Sep 09 07:51:22 PM UTC 24	124842949 ps
T848	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.2709567604	Sep 09 07:51:18 PM UTC 24	Sep 09 07:51:22 PM UTC 24	461695436 ps
T849	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.469138678	Sep 09 07:51:19 PM UTC 24	Sep 09 07:51:22 PM UTC 24	64477854 ps
T850	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.1839015917	Sep 09 07:51:21 PM UTC 24	Sep 09 07:51:23 PM UTC 24	69803504 ps
T851	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.4266732590	Sep 09 07:51:19 PM UTC 24	Sep 09 07:51:23 PM UTC 24	101660255 ps
T852	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.37551920	Sep 09 07:51:19 PM UTC 24	Sep 09 07:51:23 PM UTC 24	350569197 ps
T853	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.2035486187	Sep 09 07:51:21 PM UTC 24	Sep 09 07:51:24 PM UTC 24	548526395 ps
T163	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.3339106397	Sep 09 07:51:20 PM UTC 24	Sep 09 07:51:24 PM UTC 24	104683943 ps
T854	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.146661174	Sep 09 07:51:22 PM UTC 24	Sep 09 07:51:24 PM UTC 24	23297543 ps
T855	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.567941097	Sep 09 07:51:22 PM UTC 24	Sep 09 07:51:24 PM UTC 24	17236364 ps
T856	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.4044158494	Sep 09 07:51:22 PM UTC 24	Sep 09 07:51:24 PM UTC 24	20282533 ps
T857	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2196203706	Sep 09 07:51:19 PM UTC 24	Sep 09 07:51:24 PM UTC 24	238632267 ps
T858	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.1646001219	Sep 09 07:51:21 PM UTC 24	Sep 09 07:51:24 PM UTC 24	251151821 ps
T859	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1026395992	Sep 09 07:51:21 PM UTC 24	Sep 09 07:51:24 PM UTC 24	212775184 ps
T860	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.664306354	Sep 09 07:51:23 PM UTC 24	Sep 09 07:51:25 PM UTC 24	55172087 ps
T861	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.1517958217	Sep 09 07:51:23 PM UTC 24	Sep 09 07:51:25 PM UTC 24	42588546 ps
T862	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.1379272382	Sep 09 07:51:23 PM UTC 24	Sep 09 07:51:25 PM UTC 24	12269654 ps
T863	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.149980749	Sep 09 07:51:23 PM UTC 24	Sep 09 07:51:25 PM UTC 24	12352638 ps
T864	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.1252075301	Sep 09 07:51:24 PM UTC 24	Sep 09 07:51:26 PM UTC 24	29596825 ps
T865	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.308530893	Sep 09 07:51:24 PM UTC 24	Sep 09 07:51:26 PM UTC 24	11687601 ps
T866	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.3308413742	Sep 09 07:51:24 PM UTC 24	Sep 09 07:51:26 PM UTC 24	14830367 ps
T867	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.3211689832	Sep 09 07:51:24 PM UTC 24	Sep 09 07:51:26 PM UTC 24	27453366 ps
T868	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.2809643209	Sep 09 07:51:24 PM UTC 24	Sep 09 07:51:26 PM UTC 24	15602945 ps
T869	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.217630778	Sep 09 07:51:26 PM UTC 24	Sep 09 07:51:28 PM UTC 24	40490008 ps
T870	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.570425973	Sep 09 07:51:26 PM UTC 24	Sep 09 07:51:28 PM UTC 24	12768673 ps
T871	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.410678878	Sep 09 07:51:26 PM UTC 24	Sep 09 07:51:28 PM UTC 24	13356265 ps
T872	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.342252848	Sep 09 07:51:26 PM UTC 24	Sep 09 07:51:28 PM UTC 24	50994453 ps
T873	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.2268947814	Sep 09 07:51:26 PM UTC 24	Sep 09 07:51:28 PM UTC 24	15641706 ps
T874	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.3868520635	Sep 09 07:51:26 PM UTC 24	Sep 09 07:51:28 PM UTC 24	27780664 ps
T875	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.1133332791	Sep 09 07:51:26 PM UTC 24	Sep 09 07:51:28 PM UTC 24	71552405 ps
T876	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.3499643095	Sep 09 07:51:26 PM UTC 24	Sep 09 07:51:28 PM UTC 24	11058724 ps
T877	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.2642337705	Sep 09 07:51:27 PM UTC 24	Sep 09 07:51:29 PM UTC 24	31769574 ps
T878	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.155024276	Sep 09 07:51:27 PM UTC 24	Sep 09 07:51:29 PM UTC 24	11826775 ps
T879	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.907060991	Sep 09 07:51:27 PM UTC 24	Sep 09 07:51:29 PM UTC 24	46838463 ps
T880	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.4077384396	Sep 09 07:51:27 PM UTC 24	Sep 09 07:51:29 PM UTC 24	29906471 ps
T881	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.2117252004	Sep 09 07:51:27 PM UTC 24	Sep 09 07:51:29 PM UTC 24	17121908 ps
T882	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.3725202443	Sep 09 07:51:27 PM UTC 24	Sep 09 07:51:29 PM UTC 24	28267030 ps
T883	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.862664999	Sep 09 07:51:27 PM UTC 24	Sep 09 07:51:29 PM UTC 24	17760271 ps
T884	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.1146289505	Sep 09 07:51:28 PM UTC 24	Sep 09 07:51:30 PM UTC 24	103576450 ps
T885	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.3070904647	Sep 09 07:51:28 PM UTC 24	Sep 09 07:51:31 PM UTC 24	17117626 ps

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/0.kmac_app.2773501693
Short name	T13
Test name
Test status
Simulation time	2153429519 ps
CPU time	43.29 seconds
Started	Sep 09 07:51:30 PM UTC 24
Finished	Sep 09 07:52:15 PM UTC 24
Peak memory	239404 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773501693 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.2773501693 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/1.kmac_stress_all_with_rand_reset.1729392950
Short name	T27
Test name
Test status
Simulation time	24712911759 ps
CPU time	210.2 seconds
Started	Sep 09 07:56:45 PM UTC 24
Finished	Sep 09 08:00:19 PM UTC 24
Peak memory	282836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1729392950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all_ with_rand_reset.1729392950 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/0.kmac_error.945284028
Short name	T24
Test name
Test status
Simulation time	26386230667 ps
CPU time	435.11 seconds
Started	Sep 09 07:51:35 PM UTC 24
Finished	Sep 09 07:58:56 PM UTC 24
Peak memory	591592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945284028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.945284028 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_intg_err.172439666
Short name	T109
Test name
Test status
Simulation time	202616801 ps
CPU time	4.61 seconds
Started	Sep 09 07:50:15 PM UTC 24
Finished	Sep 09 07:50:21 PM UTC 24
Peak memory	229388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172439666 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.172439666 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/1.kmac_sec_cm.5838348
Short name	T10
Test name
Test status
Simulation time	28778761163 ps
CPU time	116.7 seconds
Started	Sep 09 07:56:46 PM UTC 24
Finished	Sep 09 07:58:45 PM UTC 24
Peak memory	300020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5838348 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.5838348 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/0.kmac_key_error.646123127
Short name	T12
Test name
Test status
Simulation time	464676175 ps
CPU time	4.95 seconds
Started	Sep 09 07:51:35 PM UTC 24
Finished	Sep 09 07:51:41 PM UTC 24
Peak memory	230380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646123127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.646123127 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/3.kmac_lc_escalation.69246400
Short name	T57
Test name
Test status
Simulation time	118663706 ps
CPU time	2.52 seconds
Started	Sep 09 08:00:55 PM UTC 24
Finished	Sep 09 08:00:59 PM UTC 24
Peak memory	230400 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69246400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.69246400 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/17.kmac_lc_escalation.3490089884
Short name	T8
Test name
Test status
Simulation time	33324858 ps
CPU time	1.83 seconds
Started	Sep 09 08:19:58 PM UTC 24
Finished	Sep 09 08:20:01 PM UTC 24
Peak memory	231772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490089884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.3490089884 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/17.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.4193152892
Short name	T96
Test name
Test status
Simulation time	417770954 ps
CPU time	3.25 seconds
Started	Sep 09 07:50:20 PM UTC 24
Finished	Sep 09 07:50:24 PM UTC 24
Peak memory	229860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193152892 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors_with_csr_rw. 4193152892 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/0.kmac_lc_escalation.2499474398
Short name	T4
Test name
Test status
Simulation time	418668423 ps
CPU time	7.31 seconds
Started	Sep 09 07:52:26 PM UTC 24
Finished	Sep 09 07:52:35 PM UTC 24
Peak memory	240772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499474398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.2499474398 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_intr_test.2111261398
Short name	T149
Test name
Test status
Simulation time	36110555 ps
CPU time	1.13 seconds
Started	Sep 09 07:50:30 PM UTC 24
Finished	Sep 09 07:50:32 PM UTC 24
Peak memory	218992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111261398 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.2111261398 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/0.kmac_app_with_partial_data.742309001
Short name	T21
Test name
Test status
Simulation time	27520524220 ps
CPU time	194.54 seconds
Started	Sep 09 07:51:31 PM UTC 24
Finished	Sep 09 07:54:49 PM UTC 24
Peak memory	364404 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742309001 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.742309001 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_app_with_partial_data/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/45.kmac_lc_escalation.4056782984
Short name	T9
Test name
Test status
Simulation time	71150901 ps
CPU time	2.07 seconds
Started	Sep 09 08:50:27 PM UTC 24
Finished	Sep 09 08:50:30 PM UTC 24
Peak memory	230532 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056782984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.4056782984 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/45.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.3376795443
Short name	T165
Test name
Test status
Simulation time	229086999 ps
CPU time	3.72 seconds
Started	Sep 09 07:50:39 PM UTC 24
Finished	Sep 09 07:50:44 PM UTC 24
Peak memory	236684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376795443 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors_with_csr_rw. 3376795443 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/2.kmac_smoke.2833854753
Short name	T84
Test name
Test status
Simulation time	4205334104 ps
CPU time	46.99 seconds
Started	Sep 09 07:56:54 PM UTC 24
Finished	Sep 09 07:57:43 PM UTC 24
Peak memory	230592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833854753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.2833854753 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_partial_access.160687236
Short name	T125
Test name
Test status
Simulation time	47626821 ps
CPU time	1.74 seconds
Started	Sep 09 07:50:09 PM UTC 24
Finished	Sep 09 07:50:12 PM UTC 24
Peak memory	228876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160687236 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial_access.160687236 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/0.kmac_alert_test.561546445
Short name	T18
Test name
Test status
Simulation time	24675972 ps
CPU time	1.26 seconds
Started	Sep 09 07:53:20 PM UTC 24
Finished	Sep 09 07:53:23 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561546445 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.561546445 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.4122948387
Short name	T158
Test name
Test status
Simulation time	120173882 ps
CPU time	5.98 seconds
Started	Sep 09 07:50:45 PM UTC 24
Finished	Sep 09 07:50:52 PM UTC 24
Peak memory	229380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122948387 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.4122948387 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/6.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/4.kmac_error.1816742389
Short name	T146
Test name
Test status
Simulation time	69856230971 ps
CPU time	398.86 seconds
Started	Sep 09 08:02:45 PM UTC 24
Finished	Sep 09 08:09:29 PM UTC 24
Peak memory	628532 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816742389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.1816742389 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_256.907946303
Short name	T40
Test name
Test status
Simulation time	3356364182 ps
CPU time	146.45 seconds
Started	Sep 09 07:51:30 PM UTC 24
Finished	Sep 09 07:53:59 PM UTC 24
Peak memory	264020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907946303 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.90794630 3 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_256/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/7.kmac_burst_write.3544036343
Short name	T44
Test name
Test status
Simulation time	738281195 ps
CPU time	83.01 seconds
Started	Sep 09 08:07:01 PM UTC 24
Finished	Sep 09 08:08:26 PM UTC 24
Peak memory	235168 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544036343 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.3544036343 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/7.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.937553877
Short name	T152
Test name
Test status
Simulation time	15045077 ps
CPU time	1.08 seconds
Started	Sep 09 07:50:56 PM UTC 24
Finished	Sep 09 07:50:58 PM UTC 24
Peak memory	219000 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937553877 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.937553877 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/9.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.4070258845
Short name	T97
Test name
Test status
Simulation time	102865117 ps
CPU time	1.5 seconds
Started	Sep 09 07:50:57 PM UTC 24
Finished	Sep 09 07:50:59 PM UTC 24
Peak memory	228808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070258845 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors.4070258845 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_ready_error.1151630840
Short name	T48
Test name
Test status
Simulation time	3222332645 ps
CPU time	38.86 seconds
Started	Sep 09 07:59:09 PM UTC 24
Finished	Sep 09 07:59:49 PM UTC 24
Peak memory	230772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151630840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.1151630840 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_entropy_ready_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.4275993197
Short name	T162
Test name
Test status
Simulation time	492531720 ps
CPU time	3.51 seconds
Started	Sep 09 07:51:03 PM UTC 24
Finished	Sep 09 07:51:08 PM UTC 24
Peak memory	229096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275993197 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.4275993197 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/12.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/0.kmac_mubi.4105645388
Short name	T29
Test name
Test status
Simulation time	16790823584 ps
CPU time	532.66 seconds
Started	Sep 09 07:51:32 PM UTC 24
Finished	Sep 09 08:00:32 PM UTC 24
Peak memory	604160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105645388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.4105645388 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_intg_err.3914843671
Short name	T108
Test name
Test status
Simulation time	519982311 ps
CPU time	6.95 seconds
Started	Sep 09 07:50:09 PM UTC 24
Finished	Sep 09 07:50:17 PM UTC 24
Peak memory	229440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914843671 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.3914843671 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.3339106397
Short name	T163
Test name
Test status
Simulation time	104683943 ps
CPU time	3.09 seconds
Started	Sep 09 07:51:20 PM UTC 24
Finished	Sep 09 07:51:24 PM UTC 24
Peak memory	229528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339106397 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.3339106397 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/19.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.273975644
Short name	T157
Test name
Test status
Simulation time	445520619 ps
CPU time	4.6 seconds
Started	Sep 09 07:50:53 PM UTC 24
Finished	Sep 09 07:50:59 PM UTC 24
Peak memory	229388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273975644 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.273975644 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/8.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/0.kmac_stress_all.2070133739
Short name	T171
Test name
Test status
Simulation time	21417058491 ps
CPU time	594.81 seconds
Started	Sep 09 07:52:36 PM UTC 24
Finished	Sep 09 08:02:38 PM UTC 24
Peak memory	513844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070133739 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.2070133739 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_refresh.4130179088
Short name	T41
Test name
Test status
Simulation time	235593843480 ps
CPU time	359.11 seconds
Started	Sep 09 07:51:31 PM UTC 24
Finished	Sep 09 07:57:36 PM UTC 24
Peak memory	472880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130179088 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.4130179088 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/4.kmac_stress_all_with_rand_reset.892880412
Short name	T52
Test name
Test status
Simulation time	34083754849 ps
CPU time	81.08 seconds
Started	Sep 09 08:03:35 PM UTC 24
Finished	Sep 09 08:04:58 PM UTC 24
Peak memory	284868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=892880412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all_w ith_rand_reset.892880412 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_aliasing.2191989078
Short name	T724
Test name
Test status
Simulation time	280431017 ps
CPU time	5.82 seconds
Started	Sep 09 07:50:11 PM UTC 24
Finished	Sep 09 07:50:18 PM UTC 24
Peak memory	219208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191989078 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.2191989078 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.1898682262
Short name	T143
Test name
Test status
Simulation time	1283362652 ps
CPU time	13.49 seconds
Started	Sep 09 07:50:11 PM UTC 24
Finished	Sep 09 07:50:26 PM UTC 24
Peak memory	219144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898682262 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.1898682262 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_hw_reset.2306104592
Short name	T112
Test name
Test status
Simulation time	32668924 ps
CPU time	1.54 seconds
Started	Sep 09 07:50:10 PM UTC 24
Finished	Sep 09 07:50:13 PM UTC 24
Peak memory	219052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306104592 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.2306104592 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.656287281
Short name	T116
Test name
Test status
Simulation time	50079063 ps
CPU time	2.28 seconds
Started	Sep 09 07:50:12 PM UTC 24
Finished	Sep 09 07:50:16 PM UTC 24
Peak memory	229456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=656287281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_m em_rw_with_rand_reset.656287281 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_rw.748795347
Short name	T166
Test name
Test status
Simulation time	15988979 ps
CPU time	1.35 seconds
Started	Sep 09 07:50:10 PM UTC 24
Finished	Sep 09 07:50:12 PM UTC 24
Peak memory	218996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748795347 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.748795347 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_intr_test.564630669
Short name	T111
Test name
Test status
Simulation time	53025232 ps
CPU time	1.13 seconds
Started	Sep 09 07:50:09 PM UTC 24
Finished	Sep 09 07:50:11 PM UTC 24
Peak memory	219000 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564630669 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.564630669 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_walk.3669961868
Short name	T721
Test name
Test status
Simulation time	31751822 ps
CPU time	1.08 seconds
Started	Sep 09 07:50:09 PM UTC 24
Finished	Sep 09 07:50:11 PM UTC 24
Peak memory	219052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669961868 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.3669961868 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_same_csr_outstanding.1871365962
Short name	T722
Test name
Test status
Simulation time	188906227 ps
CPU time	2.28 seconds
Started	Sep 09 07:50:12 PM UTC 24
Finished	Sep 09 07:50:15 PM UTC 24
Peak memory	229396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871365962 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_outstanding.1871365962 +enable _masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3785419795
Short name	T92
Test name
Test status
Simulation time	52751486 ps
CPU time	1.9 seconds
Started	Sep 09 07:50:08 PM UTC 24
Finished	Sep 09 07:50:10 PM UTC 24
Peak memory	229456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785419795 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors.3785419795 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.4282036552
Short name	T93
Test name
Test status
Simulation time	124958107 ps
CPU time	2.25 seconds
Started	Sep 09 07:50:09 PM UTC 24
Finished	Sep 09 07:50:12 PM UTC 24
Peak memory	229440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282036552 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors_with_csr_rw. 4282036552 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_errors.1768990677
Short name	T115
Test name
Test status
Simulation time	37958203 ps
CPU time	2.72 seconds
Started	Sep 09 07:50:09 PM UTC 24
Finished	Sep 09 07:50:13 PM UTC 24
Peak memory	236592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768990677 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.1768990677 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_aliasing.2094336588
Short name	T730
Test name
Test status
Simulation time	140266422 ps
CPU time	10.04 seconds
Started	Sep 09 07:50:18 PM UTC 24
Finished	Sep 09 07:50:29 PM UTC 24
Peak memory	219332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094336588 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.2094336588 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.3455419517
Short name	T731
Test name
Test status
Simulation time	151627164 ps
CPU time	12.38 seconds
Started	Sep 09 07:50:17 PM UTC 24
Finished	Sep 09 07:50:30 PM UTC 24
Peak memory	219224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455419517 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.3455419517 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_hw_reset.2187028760
Short name	T133
Test name
Test status
Simulation time	107060589 ps
CPU time	1.85 seconds
Started	Sep 09 07:50:17 PM UTC 24
Finished	Sep 09 07:50:19 PM UTC 24
Peak memory	219012 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187028760 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.2187028760 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.2419979814
Short name	T118
Test name
Test status
Simulation time	454458762 ps
CPU time	3.71 seconds
Started	Sep 09 07:50:19 PM UTC 24
Finished	Sep 09 07:50:24 PM UTC 24
Peak memory	231508 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2419979814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_ mem_rw_with_rand_reset.2419979814 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_rw.2934249165
Short name	T134
Test name
Test status
Simulation time	126261427 ps
CPU time	1.93 seconds
Started	Sep 09 07:50:17 PM UTC 24
Finished	Sep 09 07:50:20 PM UTC 24
Peak memory	218952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934249165 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.2934249165 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_intr_test.3327167086
Short name	T113
Test name
Test status
Simulation time	25215256 ps
CPU time	1.08 seconds
Started	Sep 09 07:50:17 PM UTC 24
Finished	Sep 09 07:50:19 PM UTC 24
Peak memory	218992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327167086 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.3327167086 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_partial_access.481505962
Short name	T126
Test name
Test status
Simulation time	27337331 ps
CPU time	1.6 seconds
Started	Sep 09 07:50:14 PM UTC 24
Finished	Sep 09 07:50:16 PM UTC 24
Peak memory	228872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481505962 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial_access.481505962 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_walk.2800388892
Short name	T723
Test name
Test status
Simulation time	13950357 ps
CPU time	1.18 seconds
Started	Sep 09 07:50:13 PM UTC 24
Finished	Sep 09 07:50:16 PM UTC 24
Peak memory	219052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800388892 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.2800388892 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_same_csr_outstanding.1489032009
Short name	T725
Test name
Test status
Simulation time	40487335 ps
CPU time	3.11 seconds
Started	Sep 09 07:50:18 PM UTC 24
Finished	Sep 09 07:50:22 PM UTC 24
Peak memory	229396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489032009 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_outstanding.1489032009 +enable _masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors.1997299161
Short name	T95
Test name
Test status
Simulation time	87687051 ps
CPU time	1.65 seconds
Started	Sep 09 07:50:12 PM UTC 24
Finished	Sep 09 07:50:15 PM UTC 24
Peak memory	228860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997299161 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors.1997299161 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.1566283337
Short name	T94
Test name
Test status
Simulation time	81103523 ps
CPU time	2.6 seconds
Started	Sep 09 07:50:13 PM UTC 24
Finished	Sep 09 07:50:17 PM UTC 24
Peak memory	229592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566283337 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors_with_csr_rw. 1566283337 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_errors.2351132107
Short name	T117
Test name
Test status
Simulation time	61751150 ps
CPU time	4.85 seconds
Started	Sep 09 07:50:15 PM UTC 24
Finished	Sep 09 07:50:21 PM UTC 24
Peak memory	229492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351132107 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.2351132107 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.4108762777
Short name	T786
Test name
Test status
Simulation time	46192420 ps
CPU time	2.58 seconds
Started	Sep 09 07:50:59 PM UTC 24
Finished	Sep 09 07:51:03 PM UTC 24
Peak memory	229460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4108762777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr _mem_rw_with_rand_reset.4108762777 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.715230212
Short name	T783
Test name
Test status
Simulation time	22154606 ps
CPU time	1.43 seconds
Started	Sep 09 07:50:59 PM UTC 24
Finished	Sep 09 07:51:02 PM UTC 24
Peak memory	218992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715230212 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.715230212 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/10.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.2982966950
Short name	T153
Test name
Test status
Simulation time	13199257 ps
CPU time	1.14 seconds
Started	Sep 09 07:50:58 PM UTC 24
Finished	Sep 09 07:51:00 PM UTC 24
Peak memory	219056 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982966950 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.2982966950 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/10.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3146517045
Short name	T784
Test name
Test status
Simulation time	77283443 ps
CPU time	1.53 seconds
Started	Sep 09 07:50:59 PM UTC 24
Finished	Sep 09 07:51:02 PM UTC 24
Peak memory	228932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146517045 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr_outstanding.3146517045 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/10.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.2934181437
Short name	T98
Test name
Test status
Simulation time	54016345 ps
CPU time	2 seconds
Started	Sep 09 07:50:57 PM UTC 24
Finished	Sep 09 07:51:00 PM UTC 24
Peak memory	228804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934181437 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors_with_csr_rw .2934181437 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.447027977
Short name	T787
Test name
Test status
Simulation time	326566456 ps
CPU time	3.78 seconds
Started	Sep 09 07:50:58 PM UTC 24
Finished	Sep 09 07:51:03 PM UTC 24
Peak memory	231740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447027977 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.447027977 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/10.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.3252791968
Short name	T785
Test name
Test status
Simulation time	123995931 ps
CPU time	2.75 seconds
Started	Sep 09 07:50:58 PM UTC 24
Finished	Sep 09 07:51:02 PM UTC 24
Peak memory	229528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252791968 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.3252791968 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/10.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1705903937
Short name	T794
Test name
Test status
Simulation time	93823014 ps
CPU time	2.07 seconds
Started	Sep 09 07:51:02 PM UTC 24
Finished	Sep 09 07:51:05 PM UTC 24
Peak memory	229652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1705903937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr _mem_rw_with_rand_reset.1705903937 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.952723815
Short name	T792
Test name
Test status
Simulation time	49880867 ps
CPU time	1.31 seconds
Started	Sep 09 07:51:02 PM UTC 24
Finished	Sep 09 07:51:04 PM UTC 24
Peak memory	228772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952723815 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.952723815 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/11.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.1434269341
Short name	T790
Test name
Test status
Simulation time	25079110 ps
CPU time	1.06 seconds
Started	Sep 09 07:51:02 PM UTC 24
Finished	Sep 09 07:51:04 PM UTC 24
Peak memory	219056 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434269341 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.1434269341 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/11.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3283277415
Short name	T796
Test name
Test status
Simulation time	236562740 ps
CPU time	2.3 seconds
Started	Sep 09 07:51:02 PM UTC 24
Finished	Sep 09 07:51:05 PM UTC 24
Peak memory	229388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283277415 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr_outstanding.3283277415 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/11.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2508615446
Short name	T788
Test name
Test status
Simulation time	47897383 ps
CPU time	1.38 seconds
Started	Sep 09 07:51:00 PM UTC 24
Finished	Sep 09 07:51:03 PM UTC 24
Peak memory	218748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508615446 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors.2508615446 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/11.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.382546236
Short name	T789
Test name
Test status
Simulation time	106629911 ps
CPU time	2.09 seconds
Started	Sep 09 07:51:00 PM UTC 24
Finished	Sep 09 07:51:04 PM UTC 24
Peak memory	229652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382546236 -asse rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors_with_csr_rw. 382546236 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.2341195429
Short name	T791
Test name
Test status
Simulation time	321615097 ps
CPU time	2.27 seconds
Started	Sep 09 07:51:00 PM UTC 24
Finished	Sep 09 07:51:04 PM UTC 24
Peak memory	229520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341195429 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.2341195429 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/11.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.2381198613
Short name	T795
Test name
Test status
Simulation time	217606019 ps
CPU time	3.38 seconds
Started	Sep 09 07:51:00 PM UTC 24
Finished	Sep 09 07:51:05 PM UTC 24
Peak memory	229652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381198613 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.2381198613 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/11.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1953635986
Short name	T802
Test name
Test status
Simulation time	175623431 ps
CPU time	1.56 seconds
Started	Sep 09 07:51:04 PM UTC 24
Finished	Sep 09 07:51:07 PM UTC 24
Peak memory	228812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1953635986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr _mem_rw_with_rand_reset.1953635986 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.3230809995
Short name	T801
Test name
Test status
Simulation time	26168044 ps
CPU time	1.64 seconds
Started	Sep 09 07:51:04 PM UTC 24
Finished	Sep 09 07:51:07 PM UTC 24
Peak memory	218852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230809995 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.3230809995 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/12.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.48727562
Short name	T800
Test name
Test status
Simulation time	77477778 ps
CPU time	1.13 seconds
Started	Sep 09 07:51:04 PM UTC 24
Finished	Sep 09 07:51:06 PM UTC 24
Peak memory	219028 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48727562 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.48727562 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/12.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.2733153016
Short name	T803
Test name
Test status
Simulation time	47779444 ps
CPU time	2.09 seconds
Started	Sep 09 07:51:04 PM UTC 24
Finished	Sep 09 07:51:07 PM UTC 24
Peak memory	229576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733153016 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr_outstanding.2733153016 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/12.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.502921203
Short name	T798
Test name
Test status
Simulation time	47896413 ps
CPU time	2.11 seconds
Started	Sep 09 07:51:03 PM UTC 24
Finished	Sep 09 07:51:06 PM UTC 24
Peak memory	229932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502921203 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors.502921203 +enable_maskin g=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/12.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.3042739599
Short name	T797
Test name
Test status
Simulation time	89955278 ps
CPU time	1.87 seconds
Started	Sep 09 07:51:03 PM UTC 24
Finished	Sep 09 07:51:06 PM UTC 24
Peak memory	228204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042739599 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors_with_csr_rw .3042739599 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.3252598238
Short name	T799
Test name
Test status
Simulation time	58592576 ps
CPU time	2.24 seconds
Started	Sep 09 07:51:03 PM UTC 24
Finished	Sep 09 07:51:06 PM UTC 24
Peak memory	229776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252598238 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.3252598238 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/12.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1852476260
Short name	T815
Test name
Test status
Simulation time	253013618 ps
CPU time	3.57 seconds
Started	Sep 09 07:51:07 PM UTC 24
Finished	Sep 09 07:51:11 PM UTC 24
Peak memory	231700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1852476260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr _mem_rw_with_rand_reset.1852476260 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.796899742
Short name	T804
Test name
Test status
Simulation time	168959837 ps
CPU time	1.19 seconds
Started	Sep 09 07:51:06 PM UTC 24
Finished	Sep 09 07:51:08 PM UTC 24
Peak memory	218992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796899742 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.796899742 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/13.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.2542220201
Short name	T806
Test name
Test status
Simulation time	47657682 ps
CPU time	1.23 seconds
Started	Sep 09 07:51:06 PM UTC 24
Finished	Sep 09 07:51:08 PM UTC 24
Peak memory	218996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542220201 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.2542220201 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/13.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.801999918
Short name	T813
Test name
Test status
Simulation time	212340774 ps
CPU time	2.82 seconds
Started	Sep 09 07:51:07 PM UTC 24
Finished	Sep 09 07:51:11 PM UTC 24
Peak memory	229448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801999918 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr_outstanding.801999918 +enable_ masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/13.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1786150010
Short name	T805
Test name
Test status
Simulation time	43935731 ps
CPU time	1.4 seconds
Started	Sep 09 07:51:05 PM UTC 24
Finished	Sep 09 07:51:08 PM UTC 24
Peak memory	228748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786150010 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors.1786150010 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/13.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2975683195
Short name	T808
Test name
Test status
Simulation time	454973089 ps
CPU time	2.81 seconds
Started	Sep 09 07:51:05 PM UTC 24
Finished	Sep 09 07:51:09 PM UTC 24
Peak memory	236960 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975683195 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors_with_csr_rw .2975683195 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.4034966065
Short name	T807
Test name
Test status
Simulation time	202784951 ps
CPU time	2.74 seconds
Started	Sep 09 07:51:05 PM UTC 24
Finished	Sep 09 07:51:09 PM UTC 24
Peak memory	229772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034966065 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.4034966065 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/13.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.1668079174
Short name	T809
Test name
Test status
Simulation time	57958460 ps
CPU time	2.84 seconds
Started	Sep 09 07:51:05 PM UTC 24
Finished	Sep 09 07:51:10 PM UTC 24
Peak memory	229588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668079174 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.1668079174 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/13.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.3194514759
Short name	T821
Test name
Test status
Simulation time	265142205 ps
CPU time	2.88 seconds
Started	Sep 09 07:51:09 PM UTC 24
Finished	Sep 09 07:51:13 PM UTC 24
Peak memory	231508 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3194514759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr _mem_rw_with_rand_reset.3194514759 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.2844602899
Short name	T812
Test name
Test status
Simulation time	179471549 ps
CPU time	1.37 seconds
Started	Sep 09 07:51:08 PM UTC 24
Finished	Sep 09 07:51:10 PM UTC 24
Peak memory	218940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844602899 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.2844602899 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/14.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.725248760
Short name	T811
Test name
Test status
Simulation time	14871609 ps
CPU time	1.03 seconds
Started	Sep 09 07:51:08 PM UTC 24
Finished	Sep 09 07:51:10 PM UTC 24
Peak memory	218936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725248760 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.725248760 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/14.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1075467243
Short name	T816
Test name
Test status
Simulation time	100619702 ps
CPU time	1.62 seconds
Started	Sep 09 07:51:09 PM UTC 24
Finished	Sep 09 07:51:12 PM UTC 24
Peak memory	228932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075467243 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr_outstanding.1075467243 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/14.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.3144922344
Short name	T810
Test name
Test status
Simulation time	92023305 ps
CPU time	1.77 seconds
Started	Sep 09 07:51:07 PM UTC 24
Finished	Sep 09 07:51:10 PM UTC 24
Peak memory	228868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144922344 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors.3144922344 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/14.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.4281876559
Short name	T814
Test name
Test status
Simulation time	84385369 ps
CPU time	2.34 seconds
Started	Sep 09 07:51:08 PM UTC 24
Finished	Sep 09 07:51:11 PM UTC 24
Peak memory	230060 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281876559 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors_with_csr_rw .4281876559 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.341015443
Short name	T817
Test name
Test status
Simulation time	126391763 ps
CPU time	2.86 seconds
Started	Sep 09 07:51:08 PM UTC 24
Finished	Sep 09 07:51:12 PM UTC 24
Peak memory	229716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341015443 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.341015443 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/14.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.2230422620
Short name	T161
Test name
Test status
Simulation time	164602181 ps
CPU time	4.11 seconds
Started	Sep 09 07:51:08 PM UTC 24
Finished	Sep 09 07:51:13 PM UTC 24
Peak memory	229400 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230422620 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.2230422620 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/14.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.2577322586
Short name	T826
Test name
Test status
Simulation time	22732879 ps
CPU time	2.01 seconds
Started	Sep 09 07:51:12 PM UTC 24
Finished	Sep 09 07:51:15 PM UTC 24
Peak memory	228912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2577322586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr _mem_rw_with_rand_reset.2577322586 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.3018051313
Short name	T820
Test name
Test status
Simulation time	26961672 ps
CPU time	1.07 seconds
Started	Sep 09 07:51:11 PM UTC 24
Finished	Sep 09 07:51:13 PM UTC 24
Peak memory	218836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018051313 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.3018051313 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/15.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.277102237
Short name	T819
Test name
Test status
Simulation time	29020300 ps
CPU time	1.15 seconds
Started	Sep 09 07:51:11 PM UTC 24
Finished	Sep 09 07:51:13 PM UTC 24
Peak memory	218908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277102237 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.277102237 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/15.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2217796378
Short name	T824
Test name
Test status
Simulation time	109357901 ps
CPU time	3.01 seconds
Started	Sep 09 07:51:11 PM UTC 24
Finished	Sep 09 07:51:15 PM UTC 24
Peak memory	229448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217796378 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr_outstanding.2217796378 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/15.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.3292614512
Short name	T818
Test name
Test status
Simulation time	132715259 ps
CPU time	1.91 seconds
Started	Sep 09 07:51:09 PM UTC 24
Finished	Sep 09 07:51:12 PM UTC 24
Peak memory	228748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292614512 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors.3292614512 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/15.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.3875799341
Short name	T822
Test name
Test status
Simulation time	112845413 ps
CPU time	3.2 seconds
Started	Sep 09 07:51:09 PM UTC 24
Finished	Sep 09 07:51:14 PM UTC 24
Peak memory	236984 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875799341 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors_with_csr_rw .3875799341 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.778681857
Short name	T823
Test name
Test status
Simulation time	242297352 ps
CPU time	2.72 seconds
Started	Sep 09 07:51:10 PM UTC 24
Finished	Sep 09 07:51:14 PM UTC 24
Peak memory	229776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778681857 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.778681857 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/15.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.4103829395
Short name	T164
Test name
Test status
Simulation time	406882007 ps
CPU time	3.07 seconds
Started	Sep 09 07:51:10 PM UTC 24
Finished	Sep 09 07:51:15 PM UTC 24
Peak memory	229528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103829395 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.4103829395 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/15.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2129188531
Short name	T838
Test name
Test status
Simulation time	67903241 ps
CPU time	3.16 seconds
Started	Sep 09 07:51:14 PM UTC 24
Finished	Sep 09 07:51:19 PM UTC 24
Peak memory	229460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2129188531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr _mem_rw_with_rand_reset.2129188531 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.3025579835
Short name	T830
Test name
Test status
Simulation time	22662829 ps
CPU time	1.24 seconds
Started	Sep 09 07:51:13 PM UTC 24
Finished	Sep 09 07:51:15 PM UTC 24
Peak memory	218996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025579835 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.3025579835 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/16.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.1423493346
Short name	T829
Test name
Test status
Simulation time	32944102 ps
CPU time	1.25 seconds
Started	Sep 09 07:51:13 PM UTC 24
Finished	Sep 09 07:51:15 PM UTC 24
Peak memory	218996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423493346 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.1423493346 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/16.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.1179520185
Short name	T831
Test name
Test status
Simulation time	112145351 ps
CPU time	1.78 seconds
Started	Sep 09 07:51:14 PM UTC 24
Finished	Sep 09 07:51:17 PM UTC 24
Peak memory	228928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179520185 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr_outstanding.1179520185 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/16.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.780657369
Short name	T827
Test name
Test status
Simulation time	483286265 ps
CPU time	2.06 seconds
Started	Sep 09 07:51:12 PM UTC 24
Finished	Sep 09 07:51:15 PM UTC 24
Peak memory	229972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780657369 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors.780657369 +enable_maskin g=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/16.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.3889774803
Short name	T828
Test name
Test status
Simulation time	121851957 ps
CPU time	2.14 seconds
Started	Sep 09 07:51:12 PM UTC 24
Finished	Sep 09 07:51:15 PM UTC 24
Peak memory	229892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889774803 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors_with_csr_rw .3889774803 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.3683554062
Short name	T836
Test name
Test status
Simulation time	97838878 ps
CPU time	4.27 seconds
Started	Sep 09 07:51:13 PM UTC 24
Finished	Sep 09 07:51:18 PM UTC 24
Peak memory	229520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683554062 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.3683554062 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/16.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.3675688085
Short name	T159
Test name
Test status
Simulation time	196269470 ps
CPU time	4.83 seconds
Started	Sep 09 07:51:13 PM UTC 24
Finished	Sep 09 07:51:19 PM UTC 24
Peak memory	229400 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675688085 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.3675688085 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/16.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1550345708
Short name	T839
Test name
Test status
Simulation time	67176166 ps
CPU time	2.07 seconds
Started	Sep 09 07:51:16 PM UTC 24
Finished	Sep 09 07:51:19 PM UTC 24
Peak memory	229460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1550345708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr _mem_rw_with_rand_reset.1550345708 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.1639890619
Short name	T835
Test name
Test status
Simulation time	24854880 ps
CPU time	1.37 seconds
Started	Sep 09 07:51:16 PM UTC 24
Finished	Sep 09 07:51:18 PM UTC 24
Peak memory	218996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639890619 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.1639890619 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/17.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.3983042508
Short name	T832
Test name
Test status
Simulation time	31960497 ps
CPU time	0.93 seconds
Started	Sep 09 07:51:16 PM UTC 24
Finished	Sep 09 07:51:17 PM UTC 24
Peak memory	218996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983042508 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.3983042508 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/17.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.367421901
Short name	T840
Test name
Test status
Simulation time	57619604 ps
CPU time	2.28 seconds
Started	Sep 09 07:51:16 PM UTC 24
Finished	Sep 09 07:51:19 PM UTC 24
Peak memory	229424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367421901 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr_outstanding.367421901 +enable_ masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/17.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2298705199
Short name	T833
Test name
Test status
Simulation time	83066907 ps
CPU time	2.2 seconds
Started	Sep 09 07:51:14 PM UTC 24
Finished	Sep 09 07:51:18 PM UTC 24
Peak memory	229812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298705199 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors.2298705199 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/17.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1089216429
Short name	T837
Test name
Test status
Simulation time	38726152 ps
CPU time	2.85 seconds
Started	Sep 09 07:51:14 PM UTC 24
Finished	Sep 09 07:51:18 PM UTC 24
Peak memory	229604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089216429 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors_with_csr_rw .1089216429 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.3359519126
Short name	T825
Test name
Test status
Simulation time	229857871 ps
CPU time	3.68 seconds
Started	Sep 09 07:51:14 PM UTC 24
Finished	Sep 09 07:51:19 PM UTC 24
Peak memory	229708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359519126 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.3359519126 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/17.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.4264346491
Short name	T841
Test name
Test status
Simulation time	191419275 ps
CPU time	3.22 seconds
Started	Sep 09 07:51:16 PM UTC 24
Finished	Sep 09 07:51:20 PM UTC 24
Peak memory	229504 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264346491 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.4264346491 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/17.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.37551920
Short name	T852
Test name
Test status
Simulation time	350569197 ps
CPU time	2.78 seconds
Started	Sep 09 07:51:19 PM UTC 24
Finished	Sep 09 07:51:23 PM UTC 24
Peak memory	231632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=37551920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_m em_rw_with_rand_reset.37551920 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.3961880533
Short name	T844
Test name
Test status
Simulation time	31086940 ps
CPU time	1.58 seconds
Started	Sep 09 07:51:18 PM UTC 24
Finished	Sep 09 07:51:21 PM UTC 24
Peak memory	218952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961880533 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.3961880533 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/18.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.3697590482
Short name	T842
Test name
Test status
Simulation time	28961766 ps
CPU time	0.94 seconds
Started	Sep 09 07:51:18 PM UTC 24
Finished	Sep 09 07:51:20 PM UTC 24
Peak memory	218996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697590482 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.3697590482 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/18.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.469138678
Short name	T849
Test name
Test status
Simulation time	64477854 ps
CPU time	2.2 seconds
Started	Sep 09 07:51:19 PM UTC 24
Finished	Sep 09 07:51:22 PM UTC 24
Peak memory	229372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469138678 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr_outstanding.469138678 +enable_ masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/18.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.3465950567
Short name	T834
Test name
Test status
Simulation time	19874403 ps
CPU time	1.2 seconds
Started	Sep 09 07:51:16 PM UTC 24
Finished	Sep 09 07:51:18 PM UTC 24
Peak memory	228680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465950567 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors.3465950567 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/18.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3601363117
Short name	T843
Test name
Test status
Simulation time	76539146 ps
CPU time	2.57 seconds
Started	Sep 09 07:51:17 PM UTC 24
Finished	Sep 09 07:51:20 PM UTC 24
Peak memory	229668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601363117 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors_with_csr_rw .3601363117 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.1749622559
Short name	T845
Test name
Test status
Simulation time	80639077 ps
CPU time	3.15 seconds
Started	Sep 09 07:51:17 PM UTC 24
Finished	Sep 09 07:51:21 PM UTC 24
Peak memory	229476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749622559 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.1749622559 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/18.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.2709567604
Short name	T848
Test name
Test status
Simulation time	461695436 ps
CPU time	3.11 seconds
Started	Sep 09 07:51:18 PM UTC 24
Finished	Sep 09 07:51:22 PM UTC 24
Peak memory	229528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709567604 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.2709567604 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/18.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.1646001219
Short name	T858
Test name
Test status
Simulation time	251151821 ps
CPU time	2.55 seconds
Started	Sep 09 07:51:21 PM UTC 24
Finished	Sep 09 07:51:24 PM UTC 24
Peak memory	229460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1646001219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr _mem_rw_with_rand_reset.1646001219 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.2035486187
Short name	T853
Test name
Test status
Simulation time	548526395 ps
CPU time	1.84 seconds
Started	Sep 09 07:51:21 PM UTC 24
Finished	Sep 09 07:51:24 PM UTC 24
Peak memory	218900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035486187 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.2035486187 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/19.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.1188465087
Short name	T846
Test name
Test status
Simulation time	14243271 ps
CPU time	1.16 seconds
Started	Sep 09 07:51:20 PM UTC 24
Finished	Sep 09 07:51:22 PM UTC 24
Peak memory	218996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188465087 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.1188465087 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/19.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1026395992
Short name	T859
Test name
Test status
Simulation time	212775184 ps
CPU time	2.63 seconds
Started	Sep 09 07:51:21 PM UTC 24
Finished	Sep 09 07:51:24 PM UTC 24
Peak memory	229384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026395992 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr_outstanding.1026395992 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/19.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.2704741920
Short name	T847
Test name
Test status
Simulation time	124842949 ps
CPU time	1.75 seconds
Started	Sep 09 07:51:19 PM UTC 24
Finished	Sep 09 07:51:22 PM UTC 24
Peak memory	228808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704741920 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors.2704741920 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/19.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2196203706
Short name	T857
Test name
Test status
Simulation time	238632267 ps
CPU time	3.81 seconds
Started	Sep 09 07:51:19 PM UTC 24
Finished	Sep 09 07:51:24 PM UTC 24
Peak memory	229888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196203706 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors_with_csr_rw .2196203706 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.4266732590
Short name	T851
Test name
Test status
Simulation time	101660255 ps
CPU time	2.54 seconds
Started	Sep 09 07:51:19 PM UTC 24
Finished	Sep 09 07:51:23 PM UTC 24
Peak memory	233744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266732590 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.4266732590 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/19.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.358743645
Short name	T746
Test name
Test status
Simulation time	936817917 ps
CPU time	9.49 seconds
Started	Sep 09 07:50:28 PM UTC 24
Finished	Sep 09 07:50:38 PM UTC 24
Peak memory	219152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358743645 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.358743645 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.404371967
Short name	T756
Test name
Test status
Simulation time	1514180279 ps
CPU time	16.03 seconds
Started	Sep 09 07:50:27 PM UTC 24
Finished	Sep 09 07:50:45 PM UTC 24
Peak memory	219152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404371967 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.404371967 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_hw_reset.1501628246
Short name	T728
Test name
Test status
Simulation time	60966477 ps
CPU time	1.52 seconds
Started	Sep 09 07:50:26 PM UTC 24
Finished	Sep 09 07:50:28 PM UTC 24
Peak memory	219052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501628246 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.1501628246 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.2788100323
Short name	T736
Test name
Test status
Simulation time	81531367 ps
CPU time	3.43 seconds
Started	Sep 09 07:50:28 PM UTC 24
Finished	Sep 09 07:50:32 PM UTC 24
Peak memory	231508 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2788100323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_ mem_rw_with_rand_reset.2788100323 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_rw.3848654515
Short name	T729
Test name
Test status
Simulation time	66642790 ps
CPU time	1.57 seconds
Started	Sep 09 07:50:26 PM UTC 24
Finished	Sep 09 07:50:29 PM UTC 24
Peak memory	228932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848654515 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.3848654515 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_intr_test.543652578
Short name	T148
Test name
Test status
Simulation time	20436101 ps
CPU time	1.1 seconds
Started	Sep 09 07:50:26 PM UTC 24
Finished	Sep 09 07:50:28 PM UTC 24
Peak memory	218988 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543652578 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.543652578 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_partial_access.3236046893
Short name	T127
Test name
Test status
Simulation time	93636296 ps
CPU time	1.86 seconds
Started	Sep 09 07:50:22 PM UTC 24
Finished	Sep 09 07:50:25 PM UTC 24
Peak memory	228872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236046893 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial_access.3236046893 +enable_mas king=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_walk.2761335117
Short name	T726
Test name
Test status
Simulation time	11483797 ps
CPU time	1.09 seconds
Started	Sep 09 07:50:20 PM UTC 24
Finished	Sep 09 07:50:22 PM UTC 24
Peak memory	219052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761335117 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.2761335117 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3753213014
Short name	T734
Test name
Test status
Simulation time	109032434 ps
CPU time	2.82 seconds
Started	Sep 09 07:50:28 PM UTC 24
Finished	Sep 09 07:50:31 PM UTC 24
Peak memory	229396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753213014 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_outstanding.3753213014 +enable _masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors.3570326458
Short name	T104
Test name
Test status
Simulation time	272818121 ps
CPU time	1.81 seconds
Started	Sep 09 07:50:19 PM UTC 24
Finished	Sep 09 07:50:22 PM UTC 24
Peak memory	218560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570326458 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors.3570326458 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_errors.869169011
Short name	T727
Test name
Test status
Simulation time	37873058 ps
CPU time	3.36 seconds
Started	Sep 09 07:50:22 PM UTC 24
Finished	Sep 09 07:50:27 PM UTC 24
Peak memory	229520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869169011 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.869169011 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_intg_err.2242343919
Short name	T110
Test name
Test status
Simulation time	376914599 ps
CPU time	5.53 seconds
Started	Sep 09 07:50:22 PM UTC 24
Finished	Sep 09 07:50:29 PM UTC 24
Peak memory	229568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242343919 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.2242343919 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.1839015917
Short name	T850
Test name
Test status
Simulation time	69803504 ps
CPU time	1.18 seconds
Started	Sep 09 07:51:21 PM UTC 24
Finished	Sep 09 07:51:23 PM UTC 24
Peak memory	218996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839015917 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.1839015917 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/20.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.567941097
Short name	T855
Test name
Test status
Simulation time	17236364 ps
CPU time	1.15 seconds
Started	Sep 09 07:51:22 PM UTC 24
Finished	Sep 09 07:51:24 PM UTC 24
Peak memory	218936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567941097 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.567941097 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/21.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.146661174
Short name	T854
Test name
Test status
Simulation time	23297543 ps
CPU time	1.1 seconds
Started	Sep 09 07:51:22 PM UTC 24
Finished	Sep 09 07:51:24 PM UTC 24
Peak memory	218936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146661174 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.146661174 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/22.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.4044158494
Short name	T856
Test name
Test status
Simulation time	20282533 ps
CPU time	1.14 seconds
Started	Sep 09 07:51:22 PM UTC 24
Finished	Sep 09 07:51:24 PM UTC 24
Peak memory	218996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044158494 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.4044158494 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/23.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.664306354
Short name	T860
Test name
Test status
Simulation time	55172087 ps
CPU time	0.95 seconds
Started	Sep 09 07:51:23 PM UTC 24
Finished	Sep 09 07:51:25 PM UTC 24
Peak memory	218996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664306354 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.664306354 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/24.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.1517958217
Short name	T861
Test name
Test status
Simulation time	42588546 ps
CPU time	1.08 seconds
Started	Sep 09 07:51:23 PM UTC 24
Finished	Sep 09 07:51:25 PM UTC 24
Peak memory	219056 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517958217 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.1517958217 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/25.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.1379272382
Short name	T862
Test name
Test status
Simulation time	12269654 ps
CPU time	1.13 seconds
Started	Sep 09 07:51:23 PM UTC 24
Finished	Sep 09 07:51:25 PM UTC 24
Peak memory	219056 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379272382 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.1379272382 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/26.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.149980749
Short name	T863
Test name
Test status
Simulation time	12352638 ps
CPU time	1.16 seconds
Started	Sep 09 07:51:23 PM UTC 24
Finished	Sep 09 07:51:25 PM UTC 24
Peak memory	218936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149980749 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.149980749 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/27.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.3308413742
Short name	T866
Test name
Test status
Simulation time	14830367 ps
CPU time	1.08 seconds
Started	Sep 09 07:51:24 PM UTC 24
Finished	Sep 09 07:51:26 PM UTC 24
Peak memory	219056 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308413742 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.3308413742 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/28.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.308530893
Short name	T865
Test name
Test status
Simulation time	11687601 ps
CPU time	0.98 seconds
Started	Sep 09 07:51:24 PM UTC 24
Finished	Sep 09 07:51:26 PM UTC 24
Peak memory	218996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308530893 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.308530893 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/29.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.1535377319
Short name	T747
Test name
Test status
Simulation time	379790489 ps
CPU time	5.11 seconds
Started	Sep 09 07:50:32 PM UTC 24
Finished	Sep 09 07:50:38 PM UTC 24
Peak memory	219144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535377319 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.1535377319 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.2272438788
Short name	T779
Test name
Test status
Simulation time	20466664889 ps
CPU time	26.82 seconds
Started	Sep 09 07:50:32 PM UTC 24
Finished	Sep 09 07:51:00 PM UTC 24
Peak memory	219208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272438788 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.2272438788 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_hw_reset.2831253826
Short name	T738
Test name
Test status
Simulation time	208326991 ps
CPU time	1.43 seconds
Started	Sep 09 07:50:31 PM UTC 24
Finished	Sep 09 07:50:34 PM UTC 24
Peak memory	219052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831253826 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.2831253826 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.3639348423
Short name	T743
Test name
Test status
Simulation time	300915450 ps
CPU time	3.85 seconds
Started	Sep 09 07:50:32 PM UTC 24
Finished	Sep 09 07:50:37 PM UTC 24
Peak memory	231508 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3639348423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_ mem_rw_with_rand_reset.3639348423 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_rw.784653126
Short name	T737
Test name
Test status
Simulation time	59182427 ps
CPU time	1.25 seconds
Started	Sep 09 07:50:31 PM UTC 24
Finished	Sep 09 07:50:33 PM UTC 24
Peak memory	218952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784653126 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.784653126 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_partial_access.1108396589
Short name	T735
Test name
Test status
Simulation time	90989023 ps
CPU time	1.83 seconds
Started	Sep 09 07:50:29 PM UTC 24
Finished	Sep 09 07:50:32 PM UTC 24
Peak memory	228872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108396589 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial_access.1108396589 +enable_mas king=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_walk.3676313465
Short name	T732
Test name
Test status
Simulation time	96698398 ps
CPU time	1.14 seconds
Started	Sep 09 07:50:29 PM UTC 24
Finished	Sep 09 07:50:31 PM UTC 24
Peak memory	219052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676313465 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.3676313465 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_same_csr_outstanding.1489423832
Short name	T740
Test name
Test status
Simulation time	54593367 ps
CPU time	2.45 seconds
Started	Sep 09 07:50:32 PM UTC 24
Finished	Sep 09 07:50:36 PM UTC 24
Peak memory	229456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489423832 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_outstanding.1489423832 +enable _masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors.2742087929
Short name	T107
Test name
Test status
Simulation time	64555645 ps
CPU time	1.69 seconds
Started	Sep 09 07:50:28 PM UTC 24
Finished	Sep 09 07:50:30 PM UTC 24
Peak memory	228668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742087929 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors.2742087929 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.59101896
Short name	T733
Test name
Test status
Simulation time	44927890 ps
CPU time	2.42 seconds
Started	Sep 09 07:50:28 PM UTC 24
Finished	Sep 09 07:50:31 PM UTC 24
Peak memory	236724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59101896 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors_with_csr_rw.59 101896 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_errors.703527426
Short name	T739
Test name
Test status
Simulation time	122904236 ps
CPU time	3.97 seconds
Started	Sep 09 07:50:30 PM UTC 24
Finished	Sep 09 07:50:35 PM UTC 24
Peak memory	229520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703527426 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.703527426 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_intg_err.937005484
Short name	T155
Test name
Test status
Simulation time	239251652 ps
CPU time	6.42 seconds
Started	Sep 09 07:50:30 PM UTC 24
Finished	Sep 09 07:50:37 PM UTC 24
Peak memory	219184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937005484 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.937005484 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.3211689832
Short name	T867
Test name
Test status
Simulation time	27453366 ps
CPU time	1.07 seconds
Started	Sep 09 07:51:24 PM UTC 24
Finished	Sep 09 07:51:26 PM UTC 24
Peak memory	218996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211689832 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.3211689832 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/30.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.2809643209
Short name	T868
Test name
Test status
Simulation time	15602945 ps
CPU time	0.99 seconds
Started	Sep 09 07:51:24 PM UTC 24
Finished	Sep 09 07:51:26 PM UTC 24
Peak memory	218996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809643209 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.2809643209 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/31.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.1252075301
Short name	T864
Test name
Test status
Simulation time	29596825 ps
CPU time	0.73 seconds
Started	Sep 09 07:51:24 PM UTC 24
Finished	Sep 09 07:51:26 PM UTC 24
Peak memory	218996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252075301 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.1252075301 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/32.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.217630778
Short name	T869
Test name
Test status
Simulation time	40490008 ps
CPU time	1.13 seconds
Started	Sep 09 07:51:26 PM UTC 24
Finished	Sep 09 07:51:28 PM UTC 24
Peak memory	218996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217630778 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.217630778 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/33.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.570425973
Short name	T870
Test name
Test status
Simulation time	12768673 ps
CPU time	1.08 seconds
Started	Sep 09 07:51:26 PM UTC 24
Finished	Sep 09 07:51:28 PM UTC 24
Peak memory	218936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570425973 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.570425973 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/34.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.410678878
Short name	T871
Test name
Test status
Simulation time	13356265 ps
CPU time	1.07 seconds
Started	Sep 09 07:51:26 PM UTC 24
Finished	Sep 09 07:51:28 PM UTC 24
Peak memory	218996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410678878 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.410678878 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/35.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.2268947814
Short name	T873
Test name
Test status
Simulation time	15641706 ps
CPU time	1.19 seconds
Started	Sep 09 07:51:26 PM UTC 24
Finished	Sep 09 07:51:28 PM UTC 24
Peak memory	218996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268947814 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.2268947814 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/36.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.3499643095
Short name	T876
Test name
Test status
Simulation time	11058724 ps
CPU time	1.21 seconds
Started	Sep 09 07:51:26 PM UTC 24
Finished	Sep 09 07:51:28 PM UTC 24
Peak memory	218924 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499643095 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.3499643095 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/37.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.342252848
Short name	T872
Test name
Test status
Simulation time	50994453 ps
CPU time	0.94 seconds
Started	Sep 09 07:51:26 PM UTC 24
Finished	Sep 09 07:51:28 PM UTC 24
Peak memory	218936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342252848 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.342252848 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/38.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.1133332791
Short name	T875
Test name
Test status
Simulation time	71552405 ps
CPU time	1.09 seconds
Started	Sep 09 07:51:26 PM UTC 24
Finished	Sep 09 07:51:28 PM UTC 24
Peak memory	218996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133332791 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.1133332791 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/39.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.2351407319
Short name	T758
Test name
Test status
Simulation time	1362026031 ps
CPU time	6.53 seconds
Started	Sep 09 07:50:38 PM UTC 24
Finished	Sep 09 07:50:46 PM UTC 24
Peak memory	219272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351407319 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.2351407319 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.3632375136
Short name	T793
Test name
Test status
Simulation time	5980059110 ps
CPU time	24.97 seconds
Started	Sep 09 07:50:38 PM UTC 24
Finished	Sep 09 07:51:04 PM UTC 24
Peak memory	219228 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632375136 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.3632375136 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_hw_reset.1917908496
Short name	T750
Test name
Test status
Simulation time	28550106 ps
CPU time	1.78 seconds
Started	Sep 09 07:50:38 PM UTC 24
Finished	Sep 09 07:50:41 PM UTC 24
Peak memory	219012 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917908496 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.1917908496 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.3814796746
Short name	T752
Test name
Test status
Simulation time	163839866 ps
CPU time	2.1 seconds
Started	Sep 09 07:50:39 PM UTC 24
Finished	Sep 09 07:50:42 PM UTC 24
Peak memory	229588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3814796746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_ mem_rw_with_rand_reset.3814796746 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.2115303210
Short name	T748
Test name
Test status
Simulation time	105883566 ps
CPU time	1.35 seconds
Started	Sep 09 07:50:38 PM UTC 24
Finished	Sep 09 07:50:40 PM UTC 24
Peak memory	228936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115303210 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.2115303210 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_intr_test.1266182801
Short name	T150
Test name
Test status
Simulation time	38997849 ps
CPU time	1.15 seconds
Started	Sep 09 07:50:37 PM UTC 24
Finished	Sep 09 07:50:39 PM UTC 24
Peak memory	218992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266182801 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.1266182801 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_partial_access.2296349649
Short name	T744
Test name
Test status
Simulation time	37341020 ps
CPU time	1.99 seconds
Started	Sep 09 07:50:35 PM UTC 24
Finished	Sep 09 07:50:38 PM UTC 24
Peak memory	228868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296349649 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial_access.2296349649 +enable_mas king=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_walk.4172816253
Short name	T741
Test name
Test status
Simulation time	15201171 ps
CPU time	1.17 seconds
Started	Sep 09 07:50:35 PM UTC 24
Finished	Sep 09 07:50:37 PM UTC 24
Peak memory	218992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172816253 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.4172816253 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.2679996418
Short name	T753
Test name
Test status
Simulation time	109383976 ps
CPU time	2.8 seconds
Started	Sep 09 07:50:39 PM UTC 24
Finished	Sep 09 07:50:43 PM UTC 24
Peak memory	229396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679996418 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_outstanding.2679996418 +enable _masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors.1079962318
Short name	T742
Test name
Test status
Simulation time	117371156 ps
CPU time	1.65 seconds
Started	Sep 09 07:50:34 PM UTC 24
Finished	Sep 09 07:50:37 PM UTC 24
Peak memory	228668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079962318 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors.1079962318 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.7066696
Short name	T745
Test name
Test status
Simulation time	47509622 ps
CPU time	2.35 seconds
Started	Sep 09 07:50:34 PM UTC 24
Finished	Sep 09 07:50:38 PM UTC 24
Peak memory	229528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7066696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors_with_csr_rw.706 6696 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.4293122966
Short name	T749
Test name
Test status
Simulation time	380061372 ps
CPU time	4.58 seconds
Started	Sep 09 07:50:35 PM UTC 24
Finished	Sep 09 07:50:40 PM UTC 24
Peak memory	229516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293122966 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.4293122966 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.435685390
Short name	T160
Test name
Test status
Simulation time	276700429 ps
CPU time	2.99 seconds
Started	Sep 09 07:50:36 PM UTC 24
Finished	Sep 09 07:50:40 PM UTC 24
Peak memory	229576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435685390 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.435685390 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.3868520635
Short name	T874
Test name
Test status
Simulation time	27780664 ps
CPU time	1.07 seconds
Started	Sep 09 07:51:26 PM UTC 24
Finished	Sep 09 07:51:28 PM UTC 24
Peak memory	218996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868520635 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.3868520635 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/40.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.2642337705
Short name	T877
Test name
Test status
Simulation time	31769574 ps
CPU time	0.97 seconds
Started	Sep 09 07:51:27 PM UTC 24
Finished	Sep 09 07:51:29 PM UTC 24
Peak memory	218996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642337705 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.2642337705 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/41.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.907060991
Short name	T879
Test name
Test status
Simulation time	46838463 ps
CPU time	1.04 seconds
Started	Sep 09 07:51:27 PM UTC 24
Finished	Sep 09 07:51:29 PM UTC 24
Peak memory	218996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907060991 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.907060991 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/42.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.4077384396
Short name	T880
Test name
Test status
Simulation time	29906471 ps
CPU time	1.04 seconds
Started	Sep 09 07:51:27 PM UTC 24
Finished	Sep 09 07:51:29 PM UTC 24
Peak memory	218812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077384396 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.4077384396 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/43.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.155024276
Short name	T878
Test name
Test status
Simulation time	11826775 ps
CPU time	0.87 seconds
Started	Sep 09 07:51:27 PM UTC 24
Finished	Sep 09 07:51:29 PM UTC 24
Peak memory	218888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155024276 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.155024276 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/44.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.3725202443
Short name	T882
Test name
Test status
Simulation time	28267030 ps
CPU time	1.12 seconds
Started	Sep 09 07:51:27 PM UTC 24
Finished	Sep 09 07:51:29 PM UTC 24
Peak memory	218936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725202443 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.3725202443 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/45.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.862664999
Short name	T883
Test name
Test status
Simulation time	17760271 ps
CPU time	1.15 seconds
Started	Sep 09 07:51:27 PM UTC 24
Finished	Sep 09 07:51:29 PM UTC 24
Peak memory	218936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862664999 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.862664999 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/46.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.2117252004
Short name	T881
Test name
Test status
Simulation time	17121908 ps
CPU time	0.9 seconds
Started	Sep 09 07:51:27 PM UTC 24
Finished	Sep 09 07:51:29 PM UTC 24
Peak memory	218996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117252004 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.2117252004 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/47.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.1146289505
Short name	T884
Test name
Test status
Simulation time	103576450 ps
CPU time	1.03 seconds
Started	Sep 09 07:51:28 PM UTC 24
Finished	Sep 09 07:51:30 PM UTC 24
Peak memory	219056 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146289505 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.1146289505 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/48.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.3070904647
Short name	T885
Test name
Test status
Simulation time	17117626 ps
CPU time	1.14 seconds
Started	Sep 09 07:51:28 PM UTC 24
Finished	Sep 09 07:51:31 PM UTC 24
Peak memory	218996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070904647 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.3070904647 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/49.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.4094526006
Short name	T762
Test name
Test status
Simulation time	179809517 ps
CPU time	3.65 seconds
Started	Sep 09 07:50:43 PM UTC 24
Finished	Sep 09 07:50:48 PM UTC 24
Peak memory	231508 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4094526006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_ mem_rw_with_rand_reset.4094526006 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_rw.1715165082
Short name	T755
Test name
Test status
Simulation time	35717026 ps
CPU time	1.79 seconds
Started	Sep 09 07:50:42 PM UTC 24
Finished	Sep 09 07:50:44 PM UTC 24
Peak memory	218952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715165082 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.1715165082 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/5.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.2732831927
Short name	T154
Test name
Test status
Simulation time	50374214 ps
CPU time	1.2 seconds
Started	Sep 09 07:50:41 PM UTC 24
Finished	Sep 09 07:50:44 PM UTC 24
Peak memory	218992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732831927 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.2732831927 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/5.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3290391825
Short name	T757
Test name
Test status
Simulation time	142790529 ps
CPU time	2.89 seconds
Started	Sep 09 07:50:42 PM UTC 24
Finished	Sep 09 07:50:46 PM UTC 24
Peak memory	229432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290391825 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_outstanding.3290391825 +enable _masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/5.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.2868804697
Short name	T751
Test name
Test status
Simulation time	31999731 ps
CPU time	1.51 seconds
Started	Sep 09 07:50:39 PM UTC 24
Finished	Sep 09 07:50:42 PM UTC 24
Peak memory	218684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868804697 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors.2868804697 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.3303941443
Short name	T754
Test name
Test status
Simulation time	87404036 ps
CPU time	2.38 seconds
Started	Sep 09 07:50:40 PM UTC 24
Finished	Sep 09 07:50:44 PM UTC 24
Peak memory	229576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303941443 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.3303941443 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/5.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.817206773
Short name	T156
Test name
Test status
Simulation time	100408263 ps
CPU time	3.03 seconds
Started	Sep 09 07:50:40 PM UTC 24
Finished	Sep 09 07:50:44 PM UTC 24
Peak memory	219148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817206773 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.817206773 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/5.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.1412104252
Short name	T766
Test name
Test status
Simulation time	341091879 ps
CPU time	3.76 seconds
Started	Sep 09 07:50:46 PM UTC 24
Finished	Sep 09 07:50:52 PM UTC 24
Peak memory	231508 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1412104252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_ mem_rw_with_rand_reset.1412104252 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_rw.3380422855
Short name	T761
Test name
Test status
Simulation time	26032028 ps
CPU time	1.31 seconds
Started	Sep 09 07:50:45 PM UTC 24
Finished	Sep 09 07:50:47 PM UTC 24
Peak memory	218920 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380422855 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.3380422855 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/6.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_intr_test.1001088056
Short name	T760
Test name
Test status
Simulation time	33821085 ps
CPU time	1.1 seconds
Started	Sep 09 07:50:45 PM UTC 24
Finished	Sep 09 07:50:47 PM UTC 24
Peak memory	219012 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001088056 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.1001088056 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/6.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.791290824
Short name	T764
Test name
Test status
Simulation time	210868284 ps
CPU time	2.3 seconds
Started	Sep 09 07:50:45 PM UTC 24
Finished	Sep 09 07:50:49 PM UTC 24
Peak memory	229448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791290824 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_outstanding.791290824 +enable_m asking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/6.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.2198878442
Short name	T759
Test name
Test status
Simulation time	40346882 ps
CPU time	1.86 seconds
Started	Sep 09 07:50:43 PM UTC 24
Finished	Sep 09 07:50:46 PM UTC 24
Peak memory	228860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198878442 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors.2198878442 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.1460989581
Short name	T99
Test name
Test status
Simulation time	53396108 ps
CPU time	2.5 seconds
Started	Sep 09 07:50:44 PM UTC 24
Finished	Sep 09 07:50:47 PM UTC 24
Peak memory	229776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460989581 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors_with_csr_rw. 1460989581 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.788237426
Short name	T763
Test name
Test status
Simulation time	219075105 ps
CPU time	2.11 seconds
Started	Sep 09 07:50:45 PM UTC 24
Finished	Sep 09 07:50:48 PM UTC 24
Peak memory	229520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788237426 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.788237426 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/6.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.974675
Short name	T771
Test name
Test status
Simulation time	173200682 ps
CPU time	2.39 seconds
Started	Sep 09 07:50:52 PM UTC 24
Finished	Sep 09 07:50:55 PM UTC 24
Peak memory	229444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=974675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_ rw_with_rand_reset.974675 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.831292532
Short name	T765
Test name
Test status
Simulation time	97315460 ps
CPU time	1.6 seconds
Started	Sep 09 07:50:49 PM UTC 24
Finished	Sep 09 07:50:52 PM UTC 24
Peak memory	228912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831292532 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.831292532 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/7.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.3961635874
Short name	T151
Test name
Test status
Simulation time	106606044 ps
CPU time	1.09 seconds
Started	Sep 09 07:50:49 PM UTC 24
Finished	Sep 09 07:50:51 PM UTC 24
Peak memory	218992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961635874 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.3961635874 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/7.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.1320763014
Short name	T768
Test name
Test status
Simulation time	77950226 ps
CPU time	2.39 seconds
Started	Sep 09 07:50:49 PM UTC 24
Finished	Sep 09 07:50:52 PM UTC 24
Peak memory	229416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320763014 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_outstanding.1320763014 +enable _masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/7.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2212760273
Short name	T101
Test name
Test status
Simulation time	118789489 ps
CPU time	1.75 seconds
Started	Sep 09 07:50:46 PM UTC 24
Finished	Sep 09 07:50:50 PM UTC 24
Peak memory	235028 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212760273 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors.2212760273 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.847404728
Short name	T100
Test name
Test status
Simulation time	100987257 ps
CPU time	3.49 seconds
Started	Sep 09 07:50:46 PM UTC 24
Finished	Sep 09 07:50:51 PM UTC 24
Peak memory	229884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847404728 -asse rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors_with_csr_rw.8 47404728 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.3689453467
Short name	T767
Test name
Test status
Simulation time	38173622 ps
CPU time	3.73 seconds
Started	Sep 09 07:50:47 PM UTC 24
Finished	Sep 09 07:50:53 PM UTC 24
Peak memory	229832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689453467 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.3689453467 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/7.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.4004450755
Short name	T769
Test name
Test status
Simulation time	590399804 ps
CPU time	3.4 seconds
Started	Sep 09 07:50:48 PM UTC 24
Finished	Sep 09 07:50:53 PM UTC 24
Peak memory	219176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004450755 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.4004450755 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/7.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2499419579
Short name	T774
Test name
Test status
Simulation time	189306064 ps
CPU time	2.01 seconds
Started	Sep 09 07:50:53 PM UTC 24
Finished	Sep 09 07:50:56 PM UTC 24
Peak memory	228876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2499419579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_ mem_rw_with_rand_reset.2499419579 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.3626866902
Short name	T773
Test name
Test status
Simulation time	81322997 ps
CPU time	1.33 seconds
Started	Sep 09 07:50:53 PM UTC 24
Finished	Sep 09 07:50:56 PM UTC 24
Peak memory	218996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626866902 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.3626866902 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/8.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.3900906635
Short name	T772
Test name
Test status
Simulation time	14826568 ps
CPU time	1.24 seconds
Started	Sep 09 07:50:53 PM UTC 24
Finished	Sep 09 07:50:55 PM UTC 24
Peak memory	218992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900906635 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.3900906635 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/8.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.3389095080
Short name	T776
Test name
Test status
Simulation time	39876677 ps
CPU time	3.08 seconds
Started	Sep 09 07:50:53 PM UTC 24
Finished	Sep 09 07:50:57 PM UTC 24
Peak memory	229588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389095080 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_outstanding.3389095080 +enable _masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/8.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.3182676139
Short name	T770
Test name
Test status
Simulation time	26170622 ps
CPU time	1.36 seconds
Started	Sep 09 07:50:52 PM UTC 24
Finished	Sep 09 07:50:54 PM UTC 24
Peak memory	228668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182676139 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors.3182676139 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.640960292
Short name	T103
Test name
Test status
Simulation time	255150624 ps
CPU time	3.06 seconds
Started	Sep 09 07:50:52 PM UTC 24
Finished	Sep 09 07:50:56 PM UTC 24
Peak memory	229884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640960292 -asse rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors_with_csr_rw.6 40960292 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.2421653276
Short name	T775
Test name
Test status
Simulation time	103098053 ps
CPU time	3.07 seconds
Started	Sep 09 07:50:53 PM UTC 24
Finished	Sep 09 07:50:57 PM UTC 24
Peak memory	229516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421653276 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.2421653276 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/8.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.4283180779
Short name	T782
Test name
Test status
Simulation time	252194937 ps
CPU time	3.61 seconds
Started	Sep 09 07:50:57 PM UTC 24
Finished	Sep 09 07:51:01 PM UTC 24
Peak memory	231508 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4283180779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_ mem_rw_with_rand_reset.4283180779 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.2996888550
Short name	T778
Test name
Test status
Simulation time	61455324 ps
CPU time	1.84 seconds
Started	Sep 09 07:50:57 PM UTC 24
Finished	Sep 09 07:51:00 PM UTC 24
Peak memory	228936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996888550 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.2996888550 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/9.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3833937997
Short name	T781
Test name
Test status
Simulation time	359405163 ps
CPU time	3.32 seconds
Started	Sep 09 07:50:57 PM UTC 24
Finished	Sep 09 07:51:01 PM UTC 24
Peak memory	229396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833937997 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_outstanding.3833937997 +enable _masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/9.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1046034157
Short name	T102
Test name
Test status
Simulation time	45067871 ps
CPU time	1.32 seconds
Started	Sep 09 07:50:53 PM UTC 24
Finished	Sep 09 07:50:56 PM UTC 24
Peak memory	234940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046034157 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors.1046034157 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.985939175
Short name	T167
Test name
Test status
Simulation time	341788567 ps
CPU time	3.35 seconds
Started	Sep 09 07:50:53 PM UTC 24
Finished	Sep 09 07:50:58 PM UTC 24
Peak memory	236896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985939175 -asse rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors_with_csr_rw.9 85939175 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.2742848075
Short name	T780
Test name
Test status
Simulation time	1419832341 ps
CPU time	5.18 seconds
Started	Sep 09 07:50:54 PM UTC 24
Finished	Sep 09 07:51:01 PM UTC 24
Peak memory	229516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742848075 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.2742848075 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/9.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.3981840034
Short name	T777
Test name
Test status
Simulation time	122703078 ps
CPU time	3.96 seconds
Started	Sep 09 07:50:54 PM UTC 24
Finished	Sep 09 07:50:59 PM UTC 24
Peak memory	229568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981840034 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.3981840034 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/9.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/0.kmac_burst_write.3827284837
Short name	T42
Test name
Test status
Simulation time	9357712866 ps
CPU time	342.4 seconds
Started	Sep 09 07:51:29 PM UTC 24
Finished	Sep 09 07:57:16 PM UTC 24
Peak memory	238980 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827284837 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.3827284837 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/0.kmac_edn_timeout_error.2057860498
Short name	T14
Test name
Test status
Simulation time	2783838058 ps
CPU time	40.3 seconds
Started	Sep 09 07:51:42 PM UTC 24
Finished	Sep 09 07:52:24 PM UTC 24
Peak memory	235044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057860498 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.2057860498 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_mode_error.1542622556
Short name	T16
Test name
Test status
Simulation time	1245893800 ps
CPU time	46.99 seconds
Started	Sep 09 07:52:10 PM UTC 24
Finished	Sep 09 07:52:59 PM UTC 24
Peak memory	235204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542622556 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.1542622556 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_ready_error.3777424856
Short name	T15
Test name
Test status
Simulation time	1360863319 ps
CPU time	18.85 seconds
Started	Sep 09 07:52:16 PM UTC 24
Finished	Sep 09 07:52:36 PM UTC 24
Peak memory	230588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777424856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.3777424856 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_entropy_ready_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/0.kmac_long_msg_and_output.2209853882
Short name	T280
Test name
Test status
Simulation time	132150933247 ps
CPU time	1481.1 seconds
Started	Sep 09 07:51:28 PM UTC 24
Finished	Sep 09 08:16:27 PM UTC 24
Peak memory	2053936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209853882 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_and_output.2209853882 +enable_mas king=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/0.kmac_sec_cm.4107690941
Short name	T5
Test name
Test status
Simulation time	13385337865 ps
CPU time	58.85 seconds
Started	Sep 09 07:53:00 PM UTC 24
Finished	Sep 09 07:54:00 PM UTC 24
Peak memory	269092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107690941 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.4107690941 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/0.kmac_sideload.2388513437
Short name	T17
Test name
Test status
Simulation time	3359877848 ps
CPU time	142.11 seconds
Started	Sep 09 07:51:29 PM UTC 24
Finished	Sep 09 07:53:53 PM UTC 24
Peak memory	319220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388513437 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.2388513437 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/0.kmac_smoke.3328643387
Short name	T1
Test name
Test status
Simulation time	93973575 ps
CPU time	1.73 seconds
Started	Sep 09 07:51:28 PM UTC 24
Finished	Sep 09 07:51:31 PM UTC 24
Peak memory	229596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328643387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.3328643387 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac.3773181348
Short name	T2
Test name
Test status
Simulation time	231960754 ps
CPU time	3.01 seconds
Started	Sep 09 07:51:30 PM UTC 24
Finished	Sep 09 07:51:34 PM UTC 24
Peak memory	230528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773181348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac.3773181348 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_test_vectors_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac_xof.3717287268
Short name	T3
Test name
Test status
Simulation time	238717439 ps
CPU time	3.61 seconds
Started	Sep 09 07:51:30 PM UTC 24
Finished	Sep 09 07:51:35 PM UTC 24
Peak memory	230460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717287268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.3717287268 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_test_vectors_kmac_xof/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_224.1289012623
Short name	T304
Test name
Test status
Simulation time	17965760326 ps
CPU time	1619.26 seconds
Started	Sep 09 07:51:29 PM UTC 24
Finished	Sep 09 08:18:46 PM UTC 24
Peak memory	1158808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289012623 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.1289012623 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_224/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_256.3335279764
Short name	T406
Test name
Test status
Simulation time	608112353001 ps
CPU time	2263.39 seconds
Started	Sep 09 07:51:29 PM UTC 24
Finished	Sep 09 08:29:36 PM UTC 24
Peak memory	2946708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335279764 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.3335279764 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_256/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_384.1116851208
Short name	T349
Test name
Test status
Simulation time	67236875426 ps
CPU time	1837.57 seconds
Started	Sep 09 07:51:30 PM UTC 24
Finished	Sep 09 08:22:29 PM UTC 24
Peak memory	2375516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116851208 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.1116851208 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_384/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_512.1930324890
Short name	T221
Test name
Test status
Simulation time	124451456389 ps
CPU time	1137.14 seconds
Started	Sep 09 07:51:30 PM UTC 24
Finished	Sep 09 08:10:41 PM UTC 24
Peak memory	1711680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930324890 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.1930324890 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_512/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_128.3302000205
Short name	T545
Test name
Test status
Simulation time	75873717936 ps
CPU time	3108.84 seconds
Started	Sep 09 07:51:30 PM UTC 24
Finished	Sep 09 08:43:56 PM UTC 24
Peak memory	3802820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302000205 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.3302000 205 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_128/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/1.kmac_alert_test.2494978326
Short name	T49
Test name
Test status
Simulation time	35771914 ps
CPU time	1.35 seconds
Started	Sep 09 07:56:51 PM UTC 24
Finished	Sep 09 07:56:54 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494978326 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.2494978326 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/1.kmac_app.2916461409
Short name	T33
Test name
Test status
Simulation time	14922255133 ps
CPU time	103.21 seconds
Started	Sep 09 07:54:51 PM UTC 24
Finished	Sep 09 07:56:36 PM UTC 24
Peak memory	292656 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916461409 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.2916461409 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/1.kmac_app_with_partial_data.1603136801
Short name	T105
Test name
Test status
Simulation time	16705533490 ps
CPU time	370.47 seconds
Started	Sep 09 07:54:55 PM UTC 24
Finished	Sep 09 08:01:11 PM UTC 24
Peak memory	534392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603136801 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.1603136801 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_app_with_partial_data/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/1.kmac_burst_write.826526618
Short name	T128
Test name
Test status
Simulation time	42823345678 ps
CPU time	456.75 seconds
Started	Sep 09 07:53:56 PM UTC 24
Finished	Sep 09 08:01:39 PM UTC 24
Peak memory	251896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826526618 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.826526618 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/1.kmac_edn_timeout_error.2424247467
Short name	T124
Test name
Test status
Simulation time	311780341 ps
CPU time	33.53 seconds
Started	Sep 09 07:56:11 PM UTC 24
Finished	Sep 09 07:56:46 PM UTC 24
Peak memory	232380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424247467 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.2424247467 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_mode_error.76336295
Short name	T72
Test name
Test status
Simulation time	1125172245 ps
CPU time	22.49 seconds
Started	Sep 09 07:56:12 PM UTC 24
Finished	Sep 09 07:56:36 PM UTC 24
Peak memory	228236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76336295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.76336295 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_ready_error.1879018427
Short name	T23
Test name
Test status
Simulation time	3404506784 ps
CPU time	32.97 seconds
Started	Sep 09 07:56:41 PM UTC 24
Finished	Sep 09 07:57:16 PM UTC 24
Peak memory	230728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879018427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.1879018427 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_entropy_ready_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_refresh.1095747661
Short name	T22
Test name
Test status
Simulation time	8472045471 ps
CPU time	47.23 seconds
Started	Sep 09 07:55:17 PM UTC 24
Finished	Sep 09 07:56:05 PM UTC 24
Peak memory	266036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095747661 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.1095747661 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/1.kmac_error.2226404981
Short name	T26
Test name
Test status
Simulation time	2491400754 ps
CPU time	257.18 seconds
Started	Sep 09 07:56:07 PM UTC 24
Finished	Sep 09 08:00:28 PM UTC 24
Peak memory	309040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226404981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.2226404981 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/1.kmac_key_error.2022451909
Short name	T19
Test name
Test status
Simulation time	103303748 ps
CPU time	2.16 seconds
Started	Sep 09 07:56:08 PM UTC 24
Finished	Sep 09 07:56:11 PM UTC 24
Peak memory	230248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022451909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.2022451909 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/1.kmac_lc_escalation.1015746522
Short name	T6
Test name
Test status
Simulation time	52219666 ps
CPU time	2.25 seconds
Started	Sep 09 07:56:41 PM UTC 24
Finished	Sep 09 07:56:44 PM UTC 24
Peak memory	232424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015746522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.1015746522 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/1.kmac_long_msg_and_output.1625079494
Short name	T375
Test name
Test status
Simulation time	313746652753 ps
CPU time	1907.92 seconds
Started	Sep 09 07:53:34 PM UTC 24
Finished	Sep 09 08:25:44 PM UTC 24
Peak memory	2400048 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625079494 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_and_output.1625079494 +enable_mas king=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/1.kmac_mubi.333073265
Short name	T32
Test name
Test status
Simulation time	1472195440 ps
CPU time	100.84 seconds
Started	Sep 09 07:55:58 PM UTC 24
Finished	Sep 09 07:57:41 PM UTC 24
Peak memory	276440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333073265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.333073265 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/1.kmac_sideload.1617390418
Short name	T68
Test name
Test status
Simulation time	331020082 ps
CPU time	26.28 seconds
Started	Sep 09 07:53:55 PM UTC 24
Finished	Sep 09 07:54:22 PM UTC 24
Peak memory	237212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617390418 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.1617390418 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/1.kmac_smoke.3382029233
Short name	T39
Test name
Test status
Simulation time	1426628886 ps
CPU time	30.09 seconds
Started	Sep 09 07:53:23 PM UTC 24
Finished	Sep 09 07:53:55 PM UTC 24
Peak memory	234608 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382029233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.3382029233 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/1.kmac_stress_all.3940778666
Short name	T287
Test name
Test status
Simulation time	384405733100 ps
CPU time	1217.61 seconds
Started	Sep 09 07:56:41 PM UTC 24
Finished	Sep 09 08:17:12 PM UTC 24
Peak memory	1347640 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940778666 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.3940778666 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac.2642753893
Short name	T70
Test name
Test status
Simulation time	133295506 ps
CPU time	3.33 seconds
Started	Sep 09 07:54:46 PM UTC 24
Finished	Sep 09 07:54:50 PM UTC 24
Peak memory	230516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642753893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac.2642753893 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_test_vectors_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac_xof.1761747769
Short name	T71
Test name
Test status
Simulation time	430425511 ps
CPU time	3.02 seconds
Started	Sep 09 07:54:50 PM UTC 24
Finished	Sep 09 07:54:54 PM UTC 24
Peak memory	230516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761747769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.1761747769 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_test_vectors_kmac_xof/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_224.3745987912
Short name	T332
Test name
Test status
Simulation time	72157099494 ps
CPU time	1601.19 seconds
Started	Sep 09 07:54:00 PM UTC 24
Finished	Sep 09 08:21:00 PM UTC 24
Peak memory	1164952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745987912 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.3745987912 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_224/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_256.4167301109
Short name	T69
Test name
Test status
Simulation time	7168620831 ps
CPU time	36.86 seconds
Started	Sep 09 07:54:02 PM UTC 24
Finished	Sep 09 07:54:40 PM UTC 24
Peak memory	232616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167301109 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.4167301109 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_256/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_384.3760464963
Short name	T409
Test name
Test status
Simulation time	417599177324 ps
CPU time	2104.14 seconds
Started	Sep 09 07:54:23 PM UTC 24
Finished	Sep 09 08:29:52 PM UTC 24
Peak memory	2358940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760464963 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.3760464963 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_384/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_512.2219230020
Short name	T215
Test name
Test status
Simulation time	52538094394 ps
CPU time	898.12 seconds
Started	Sep 09 07:54:26 PM UTC 24
Finished	Sep 09 08:09:36 PM UTC 24
Peak memory	702108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219230020 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.2219230020 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_512/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_128.2544346609
Short name	T119
Test name
Test status
Simulation time	57208203542 ps
CPU time	349.2 seconds
Started	Sep 09 07:54:36 PM UTC 24
Finished	Sep 09 08:00:31 PM UTC 24
Peak memory	280420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544346609 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.2544346 609 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_128/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_256.772609969
Short name	T85
Test name
Test status
Simulation time	7015789756 ps
CPU time	196.99 seconds
Started	Sep 09 07:54:41 PM UTC 24
Finished	Sep 09 07:58:02 PM UTC 24
Peak memory	360292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772609969 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.77260996 9 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_256/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/10.kmac_alert_test.1780866587
Short name	T236
Test name
Test status
Simulation time	61034300 ps
CPU time	1.29 seconds
Started	Sep 09 08:12:17 PM UTC 24
Finished	Sep 09 08:12:20 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780866587 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.1780866587 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/10.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/10.kmac_app.1464482487
Short name	T239
Test name
Test status
Simulation time	1563767286 ps
CPU time	93.66 seconds
Started	Sep 09 08:11:21 PM UTC 24
Finished	Sep 09 08:12:57 PM UTC 24
Peak memory	276136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464482487 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.1464482487 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/10.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/10.kmac_burst_write.1120334273
Short name	T359
Test name
Test status
Simulation time	6918893208 ps
CPU time	724.62 seconds
Started	Sep 09 08:11:20 PM UTC 24
Finished	Sep 09 08:23:34 PM UTC 24
Peak memory	249824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120334273 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.1120334273 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/10.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/10.kmac_edn_timeout_error.2617828464
Short name	T235
Test name
Test status
Simulation time	113512464 ps
CPU time	11.1 seconds
Started	Sep 09 08:12:04 PM UTC 24
Finished	Sep 09 08:12:16 PM UTC 24
Peak memory	228540 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617828464 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.2617828464 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/10.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/10.kmac_entropy_mode_error.2242464833
Short name	T238
Test name
Test status
Simulation time	849517513 ps
CPU time	44.53 seconds
Started	Sep 09 08:12:05 PM UTC 24
Finished	Sep 09 08:12:51 PM UTC 24
Peak memory	235248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242464833 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.2242464833 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/10.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/10.kmac_entropy_refresh.3966192978
Short name	T282
Test name
Test status
Simulation time	28375091583 ps
CPU time	292.24 seconds
Started	Sep 09 08:11:34 PM UTC 24
Finished	Sep 09 08:16:31 PM UTC 24
Peak memory	454444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966192978 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.3966192978 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/10.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/10.kmac_error.4094961285
Short name	T312
Test name
Test status
Simulation time	20657751949 ps
CPU time	444.71 seconds
Started	Sep 09 08:11:49 PM UTC 24
Finished	Sep 09 08:19:20 PM UTC 24
Peak memory	641012 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094961285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.4094961285 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/10.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/10.kmac_key_error.1983490979
Short name	T233
Test name
Test status
Simulation time	1720701801 ps
CPU time	8.77 seconds
Started	Sep 09 08:11:53 PM UTC 24
Finished	Sep 09 08:12:03 PM UTC 24
Peak memory	230728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983490979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.1983490979 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/10.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/10.kmac_lc_escalation.3971479120
Short name	T234
Test name
Test status
Simulation time	56615309 ps
CPU time	2.07 seconds
Started	Sep 09 08:12:09 PM UTC 24
Finished	Sep 09 08:12:12 PM UTC 24
Peak memory	230692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971479120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.3971479120 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/10.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/10.kmac_long_msg_and_output.20806978
Short name	T695
Test name
Test status
Simulation time	90300508111 ps
CPU time	3058.63 seconds
Started	Sep 09 08:11:10 PM UTC 24
Finished	Sep 09 09:02:44 PM UTC 24
Peak memory	3596120 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20806978 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_and_output.20806978 +enable_maskin g=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/10.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/10.kmac_sideload.3047833859
Short name	T300
Test name
Test status
Simulation time	18770471016 ps
CPU time	423.77 seconds
Started	Sep 09 08:11:17 PM UTC 24
Finished	Sep 09 08:18:26 PM UTC 24
Peak memory	667504 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047833859 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.3047833859 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/10.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/10.kmac_smoke.1685216687
Short name	T232
Test name
Test status
Simulation time	1691796121 ps
CPU time	43.7 seconds
Started	Sep 09 08:11:07 PM UTC 24
Finished	Sep 09 08:11:52 PM UTC 24
Peak memory	230512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685216687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.1685216687 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/10.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/10.kmac_stress_all.3448162292
Short name	T441
Test name
Test status
Simulation time	191654062670 ps
CPU time	1297.69 seconds
Started	Sep 09 08:12:13 PM UTC 24
Finished	Sep 09 08:34:08 PM UTC 24
Peak memory	1218464 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448162292 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.3448162292 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/10.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/11.kmac_alert_test.3558317767
Short name	T248
Test name
Test status
Simulation time	50526122 ps
CPU time	1.2 seconds
Started	Sep 09 08:13:42 PM UTC 24
Finished	Sep 09 08:13:44 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558317767 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.3558317767 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/11.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/11.kmac_app.932358680
Short name	T277
Test name
Test status
Simulation time	3314296941 ps
CPU time	194.29 seconds
Started	Sep 09 08:12:59 PM UTC 24
Finished	Sep 09 08:16:17 PM UTC 24
Peak memory	305208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932358680 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.932358680 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/11.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/11.kmac_burst_write.3932371313
Short name	T425
Test name
Test status
Simulation time	32220045171 ps
CPU time	1154.97 seconds
Started	Sep 09 08:12:58 PM UTC 24
Finished	Sep 09 08:32:27 PM UTC 24
Peak memory	270124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932371313 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.3932371313 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/11.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/11.kmac_edn_timeout_error.2573704871
Short name	T249
Test name
Test status
Simulation time	1304534703 ps
CPU time	11.81 seconds
Started	Sep 09 08:13:39 PM UTC 24
Finished	Sep 09 08:13:52 PM UTC 24
Peak memory	234552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573704871 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.2573704871 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/11.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/11.kmac_entropy_mode_error.586469587
Short name	T250
Test name
Test status
Simulation time	2275040966 ps
CPU time	13.06 seconds
Started	Sep 09 08:13:39 PM UTC 24
Finished	Sep 09 08:13:53 PM UTC 24
Peak memory	228344 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586469587 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.586469587 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/11.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/11.kmac_entropy_refresh.2530474528
Short name	T262
Test name
Test status
Simulation time	6468836998 ps
CPU time	132.18 seconds
Started	Sep 09 08:13:00 PM UTC 24
Finished	Sep 09 08:15:15 PM UTC 24
Peak memory	341800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530474528 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.2530474528 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/11.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/11.kmac_error.2896375326
Short name	T272
Test name
Test status
Simulation time	7684164110 ps
CPU time	137.99 seconds
Started	Sep 09 08:13:25 PM UTC 24
Finished	Sep 09 08:15:46 PM UTC 24
Peak memory	315180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896375326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.2896375326 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/11.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/11.kmac_key_error.1836559643
Short name	T247
Test name
Test status
Simulation time	1356450004 ps
CPU time	4.31 seconds
Started	Sep 09 08:13:37 PM UTC 24
Finished	Sep 09 08:13:43 PM UTC 24
Peak memory	230380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836559643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.1836559643 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/11.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/11.kmac_lc_escalation.314399762
Short name	T246
Test name
Test status
Simulation time	23538725 ps
CPU time	1.34 seconds
Started	Sep 09 08:13:39 PM UTC 24
Finished	Sep 09 08:13:41 PM UTC 24
Peak memory	231792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314399762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.314399762 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/11.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/11.kmac_long_msg_and_output.441553829
Short name	T245
Test name
Test status
Simulation time	2467412057 ps
CPU time	74.38 seconds
Started	Sep 09 08:12:22 PM UTC 24
Finished	Sep 09 08:13:38 PM UTC 24
Peak memory	261936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441553829 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_and_output.441553829 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/11.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/11.kmac_sideload.3849108108
Short name	T263
Test name
Test status
Simulation time	5791243170 ps
CPU time	141.72 seconds
Started	Sep 09 08:12:52 PM UTC 24
Finished	Sep 09 08:15:16 PM UTC 24
Peak memory	288548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849108108 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.3849108108 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/11.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/11.kmac_smoke.3453744062
Short name	T241
Test name
Test status
Simulation time	20524565422 ps
CPU time	61.51 seconds
Started	Sep 09 08:12:21 PM UTC 24
Finished	Sep 09 08:13:24 PM UTC 24
Peak memory	235232 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453744062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.3453744062 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/11.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/11.kmac_stress_all.2125224310
Short name	T466
Test name
Test status
Simulation time	188982387356 ps
CPU time	1380.43 seconds
Started	Sep 09 08:13:39 PM UTC 24
Finished	Sep 09 08:36:55 PM UTC 24
Peak memory	972764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125224310 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.2125224310 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/11.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/12.kmac_alert_test.2166631
Short name	T257
Test name
Test status
Simulation time	58475666 ps
CPU time	1.27 seconds
Started	Sep 09 08:14:28 PM UTC 24
Finished	Sep 09 08:14:30 PM UTC 24
Peak memory	216352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166631 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.2166631 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/12.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/12.kmac_app.4095790587
Short name	T323
Test name
Test status
Simulation time	61983091624 ps
CPU time	387.21 seconds
Started	Sep 09 08:13:56 PM UTC 24
Finished	Sep 09 08:20:29 PM UTC 24
Peak memory	548640 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095790587 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.4095790587 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/12.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/12.kmac_burst_write.2764851680
Short name	T325
Test name
Test status
Simulation time	37675458928 ps
CPU time	392.28 seconds
Started	Sep 09 08:13:54 PM UTC 24
Finished	Sep 09 08:20:32 PM UTC 24
Peak memory	251620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764851680 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.2764851680 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/12.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/12.kmac_edn_timeout_error.1153303937
Short name	T255
Test name
Test status
Simulation time	34413247 ps
CPU time	3.6 seconds
Started	Sep 09 08:14:20 PM UTC 24
Finished	Sep 09 08:14:24 PM UTC 24
Peak memory	228352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153303937 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.1153303937 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/12.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/12.kmac_entropy_mode_error.2237379443
Short name	T260
Test name
Test status
Simulation time	16799112636 ps
CPU time	35.86 seconds
Started	Sep 09 08:14:23 PM UTC 24
Finished	Sep 09 08:15:00 PM UTC 24
Peak memory	234424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237379443 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.2237379443 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/12.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/12.kmac_entropy_refresh.2702957974
Short name	T278
Test name
Test status
Simulation time	5235089694 ps
CPU time	133.92 seconds
Started	Sep 09 08:14:04 PM UTC 24
Finished	Sep 09 08:16:21 PM UTC 24
Peak memory	304892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702957974 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.2702957974 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/12.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/12.kmac_error.2959305738
Short name	T34
Test name
Test status
Simulation time	478796846 ps
CPU time	10.97 seconds
Started	Sep 09 08:14:16 PM UTC 24
Finished	Sep 09 08:14:28 PM UTC 24
Peak memory	251760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959305738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.2959305738 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/12.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/12.kmac_key_error.2464570124
Short name	T256
Test name
Test status
Simulation time	2401254563 ps
CPU time	7.84 seconds
Started	Sep 09 08:14:19 PM UTC 24
Finished	Sep 09 08:14:28 PM UTC 24
Peak memory	230440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464570124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.2464570124 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/12.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/12.kmac_lc_escalation.1835697420
Short name	T258
Test name
Test status
Simulation time	325579250 ps
CPU time	6.84 seconds
Started	Sep 09 08:14:25 PM UTC 24
Finished	Sep 09 08:14:33 PM UTC 24
Peak memory	234632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835697420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.1835697420 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/12.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/12.kmac_long_msg_and_output.2035467403
Short name	T715
Test name
Test status
Simulation time	130443362087 ps
CPU time	4468.08 seconds
Started	Sep 09 08:13:45 PM UTC 24
Finished	Sep 09 09:29:00 PM UTC 24
Peak memory	4851604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035467403 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_and_output.2035467403 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/12.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/12.kmac_sideload.3236421462
Short name	T330
Test name
Test status
Simulation time	19542958122 ps
CPU time	415.62 seconds
Started	Sep 09 08:13:52 PM UTC 24
Finished	Sep 09 08:20:54 PM UTC 24
Peak memory	589600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236421462 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.3236421462 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/12.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/12.kmac_smoke.2209379139
Short name	T254
Test name
Test status
Simulation time	1525128713 ps
CPU time	38.91 seconds
Started	Sep 09 08:13:44 PM UTC 24
Finished	Sep 09 08:14:24 PM UTC 24
Peak memory	230712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209379139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.2209379139 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/12.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/12.kmac_stress_all.796002096
Short name	T547
Test name
Test status
Simulation time	196817794757 ps
CPU time	1752.96 seconds
Started	Sep 09 08:14:25 PM UTC 24
Finished	Sep 09 08:43:59 PM UTC 24
Peak memory	1636660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796002096 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.796002096 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/12.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/13.kmac_alert_test.868734246
Short name	T269
Test name
Test status
Simulation time	14207269 ps
CPU time	1.22 seconds
Started	Sep 09 08:15:25 PM UTC 24
Finished	Sep 09 08:15:27 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868734246 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.868734246 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/13.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/13.kmac_app.1083200258
Short name	T297
Test name
Test status
Simulation time	9937041462 ps
CPU time	183.97 seconds
Started	Sep 09 08:15:01 PM UTC 24
Finished	Sep 09 08:18:08 PM UTC 24
Peak memory	425788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083200258 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.1083200258 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/13.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/13.kmac_burst_write.4126662005
Short name	T401
Test name
Test status
Simulation time	21355556768 ps
CPU time	856.82 seconds
Started	Sep 09 08:14:34 PM UTC 24
Finished	Sep 09 08:29:02 PM UTC 24
Peak memory	264048 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126662005 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.4126662005 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/13.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/13.kmac_edn_timeout_error.1681239667
Short name	T274
Test name
Test status
Simulation time	2069752682 ps
CPU time	39.66 seconds
Started	Sep 09 08:15:19 PM UTC 24
Finished	Sep 09 08:16:00 PM UTC 24
Peak memory	235144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681239667 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.1681239667 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/13.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/13.kmac_entropy_mode_error.2308885556
Short name	T271
Test name
Test status
Simulation time	740913922 ps
CPU time	21.14 seconds
Started	Sep 09 08:15:20 PM UTC 24
Finished	Sep 09 08:15:42 PM UTC 24
Peak memory	230272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308885556 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.2308885556 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/13.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/13.kmac_entropy_refresh.2946907549
Short name	T311
Test name
Test status
Simulation time	19539686757 ps
CPU time	244.54 seconds
Started	Sep 09 08:15:04 PM UTC 24
Finished	Sep 09 08:19:12 PM UTC 24
Peak memory	391024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946907549 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.2946907549 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/13.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/13.kmac_error.2754228468
Short name	T285
Test name
Test status
Simulation time	5154828675 ps
CPU time	83.14 seconds
Started	Sep 09 08:15:16 PM UTC 24
Finished	Sep 09 08:16:41 PM UTC 24
Peak memory	300848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754228468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.2754228468 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/13.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/13.kmac_key_error.1944266442
Short name	T266
Test name
Test status
Simulation time	639606532 ps
CPU time	2.77 seconds
Started	Sep 09 08:15:17 PM UTC 24
Finished	Sep 09 08:15:20 PM UTC 24
Peak memory	230636 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944266442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.1944266442 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/13.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/13.kmac_lc_escalation.3689403900
Short name	T268
Test name
Test status
Simulation time	156500659 ps
CPU time	1.82 seconds
Started	Sep 09 08:15:21 PM UTC 24
Finished	Sep 09 08:15:24 PM UTC 24
Peak memory	229784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689403900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.3689403900 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/13.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/13.kmac_long_msg_and_output.4106219577
Short name	T556
Test name
Test status
Simulation time	73637692185 ps
CPU time	1811.81 seconds
Started	Sep 09 08:14:31 PM UTC 24
Finished	Sep 09 08:45:03 PM UTC 24
Peak memory	1378264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106219577 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_and_output.4106219577 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/13.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/13.kmac_sideload.3660141094
Short name	T326
Test name
Test status
Simulation time	19874580405 ps
CPU time	357.4 seconds
Started	Sep 09 08:14:34 PM UTC 24
Finished	Sep 09 08:20:37 PM UTC 24
Peak memory	376628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660141094 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.3660141094 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/13.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/13.kmac_smoke.368754373
Short name	T264
Test name
Test status
Simulation time	1431410669 ps
CPU time	46.95 seconds
Started	Sep 09 08:14:29 PM UTC 24
Finished	Sep 09 08:15:18 PM UTC 24
Peak memory	230576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368754373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.368754373 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/13.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/13.kmac_stress_all.4008479657
Short name	T296
Test name
Test status
Simulation time	2920570792 ps
CPU time	150.67 seconds
Started	Sep 09 08:15:23 PM UTC 24
Finished	Sep 09 08:17:56 PM UTC 24
Peak memory	297080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008479657 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.4008479657 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/13.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/14.kmac_alert_test.4206294617
Short name	T281
Test name
Test status
Simulation time	196092252 ps
CPU time	1.16 seconds
Started	Sep 09 08:16:27 PM UTC 24
Finished	Sep 09 08:16:30 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206294617 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.4206294617 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/14.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/14.kmac_app.541558493
Short name	T341
Test name
Test status
Simulation time	49842724107 ps
CPU time	351.94 seconds
Started	Sep 09 08:15:50 PM UTC 24
Finished	Sep 09 08:21:47 PM UTC 24
Peak memory	452664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541558493 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.541558493 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/14.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/14.kmac_burst_write.2072924650
Short name	T366
Test name
Test status
Simulation time	11849396017 ps
CPU time	502 seconds
Started	Sep 09 08:15:46 PM UTC 24
Finished	Sep 09 08:24:15 PM UTC 24
Peak memory	251836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072924650 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.2072924650 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/14.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/14.kmac_edn_timeout_error.3457943578
Short name	T283
Test name
Test status
Simulation time	1752270374 ps
CPU time	13.74 seconds
Started	Sep 09 08:16:16 PM UTC 24
Finished	Sep 09 08:16:31 PM UTC 24
Peak memory	234488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457943578 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.3457943578 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/14.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/14.kmac_entropy_mode_error.2303242861
Short name	T284
Test name
Test status
Simulation time	1685758768 ps
CPU time	14.48 seconds
Started	Sep 09 08:16:18 PM UTC 24
Finished	Sep 09 08:16:34 PM UTC 24
Peak memory	228216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303242861 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.2303242861 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/14.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/14.kmac_entropy_refresh.3374508733
Short name	T290
Test name
Test status
Simulation time	2012512976 ps
CPU time	89.59 seconds
Started	Sep 09 08:16:01 PM UTC 24
Finished	Sep 09 08:17:32 PM UTC 24
Peak memory	276220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374508733 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.3374508733 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/14.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/14.kmac_error.3482792151
Short name	T309
Test name
Test status
Simulation time	25382676897 ps
CPU time	172.59 seconds
Started	Sep 09 08:16:08 PM UTC 24
Finished	Sep 09 08:19:03 PM UTC 24
Peak memory	403364 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482792151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.3482792151 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/14.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/14.kmac_key_error.1829086386
Short name	T276
Test name
Test status
Simulation time	520280682 ps
CPU time	2.58 seconds
Started	Sep 09 08:16:11 PM UTC 24
Finished	Sep 09 08:16:15 PM UTC 24
Peak memory	230532 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829086386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.1829086386 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/14.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/14.kmac_lc_escalation.4207502522
Short name	T279
Test name
Test status
Simulation time	39270897 ps
CPU time	1.96 seconds
Started	Sep 09 08:16:22 PM UTC 24
Finished	Sep 09 08:16:25 PM UTC 24
Peak memory	229752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207502522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.4207502522 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/14.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/14.kmac_long_msg_and_output.2085601666
Short name	T422
Test name
Test status
Simulation time	39140135982 ps
CPU time	976.84 seconds
Started	Sep 09 08:15:34 PM UTC 24
Finished	Sep 09 08:32:03 PM UTC 24
Peak memory	847908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085601666 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_and_output.2085601666 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/14.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/14.kmac_sideload.630184822
Short name	T307
Test name
Test status
Simulation time	6476563188 ps
CPU time	183.91 seconds
Started	Sep 09 08:15:43 PM UTC 24
Finished	Sep 09 08:18:50 PM UTC 24
Peak memory	364332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630184822 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.630184822 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/14.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/14.kmac_smoke.2988502902
Short name	T270
Test name
Test status
Simulation time	924866337 ps
CPU time	4.27 seconds
Started	Sep 09 08:15:28 PM UTC 24
Finished	Sep 09 08:15:34 PM UTC 24
Peak memory	230868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988502902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.2988502902 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/14.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/14.kmac_stress_all.1940433393
Short name	T664
Test name
Test status
Simulation time	73691051135 ps
CPU time	2253.12 seconds
Started	Sep 09 08:16:26 PM UTC 24
Finished	Sep 09 08:54:25 PM UTC 24
Peak memory	1357680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940433393 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.1940433393 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/14.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/15.kmac_alert_test.3049168718
Short name	T294
Test name
Test status
Simulation time	53022892 ps
CPU time	1.06 seconds
Started	Sep 09 08:17:36 PM UTC 24
Finished	Sep 09 08:17:38 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049168718 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.3049168718 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/15.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/15.kmac_app.1609135789
Short name	T321
Test name
Test status
Simulation time	6332712305 ps
CPU time	219.4 seconds
Started	Sep 09 08:16:41 PM UTC 24
Finished	Sep 09 08:20:24 PM UTC 24
Peak memory	362296 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609135789 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.1609135789 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/15.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/15.kmac_burst_write.3670402649
Short name	T442
Test name
Test status
Simulation time	27085898622 ps
CPU time	1046 seconds
Started	Sep 09 08:16:35 PM UTC 24
Finished	Sep 09 08:34:13 PM UTC 24
Peak memory	272088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670402649 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.3670402649 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/15.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/15.kmac_edn_timeout_error.2589467994
Short name	T291
Test name
Test status
Simulation time	98097906 ps
CPU time	5.02 seconds
Started	Sep 09 08:17:27 PM UTC 24
Finished	Sep 09 08:17:34 PM UTC 24
Peak memory	232440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589467994 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.2589467994 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/15.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/15.kmac_entropy_mode_error.714294076
Short name	T295
Test name
Test status
Simulation time	5991211222 ps
CPU time	16.63 seconds
Started	Sep 09 08:17:29 PM UTC 24
Finished	Sep 09 08:17:46 PM UTC 24
Peak memory	235044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714294076 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.714294076 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/15.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/15.kmac_entropy_refresh.553180426
Short name	T346
Test name
Test status
Simulation time	16632844632 ps
CPU time	324.7 seconds
Started	Sep 09 08:16:42 PM UTC 24
Finished	Sep 09 08:22:11 PM UTC 24
Peak memory	503600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553180426 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.553180426 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/15.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/15.kmac_error.4072135307
Short name	T298
Test name
Test status
Simulation time	34388325832 ps
CPU time	84.26 seconds
Started	Sep 09 08:16:55 PM UTC 24
Finished	Sep 09 08:18:21 PM UTC 24
Peak memory	298724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072135307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.4072135307 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/15.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/15.kmac_key_error.2200444284
Short name	T288
Test name
Test status
Simulation time	8383850323 ps
CPU time	12.6 seconds
Started	Sep 09 08:17:13 PM UTC 24
Finished	Sep 09 08:17:27 PM UTC 24
Peak memory	230652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200444284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.2200444284 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/15.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/15.kmac_lc_escalation.3623926554
Short name	T293
Test name
Test status
Simulation time	104811995 ps
CPU time	1.82 seconds
Started	Sep 09 08:17:33 PM UTC 24
Finished	Sep 09 08:17:35 PM UTC 24
Peak memory	229740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623926554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.3623926554 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/15.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/15.kmac_long_msg_and_output.2883831131
Short name	T589
Test name
Test status
Simulation time	136536438397 ps
CPU time	1849.23 seconds
Started	Sep 09 08:16:31 PM UTC 24
Finished	Sep 09 08:47:41 PM UTC 24
Peak memory	1496864 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883831131 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_and_output.2883831131 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/15.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/15.kmac_sideload.4041946223
Short name	T314
Test name
Test status
Simulation time	97168725651 ps
CPU time	200.3 seconds
Started	Sep 09 08:16:32 PM UTC 24
Finished	Sep 09 08:19:55 PM UTC 24
Peak memory	421800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041946223 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.4041946223 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/15.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/15.kmac_smoke.1818013746
Short name	T286
Test name
Test status
Simulation time	1311317710 ps
CPU time	22.3 seconds
Started	Sep 09 08:16:30 PM UTC 24
Finished	Sep 09 08:16:54 PM UTC 24
Peak memory	230504 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818013746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.1818013746 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/15.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/15.kmac_stress_all.3920562181
Short name	T521
Test name
Test status
Simulation time	59132815760 ps
CPU time	1478.39 seconds
Started	Sep 09 08:17:35 PM UTC 24
Finished	Sep 09 08:42:30 PM UTC 24
Peak memory	1132608 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920562181 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.3920562181 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/15.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/16.kmac_alert_test.3707614804
Short name	T306
Test name
Test status
Simulation time	48900831 ps
CPU time	1.19 seconds
Started	Sep 09 08:18:48 PM UTC 24
Finished	Sep 09 08:18:50 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707614804 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.3707614804 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/16.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/16.kmac_app.996565943
Short name	T145
Test name
Test status
Simulation time	3376658641 ps
CPU time	61.81 seconds
Started	Sep 09 08:18:09 PM UTC 24
Finished	Sep 09 08:19:13 PM UTC 24
Peak memory	247612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996565943 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.996565943 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/16.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/16.kmac_burst_write.3672021199
Short name	T387
Test name
Test status
Simulation time	26717945480 ps
CPU time	559.57 seconds
Started	Sep 09 08:17:57 PM UTC 24
Finished	Sep 09 08:27:24 PM UTC 24
Peak memory	255980 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672021199 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.3672021199 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/16.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/16.kmac_edn_timeout_error.3432687105
Short name	T302
Test name
Test status
Simulation time	37859243 ps
CPU time	3.54 seconds
Started	Sep 09 08:18:32 PM UTC 24
Finished	Sep 09 08:18:36 PM UTC 24
Peak memory	228292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432687105 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.3432687105 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/16.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/16.kmac_entropy_mode_error.877539484
Short name	T308
Test name
Test status
Simulation time	419330867 ps
CPU time	15.03 seconds
Started	Sep 09 08:18:38 PM UTC 24
Finished	Sep 09 08:18:54 PM UTC 24
Peak memory	228288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877539484 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.877539484 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/16.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/16.kmac_entropy_refresh.1911120351
Short name	T367
Test name
Test status
Simulation time	84844986182 ps
CPU time	364.2 seconds
Started	Sep 09 08:18:22 PM UTC 24
Finished	Sep 09 08:24:32 PM UTC 24
Peak memory	442156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911120351 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.1911120351 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/16.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/16.kmac_error.3902926006
Short name	T320
Test name
Test status
Simulation time	4000400912 ps
CPU time	114.84 seconds
Started	Sep 09 08:18:24 PM UTC 24
Finished	Sep 09 08:20:22 PM UTC 24
Peak memory	333552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902926006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.3902926006 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/16.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/16.kmac_key_error.2579482104
Short name	T305
Test name
Test status
Simulation time	10525997824 ps
CPU time	18.8 seconds
Started	Sep 09 08:18:28 PM UTC 24
Finished	Sep 09 08:18:48 PM UTC 24
Peak memory	230656 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579482104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.2579482104 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/16.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/16.kmac_lc_escalation.3021364103
Short name	T310
Test name
Test status
Simulation time	1093042390 ps
CPU time	19.36 seconds
Started	Sep 09 08:18:46 PM UTC 24
Finished	Sep 09 08:19:07 PM UTC 24
Peak memory	245192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021364103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.3021364103 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/16.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/16.kmac_long_msg_and_output.72307508
Short name	T378
Test name
Test status
Simulation time	49483386792 ps
CPU time	486.69 seconds
Started	Sep 09 08:17:39 PM UTC 24
Finished	Sep 09 08:25:52 PM UTC 24
Peak memory	782056 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72307508 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_and_output.72307508 +enable_maskin g=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/16.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/16.kmac_sideload.2974155305
Short name	T301
Test name
Test status
Simulation time	2449011205 ps
CPU time	42.18 seconds
Started	Sep 09 08:17:47 PM UTC 24
Finished	Sep 09 08:18:31 PM UTC 24
Peak memory	255788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974155305 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.2974155305 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/16.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/16.kmac_smoke.3207378056
Short name	T303
Test name
Test status
Simulation time	10155034896 ps
CPU time	66.98 seconds
Started	Sep 09 08:17:36 PM UTC 24
Finished	Sep 09 08:18:45 PM UTC 24
Peak memory	230580 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207378056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.3207378056 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/16.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/16.kmac_stress_all.2243454279
Short name	T494
Test name
Test status
Simulation time	72076891130 ps
CPU time	1202.2 seconds
Started	Sep 09 08:18:47 PM UTC 24
Finished	Sep 09 08:39:03 PM UTC 24
Peak memory	694492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243454279 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.2243454279 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/16.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/17.kmac_alert_test.2149034863
Short name	T317
Test name
Test status
Simulation time	14135416 ps
CPU time	1.15 seconds
Started	Sep 09 08:20:07 PM UTC 24
Finished	Sep 09 08:20:09 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149034863 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.2149034863 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/17.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/17.kmac_app.34379243
Short name	T322
Test name
Test status
Simulation time	25951362787 ps
CPU time	98.34 seconds
Started	Sep 09 08:19:07 PM UTC 24
Finished	Sep 09 08:20:48 PM UTC 24
Peak memory	317168 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34379243 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.34379243 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/17.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/17.kmac_burst_write.1380763379
Short name	T343
Test name
Test status
Simulation time	6366480429 ps
CPU time	160.67 seconds
Started	Sep 09 08:19:04 PM UTC 24
Finished	Sep 09 08:21:48 PM UTC 24
Peak memory	235368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380763379 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.1380763379 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/17.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/17.kmac_edn_timeout_error.3549700469
Short name	T318
Test name
Test status
Simulation time	2940741706 ps
CPU time	36.28 seconds
Started	Sep 09 08:19:40 PM UTC 24
Finished	Sep 09 08:20:18 PM UTC 24
Peak memory	234484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549700469 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.3549700469 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/17.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/17.kmac_entropy_mode_error.232123452
Short name	T316
Test name
Test status
Simulation time	828264093 ps
CPU time	9.58 seconds
Started	Sep 09 08:19:56 PM UTC 24
Finished	Sep 09 08:20:07 PM UTC 24
Peak memory	235232 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232123452 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.232123452 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/17.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/17.kmac_entropy_refresh.4124420692
Short name	T355
Test name
Test status
Simulation time	79054334982 ps
CPU time	225.68 seconds
Started	Sep 09 08:19:12 PM UTC 24
Finished	Sep 09 08:23:02 PM UTC 24
Peak memory	423704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124420692 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.4124420692 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/17.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/17.kmac_error.3502452551
Short name	T324
Test name
Test status
Simulation time	1864513708 ps
CPU time	75.64 seconds
Started	Sep 09 08:19:14 PM UTC 24
Finished	Sep 09 08:20:31 PM UTC 24
Peak memory	268152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502452551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.3502452551 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/17.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/17.kmac_key_error.3692948488
Short name	T313
Test name
Test status
Simulation time	1723952422 ps
CPU time	17.09 seconds
Started	Sep 09 08:19:21 PM UTC 24
Finished	Sep 09 08:19:39 PM UTC 24
Peak memory	230412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692948488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.3692948488 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/17.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/17.kmac_long_msg_and_output.3162065498
Short name	T680
Test name
Test status
Simulation time	25705269135 ps
CPU time	2364.17 seconds
Started	Sep 09 08:18:51 PM UTC 24
Finished	Sep 09 08:58:40 PM UTC 24
Peak memory	1818656 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162065498 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_and_output.3162065498 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/17.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/17.kmac_sideload.2391949816
Short name	T337
Test name
Test status
Simulation time	16137613861 ps
CPU time	150.26 seconds
Started	Sep 09 08:18:55 PM UTC 24
Finished	Sep 09 08:21:28 PM UTC 24
Peak memory	341752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391949816 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.2391949816 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/17.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/17.kmac_smoke.2189575564
Short name	T315
Test name
Test status
Simulation time	3910922706 ps
CPU time	64.24 seconds
Started	Sep 09 08:18:51 PM UTC 24
Finished	Sep 09 08:19:57 PM UTC 24
Peak memory	230520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189575564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.2189575564 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/17.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/17.kmac_stress_all.327356456
Short name	T370
Test name
Test status
Simulation time	4259527881 ps
CPU time	308.22 seconds
Started	Sep 09 08:20:01 PM UTC 24
Finished	Sep 09 08:25:14 PM UTC 24
Peak memory	444444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327356456 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.327356456 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/17.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/18.kmac_alert_test.1482932465
Short name	T329
Test name
Test status
Simulation time	55311297 ps
CPU time	1.22 seconds
Started	Sep 09 08:20:49 PM UTC 24
Finished	Sep 09 08:20:51 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482932465 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.1482932465 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/18.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/18.kmac_app.2695174124
Short name	T334
Test name
Test status
Simulation time	1003312972 ps
CPU time	28.91 seconds
Started	Sep 09 08:20:32 PM UTC 24
Finished	Sep 09 08:21:02 PM UTC 24
Peak memory	235092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695174124 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.2695174124 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/18.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/18.kmac_burst_write.4158208329
Short name	T438
Test name
Test status
Simulation time	7900877327 ps
CPU time	774.34 seconds
Started	Sep 09 08:20:31 PM UTC 24
Finished	Sep 09 08:33:35 PM UTC 24
Peak memory	249700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158208329 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.4158208329 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/18.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/18.kmac_edn_timeout_error.2986289287
Short name	T335
Test name
Test status
Simulation time	6202992812 ps
CPU time	31.81 seconds
Started	Sep 09 08:20:33 PM UTC 24
Finished	Sep 09 08:21:06 PM UTC 24
Peak memory	235172 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986289287 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.2986289287 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/18.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/18.kmac_entropy_mode_error.126539257
Short name	T336
Test name
Test status
Simulation time	463924248 ps
CPU time	36.35 seconds
Started	Sep 09 08:20:37 PM UTC 24
Finished	Sep 09 08:21:15 PM UTC 24
Peak memory	235008 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126539257 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.126539257 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/18.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/18.kmac_entropy_refresh.1871369060
Short name	T357
Test name
Test status
Simulation time	9702989631 ps
CPU time	169.01 seconds
Started	Sep 09 08:20:32 PM UTC 24
Finished	Sep 09 08:23:24 PM UTC 24
Peak memory	290592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871369060 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.1871369060 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/18.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/18.kmac_error.540085922
Short name	T374
Test name
Test status
Simulation time	3400179748 ps
CPU time	305.05 seconds
Started	Sep 09 08:20:32 PM UTC 24
Finished	Sep 09 08:25:42 PM UTC 24
Peak memory	339944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540085922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.540085922 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/18.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/18.kmac_key_error.2723584319
Short name	T327
Test name
Test status
Simulation time	788829600 ps
CPU time	8.74 seconds
Started	Sep 09 08:20:32 PM UTC 24
Finished	Sep 09 08:20:42 PM UTC 24
Peak memory	230348 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723584319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.2723584319 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/18.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/18.kmac_lc_escalation.3338443349
Short name	T328
Test name
Test status
Simulation time	455401863 ps
CPU time	2.35 seconds
Started	Sep 09 08:20:43 PM UTC 24
Finished	Sep 09 08:20:46 PM UTC 24
Peak memory	230388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338443349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.3338443349 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/18.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/18.kmac_long_msg_and_output.1081401445
Short name	T652
Test name
Test status
Simulation time	45796327041 ps
CPU time	1953.18 seconds
Started	Sep 09 08:20:18 PM UTC 24
Finished	Sep 09 08:53:15 PM UTC 24
Peak memory	1312804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081401445 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_and_output.1081401445 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/18.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/18.kmac_sideload.1277722724
Short name	T354
Test name
Test status
Simulation time	17057112418 ps
CPU time	144.49 seconds
Started	Sep 09 08:20:31 PM UTC 24
Finished	Sep 09 08:22:58 PM UTC 24
Peak memory	301100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277722724 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.1277722724 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/18.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/18.kmac_smoke.2130910192
Short name	T331
Test name
Test status
Simulation time	892022098 ps
CPU time	46.12 seconds
Started	Sep 09 08:20:10 PM UTC 24
Finished	Sep 09 08:20:58 PM UTC 24
Peak memory	230596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130910192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.2130910192 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/18.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/18.kmac_stress_all.713511558
Short name	T565
Test name
Test status
Simulation time	509525892495 ps
CPU time	1468.21 seconds
Started	Sep 09 08:20:47 PM UTC 24
Finished	Sep 09 08:45:32 PM UTC 24
Peak memory	1087540 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713511558 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.713511558 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/18.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/19.kmac_alert_test.4249707585
Short name	T342
Test name
Test status
Simulation time	36574222 ps
CPU time	1.19 seconds
Started	Sep 09 08:21:45 PM UTC 24
Finished	Sep 09 08:21:47 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249707585 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.4249707585 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/19.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/19.kmac_app.4183417803
Short name	T356
Test name
Test status
Simulation time	2669826380 ps
CPU time	131.48 seconds
Started	Sep 09 08:21:01 PM UTC 24
Finished	Sep 09 08:23:16 PM UTC 24
Peak memory	286576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183417803 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.4183417803 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/19.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/19.kmac_burst_write.3491826443
Short name	T471
Test name
Test status
Simulation time	104496098271 ps
CPU time	958 seconds
Started	Sep 09 08:21:00 PM UTC 24
Finished	Sep 09 08:37:10 PM UTC 24
Peak memory	270108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491826443 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.3491826443 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/19.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/19.kmac_edn_timeout_error.1652853282
Short name	T344
Test name
Test status
Simulation time	1321433978 ps
CPU time	35.6 seconds
Started	Sep 09 08:21:29 PM UTC 24
Finished	Sep 09 08:22:06 PM UTC 24
Peak memory	235176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652853282 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.1652853282 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/19.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/19.kmac_entropy_mode_error.3311402242
Short name	T345
Test name
Test status
Simulation time	596619470 ps
CPU time	33.04 seconds
Started	Sep 09 08:21:34 PM UTC 24
Finished	Sep 09 08:22:08 PM UTC 24
Peak memory	234976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311402242 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.3311402242 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/19.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/19.kmac_entropy_refresh.2016541838
Short name	T407
Test name
Test status
Simulation time	136359609831 ps
CPU time	513.43 seconds
Started	Sep 09 08:21:03 PM UTC 24
Finished	Sep 09 08:29:44 PM UTC 24
Peak memory	517928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016541838 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.2016541838 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/19.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/19.kmac_error.103755485
Short name	T405
Test name
Test status
Simulation time	29758661068 ps
CPU time	488.2 seconds
Started	Sep 09 08:21:07 PM UTC 24
Finished	Sep 09 08:29:22 PM UTC 24
Peak memory	692192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103755485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.103755485 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/19.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/19.kmac_key_error.1354400097
Short name	T338
Test name
Test status
Simulation time	1614878113 ps
CPU time	14.81 seconds
Started	Sep 09 08:21:16 PM UTC 24
Finished	Sep 09 08:21:33 PM UTC 24
Peak memory	230412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354400097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.1354400097 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/19.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/19.kmac_lc_escalation.4191865096
Short name	T54
Test name
Test status
Simulation time	72547214 ps
CPU time	2.5 seconds
Started	Sep 09 08:21:35 PM UTC 24
Finished	Sep 09 08:21:38 PM UTC 24
Peak memory	234688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191865096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.4191865096 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/19.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/19.kmac_long_msg_and_output.2107359902
Short name	T419
Test name
Test status
Simulation time	32804978884 ps
CPU time	611.84 seconds
Started	Sep 09 08:20:55 PM UTC 24
Finished	Sep 09 08:31:15 PM UTC 24
Peak memory	925544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107359902 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_and_output.2107359902 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/19.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/19.kmac_sideload.2475183479
Short name	T339
Test name
Test status
Simulation time	438138028 ps
CPU time	32.55 seconds
Started	Sep 09 08:20:59 PM UTC 24
Finished	Sep 09 08:21:34 PM UTC 24
Peak memory	239324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475183479 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.2475183479 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/19.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/19.kmac_smoke.2032144368
Short name	T340
Test name
Test status
Simulation time	7292316823 ps
CPU time	50.36 seconds
Started	Sep 09 08:20:52 PM UTC 24
Finished	Sep 09 08:21:44 PM UTC 24
Peak memory	230528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032144368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.2032144368 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/19.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/19.kmac_stress_all.166702177
Short name	T495
Test name
Test status
Simulation time	63134545644 ps
CPU time	1038.25 seconds
Started	Sep 09 08:21:39 PM UTC 24
Finished	Sep 09 08:39:10 PM UTC 24
Peak memory	411632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166702177 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.166702177 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/19.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/2.kmac_alert_test.594133179
Short name	T50
Test name
Test status
Simulation time	12108783 ps
CPU time	1.18 seconds
Started	Sep 09 07:59:49 PM UTC 24
Finished	Sep 09 07:59:52 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594133179 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.594133179 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/2.kmac_app.3151383416
Short name	T89
Test name
Test status
Simulation time	479869923 ps
CPU time	3.77 seconds
Started	Sep 09 07:58:25 PM UTC 24
Finished	Sep 09 07:58:30 PM UTC 24
Peak memory	230464 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151383416 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.3151383416 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/2.kmac_app_with_partial_data.2225827221
Short name	T177
Test name
Test status
Simulation time	9824910625 ps
CPU time	92.78 seconds
Started	Sep 09 07:58:32 PM UTC 24
Finished	Sep 09 08:00:07 PM UTC 24
Peak memory	253740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225827221 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.2225827221 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_app_with_partial_data/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/2.kmac_burst_write.611417079
Short name	T244
Test name
Test status
Simulation time	44065205308 ps
CPU time	948.7 seconds
Started	Sep 09 07:57:37 PM UTC 24
Finished	Sep 09 08:13:37 PM UTC 24
Peak memory	263928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611417079 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.611417079 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/2.kmac_edn_timeout_error.81138169
Short name	T106
Test name
Test status
Simulation time	2804718098 ps
CPU time	55.68 seconds
Started	Sep 09 07:58:57 PM UTC 24
Finished	Sep 09 07:59:54 PM UTC 24
Peak memory	235040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81138169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.81138169 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_mode_error.643630794
Short name	T175
Test name
Test status
Simulation time	763788328 ps
CPU time	16.64 seconds
Started	Sep 09 07:59:08 PM UTC 24
Finished	Sep 09 07:59:26 PM UTC 24
Peak memory	235108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643630794 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.643630794 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_refresh.1584791890
Short name	T194
Test name
Test status
Simulation time	15588676680 ps
CPU time	343.34 seconds
Started	Sep 09 07:58:33 PM UTC 24
Finished	Sep 09 08:04:22 PM UTC 24
Peak memory	483316 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584791890 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.1584791890 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/2.kmac_error.1518240560
Short name	T25
Test name
Test status
Simulation time	2938555734 ps
CPU time	78.23 seconds
Started	Sep 09 07:58:50 PM UTC 24
Finished	Sep 09 08:00:10 PM UTC 24
Peak memory	263976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518240560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.1518240560 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/2.kmac_key_error.3004789602
Short name	T20
Test name
Test status
Simulation time	1188698444 ps
CPU time	11.75 seconds
Started	Sep 09 07:58:51 PM UTC 24
Finished	Sep 09 07:59:04 PM UTC 24
Peak memory	230396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004789602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.3004789602 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/2.kmac_lc_escalation.2517057996
Short name	T38
Test name
Test status
Simulation time	112721930 ps
CPU time	2.03 seconds
Started	Sep 09 07:59:09 PM UTC 24
Finished	Sep 09 07:59:12 PM UTC 24
Peak memory	230512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517057996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.2517057996 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/2.kmac_long_msg_and_output.4193540910
Short name	T408
Test name
Test status
Simulation time	233022045665 ps
CPU time	1932.24 seconds
Started	Sep 09 07:57:17 PM UTC 24
Finished	Sep 09 08:29:51 PM UTC 24
Peak memory	2543292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193540910 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and_output.4193540910 +enable_mas king=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/2.kmac_mubi.1435194569
Short name	T76
Test name
Test status
Simulation time	3933126536 ps
CPU time	128.75 seconds
Started	Sep 09 07:58:33 PM UTC 24
Finished	Sep 09 08:00:45 PM UTC 24
Peak memory	317616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435194569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.1435194569 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/2.kmac_sec_cm.647750333
Short name	T11
Test name
Test status
Simulation time	5370339575 ps
CPU time	50.28 seconds
Started	Sep 09 07:59:34 PM UTC 24
Finished	Sep 09 08:00:26 PM UTC 24
Peak memory	275292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647750333 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.647750333 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/2.kmac_sideload.1954797417
Short name	T83
Test name
Test status
Simulation time	2713570669 ps
CPU time	23.01 seconds
Started	Sep 09 07:57:17 PM UTC 24
Finished	Sep 09 07:57:41 PM UTC 24
Peak memory	245456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954797417 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.1954797417 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/2.kmac_stress_all.3872033490
Short name	T45
Test name
Test status
Simulation time	10655668482 ps
CPU time	890.4 seconds
Started	Sep 09 07:59:13 PM UTC 24
Finished	Sep 09 08:14:14 PM UTC 24
Peak memory	612400 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872033490 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.3872033490 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac.3575745841
Short name	T86
Test name
Test status
Simulation time	226775602 ps
CPU time	4.69 seconds
Started	Sep 09 07:58:17 PM UTC 24
Finished	Sep 09 07:58:23 PM UTC 24
Peak memory	230468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575745841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac.3575745841 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_test_vectors_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac_xof.3640445601
Short name	T88
Test name
Test status
Simulation time	587547605 ps
CPU time	2.85 seconds
Started	Sep 09 07:58:24 PM UTC 24
Finished	Sep 09 07:58:28 PM UTC 24
Peak memory	230476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640445601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.3640445601 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_test_vectors_kmac_xof/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_224.796082999
Short name	T169
Test name
Test status
Simulation time	5306281666 ps
CPU time	66.85 seconds
Started	Sep 09 07:57:51 PM UTC 24
Finished	Sep 09 07:58:59 PM UTC 24
Peak memory	257672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796082999 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.796082999 + enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_224/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_256.3978275420
Short name	T412
Test name
Test status
Simulation time	58907222013 ps
CPU time	1936.01 seconds
Started	Sep 09 07:57:53 PM UTC 24
Finished	Sep 09 08:30:30 PM UTC 24
Peak memory	2993800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978275420 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.3978275420 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_256/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_384.1387027570
Short name	T87
Test name
Test status
Simulation time	419376918 ps
CPU time	29.79 seconds
Started	Sep 09 07:57:53 PM UTC 24
Finished	Sep 09 07:58:24 PM UTC 24
Peak memory	228408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387027570 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.1387027570 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_384/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_512.2542142727
Short name	T319
Test name
Test status
Simulation time	70903952899 ps
CPU time	1329.59 seconds
Started	Sep 09 07:57:53 PM UTC 24
Finished	Sep 09 08:20:18 PM UTC 24
Peak memory	1746588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542142727 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.2542142727 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_512/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_128.1682776797
Short name	T170
Test name
Test status
Simulation time	15010994808 ps
CPU time	177.32 seconds
Started	Sep 09 07:57:53 PM UTC 24
Finished	Sep 09 08:00:54 PM UTC 24
Peak memory	239264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682776797 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.1682776 797 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_128/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_256.2897983365
Short name	T176
Test name
Test status
Simulation time	6245238074 ps
CPU time	121.78 seconds
Started	Sep 09 07:58:03 PM UTC 24
Finished	Sep 09 08:00:07 PM UTC 24
Peak memory	263828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897983365 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.2897983 365 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_256/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/20.kmac_alert_test.1622110862
Short name	T353
Test name
Test status
Simulation time	16199725 ps
CPU time	1.2 seconds
Started	Sep 09 08:22:36 PM UTC 24
Finished	Sep 09 08:22:38 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622110862 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.1622110862 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/20.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/20.kmac_app.836753307
Short name	T373
Test name
Test status
Simulation time	22219536000 ps
CPU time	204.32 seconds
Started	Sep 09 08:22:09 PM UTC 24
Finished	Sep 09 08:25:37 PM UTC 24
Peak memory	436068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836753307 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.836753307 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/20.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/20.kmac_burst_write.4223227326
Short name	T433
Test name
Test status
Simulation time	31033605106 ps
CPU time	644.21 seconds
Started	Sep 09 08:22:07 PM UTC 24
Finished	Sep 09 08:33:00 PM UTC 24
Peak memory	257828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223227326 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.4223227326 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/20.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/20.kmac_entropy_refresh.687818640
Short name	T365
Test name
Test status
Simulation time	15917811458 ps
CPU time	115.75 seconds
Started	Sep 09 08:22:12 PM UTC 24
Finished	Sep 09 08:24:10 PM UTC 24
Peak memory	282588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687818640 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.687818640 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/20.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/20.kmac_error.1071235358
Short name	T376
Test name
Test status
Simulation time	62102523357 ps
CPU time	210 seconds
Started	Sep 09 08:22:14 PM UTC 24
Finished	Sep 09 08:25:48 PM UTC 24
Peak memory	464680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071235358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.1071235358 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/20.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/20.kmac_key_error.531890567
Short name	T352
Test name
Test status
Simulation time	3167755864 ps
CPU time	14.35 seconds
Started	Sep 09 08:22:20 PM UTC 24
Finished	Sep 09 08:22:35 PM UTC 24
Peak memory	230392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531890567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.531890567 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/20.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/20.kmac_lc_escalation.625076313
Short name	T350
Test name
Test status
Simulation time	134148259 ps
CPU time	1.95 seconds
Started	Sep 09 08:22:30 PM UTC 24
Finished	Sep 09 08:22:33 PM UTC 24
Peak memory	234488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625076313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.625076313 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/20.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/20.kmac_long_msg_and_output.3495609842
Short name	T636
Test name
Test status
Simulation time	119227908640 ps
CPU time	1798.37 seconds
Started	Sep 09 08:21:48 PM UTC 24
Finished	Sep 09 08:52:07 PM UTC 24
Peak memory	2312036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495609842 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_and_output.3495609842 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/20.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/20.kmac_sideload.3024082240
Short name	T347
Test name
Test status
Simulation time	263125924 ps
CPU time	23.64 seconds
Started	Sep 09 08:21:49 PM UTC 24
Finished	Sep 09 08:22:14 PM UTC 24
Peak memory	234608 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024082240 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.3024082240 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/20.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/20.kmac_smoke.3290016283
Short name	T348
Test name
Test status
Simulation time	958919871 ps
CPU time	29.78 seconds
Started	Sep 09 08:21:48 PM UTC 24
Finished	Sep 09 08:22:19 PM UTC 24
Peak memory	230520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290016283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.3290016283 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/20.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/20.kmac_stress_all.211286662
Short name	T410
Test name
Test status
Simulation time	38568474269 ps
CPU time	433.53 seconds
Started	Sep 09 08:22:34 PM UTC 24
Finished	Sep 09 08:29:53 PM UTC 24
Peak memory	436288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211286662 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.211286662 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/20.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/21.kmac_alert_test.924880464
Short name	T363
Test name
Test status
Simulation time	20681452 ps
CPU time	1.18 seconds
Started	Sep 09 08:23:56 PM UTC 24
Finished	Sep 09 08:23:58 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924880464 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.924880464 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/21.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/21.kmac_app.1110580567
Short name	T364
Test name
Test status
Simulation time	937558149 ps
CPU time	50.48 seconds
Started	Sep 09 08:23:16 PM UTC 24
Finished	Sep 09 08:24:08 PM UTC 24
Peak memory	251952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110580567 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.1110580567 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/21.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/21.kmac_burst_write.1325902039
Short name	T450
Test name
Test status
Simulation time	94286006071 ps
CPU time	708.27 seconds
Started	Sep 09 08:23:02 PM UTC 24
Finished	Sep 09 08:34:59 PM UTC 24
Peak memory	256044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325902039 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.1325902039 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/21.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/21.kmac_entropy_refresh.3969579977
Short name	T394
Test name
Test status
Simulation time	15514362152 ps
CPU time	283.12 seconds
Started	Sep 09 08:23:25 PM UTC 24
Finished	Sep 09 08:28:13 PM UTC 24
Peak memory	339680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969579977 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.3969579977 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/21.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/21.kmac_error.3308240661
Short name	T360
Test name
Test status
Simulation time	633997630 ps
CPU time	6.91 seconds
Started	Sep 09 08:23:26 PM UTC 24
Finished	Sep 09 08:23:34 PM UTC 24
Peak memory	232520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308240661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.3308240661 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/21.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/21.kmac_key_error.117884882
Short name	T361
Test name
Test status
Simulation time	1315908734 ps
CPU time	12.68 seconds
Started	Sep 09 08:23:36 PM UTC 24
Finished	Sep 09 08:23:49 PM UTC 24
Peak memory	230448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117884882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.117884882 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/21.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/21.kmac_lc_escalation.3672964986
Short name	T362
Test name
Test status
Simulation time	2252462335 ps
CPU time	18.11 seconds
Started	Sep 09 08:23:36 PM UTC 24
Finished	Sep 09 08:23:55 PM UTC 24
Peak memory	245464 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672964986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.3672964986 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/21.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/21.kmac_long_msg_and_output.1408322361
Short name	T397
Test name
Test status
Simulation time	48900494817 ps
CPU time	341.57 seconds
Started	Sep 09 08:22:39 PM UTC 24
Finished	Sep 09 08:28:25 PM UTC 24
Peak memory	608140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408322361 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_and_output.1408322361 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/21.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/21.kmac_sideload.3169139612
Short name	T368
Test name
Test status
Simulation time	3318495713 ps
CPU time	106.83 seconds
Started	Sep 09 08:22:59 PM UTC 24
Finished	Sep 09 08:24:48 PM UTC 24
Peak memory	313140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169139612 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.3169139612 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/21.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/21.kmac_smoke.1204103536
Short name	T358
Test name
Test status
Simulation time	21553720659 ps
CPU time	48.34 seconds
Started	Sep 09 08:22:36 PM UTC 24
Finished	Sep 09 08:23:26 PM UTC 24
Peak memory	230664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204103536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.1204103536 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/21.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/21.kmac_stress_all.787000591
Short name	T379
Test name
Test status
Simulation time	5182401377 ps
CPU time	124.45 seconds
Started	Sep 09 08:23:50 PM UTC 24
Finished	Sep 09 08:25:57 PM UTC 24
Peak memory	292588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787000591 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.787000591 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/21.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/22.kmac_alert_test.564794551
Short name	T377
Test name
Test status
Simulation time	92775241 ps
CPU time	1.17 seconds
Started	Sep 09 08:25:46 PM UTC 24
Finished	Sep 09 08:25:48 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564794551 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.564794551 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/22.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/22.kmac_app.3210451309
Short name	T386
Test name
Test status
Simulation time	6657234992 ps
CPU time	124.67 seconds
Started	Sep 09 08:24:32 PM UTC 24
Finished	Sep 09 08:26:40 PM UTC 24
Peak memory	274224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210451309 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.3210451309 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/22.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/22.kmac_burst_write.4041270393
Short name	T487
Test name
Test status
Simulation time	46694597596 ps
CPU time	854.63 seconds
Started	Sep 09 08:24:16 PM UTC 24
Finished	Sep 09 08:38:41 PM UTC 24
Peak memory	263976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041270393 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.4041270393 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/22.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/22.kmac_entropy_refresh.2004118015
Short name	T398
Test name
Test status
Simulation time	21213469471 ps
CPU time	232.99 seconds
Started	Sep 09 08:24:49 PM UTC 24
Finished	Sep 09 08:28:46 PM UTC 24
Peak memory	405360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004118015 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.2004118015 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/22.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/22.kmac_error.2256097232
Short name	T380
Test name
Test status
Simulation time	1507898213 ps
CPU time	46.43 seconds
Started	Sep 09 08:25:15 PM UTC 24
Finished	Sep 09 08:26:02 PM UTC 24
Peak memory	274420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256097232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.2256097232 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/22.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/22.kmac_key_error.1260932970
Short name	T371
Test name
Test status
Simulation time	1189905470 ps
CPU time	11.75 seconds
Started	Sep 09 08:25:15 PM UTC 24
Finished	Sep 09 08:25:28 PM UTC 24
Peak memory	230452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260932970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.1260932970 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/22.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/22.kmac_lc_escalation.2765690761
Short name	T372
Test name
Test status
Simulation time	43472350 ps
CPU time	2.09 seconds
Started	Sep 09 08:25:29 PM UTC 24
Finished	Sep 09 08:25:32 PM UTC 24
Peak memory	230336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765690761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.2765690761 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/22.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/22.kmac_long_msg_and_output.3113120000
Short name	T694
Test name
Test status
Simulation time	100084684707 ps
CPU time	2284.74 seconds
Started	Sep 09 08:24:09 PM UTC 24
Finished	Sep 09 09:02:41 PM UTC 24
Peak memory	1595156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113120000 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_and_output.3113120000 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/22.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/22.kmac_sideload.3877584905
Short name	T390
Test name
Test status
Simulation time	18045475221 ps
CPU time	215.37 seconds
Started	Sep 09 08:24:11 PM UTC 24
Finished	Sep 09 08:27:50 PM UTC 24
Peak memory	429808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877584905 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.3877584905 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/22.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/22.kmac_smoke.3063856104
Short name	T369
Test name
Test status
Simulation time	10076722300 ps
CPU time	72.68 seconds
Started	Sep 09 08:23:59 PM UTC 24
Finished	Sep 09 08:25:13 PM UTC 24
Peak memory	232692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063856104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.3063856104 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/22.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/22.kmac_stress_all.1279128461
Short name	T388
Test name
Test status
Simulation time	1257437730 ps
CPU time	111.22 seconds
Started	Sep 09 08:25:33 PM UTC 24
Finished	Sep 09 08:27:26 PM UTC 24
Peak memory	247472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279128461 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.1279128461 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/22.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/23.kmac_alert_test.3850911669
Short name	T384
Test name
Test status
Simulation time	19186135 ps
CPU time	1.12 seconds
Started	Sep 09 08:26:13 PM UTC 24
Finished	Sep 09 08:26:16 PM UTC 24
Peak memory	216232 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850911669 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.3850911669 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/23.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/23.kmac_app.169989989
Short name	T429
Test name
Test status
Simulation time	26604884450 ps
CPU time	397.4 seconds
Started	Sep 09 08:25:50 PM UTC 24
Finished	Sep 09 08:32:33 PM UTC 24
Peak memory	522208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169989989 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.169989989 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/23.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/23.kmac_burst_write.2317021511
Short name	T506
Test name
Test status
Simulation time	8028529047 ps
CPU time	861.07 seconds
Started	Sep 09 08:25:48 PM UTC 24
Finished	Sep 09 08:40:21 PM UTC 24
Peak memory	251636 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317021511 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.2317021511 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/23.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/23.kmac_entropy_refresh.4187722649
Short name	T391
Test name
Test status
Simulation time	15212528887 ps
CPU time	122.19 seconds
Started	Sep 09 08:25:54 PM UTC 24
Finished	Sep 09 08:27:58 PM UTC 24
Peak memory	286456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187722649 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.4187722649 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/23.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/23.kmac_error.1786527936
Short name	T451
Test name
Test status
Simulation time	21012997697 ps
CPU time	537.18 seconds
Started	Sep 09 08:25:58 PM UTC 24
Finished	Sep 09 08:35:02 PM UTC 24
Peak memory	642868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786527936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.1786527936 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/23.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/23.kmac_key_error.3805638668
Short name	T382
Test name
Test status
Simulation time	321644615 ps
CPU time	4 seconds
Started	Sep 09 08:26:04 PM UTC 24
Finished	Sep 09 08:26:09 PM UTC 24
Peak memory	230320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805638668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.3805638668 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/23.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/23.kmac_lc_escalation.1011263083
Short name	T383
Test name
Test status
Simulation time	49347743 ps
CPU time	1.85 seconds
Started	Sep 09 08:26:09 PM UTC 24
Finished	Sep 09 08:26:12 PM UTC 24
Peak memory	231728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011263083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.1011263083 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/23.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/23.kmac_long_msg_and_output.1418783405
Short name	T711
Test name
Test status
Simulation time	97186975240 ps
CPU time	3152.55 seconds
Started	Sep 09 08:25:47 PM UTC 24
Finished	Sep 09 09:18:53 PM UTC 24
Peak memory	3966760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418783405 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_and_output.1418783405 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/23.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/23.kmac_sideload.2690725108
Short name	T428
Test name
Test status
Simulation time	15791788562 ps
CPU time	397.82 seconds
Started	Sep 09 08:25:47 PM UTC 24
Finished	Sep 09 08:32:31 PM UTC 24
Peak memory	567080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690725108 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.2690725108 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/23.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/23.kmac_smoke.3455216701
Short name	T385
Test name
Test status
Simulation time	3532103392 ps
CPU time	43.03 seconds
Started	Sep 09 08:25:47 PM UTC 24
Finished	Sep 09 08:26:32 PM UTC 24
Peak memory	230536 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455216701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.3455216701 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/23.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/23.kmac_stress_all.4120384579
Short name	T543
Test name
Test status
Simulation time	43099846454 ps
CPU time	1039.51 seconds
Started	Sep 09 08:26:10 PM UTC 24
Finished	Sep 09 08:43:42 PM UTC 24
Peak memory	421896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120384579 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.4120384579 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/23.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/24.kmac_alert_test.2362578471
Short name	T395
Test name
Test status
Simulation time	15972337 ps
CPU time	1.17 seconds
Started	Sep 09 08:28:13 PM UTC 24
Finished	Sep 09 08:28:15 PM UTC 24
Peak memory	216232 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362578471 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.2362578471 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/24.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/24.kmac_app.954677366
Short name	T396
Test name
Test status
Simulation time	595753589 ps
CPU time	48.24 seconds
Started	Sep 09 08:27:28 PM UTC 24
Finished	Sep 09 08:28:18 PM UTC 24
Peak memory	243372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954677366 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.954677366 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/24.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/24.kmac_burst_write.3655373363
Short name	T459
Test name
Test status
Simulation time	12153166698 ps
CPU time	532.04 seconds
Started	Sep 09 08:27:25 PM UTC 24
Finished	Sep 09 08:36:24 PM UTC 24
Peak memory	251644 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655373363 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.3655373363 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/24.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/24.kmac_entropy_refresh.908604081
Short name	T399
Test name
Test status
Simulation time	7521208866 ps
CPU time	78.77 seconds
Started	Sep 09 08:27:28 PM UTC 24
Finished	Sep 09 08:28:48 PM UTC 24
Peak memory	253700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908604081 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.908604081 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/24.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/24.kmac_error.1324867985
Short name	T415
Test name
Test status
Simulation time	2103974245 ps
CPU time	163.05 seconds
Started	Sep 09 08:27:51 PM UTC 24
Finished	Sep 09 08:30:37 PM UTC 24
Peak memory	300900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324867985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.1324867985 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/24.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/24.kmac_key_error.2022371918
Short name	T392
Test name
Test status
Simulation time	277244981 ps
CPU time	3.23 seconds
Started	Sep 09 08:27:59 PM UTC 24
Finished	Sep 09 08:28:03 PM UTC 24
Peak memory	230780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022371918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.2022371918 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/24.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/24.kmac_lc_escalation.347515288
Short name	T53
Test name
Test status
Simulation time	1327505885 ps
CPU time	10.06 seconds
Started	Sep 09 08:28:04 PM UTC 24
Finished	Sep 09 08:28:15 PM UTC 24
Peak memory	245752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347515288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.347515288 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/24.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/24.kmac_long_msg_and_output.3826583758
Short name	T714
Test name
Test status
Simulation time	83091432387 ps
CPU time	3457.18 seconds
Started	Sep 09 08:26:32 PM UTC 24
Finished	Sep 09 09:24:47 PM UTC 24
Peak memory	4044576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826583758 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_and_output.3826583758 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/24.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/24.kmac_sideload.2390303368
Short name	T421
Test name
Test status
Simulation time	12701324003 ps
CPU time	314.51 seconds
Started	Sep 09 08:26:40 PM UTC 24
Finished	Sep 09 08:31:59 PM UTC 24
Peak memory	493356 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390303368 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.2390303368 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/24.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/24.kmac_smoke.1708525238
Short name	T389
Test name
Test status
Simulation time	4226327921 ps
CPU time	67.68 seconds
Started	Sep 09 08:26:17 PM UTC 24
Finished	Sep 09 08:27:27 PM UTC 24
Peak memory	235236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708525238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.1708525238 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/24.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/24.kmac_stress_all.3385653145
Short name	T535
Test name
Test status
Simulation time	28108946508 ps
CPU time	898.98 seconds
Started	Sep 09 08:28:11 PM UTC 24
Finished	Sep 09 08:43:21 PM UTC 24
Peak memory	743460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385653145 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.3385653145 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/24.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/25.kmac_alert_test.4016604363
Short name	T404
Test name
Test status
Simulation time	19150046 ps
CPU time	1.23 seconds
Started	Sep 09 08:29:11 PM UTC 24
Finished	Sep 09 08:29:13 PM UTC 24
Peak memory	216232 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016604363 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.4016604363 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/25.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/25.kmac_app.1933329955
Short name	T445
Test name
Test status
Simulation time	13109109282 ps
CPU time	346.48 seconds
Started	Sep 09 08:28:48 PM UTC 24
Finished	Sep 09 08:34:40 PM UTC 24
Peak memory	464684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933329955 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.1933329955 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/25.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/25.kmac_burst_write.3659593302
Short name	T607
Test name
Test status
Simulation time	286769248437 ps
CPU time	1265.15 seconds
Started	Sep 09 08:28:27 PM UTC 24
Finished	Sep 09 08:49:47 PM UTC 24
Peak memory	274344 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659593302 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.3659593302 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/25.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/25.kmac_entropy_refresh.1392339892
Short name	T435
Test name
Test status
Simulation time	23911021417 ps
CPU time	260.58 seconds
Started	Sep 09 08:28:49 PM UTC 24
Finished	Sep 09 08:33:14 PM UTC 24
Peak memory	428024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392339892 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.1392339892 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/25.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/25.kmac_error.4232807692
Short name	T476
Test name
Test status
Simulation time	33668731636 ps
CPU time	553.44 seconds
Started	Sep 09 08:28:50 PM UTC 24
Finished	Sep 09 08:38:11 PM UTC 24
Peak memory	626488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232807692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.4232807692 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/25.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/25.kmac_key_error.2351609631
Short name	T403
Test name
Test status
Simulation time	6095253149 ps
CPU time	7.05 seconds
Started	Sep 09 08:29:02 PM UTC 24
Finished	Sep 09 08:29:10 PM UTC 24
Peak memory	230464 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351609631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.2351609631 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/25.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/25.kmac_lc_escalation.1791352686
Short name	T402
Test name
Test status
Simulation time	70987150 ps
CPU time	1.92 seconds
Started	Sep 09 08:29:03 PM UTC 24
Finished	Sep 09 08:29:06 PM UTC 24
Peak memory	229684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791352686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.1791352686 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/25.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/25.kmac_long_msg_and_output.1930287618
Short name	T458
Test name
Test status
Simulation time	13038449091 ps
CPU time	479.76 seconds
Started	Sep 09 08:28:16 PM UTC 24
Finished	Sep 09 08:36:22 PM UTC 24
Peak memory	847656 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930287618 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_and_output.1930287618 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/25.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/25.kmac_sideload.1483668510
Short name	T417
Test name
Test status
Simulation time	14795561958 ps
CPU time	147.26 seconds
Started	Sep 09 08:28:18 PM UTC 24
Finished	Sep 09 08:30:49 PM UTC 24
Peak memory	329524 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483668510 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.1483668510 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/25.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/25.kmac_smoke.3628105077
Short name	T400
Test name
Test status
Simulation time	1538133065 ps
CPU time	42.61 seconds
Started	Sep 09 08:28:16 PM UTC 24
Finished	Sep 09 08:29:00 PM UTC 24
Peak memory	230516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628105077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.3628105077 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/25.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/25.kmac_stress_all.2127426298
Short name	T507
Test name
Test status
Simulation time	57884948375 ps
CPU time	672.17 seconds
Started	Sep 09 08:29:07 PM UTC 24
Finished	Sep 09 08:40:28 PM UTC 24
Peak memory	511984 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127426298 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.2127426298 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/25.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/26.kmac_alert_test.3536586818
Short name	T416
Test name
Test status
Simulation time	55884731 ps
CPU time	1.28 seconds
Started	Sep 09 08:30:36 PM UTC 24
Finished	Sep 09 08:30:38 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536586818 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.3536586818 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/26.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/26.kmac_app.335572383
Short name	T439
Test name
Test status
Simulation time	3856023488 ps
CPU time	220.59 seconds
Started	Sep 09 08:29:51 PM UTC 24
Finished	Sep 09 08:33:35 PM UTC 24
Peak memory	319212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335572383 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.335572383 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/26.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/26.kmac_burst_write.2702259566
Short name	T528
Test name
Test status
Simulation time	7993944559 ps
CPU time	771.54 seconds
Started	Sep 09 08:29:44 PM UTC 24
Finished	Sep 09 08:42:46 PM UTC 24
Peak memory	249652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702259566 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.2702259566 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/26.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/26.kmac_entropy_refresh.2615023449
Short name	T452
Test name
Test status
Simulation time	8668877129 ps
CPU time	312.79 seconds
Started	Sep 09 08:29:53 PM UTC 24
Finished	Sep 09 08:35:10 PM UTC 24
Peak memory	335924 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615023449 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.2615023449 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/26.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/26.kmac_error.1223012066
Short name	T427
Test name
Test status
Simulation time	3585410651 ps
CPU time	153.43 seconds
Started	Sep 09 08:29:54 PM UTC 24
Finished	Sep 09 08:32:30 PM UTC 24
Peak memory	298804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223012066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.1223012066 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/26.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/26.kmac_key_error.3106335626
Short name	T414
Test name
Test status
Simulation time	14585931056 ps
CPU time	13.38 seconds
Started	Sep 09 08:30:21 PM UTC 24
Finished	Sep 09 08:30:35 PM UTC 24
Peak memory	232568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106335626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.3106335626 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/26.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/26.kmac_lc_escalation.2316901084
Short name	T413
Test name
Test status
Simulation time	103936422 ps
CPU time	2.1 seconds
Started	Sep 09 08:30:31 PM UTC 24
Finished	Sep 09 08:30:34 PM UTC 24
Peak memory	230580 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316901084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.2316901084 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/26.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/26.kmac_long_msg_and_output.3346766150
Short name	T661
Test name
Test status
Simulation time	15983179361 ps
CPU time	1465.58 seconds
Started	Sep 09 08:29:23 PM UTC 24
Finished	Sep 09 08:54:06 PM UTC 24
Peak memory	1205992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346766150 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_and_output.3346766150 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/26.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/26.kmac_sideload.1670169196
Short name	T418
Test name
Test status
Simulation time	49975517949 ps
CPU time	79.18 seconds
Started	Sep 09 08:29:37 PM UTC 24
Finished	Sep 09 08:30:58 PM UTC 24
Peak memory	309032 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670169196 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.1670169196 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/26.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/26.kmac_smoke.2487930274
Short name	T411
Test name
Test status
Simulation time	13701160382 ps
CPU time	63.48 seconds
Started	Sep 09 08:29:14 PM UTC 24
Finished	Sep 09 08:30:20 PM UTC 24
Peak memory	235368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487930274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.2487930274 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/26.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/26.kmac_stress_all.3327384723
Short name	T592
Test name
Test status
Simulation time	70342344598 ps
CPU time	1022.12 seconds
Started	Sep 09 08:30:35 PM UTC 24
Finished	Sep 09 08:47:48 PM UTC 24
Peak memory	1284028 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327384723 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.3327384723 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/26.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/27.kmac_alert_test.2472330904
Short name	T426
Test name
Test status
Simulation time	48371559 ps
CPU time	1.19 seconds
Started	Sep 09 08:32:27 PM UTC 24
Finished	Sep 09 08:32:30 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472330904 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.2472330904 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/27.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/27.kmac_app.1985522015
Short name	T432
Test name
Test status
Simulation time	5208934990 ps
CPU time	99.19 seconds
Started	Sep 09 08:31:15 PM UTC 24
Finished	Sep 09 08:32:57 PM UTC 24
Peak memory	276392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985522015 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.1985522015 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/27.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/27.kmac_burst_write.2236353167
Short name	T553
Test name
Test status
Simulation time	340631094364 ps
CPU time	819.53 seconds
Started	Sep 09 08:30:59 PM UTC 24
Finished	Sep 09 08:44:49 PM UTC 24
Peak memory	261912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236353167 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.2236353167 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/27.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/27.kmac_entropy_refresh.252274644
Short name	T477
Test name
Test status
Simulation time	30103631952 ps
CPU time	403.59 seconds
Started	Sep 09 08:31:22 PM UTC 24
Finished	Sep 09 08:38:11 PM UTC 24
Peak memory	503608 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252274644 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.252274644 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/27.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/27.kmac_error.1821567018
Short name	T440
Test name
Test status
Simulation time	19157151357 ps
CPU time	106.26 seconds
Started	Sep 09 08:32:00 PM UTC 24
Finished	Sep 09 08:33:49 PM UTC 24
Peak memory	333616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821567018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.1821567018 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/27.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/27.kmac_key_error.3478902727
Short name	T423
Test name
Test status
Simulation time	370984744 ps
CPU time	4.6 seconds
Started	Sep 09 08:32:03 PM UTC 24
Finished	Sep 09 08:32:09 PM UTC 24
Peak memory	230316 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478902727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.3478902727 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/27.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/27.kmac_lc_escalation.1855737218
Short name	T424
Test name
Test status
Simulation time	37201316 ps
CPU time	1.78 seconds
Started	Sep 09 08:32:09 PM UTC 24
Finished	Sep 09 08:32:12 PM UTC 24
Peak memory	229848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855737218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.1855737218 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/27.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/27.kmac_long_msg_and_output.3316848260
Short name	T716
Test name
Test status
Simulation time	84622355737 ps
CPU time	3563.76 seconds
Started	Sep 09 08:30:39 PM UTC 24
Finished	Sep 09 09:30:43 PM UTC 24
Peak memory	4061076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316848260 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_and_output.3316848260 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/27.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/27.kmac_sideload.3932706253
Short name	T430
Test name
Test status
Simulation time	1186059813 ps
CPU time	121.05 seconds
Started	Sep 09 08:30:49 PM UTC 24
Finished	Sep 09 08:32:53 PM UTC 24
Peak memory	274140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932706253 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.3932706253 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/27.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/27.kmac_smoke.1442412446
Short name	T420
Test name
Test status
Simulation time	27320512187 ps
CPU time	41.25 seconds
Started	Sep 09 08:30:38 PM UTC 24
Finished	Sep 09 08:31:21 PM UTC 24
Peak memory	235428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442412446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.1442412446 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/27.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/27.kmac_stress_all.284162387
Short name	T516
Test name
Test status
Simulation time	9520325594 ps
CPU time	568.04 seconds
Started	Sep 09 08:32:12 PM UTC 24
Finished	Sep 09 08:41:48 PM UTC 24
Peak memory	381032 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284162387 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.284162387 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/27.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/28.kmac_alert_test.147310912
Short name	T437
Test name
Test status
Simulation time	14373827 ps
CPU time	1.18 seconds
Started	Sep 09 08:33:15 PM UTC 24
Finished	Sep 09 08:33:18 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147310912 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.147310912 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/28.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/28.kmac_app.4291249729
Short name	T462
Test name
Test status
Simulation time	16628496869 ps
CPU time	221.63 seconds
Started	Sep 09 08:32:54 PM UTC 24
Finished	Sep 09 08:36:39 PM UTC 24
Peak memory	329580 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291249729 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.4291249729 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/28.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/28.kmac_burst_write.3447204685
Short name	T461
Test name
Test status
Simulation time	16675930610 ps
CPU time	239.43 seconds
Started	Sep 09 08:32:34 PM UTC 24
Finished	Sep 09 08:36:37 PM UTC 24
Peak memory	239400 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447204685 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.3447204685 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/28.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/28.kmac_entropy_refresh.2460143543
Short name	T449
Test name
Test status
Simulation time	15162650954 ps
CPU time	108.99 seconds
Started	Sep 09 08:32:54 PM UTC 24
Finished	Sep 09 08:34:45 PM UTC 24
Peak memory	294964 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460143543 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.2460143543 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/28.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/28.kmac_error.1874350148
Short name	T484
Test name
Test status
Simulation time	23570276544 ps
CPU time	325.95 seconds
Started	Sep 09 08:32:58 PM UTC 24
Finished	Sep 09 08:38:28 PM UTC 24
Peak memory	554800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874350148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.1874350148 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/28.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/28.kmac_key_error.3682504809
Short name	T434
Test name
Test status
Simulation time	3295600397 ps
CPU time	9.61 seconds
Started	Sep 09 08:33:00 PM UTC 24
Finished	Sep 09 08:33:11 PM UTC 24
Peak memory	230380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682504809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.3682504809 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/28.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/28.kmac_lc_escalation.1212974238
Short name	T436
Test name
Test status
Simulation time	57210855 ps
CPU time	2.34 seconds
Started	Sep 09 08:33:11 PM UTC 24
Finished	Sep 09 08:33:15 PM UTC 24
Peak memory	230376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212974238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.1212974238 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/28.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/28.kmac_long_msg_and_output.1717974373
Short name	T566
Test name
Test status
Simulation time	22396284178 ps
CPU time	781.3 seconds
Started	Sep 09 08:32:31 PM UTC 24
Finished	Sep 09 08:45:42 PM UTC 24
Peak memory	763672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717974373 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_and_output.1717974373 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/28.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/28.kmac_sideload.781003225
Short name	T465
Test name
Test status
Simulation time	16324296335 ps
CPU time	256.61 seconds
Started	Sep 09 08:32:32 PM UTC 24
Finished	Sep 09 08:36:53 PM UTC 24
Peak memory	450408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781003225 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.781003225 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/28.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/28.kmac_smoke.1685457832
Short name	T431
Test name
Test status
Simulation time	1168721562 ps
CPU time	20.89 seconds
Started	Sep 09 08:32:31 PM UTC 24
Finished	Sep 09 08:32:53 PM UTC 24
Peak memory	230464 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685457832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.1685457832 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/28.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/28.kmac_stress_all.871142860
Short name	T701
Test name
Test status
Simulation time	275446477388 ps
CPU time	1958.76 seconds
Started	Sep 09 08:33:15 PM UTC 24
Finished	Sep 09 09:06:17 PM UTC 24
Peak memory	1493016 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871142860 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.871142860 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/28.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/29.kmac_alert_test.1019731016
Short name	T448
Test name
Test status
Simulation time	44461957 ps
CPU time	1.11 seconds
Started	Sep 09 08:34:42 PM UTC 24
Finished	Sep 09 08:34:44 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019731016 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.1019731016 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/29.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/29.kmac_app.2893206627
Short name	T467
Test name
Test status
Simulation time	49369028671 ps
CPU time	164.76 seconds
Started	Sep 09 08:34:09 PM UTC 24
Finished	Sep 09 08:36:57 PM UTC 24
Peak memory	372452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893206627 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.2893206627 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/29.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/29.kmac_burst_write.2371378178
Short name	T454
Test name
Test status
Simulation time	987525007 ps
CPU time	114.95 seconds
Started	Sep 09 08:33:50 PM UTC 24
Finished	Sep 09 08:35:47 PM UTC 24
Peak memory	245484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371378178 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.2371378178 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/29.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/29.kmac_entropy_refresh.3769434054
Short name	T496
Test name
Test status
Simulation time	39499381077 ps
CPU time	303.58 seconds
Started	Sep 09 08:34:14 PM UTC 24
Finished	Sep 09 08:39:22 PM UTC 24
Peak memory	431908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769434054 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.3769434054 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/29.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/29.kmac_error.1667953644
Short name	T444
Test name
Test status
Simulation time	84945604 ps
CPU time	1.77 seconds
Started	Sep 09 08:34:33 PM UTC 24
Finished	Sep 09 08:34:36 PM UTC 24
Peak memory	229680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667953644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.1667953644 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/29.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/29.kmac_key_error.1342513915
Short name	T447
Test name
Test status
Simulation time	1274810222 ps
CPU time	6.78 seconds
Started	Sep 09 08:34:35 PM UTC 24
Finished	Sep 09 08:34:42 PM UTC 24
Peak memory	230512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342513915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.1342513915 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/29.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/29.kmac_lc_escalation.1482776048
Short name	T446
Test name
Test status
Simulation time	73378251 ps
CPU time	2.78 seconds
Started	Sep 09 08:34:37 PM UTC 24
Finished	Sep 09 08:34:41 PM UTC 24
Peak memory	230592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482776048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.1482776048 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/29.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/29.kmac_long_msg_and_output.2697114176
Short name	T703
Test name
Test status
Simulation time	40735296588 ps
CPU time	2070.29 seconds
Started	Sep 09 08:33:36 PM UTC 24
Finished	Sep 09 09:08:30 PM UTC 24
Peak memory	1507044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697114176 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_and_output.2697114176 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/29.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/29.kmac_sideload.2710973935
Short name	T472
Test name
Test status
Simulation time	8879092197 ps
CPU time	219.68 seconds
Started	Sep 09 08:33:37 PM UTC 24
Finished	Sep 09 08:37:20 PM UTC 24
Peak memory	340032 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710973935 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.2710973935 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/29.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/29.kmac_smoke.3703457474
Short name	T443
Test name
Test status
Simulation time	19309189280 ps
CPU time	63.73 seconds
Started	Sep 09 08:33:18 PM UTC 24
Finished	Sep 09 08:34:24 PM UTC 24
Peak memory	235364 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703457474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.3703457474 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/29.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/29.kmac_stress_all.572222006
Short name	T486
Test name
Test status
Simulation time	5061320189 ps
CPU time	225.68 seconds
Started	Sep 09 08:34:41 PM UTC 24
Finished	Sep 09 08:38:30 PM UTC 24
Peak memory	252000 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572222006 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.572222006 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/29.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/3.kmac_alert_test.1289196145
Short name	T51
Test name
Test status
Simulation time	68812689 ps
CPU time	1.29 seconds
Started	Sep 09 08:01:06 PM UTC 24
Finished	Sep 09 08:01:09 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289196145 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.1289196145 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/3.kmac_app.3966129042
Short name	T179
Test name
Test status
Simulation time	765861025 ps
CPU time	14.77 seconds
Started	Sep 09 08:00:37 PM UTC 24
Finished	Sep 09 08:00:53 PM UTC 24
Peak memory	235444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966129042 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.3966129042 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/3.kmac_app_with_partial_data.2216241467
Short name	T172
Test name
Test status
Simulation time	27295482755 ps
CPU time	256.31 seconds
Started	Sep 09 08:00:37 PM UTC 24
Finished	Sep 09 08:04:57 PM UTC 24
Peak memory	331648 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216241467 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.2216241467 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_app_with_partial_data/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/3.kmac_burst_write.981679930
Short name	T168
Test name
Test status
Simulation time	17245937331 ps
CPU time	125.3 seconds
Started	Sep 09 07:59:57 PM UTC 24
Finished	Sep 09 08:02:04 PM UTC 24
Peak memory	235504 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981679930 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.981679930 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/3.kmac_edn_timeout_error.2792761666
Short name	T180
Test name
Test status
Simulation time	96772642 ps
CPU time	7.11 seconds
Started	Sep 09 08:00:46 PM UTC 24
Finished	Sep 09 08:00:54 PM UTC 24
Peak memory	232320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792761666 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.2792761666 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_mode_error.472555921
Short name	T183
Test name
Test status
Simulation time	897300050 ps
CPU time	41.44 seconds
Started	Sep 09 08:00:52 PM UTC 24
Finished	Sep 09 08:01:35 PM UTC 24
Peak memory	235028 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472555921 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.472555921 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_ready_error.2439467397
Short name	T184
Test name
Test status
Simulation time	2351389983 ps
CPU time	49.07 seconds
Started	Sep 09 08:00:54 PM UTC 24
Finished	Sep 09 08:01:45 PM UTC 24
Peak memory	230728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439467397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.2439467397 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_entropy_ready_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_refresh.879287343
Short name	T47
Test name
Test status
Simulation time	7275977024 ps
CPU time	170.23 seconds
Started	Sep 09 08:00:40 PM UTC 24
Finished	Sep 09 08:03:33 PM UTC 24
Peak memory	298840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879287343 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.879287343 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/3.kmac_error.3332672739
Short name	T74
Test name
Test status
Simulation time	6529410823 ps
CPU time	102.99 seconds
Started	Sep 09 08:00:43 PM UTC 24
Finished	Sep 09 08:02:29 PM UTC 24
Peak memory	300912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332672739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.3332672739 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/3.kmac_key_error.3134803157
Short name	T59
Test name
Test status
Simulation time	1430010124 ps
CPU time	13.31 seconds
Started	Sep 09 08:00:44 PM UTC 24
Finished	Sep 09 08:00:59 PM UTC 24
Peak memory	230464 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134803157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.3134803157 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/3.kmac_long_msg_and_output.3244901467
Short name	T265
Test name
Test status
Simulation time	9292516444 ps
CPU time	915.65 seconds
Started	Sep 09 07:59:53 PM UTC 24
Finished	Sep 09 08:15:19 PM UTC 24
Peak memory	825156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244901467 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_and_output.3244901467 +enable_mas king=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/3.kmac_mubi.821387729
Short name	T77
Test name
Test status
Simulation time	1076216114 ps
CPU time	22.74 seconds
Started	Sep 09 08:00:41 PM UTC 24
Finished	Sep 09 08:01:05 PM UTC 24
Peak memory	235676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821387729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.821387729 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/3.kmac_sec_cm.3474997029
Short name	T66
Test name
Test status
Simulation time	5242944318 ps
CPU time	86.43 seconds
Started	Sep 09 08:01:00 PM UTC 24
Finished	Sep 09 08:02:29 PM UTC 24
Peak memory	295904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474997029 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.3474997029 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/3.kmac_sideload.1325283459
Short name	T28
Test name
Test status
Simulation time	7258758966 ps
CPU time	269.83 seconds
Started	Sep 09 07:59:57 PM UTC 24
Finished	Sep 09 08:04:30 PM UTC 24
Peak memory	442156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325283459 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.1325283459 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/3.kmac_smoke.704387672
Short name	T123
Test name
Test status
Simulation time	1109819184 ps
CPU time	52.45 seconds
Started	Sep 09 07:59:49 PM UTC 24
Finished	Sep 09 08:00:44 PM UTC 24
Peak memory	234672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704387672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.704387672 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/3.kmac_stress_all.2146056784
Short name	T240
Test name
Test status
Simulation time	200568501861 ps
CPU time	714.28 seconds
Started	Sep 09 08:00:55 PM UTC 24
Finished	Sep 09 08:12:58 PM UTC 24
Peak memory	949996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146056784 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.2146056784 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/3.kmac_stress_all_with_rand_reset.3837905079
Short name	T43
Test name
Test status
Simulation time	18747195880 ps
CPU time	349.62 seconds
Started	Sep 09 08:00:59 PM UTC 24
Finished	Sep 09 08:06:54 PM UTC 24
Peak memory	333804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3837905079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all_ with_rand_reset.3837905079 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac.3890795191
Short name	T121
Test name
Test status
Simulation time	126556498 ps
CPU time	3.18 seconds
Started	Sep 09 08:00:36 PM UTC 24
Finished	Sep 09 08:00:40 PM UTC 24
Peak memory	230532 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890795191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac.3890795191 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_test_vectors_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac_xof.1839666409
Short name	T120
Test name
Test status
Simulation time	116982506 ps
CPU time	2.66 seconds
Started	Sep 09 08:00:36 PM UTC 24
Finished	Sep 09 08:00:40 PM UTC 24
Peak memory	230460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839666409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.1839666409 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_test_vectors_kmac_xof/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_224.2066790112
Short name	T181
Test name
Test status
Simulation time	3525523275 ps
CPU time	57.42 seconds
Started	Sep 09 08:00:08 PM UTC 24
Finished	Sep 09 08:01:07 PM UTC 24
Peak memory	258080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066790112 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.2066790112 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_224/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_256.4114338650
Short name	T178
Test name
Test status
Simulation time	587754125 ps
CPU time	41.25 seconds
Started	Sep 09 08:00:08 PM UTC 24
Finished	Sep 09 08:00:51 PM UTC 24
Peak memory	230532 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114338650 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.4114338650 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_256/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_384.2645202686
Short name	T122
Test name
Test status
Simulation time	831597585 ps
CPU time	30.45 seconds
Started	Sep 09 08:00:11 PM UTC 24
Finished	Sep 09 08:00:43 PM UTC 24
Peak memory	230524 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645202686 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.2645202686 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_384/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_512.932928157
Short name	T259
Test name
Test status
Simulation time	23844791855 ps
CPU time	844.08 seconds
Started	Sep 09 08:00:19 PM UTC 24
Finished	Sep 09 08:14:34 PM UTC 24
Peak memory	693908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932928157 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.932928157 + enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_512/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_128.3909470764
Short name	T568
Test name
Test status
Simulation time	73698269407 ps
CPU time	2704.6 seconds
Started	Sep 09 08:00:20 PM UTC 24
Finished	Sep 09 08:45:56 PM UTC 24
Peak memory	3620608 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909470764 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.3909470 764 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_test_vectors_shake_128/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_256.3513075497
Short name	T381
Test name
Test status
Simulation time	65859032059 ps
CPU time	1523.58 seconds
Started	Sep 09 08:00:27 PM UTC 24
Finished	Sep 09 08:26:08 PM UTC 24
Peak memory	1118044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513075497 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.3513075 497 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/3.kmac_test_vectors_shake_256/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/30.kmac_alert_test.307592012
Short name	T457
Test name
Test status
Simulation time	21632268 ps
CPU time	1.27 seconds
Started	Sep 09 08:36:17 PM UTC 24
Finished	Sep 09 08:36:19 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307592012 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.307592012 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/30.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/30.kmac_app.3037710043
Short name	T460
Test name
Test status
Simulation time	1547089084 ps
CPU time	89.61 seconds
Started	Sep 09 08:35:03 PM UTC 24
Finished	Sep 09 08:36:35 PM UTC 24
Peak memory	258092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037710043 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.3037710043 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/30.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/30.kmac_burst_write.1941140409
Short name	T541
Test name
Test status
Simulation time	155011337314 ps
CPU time	507.75 seconds
Started	Sep 09 08:35:00 PM UTC 24
Finished	Sep 09 08:43:34 PM UTC 24
Peak memory	255904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941140409 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.1941140409 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/30.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/30.kmac_entropy_refresh.976812796
Short name	T530
Test name
Test status
Simulation time	90945451219 ps
CPU time	451.85 seconds
Started	Sep 09 08:35:10 PM UTC 24
Finished	Sep 09 08:42:49 PM UTC 24
Peak memory	542440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976812796 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.976812796 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/30.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/30.kmac_error.3172272716
Short name	T481
Test name
Test status
Simulation time	2592826702 ps
CPU time	184.5 seconds
Started	Sep 09 08:35:15 PM UTC 24
Finished	Sep 09 08:38:23 PM UTC 24
Peak memory	317216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172272716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.3172272716 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/30.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/30.kmac_key_error.3646202571
Short name	T455
Test name
Test status
Simulation time	859209461 ps
CPU time	5.75 seconds
Started	Sep 09 08:35:49 PM UTC 24
Finished	Sep 09 08:35:56 PM UTC 24
Peak memory	230452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646202571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.3646202571 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/30.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/30.kmac_lc_escalation.955817941
Short name	T75
Test name
Test status
Simulation time	1129151863 ps
CPU time	18.01 seconds
Started	Sep 09 08:35:57 PM UTC 24
Finished	Sep 09 08:36:16 PM UTC 24
Peak memory	245732 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955817941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.955817941 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/30.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/30.kmac_long_msg_and_output.4059050860
Short name	T544
Test name
Test status
Simulation time	21138742664 ps
CPU time	539.88 seconds
Started	Sep 09 08:34:45 PM UTC 24
Finished	Sep 09 08:43:52 PM UTC 24
Peak memory	931880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059050860 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_and_output.4059050860 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/30.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/30.kmac_sideload.2819262698
Short name	T493
Test name
Test status
Simulation time	14253767782 ps
CPU time	244.21 seconds
Started	Sep 09 08:34:46 PM UTC 24
Finished	Sep 09 08:38:54 PM UTC 24
Peak memory	438296 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819262698 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.2819262698 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/30.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/30.kmac_smoke.3387661256
Short name	T453
Test name
Test status
Simulation time	4451224352 ps
CPU time	30.17 seconds
Started	Sep 09 08:34:43 PM UTC 24
Finished	Sep 09 08:35:14 PM UTC 24
Peak memory	230648 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387661256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.3387661256 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/30.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/30.kmac_stress_all.664763610
Short name	T575
Test name
Test status
Simulation time	7624624371 ps
CPU time	606.13 seconds
Started	Sep 09 08:36:06 PM UTC 24
Finished	Sep 09 08:46:21 PM UTC 24
Peak memory	628784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664763610 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.664763610 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/30.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/31.kmac_alert_test.1842236375
Short name	T470
Test name
Test status
Simulation time	13143317 ps
CPU time	1.21 seconds
Started	Sep 09 08:37:04 PM UTC 24
Finished	Sep 09 08:37:06 PM UTC 24
Peak memory	216232 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842236375 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.1842236375 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/31.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/31.kmac_app.1816633567
Short name	T498
Test name
Test status
Simulation time	35253767712 ps
CPU time	183.11 seconds
Started	Sep 09 08:36:37 PM UTC 24
Finished	Sep 09 08:39:44 PM UTC 24
Peak memory	345900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816633567 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.1816633567 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/31.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/31.kmac_burst_write.560261960
Short name	T515
Test name
Test status
Simulation time	79881213500 ps
CPU time	292.71 seconds
Started	Sep 09 08:36:36 PM UTC 24
Finished	Sep 09 08:41:33 PM UTC 24
Peak memory	239536 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560261960 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.560261960 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/31.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/31.kmac_entropy_refresh.3907689969
Short name	T491
Test name
Test status
Simulation time	3799365107 ps
CPU time	125.99 seconds
Started	Sep 09 08:36:39 PM UTC 24
Finished	Sep 09 08:38:48 PM UTC 24
Peak memory	290724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907689969 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.3907689969 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/31.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/31.kmac_error.426220908
Short name	T529
Test name
Test status
Simulation time	174603053922 ps
CPU time	351.46 seconds
Started	Sep 09 08:36:51 PM UTC 24
Finished	Sep 09 08:42:47 PM UTC 24
Peak memory	511796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426220908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.426220908 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/31.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/31.kmac_key_error.348330299
Short name	T468
Test name
Test status
Simulation time	5064027502 ps
CPU time	11.38 seconds
Started	Sep 09 08:36:52 PM UTC 24
Finished	Sep 09 08:37:04 PM UTC 24
Peak memory	230396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348330299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.348330299 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/31.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/31.kmac_lc_escalation.3209943893
Short name	T469
Test name
Test status
Simulation time	153277257 ps
CPU time	2.01 seconds
Started	Sep 09 08:37:03 PM UTC 24
Finished	Sep 09 08:37:06 PM UTC 24
Peak memory	231772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209943893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.3209943893 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/31.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/31.kmac_long_msg_and_output.322995429
Short name	T697
Test name
Test status
Simulation time	197898912539 ps
CPU time	1668.05 seconds
Started	Sep 09 08:36:23 PM UTC 24
Finished	Sep 09 09:04:30 PM UTC 24
Peak memory	2258736 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322995429 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_and_output.322995429 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/31.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/31.kmac_sideload.1423550225
Short name	T502
Test name
Test status
Simulation time	2427212963 ps
CPU time	202.01 seconds
Started	Sep 09 08:36:24 PM UTC 24
Finished	Sep 09 08:39:49 PM UTC 24
Peak memory	315108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423550225 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.1423550225 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/31.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/31.kmac_smoke.2217228817
Short name	T464
Test name
Test status
Simulation time	2620983146 ps
CPU time	29.19 seconds
Started	Sep 09 08:36:20 PM UTC 24
Finished	Sep 09 08:36:51 PM UTC 24
Peak memory	230536 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217228817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.2217228817 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/31.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/31.kmac_stress_all.2386580978
Short name	T602
Test name
Test status
Simulation time	65871927874 ps
CPU time	733.45 seconds
Started	Sep 09 08:37:04 PM UTC 24
Finished	Sep 09 08:49:27 PM UTC 24
Peak memory	434164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386580978 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.2386580978 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/31.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/32.kmac_alert_test.4130709007
Short name	T479
Test name
Test status
Simulation time	47670325 ps
CPU time	1.26 seconds
Started	Sep 09 08:38:12 PM UTC 24
Finished	Sep 09 08:38:14 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130709007 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.4130709007 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/32.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/32.kmac_app.3954247831
Short name	T473
Test name
Test status
Simulation time	1161397375 ps
CPU time	37.26 seconds
Started	Sep 09 08:37:11 PM UTC 24
Finished	Sep 09 08:37:49 PM UTC 24
Peak memory	247604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954247831 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.3954247831 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/32.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/32.kmac_burst_write.2734201404
Short name	T599
Test name
Test status
Simulation time	32353082501 ps
CPU time	693.38 seconds
Started	Sep 09 08:37:07 PM UTC 24
Finished	Sep 09 08:48:49 PM UTC 24
Peak memory	253732 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734201404 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.2734201404 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/32.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/32.kmac_entropy_refresh.2101692609
Short name	T525
Test name
Test status
Simulation time	21840819179 ps
CPU time	318.01 seconds
Started	Sep 09 08:37:21 PM UTC 24
Finished	Sep 09 08:42:44 PM UTC 24
Peak memory	333688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101692609 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.2101692609 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/32.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/32.kmac_error.3744906375
Short name	T511
Test name
Test status
Simulation time	2406370274 ps
CPU time	185.31 seconds
Started	Sep 09 08:37:50 PM UTC 24
Finished	Sep 09 08:40:58 PM UTC 24
Peak memory	317236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744906375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.3744906375 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/32.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/32.kmac_key_error.3552451218
Short name	T475
Test name
Test status
Simulation time	1321227795 ps
CPU time	12.89 seconds
Started	Sep 09 08:37:55 PM UTC 24
Finished	Sep 09 08:38:09 PM UTC 24
Peak memory	230380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552451218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.3552451218 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/32.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/32.kmac_lc_escalation.2401665850
Short name	T478
Test name
Test status
Simulation time	155120409 ps
CPU time	2 seconds
Started	Sep 09 08:38:10 PM UTC 24
Finished	Sep 09 08:38:13 PM UTC 24
Peak memory	229680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401665850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.2401665850 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/32.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/32.kmac_long_msg_and_output.78843653
Short name	T708
Test name
Test status
Simulation time	148817448179 ps
CPU time	1990.44 seconds
Started	Sep 09 08:37:05 PM UTC 24
Finished	Sep 09 09:10:37 PM UTC 24
Peak memory	1663020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78843653 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_and_output.78843653 +enable_maskin g=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/32.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/32.kmac_sideload.1566350333
Short name	T482
Test name
Test status
Simulation time	2296237007 ps
CPU time	77.69 seconds
Started	Sep 09 08:37:06 PM UTC 24
Finished	Sep 09 08:38:26 PM UTC 24
Peak memory	288560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566350333 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.1566350333 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/32.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/32.kmac_smoke.2076569456
Short name	T483
Test name
Test status
Simulation time	2778326678 ps
CPU time	81.18 seconds
Started	Sep 09 08:37:04 PM UTC 24
Finished	Sep 09 08:38:27 PM UTC 24
Peak memory	235284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076569456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.2076569456 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/32.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/32.kmac_stress_all.2231515772
Short name	T690
Test name
Test status
Simulation time	57052470475 ps
CPU time	1412.23 seconds
Started	Sep 09 08:38:11 PM UTC 24
Finished	Sep 09 09:02:00 PM UTC 24
Peak memory	1011832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231515772 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.2231515772 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/32.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/33.kmac_alert_test.2025731264
Short name	T490
Test name
Test status
Simulation time	29421249 ps
CPU time	0.92 seconds
Started	Sep 09 08:38:43 PM UTC 24
Finished	Sep 09 08:38:45 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025731264 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.2025731264 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/33.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/33.kmac_app.3275963394
Short name	T563
Test name
Test status
Simulation time	23629677939 ps
CPU time	413.95 seconds
Started	Sep 09 08:38:27 PM UTC 24
Finished	Sep 09 08:45:26 PM UTC 24
Peak memory	522032 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275963394 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.3275963394 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/33.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/33.kmac_burst_write.138260159
Short name	T557
Test name
Test status
Simulation time	4392251898 ps
CPU time	401.5 seconds
Started	Sep 09 08:38:24 PM UTC 24
Finished	Sep 09 08:45:10 PM UTC 24
Peak memory	245492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138260159 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.138260159 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/33.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/33.kmac_entropy_refresh.158643134
Short name	T527
Test name
Test status
Simulation time	17988306194 ps
CPU time	252.95 seconds
Started	Sep 09 08:38:29 PM UTC 24
Finished	Sep 09 08:42:46 PM UTC 24
Peak memory	366380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158643134 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.158643134 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/33.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/33.kmac_error.674963892
Short name	T517
Test name
Test status
Simulation time	2355073659 ps
CPU time	196.85 seconds
Started	Sep 09 08:38:30 PM UTC 24
Finished	Sep 09 08:41:50 PM UTC 24
Peak memory	317568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674963892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.674963892 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/33.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/33.kmac_key_error.1999605181
Short name	T489
Test name
Test status
Simulation time	6970996431 ps
CPU time	12.79 seconds
Started	Sep 09 08:38:31 PM UTC 24
Finished	Sep 09 08:38:45 PM UTC 24
Peak memory	232572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999605181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.1999605181 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/33.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/33.kmac_lc_escalation.2855059455
Short name	T488
Test name
Test status
Simulation time	1559428086 ps
CPU time	10.22 seconds
Started	Sep 09 08:38:31 PM UTC 24
Finished	Sep 09 08:38:42 PM UTC 24
Peak memory	245064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855059455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.2855059455 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/33.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/33.kmac_long_msg_and_output.1368322004
Short name	T681
Test name
Test status
Simulation time	53656101881 ps
CPU time	1218.64 seconds
Started	Sep 09 08:38:15 PM UTC 24
Finished	Sep 09 08:58:49 PM UTC 24
Peak memory	1011496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368322004 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_and_output.1368322004 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/33.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/33.kmac_sideload.1824754370
Short name	T510
Test name
Test status
Simulation time	20204587466 ps
CPU time	145.24 seconds
Started	Sep 09 08:38:20 PM UTC 24
Finished	Sep 09 08:40:48 PM UTC 24
Peak memory	364532 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824754370 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.1824754370 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/33.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/33.kmac_smoke.3466307563
Short name	T485
Test name
Test status
Simulation time	944137895 ps
CPU time	14.47 seconds
Started	Sep 09 08:38:14 PM UTC 24
Finished	Sep 09 08:38:30 PM UTC 24
Peak memory	230664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466307563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.3466307563 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/33.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/33.kmac_stress_all.3803666536
Short name	T501
Test name
Test status
Simulation time	4058454258 ps
CPU time	63.92 seconds
Started	Sep 09 08:38:42 PM UTC 24
Finished	Sep 09 08:39:48 PM UTC 24
Peak memory	270188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803666536 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.3803666536 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/33.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/34.kmac_alert_test.2017477322
Short name	T500
Test name
Test status
Simulation time	17707456 ps
CPU time	1.2 seconds
Started	Sep 09 08:39:44 PM UTC 24
Finished	Sep 09 08:39:47 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017477322 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.2017477322 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/34.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/34.kmac_app.2790258669
Short name	T514
Test name
Test status
Simulation time	13221529874 ps
CPU time	148.25 seconds
Started	Sep 09 08:38:55 PM UTC 24
Finished	Sep 09 08:41:26 PM UTC 24
Peak memory	368692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790258669 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.2790258669 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/34.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/34.kmac_burst_write.604864858
Short name	T623
Test name
Test status
Simulation time	99454169402 ps
CPU time	727.85 seconds
Started	Sep 09 08:38:53 PM UTC 24
Finished	Sep 09 08:51:11 PM UTC 24
Peak memory	260024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604864858 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.604864858 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/34.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/34.kmac_entropy_refresh.2052090273
Short name	T499
Test name
Test status
Simulation time	8600459036 ps
CPU time	39.5 seconds
Started	Sep 09 08:39:04 PM UTC 24
Finished	Sep 09 08:39:45 PM UTC 24
Peak memory	255928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052090273 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.2052090273 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/34.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/34.kmac_error.3422176722
Short name	T569
Test name
Test status
Simulation time	56983638550 ps
CPU time	406.74 seconds
Started	Sep 09 08:39:11 PM UTC 24
Finished	Sep 09 08:46:04 PM UTC 24
Peak memory	513768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422176722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.3422176722 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/34.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/34.kmac_key_error.2798707668
Short name	T497
Test name
Test status
Simulation time	3814377295 ps
CPU time	13.8 seconds
Started	Sep 09 08:39:23 PM UTC 24
Finished	Sep 09 08:39:38 PM UTC 24
Peak memory	230476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798707668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.2798707668 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/34.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/34.kmac_lc_escalation.2512706290
Short name	T58
Test name
Test status
Simulation time	34829987 ps
CPU time	1.87 seconds
Started	Sep 09 08:39:39 PM UTC 24
Finished	Sep 09 08:39:42 PM UTC 24
Peak memory	231672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512706290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.2512706290 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/34.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/34.kmac_long_msg_and_output.3539917148
Short name	T610
Test name
Test status
Simulation time	7870082939 ps
CPU time	663.07 seconds
Started	Sep 09 08:38:46 PM UTC 24
Finished	Sep 09 08:49:57 PM UTC 24
Peak memory	634852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539917148 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_and_output.3539917148 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/34.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/34.kmac_sideload.1845928819
Short name	T564
Test name
Test status
Simulation time	20956059374 ps
CPU time	395.07 seconds
Started	Sep 09 08:38:48 PM UTC 24
Finished	Sep 09 08:45:29 PM UTC 24
Peak memory	538416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845928819 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.1845928819 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/34.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/34.kmac_smoke.2333593978
Short name	T492
Test name
Test status
Simulation time	676147275 ps
CPU time	6.46 seconds
Started	Sep 09 08:38:45 PM UTC 24
Finished	Sep 09 08:38:53 PM UTC 24
Peak memory	230512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333593978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.2333593978 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/34.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/34.kmac_stress_all.1008910385
Short name	T693
Test name
Test status
Simulation time	316530149424 ps
CPU time	1333.84 seconds
Started	Sep 09 08:39:43 PM UTC 24
Finished	Sep 09 09:02:13 PM UTC 24
Peak memory	557108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008910385 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.1008910385 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/34.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/35.kmac_alert_test.1558514183
Short name	T509
Test name
Test status
Simulation time	20391991 ps
CPU time	1.19 seconds
Started	Sep 09 08:40:32 PM UTC 24
Finished	Sep 09 08:40:35 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558514183 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.1558514183 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/35.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/35.kmac_app.3336207445
Short name	T570
Test name
Test status
Simulation time	26428210427 ps
CPU time	363.68 seconds
Started	Sep 09 08:39:58 PM UTC 24
Finished	Sep 09 08:46:07 PM UTC 24
Peak memory	460528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336207445 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.3336207445 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/35.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/35.kmac_burst_write.1928510537
Short name	T504
Test name
Test status
Simulation time	139963343 ps
CPU time	8.31 seconds
Started	Sep 09 08:39:51 PM UTC 24
Finished	Sep 09 08:40:00 PM UTC 24
Peak memory	230456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928510537 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.1928510537 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/35.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/35.kmac_entropy_refresh.1683080811
Short name	T523
Test name
Test status
Simulation time	35913341794 ps
CPU time	153.35 seconds
Started	Sep 09 08:40:01 PM UTC 24
Finished	Sep 09 08:42:37 PM UTC 24
Peak memory	319216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683080811 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.1683080811 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/35.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/35.kmac_error.1690144328
Short name	T533
Test name
Test status
Simulation time	5762110995 ps
CPU time	193.52 seconds
Started	Sep 09 08:40:03 PM UTC 24
Finished	Sep 09 08:43:20 PM UTC 24
Peak memory	374576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690144328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.1690144328 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/35.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/35.kmac_key_error.2507735479
Short name	T508
Test name
Test status
Simulation time	2150608703 ps
CPU time	7.34 seconds
Started	Sep 09 08:40:22 PM UTC 24
Finished	Sep 09 08:40:31 PM UTC 24
Peak memory	230396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507735479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.2507735479 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/35.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/35.kmac_lc_escalation.4212718988
Short name	T55
Test name
Test status
Simulation time	176243666 ps
CPU time	2 seconds
Started	Sep 09 08:40:28 PM UTC 24
Finished	Sep 09 08:40:31 PM UTC 24
Peak memory	234416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212718988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.4212718988 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/35.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/35.kmac_long_msg_and_output.2725278609
Short name	T503
Test name
Test status
Simulation time	232490312 ps
CPU time	8.49 seconds
Started	Sep 09 08:39:47 PM UTC 24
Finished	Sep 09 08:39:57 PM UTC 24
Peak memory	235348 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725278609 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_and_output.2725278609 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/35.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/35.kmac_sideload.3971923463
Short name	T555
Test name
Test status
Simulation time	4127647589 ps
CPU time	307.2 seconds
Started	Sep 09 08:39:48 PM UTC 24
Finished	Sep 09 08:45:00 PM UTC 24
Peak memory	376612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971923463 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.3971923463 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/35.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/35.kmac_smoke.3385198662
Short name	T505
Test name
Test status
Simulation time	2509493993 ps
CPU time	15.14 seconds
Started	Sep 09 08:39:45 PM UTC 24
Finished	Sep 09 08:40:02 PM UTC 24
Peak memory	230528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385198662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.3385198662 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/35.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/35.kmac_stress_all.1139391138
Short name	T645
Test name
Test status
Simulation time	118575542898 ps
CPU time	733.43 seconds
Started	Sep 09 08:40:31 PM UTC 24
Finished	Sep 09 08:52:54 PM UTC 24
Peak memory	507892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139391138 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.1139391138 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/35.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/36.kmac_alert_test.590392793
Short name	T519
Test name
Test status
Simulation time	20244233 ps
CPU time	1.28 seconds
Started	Sep 09 08:42:07 PM UTC 24
Finished	Sep 09 08:42:09 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590392793 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.590392793 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/36.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/36.kmac_app.3159141514
Short name	T551
Test name
Test status
Simulation time	29001604850 ps
CPU time	182.64 seconds
Started	Sep 09 08:41:20 PM UTC 24
Finished	Sep 09 08:44:26 PM UTC 24
Peak memory	384988 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159141514 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.3159141514 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/36.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/36.kmac_burst_write.3595393953
Short name	T676
Test name
Test status
Simulation time	30613634504 ps
CPU time	994.21 seconds
Started	Sep 09 08:41:01 PM UTC 24
Finished	Sep 09 08:57:47 PM UTC 24
Peak memory	268012 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595393953 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.3595393953 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/36.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/36.kmac_entropy_refresh.2010336025
Short name	T559
Test name
Test status
Simulation time	6200210596 ps
CPU time	227 seconds
Started	Sep 09 08:41:27 PM UTC 24
Finished	Sep 09 08:45:17 PM UTC 24
Peak memory	341808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010336025 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.2010336025 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/36.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/36.kmac_error.1998250486
Short name	T593
Test name
Test status
Simulation time	10805415364 ps
CPU time	369.37 seconds
Started	Sep 09 08:41:34 PM UTC 24
Finished	Sep 09 08:47:49 PM UTC 24
Peak memory	507644 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998250486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.1998250486 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/36.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/36.kmac_key_error.1510144576
Short name	T518
Test name
Test status
Simulation time	7231134058 ps
CPU time	16.35 seconds
Started	Sep 09 08:41:48 PM UTC 24
Finished	Sep 09 08:42:06 PM UTC 24
Peak memory	230444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510144576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.1510144576 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/36.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/36.kmac_lc_escalation.3807225620
Short name	T73
Test name
Test status
Simulation time	30381478 ps
CPU time	1.82 seconds
Started	Sep 09 08:41:50 PM UTC 24
Finished	Sep 09 08:41:53 PM UTC 24
Peak memory	229684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807225620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.3807225620 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/36.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/36.kmac_long_msg_and_output.1542627333
Short name	T705
Test name
Test status
Simulation time	747102889226 ps
CPU time	1751.34 seconds
Started	Sep 09 08:40:49 PM UTC 24
Finished	Sep 09 09:10:22 PM UTC 24
Peak memory	2006800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542627333 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_and_output.1542627333 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/36.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/36.kmac_sideload.1652289190
Short name	T522
Test name
Test status
Simulation time	6330727195 ps
CPU time	94.95 seconds
Started	Sep 09 08:41:00 PM UTC 24
Finished	Sep 09 08:42:37 PM UTC 24
Peak memory	302888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652289190 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.1652289190 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/36.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/36.kmac_smoke.3749565568
Short name	T512
Test name
Test status
Simulation time	2734326137 ps
CPU time	23.18 seconds
Started	Sep 09 08:40:35 PM UTC 24
Finished	Sep 09 08:41:00 PM UTC 24
Peak memory	232580 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749565568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.3749565568 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/36.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/36.kmac_stress_all.2803748587
Short name	T648
Test name
Test status
Simulation time	8894261091 ps
CPU time	655.25 seconds
Started	Sep 09 08:41:54 PM UTC 24
Finished	Sep 09 08:52:58 PM UTC 24
Peak memory	585956 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803748587 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.2803748587 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/36.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/37.kmac_alert_test.1122394164
Short name	T531
Test name
Test status
Simulation time	44250464 ps
CPU time	1.11 seconds
Started	Sep 09 08:42:48 PM UTC 24
Finished	Sep 09 08:42:50 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122394164 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.1122394164 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/37.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/37.kmac_app.2517143139
Short name	T577
Test name
Test status
Simulation time	9058028147 ps
CPU time	233.03 seconds
Started	Sep 09 08:42:38 PM UTC 24
Finished	Sep 09 08:46:35 PM UTC 24
Peak memory	454444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517143139 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.2517143139 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/37.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/37.kmac_burst_write.358122673
Short name	T621
Test name
Test status
Simulation time	17915509651 ps
CPU time	476.31 seconds
Started	Sep 09 08:42:38 PM UTC 24
Finished	Sep 09 08:50:40 PM UTC 24
Peak memory	253740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358122673 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.358122673 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/37.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/37.kmac_entropy_refresh.2483276063
Short name	T536
Test name
Test status
Simulation time	933149142 ps
CPU time	41.2 seconds
Started	Sep 09 08:42:39 PM UTC 24
Finished	Sep 09 08:43:22 PM UTC 24
Peak memory	239328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483276063 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.2483276063 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/37.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/37.kmac_error.1234528925
Short name	T567
Test name
Test status
Simulation time	8331644351 ps
CPU time	185.24 seconds
Started	Sep 09 08:42:45 PM UTC 24
Finished	Sep 09 08:45:54 PM UTC 24
Peak memory	302900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234528925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.1234528925 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/37.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/37.kmac_key_error.2147008799
Short name	T532
Test name
Test status
Simulation time	647045764 ps
CPU time	4.18 seconds
Started	Sep 09 08:42:46 PM UTC 24
Finished	Sep 09 08:42:52 PM UTC 24
Peak memory	230324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147008799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.2147008799 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/37.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/37.kmac_lc_escalation.2465482737
Short name	T90
Test name
Test status
Simulation time	1126961301 ps
CPU time	37.6 seconds
Started	Sep 09 08:42:46 PM UTC 24
Finished	Sep 09 08:43:26 PM UTC 24
Peak memory	249648 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465482737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.2465482737 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/37.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/37.kmac_long_msg_and_output.827686098
Short name	T702
Test name
Test status
Simulation time	225460741815 ps
CPU time	1500.7 seconds
Started	Sep 09 08:42:21 PM UTC 24
Finished	Sep 09 09:07:40 PM UTC 24
Peak memory	2041652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827686098 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_and_output.827686098 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/37.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/37.kmac_sideload.1766740090
Short name	T526
Test name
Test status
Simulation time	369961627 ps
CPU time	13.17 seconds
Started	Sep 09 08:42:31 PM UTC 24
Finished	Sep 09 08:42:45 PM UTC 24
Peak memory	232580 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766740090 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.1766740090 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/37.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/37.kmac_smoke.2037097292
Short name	T520
Test name
Test status
Simulation time	118144042 ps
CPU time	8.77 seconds
Started	Sep 09 08:42:10 PM UTC 24
Finished	Sep 09 08:42:19 PM UTC 24
Peak memory	230572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037097292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.2037097292 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/37.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/37.kmac_stress_all.2774713065
Short name	T685
Test name
Test status
Simulation time	13901778964 ps
CPU time	1012.68 seconds
Started	Sep 09 08:42:46 PM UTC 24
Finished	Sep 09 08:59:52 PM UTC 24
Peak memory	639048 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774713065 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.2774713065 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/37.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/38.kmac_alert_test.4140813608
Short name	T542
Test name
Test status
Simulation time	232315979 ps
CPU time	1.23 seconds
Started	Sep 09 08:43:33 PM UTC 24
Finished	Sep 09 08:43:35 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140813608 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.4140813608 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/38.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/38.kmac_app.2677811147
Short name	T546
Test name
Test status
Simulation time	4200620644 ps
CPU time	33.47 seconds
Started	Sep 09 08:43:21 PM UTC 24
Finished	Sep 09 08:43:56 PM UTC 24
Peak memory	247852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677811147 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.2677811147 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/38.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/38.kmac_burst_write.4055031538
Short name	T619
Test name
Test status
Simulation time	17213341944 ps
CPU time	430.85 seconds
Started	Sep 09 08:43:21 PM UTC 24
Finished	Sep 09 08:50:38 PM UTC 24
Peak memory	243476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055031538 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.4055031538 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/38.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/38.kmac_entropy_refresh.2942967764
Short name	T598
Test name
Test status
Simulation time	46187461897 ps
CPU time	318.38 seconds
Started	Sep 09 08:43:22 PM UTC 24
Finished	Sep 09 08:48:45 PM UTC 24
Peak memory	485244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942967764 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.2942967764 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/38.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/38.kmac_error.1993094291
Short name	T538
Test name
Test status
Simulation time	129494699 ps
CPU time	6.73 seconds
Started	Sep 09 08:43:23 PM UTC 24
Finished	Sep 09 08:43:31 PM UTC 24
Peak memory	234828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993094291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.1993094291 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/38.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/38.kmac_key_error.2923015802
Short name	T537
Test name
Test status
Simulation time	109001543 ps
CPU time	2.22 seconds
Started	Sep 09 08:43:26 PM UTC 24
Finished	Sep 09 08:43:30 PM UTC 24
Peak memory	230448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923015802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.2923015802 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/38.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/38.kmac_lc_escalation.1319769270
Short name	T540
Test name
Test status
Simulation time	50678811 ps
CPU time	2.06 seconds
Started	Sep 09 08:43:30 PM UTC 24
Finished	Sep 09 08:43:34 PM UTC 24
Peak memory	230368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319769270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.1319769270 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/38.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/38.kmac_long_msg_and_output.2162366908
Short name	T718
Test name
Test status
Simulation time	290207134497 ps
CPU time	3373.7 seconds
Started	Sep 09 08:42:51 PM UTC 24
Finished	Sep 09 09:39:43 PM UTC 24
Peak memory	3622856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162366908 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_and_output.2162366908 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/38.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/38.kmac_sideload.592614352
Short name	T554
Test name
Test status
Simulation time	7970959777 ps
CPU time	115.28 seconds
Started	Sep 09 08:42:53 PM UTC 24
Finished	Sep 09 08:44:50 PM UTC 24
Peak memory	325616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592614352 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.592614352 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/38.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/38.kmac_smoke.1549763341
Short name	T539
Test name
Test status
Simulation time	7212980177 ps
CPU time	39.98 seconds
Started	Sep 09 08:42:50 PM UTC 24
Finished	Sep 09 08:43:31 PM UTC 24
Peak memory	235228 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549763341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.1549763341 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/38.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/38.kmac_stress_all.1807954646
Short name	T688
Test name
Test status
Simulation time	198774877891 ps
CPU time	1076.9 seconds
Started	Sep 09 08:43:32 PM UTC 24
Finished	Sep 09 09:01:43 PM UTC 24
Peak memory	1543920 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807954646 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.1807954646 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/38.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/39.kmac_alert_test.3512142652
Short name	T550
Test name
Test status
Simulation time	18587746 ps
CPU time	1.22 seconds
Started	Sep 09 08:44:09 PM UTC 24
Finished	Sep 09 08:44:11 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512142652 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.3512142652 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/39.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/39.kmac_app.2619676090
Short name	T552
Test name
Test status
Simulation time	2411038411 ps
CPU time	39.42 seconds
Started	Sep 09 08:43:52 PM UTC 24
Finished	Sep 09 08:44:33 PM UTC 24
Peak memory	239360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619676090 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.2619676090 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/39.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/39.kmac_burst_write.1462422749
Short name	T679
Test name
Test status
Simulation time	95990100896 ps
CPU time	880.8 seconds
Started	Sep 09 08:43:43 PM UTC 24
Finished	Sep 09 08:58:34 PM UTC 24
Peak memory	266024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462422749 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.1462422749 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/39.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/39.kmac_entropy_refresh.4277668466
Short name	T601
Test name
Test status
Simulation time	67996929024 ps
CPU time	314.95 seconds
Started	Sep 09 08:43:56 PM UTC 24
Finished	Sep 09 08:49:15 PM UTC 24
Peak memory	466756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277668466 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.4277668466 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/39.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/39.kmac_error.1160411914
Short name	T611
Test name
Test status
Simulation time	29292736460 ps
CPU time	359.15 seconds
Started	Sep 09 08:43:57 PM UTC 24
Finished	Sep 09 08:50:02 PM UTC 24
Peak memory	505784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160411914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.1160411914 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/39.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/39.kmac_key_error.266329609
Short name	T549
Test name
Test status
Simulation time	7070849649 ps
CPU time	4.67 seconds
Started	Sep 09 08:43:59 PM UTC 24
Finished	Sep 09 08:44:05 PM UTC 24
Peak memory	230396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266329609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.266329609 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/39.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/39.kmac_lc_escalation.3524929254
Short name	T56
Test name
Test status
Simulation time	43697415 ps
CPU time	1.95 seconds
Started	Sep 09 08:44:04 PM UTC 24
Finished	Sep 09 08:44:07 PM UTC 24
Peak memory	231796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524929254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.3524929254 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/39.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/39.kmac_long_msg_and_output.1295195499
Short name	T669
Test name
Test status
Simulation time	47693099665 ps
CPU time	694.57 seconds
Started	Sep 09 08:43:35 PM UTC 24
Finished	Sep 09 08:55:18 PM UTC 24
Peak memory	1113876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295195499 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_and_output.1295195499 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/39.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/39.kmac_sideload.2141133945
Short name	T585
Test name
Test status
Simulation time	15465574099 ps
CPU time	219.77 seconds
Started	Sep 09 08:43:36 PM UTC 24
Finished	Sep 09 08:47:19 PM UTC 24
Peak memory	425848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141133945 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.2141133945 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/39.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/39.kmac_smoke.1620617535
Short name	T548
Test name
Test status
Simulation time	2368505536 ps
CPU time	27.25 seconds
Started	Sep 09 08:43:35 PM UTC 24
Finished	Sep 09 08:44:03 PM UTC 24
Peak memory	234696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620617535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.1620617535 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/39.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/39.kmac_stress_all.1884995081
Short name	T571
Test name
Test status
Simulation time	5834656970 ps
CPU time	121.9 seconds
Started	Sep 09 08:44:06 PM UTC 24
Finished	Sep 09 08:46:10 PM UTC 24
Peak memory	270456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884995081 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.1884995081 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/39.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/4.kmac_alert_test.2757361817
Short name	T192
Test name
Test status
Simulation time	34066754 ps
CPU time	1.29 seconds
Started	Sep 09 08:03:44 PM UTC 24
Finished	Sep 09 08:03:47 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757361817 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.2757361817 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/4.kmac_app.1484697665
Short name	T195
Test name
Test status
Simulation time	2809133667 ps
CPU time	118.06 seconds
Started	Sep 09 08:02:37 PM UTC 24
Finished	Sep 09 08:04:37 PM UTC 24
Peak memory	270308 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484697665 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.1484697665 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/4.kmac_app_with_partial_data.3014005976
Short name	T210
Test name
Test status
Simulation time	31637228446 ps
CPU time	368.85 seconds
Started	Sep 09 08:02:37 PM UTC 24
Finished	Sep 09 08:08:51 PM UTC 24
Peak memory	476912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014005976 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.3014005976 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_app_with_partial_data/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/4.kmac_burst_write.943610623
Short name	T261
Test name
Test status
Simulation time	64925943103 ps
CPU time	814.59 seconds
Started	Sep 09 08:01:17 PM UTC 24
Finished	Sep 09 08:15:02 PM UTC 24
Peak memory	258100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943610623 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.943610623 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/4.kmac_edn_timeout_error.1038369036
Short name	T188
Test name
Test status
Simulation time	349952786 ps
CPU time	10.97 seconds
Started	Sep 09 08:02:46 PM UTC 24
Finished	Sep 09 08:02:58 PM UTC 24
Peak memory	230268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038369036 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.1038369036 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_mode_error.876394284
Short name	T189
Test name
Test status
Simulation time	1473805416 ps
CPU time	19.91 seconds
Started	Sep 09 08:02:52 PM UTC 24
Finished	Sep 09 08:03:14 PM UTC 24
Peak memory	230336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876394284 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.876394284 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_ready_error.61642481
Short name	T191
Test name
Test status
Simulation time	8489513340 ps
CPU time	43.83 seconds
Started	Sep 09 08:02:59 PM UTC 24
Finished	Sep 09 08:03:45 PM UTC 24
Peak memory	230580 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61642481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_un masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.61642481 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_entropy_ready_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_refresh.1221452314
Short name	T30
Test name
Test status
Simulation time	31054557586 ps
CPU time	281.57 seconds
Started	Sep 09 08:02:37 PM UTC 24
Finished	Sep 09 08:07:23 PM UTC 24
Peak memory	331564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221452314 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.1221452314 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/4.kmac_key_error.2952118661
Short name	T60
Test name
Test status
Simulation time	1610939732 ps
CPU time	4.99 seconds
Started	Sep 09 08:02:45 PM UTC 24
Finished	Sep 09 08:02:51 PM UTC 24
Peak memory	232444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952118661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.2952118661 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/4.kmac_lc_escalation.3786472202
Short name	T35
Test name
Test status
Simulation time	93413146 ps
CPU time	1.66 seconds
Started	Sep 09 08:03:15 PM UTC 24
Finished	Sep 09 08:03:17 PM UTC 24
Peak memory	229676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786472202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.3786472202 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/4.kmac_long_msg_and_output.3238431969
Short name	T351
Test name
Test status
Simulation time	13210942708 ps
CPU time	1270.51 seconds
Started	Sep 09 08:01:09 PM UTC 24
Finished	Sep 09 08:22:35 PM UTC 24
Peak memory	1011696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238431969 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and_output.3238431969 +enable_mas king=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/4.kmac_mubi.3297294749
Short name	T78
Test name
Test status
Simulation time	9320092536 ps
CPU time	73.12 seconds
Started	Sep 09 08:02:39 PM UTC 24
Finished	Sep 09 08:03:54 PM UTC 24
Peak memory	280632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297294749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.3297294749 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/4.kmac_sec_cm.2350489974
Short name	T67
Test name
Test status
Simulation time	5574221210 ps
CPU time	44.09 seconds
Started	Sep 09 08:03:42 PM UTC 24
Finished	Sep 09 08:04:28 PM UTC 24
Peak memory	275056 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350489974 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.2350489974 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/4.kmac_sideload.716396023
Short name	T190
Test name
Test status
Simulation time	2174878236 ps
CPU time	149.25 seconds
Started	Sep 09 08:01:12 PM UTC 24
Finished	Sep 09 08:03:44 PM UTC 24
Peak memory	294632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716396023 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.716396023 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/4.kmac_smoke.4188946915
Short name	T182
Test name
Test status
Simulation time	110327871 ps
CPU time	7.59 seconds
Started	Sep 09 08:01:07 PM UTC 24
Finished	Sep 09 08:01:16 PM UTC 24
Peak memory	230668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188946915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.4188946915 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/4.kmac_stress_all.3954098155
Short name	T131
Test name
Test status
Simulation time	17390096499 ps
CPU time	474.65 seconds
Started	Sep 09 08:03:18 PM UTC 24
Finished	Sep 09 08:11:19 PM UTC 24
Peak memory	384888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954098155 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.3954098155 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac.2212078590
Short name	T186
Test name
Test status
Simulation time	86734646 ps
CPU time	2.72 seconds
Started	Sep 09 08:02:35 PM UTC 24
Finished	Sep 09 08:02:39 PM UTC 24
Peak memory	230600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212078590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac.2212078590 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_test_vectors_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac_xof.2365148333
Short name	T187
Test name
Test status
Simulation time	124149043 ps
CPU time	2.75 seconds
Started	Sep 09 08:02:36 PM UTC 24
Finished	Sep 09 08:02:39 PM UTC 24
Peak memory	230604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365148333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac_xof.2365148333 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_test_vectors_kmac_xof/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_224.3769871785
Short name	T524
Test name
Test status
Simulation time	315144659933 ps
CPU time	2434.86 seconds
Started	Sep 09 08:01:36 PM UTC 24
Finished	Sep 09 08:42:38 PM UTC 24
Peak memory	3133076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769871785 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.3769871785 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_224/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_256.3096015654
Short name	T474
Test name
Test status
Simulation time	167911459321 ps
CPU time	2151.38 seconds
Started	Sep 09 08:01:40 PM UTC 24
Finished	Sep 09 08:37:54 PM UTC 24
Peak memory	3047064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096015654 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.3096015654 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_256/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_384.2674566930
Short name	T185
Test name
Test status
Simulation time	6121574480 ps
CPU time	43.11 seconds
Started	Sep 09 08:01:45 PM UTC 24
Finished	Sep 09 08:02:29 PM UTC 24
Peak memory	239372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674566930 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.2674566930 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_384/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_512.3514662811
Short name	T275
Test name
Test status
Simulation time	18173546534 ps
CPU time	847.94 seconds
Started	Sep 09 08:01:52 PM UTC 24
Finished	Sep 09 08:16:10 PM UTC 24
Peak memory	722584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514662811 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.3514662811 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_512/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_128.3333794910
Short name	T196
Test name
Test status
Simulation time	4728351539 ps
CPU time	165.14 seconds
Started	Sep 09 08:02:05 PM UTC 24
Finished	Sep 09 08:04:53 PM UTC 24
Peak memory	286544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333794910 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.3333794 910 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_test_vectors_shake_128/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_256.3720232555
Short name	T513
Test name
Test status
Simulation time	1082942103012 ps
CPU time	2321.86 seconds
Started	Sep 09 08:02:12 PM UTC 24
Finished	Sep 09 08:41:19 PM UTC 24
Peak memory	2999956 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720232555 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.3720232 555 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/4.kmac_test_vectors_shake_256/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/40.kmac_alert_test.2797882639
Short name	T562
Test name
Test status
Simulation time	36397528 ps
CPU time	0.96 seconds
Started	Sep 09 08:45:21 PM UTC 24
Finished	Sep 09 08:45:23 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797882639 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.2797882639 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/40.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/40.kmac_app.2716913924
Short name	T590
Test name
Test status
Simulation time	19798663603 ps
CPU time	167.06 seconds
Started	Sep 09 08:44:51 PM UTC 24
Finished	Sep 09 08:47:41 PM UTC 24
Peak memory	335600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716913924 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.2716913924 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/40.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/40.kmac_burst_write.2201969414
Short name	T612
Test name
Test status
Simulation time	48518267610 ps
CPU time	323.47 seconds
Started	Sep 09 08:44:50 PM UTC 24
Finished	Sep 09 08:50:18 PM UTC 24
Peak memory	251680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201969414 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.2201969414 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/40.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/40.kmac_entropy_refresh.1337863159
Short name	T600
Test name
Test status
Simulation time	26044561918 ps
CPU time	243.97 seconds
Started	Sep 09 08:45:00 PM UTC 24
Finished	Sep 09 08:49:08 PM UTC 24
Peak memory	395060 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337863159 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.1337863159 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/40.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/40.kmac_error.2433308182
Short name	T597
Test name
Test status
Simulation time	2291523390 ps
CPU time	189.27 seconds
Started	Sep 09 08:45:05 PM UTC 24
Finished	Sep 09 08:48:17 PM UTC 24
Peak memory	317228 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433308182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.2433308182 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/40.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/40.kmac_key_error.2549239460
Short name	T558
Test name
Test status
Simulation time	639951501 ps
CPU time	3 seconds
Started	Sep 09 08:45:12 PM UTC 24
Finished	Sep 09 08:45:16 PM UTC 24
Peak memory	230328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549239460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.2549239460 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/40.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/40.kmac_lc_escalation.2117818510
Short name	T560
Test name
Test status
Simulation time	40145863 ps
CPU time	1.98 seconds
Started	Sep 09 08:45:17 PM UTC 24
Finished	Sep 09 08:45:20 PM UTC 24
Peak memory	229728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117818510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.2117818510 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/40.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/40.kmac_long_msg_and_output.3149630220
Short name	T686
Test name
Test status
Simulation time	44546490352 ps
CPU time	973.13 seconds
Started	Sep 09 08:44:27 PM UTC 24
Finished	Sep 09 09:00:52 PM UTC 24
Peak memory	909108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149630220 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_and_output.3149630220 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/40.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/40.kmac_sideload.3858269054
Short name	T578
Test name
Test status
Simulation time	4065543345 ps
CPU time	122.42 seconds
Started	Sep 09 08:44:34 PM UTC 24
Finished	Sep 09 08:46:39 PM UTC 24
Peak memory	335920 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858269054 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.3858269054 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/40.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/40.kmac_smoke.1048881781
Short name	T561
Test name
Test status
Simulation time	5164710861 ps
CPU time	69.04 seconds
Started	Sep 09 08:44:12 PM UTC 24
Finished	Sep 09 08:45:23 PM UTC 24
Peak memory	234620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048881781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.1048881781 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/40.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/40.kmac_stress_all.3123586766
Short name	T713
Test name
Test status
Simulation time	651137089278 ps
CPU time	2214.59 seconds
Started	Sep 09 08:45:18 PM UTC 24
Finished	Sep 09 09:22:38 PM UTC 24
Peak memory	1175624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123586766 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.3123586766 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/40.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/41.kmac_alert_test.3997346582
Short name	T573
Test name
Test status
Simulation time	20366165 ps
CPU time	1.2 seconds
Started	Sep 09 08:46:11 PM UTC 24
Finished	Sep 09 08:46:14 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997346582 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.3997346582 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/41.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/41.kmac_app.2371630361
Short name	T631
Test name
Test status
Simulation time	42842647424 ps
CPU time	376.41 seconds
Started	Sep 09 08:45:34 PM UTC 24
Finished	Sep 09 08:51:56 PM UTC 24
Peak memory	485172 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371630361 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.2371630361 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/41.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/41.kmac_burst_write.2003927627
Short name	T683
Test name
Test status
Simulation time	27103413150 ps
CPU time	830.83 seconds
Started	Sep 09 08:45:30 PM UTC 24
Finished	Sep 09 08:59:31 PM UTC 24
Peak memory	260068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003927627 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.2003927627 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/41.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/41.kmac_entropy_refresh.200366154
Short name	T604
Test name
Test status
Simulation time	44728441171 ps
CPU time	235.6 seconds
Started	Sep 09 08:45:43 PM UTC 24
Finished	Sep 09 08:49:42 PM UTC 24
Peak memory	448560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200366154 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.200366154 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/41.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/41.kmac_error.3140388130
Short name	T620
Test name
Test status
Simulation time	42834640200 ps
CPU time	278.96 seconds
Started	Sep 09 08:45:55 PM UTC 24
Finished	Sep 09 08:50:38 PM UTC 24
Peak memory	468716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140388130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.3140388130 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/41.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/41.kmac_key_error.3610918259
Short name	T572
Test name
Test status
Simulation time	2934842892 ps
CPU time	12.73 seconds
Started	Sep 09 08:45:56 PM UTC 24
Finished	Sep 09 08:46:10 PM UTC 24
Peak memory	230476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610918259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.3610918259 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/41.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/41.kmac_lc_escalation.3277344298
Short name	T576
Test name
Test status
Simulation time	1065230658 ps
CPU time	22.36 seconds
Started	Sep 09 08:46:04 PM UTC 24
Finished	Sep 09 08:46:28 PM UTC 24
Peak memory	245424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277344298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.3277344298 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/41.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/41.kmac_long_msg_and_output.1174222026
Short name	T720
Test name
Test status
Simulation time	364392696376 ps
CPU time	3982.18 seconds
Started	Sep 09 08:45:24 PM UTC 24
Finished	Sep 09 09:52:30 PM UTC 24
Peak memory	4306828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174222026 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_and_output.1174222026 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/41.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/41.kmac_sideload.4211678596
Short name	T579
Test name
Test status
Simulation time	16504285686 ps
CPU time	89.09 seconds
Started	Sep 09 08:45:27 PM UTC 24
Finished	Sep 09 08:46:59 PM UTC 24
Peak memory	302900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211678596 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.4211678596 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/41.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/41.kmac_smoke.1075105254
Short name	T584
Test name
Test status
Simulation time	19864196082 ps
CPU time	111.29 seconds
Started	Sep 09 08:45:23 PM UTC 24
Finished	Sep 09 08:47:17 PM UTC 24
Peak memory	235372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075105254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.1075105254 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/41.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/41.kmac_stress_all.2027652983
Short name	T698
Test name
Test status
Simulation time	69449634019 ps
CPU time	1112.95 seconds
Started	Sep 09 08:46:07 PM UTC 24
Finished	Sep 09 09:04:55 PM UTC 24
Peak memory	991028 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027652983 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.2027652983 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/41.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/42.kmac_alert_test.475028360
Short name	T583
Test name
Test status
Simulation time	43754814 ps
CPU time	1.19 seconds
Started	Sep 09 08:47:12 PM UTC 24
Finished	Sep 09 08:47:15 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475028360 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.475028360 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/42.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/42.kmac_app.322990247
Short name	T625
Test name
Test status
Simulation time	8656955696 ps
CPU time	284.14 seconds
Started	Sep 09 08:46:29 PM UTC 24
Finished	Sep 09 08:51:19 PM UTC 24
Peak memory	433952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322990247 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.322990247 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/42.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/42.kmac_burst_write.4206044197
Short name	T629
Test name
Test status
Simulation time	13045451855 ps
CPU time	316.77 seconds
Started	Sep 09 08:46:22 PM UTC 24
Finished	Sep 09 08:51:44 PM UTC 24
Peak memory	241384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206044197 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.4206044197 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/42.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/42.kmac_entropy_refresh.3205357798
Short name	T635
Test name
Test status
Simulation time	46217625903 ps
CPU time	325.29 seconds
Started	Sep 09 08:46:36 PM UTC 24
Finished	Sep 09 08:52:06 PM UTC 24
Peak memory	481060 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205357798 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.3205357798 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/42.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/42.kmac_error.3854760800
Short name	T651
Test name
Test status
Simulation time	31361282123 ps
CPU time	387.93 seconds
Started	Sep 09 08:46:40 PM UTC 24
Finished	Sep 09 08:53:13 PM UTC 24
Peak memory	552732 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854760800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.3854760800 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/42.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/42.kmac_key_error.3069284180
Short name	T580
Test name
Test status
Simulation time	209924647 ps
CPU time	3.1 seconds
Started	Sep 09 08:47:00 PM UTC 24
Finished	Sep 09 08:47:04 PM UTC 24
Peak memory	230328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069284180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.3069284180 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/42.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/42.kmac_lc_escalation.887655877
Short name	T581
Test name
Test status
Simulation time	353030702 ps
CPU time	1.93 seconds
Started	Sep 09 08:47:05 PM UTC 24
Finished	Sep 09 08:47:08 PM UTC 24
Peak memory	229868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887655877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.887655877 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/42.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/42.kmac_long_msg_and_output.2266831263
Short name	T691
Test name
Test status
Simulation time	100047040928 ps
CPU time	937.98 seconds
Started	Sep 09 08:46:15 PM UTC 24
Finished	Sep 09 09:02:06 PM UTC 24
Peak memory	1359784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266831263 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_and_output.2266831263 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/42.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/42.kmac_sideload.1314814801
Short name	T628
Test name
Test status
Simulation time	3597288186 ps
CPU time	305.52 seconds
Started	Sep 09 08:46:21 PM UTC 24
Finished	Sep 09 08:51:31 PM UTC 24
Peak memory	364596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314814801 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.1314814801 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/42.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/42.kmac_smoke.3790994115
Short name	T574
Test name
Test status
Simulation time	368009749 ps
CPU time	6.51 seconds
Started	Sep 09 08:46:12 PM UTC 24
Finished	Sep 09 08:46:20 PM UTC 24
Peak memory	230600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790994115 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.3790994115 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/42.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/42.kmac_stress_all.4020531767
Short name	T696
Test name
Test status
Simulation time	24221962191 ps
CPU time	935.12 seconds
Started	Sep 09 08:47:09 PM UTC 24
Finished	Sep 09 09:02:56 PM UTC 24
Peak memory	639092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020531767 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.4020531767 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/42.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/43.kmac_alert_test.3166777202
Short name	T595
Test name
Test status
Simulation time	18616072 ps
CPU time	1.15 seconds
Started	Sep 09 08:47:50 PM UTC 24
Finished	Sep 09 08:47:52 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166777202 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.3166777202 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/43.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/43.kmac_app.325697311
Short name	T640
Test name
Test status
Simulation time	15665054674 ps
CPU time	284.1 seconds
Started	Sep 09 08:47:30 PM UTC 24
Finished	Sep 09 08:52:18 PM UTC 24
Peak memory	536284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325697311 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.325697311 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/43.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/43.kmac_burst_write.521748739
Short name	T689
Test name
Test status
Simulation time	223888995136 ps
CPU time	847.64 seconds
Started	Sep 09 08:47:28 PM UTC 24
Finished	Sep 09 09:01:47 PM UTC 24
Peak memory	257808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521748739 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.521748739 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/43.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/43.kmac_entropy_refresh.1754366536
Short name	T632
Test name
Test status
Simulation time	10139531525 ps
CPU time	255.75 seconds
Started	Sep 09 08:47:40 PM UTC 24
Finished	Sep 09 08:52:00 PM UTC 24
Peak memory	405296 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754366536 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.1754366536 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/43.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/43.kmac_error.2453298171
Short name	T650
Test name
Test status
Simulation time	16204389811 ps
CPU time	317.42 seconds
Started	Sep 09 08:47:43 PM UTC 24
Finished	Sep 09 08:53:05 PM UTC 24
Peak memory	378728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453298171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.2453298171 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/43.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/43.kmac_key_error.1799904548
Short name	T591
Test name
Test status
Simulation time	588245787 ps
CPU time	4.04 seconds
Started	Sep 09 08:47:43 PM UTC 24
Finished	Sep 09 08:47:48 PM UTC 24
Peak memory	230336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799904548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.1799904548 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/43.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/43.kmac_lc_escalation.3371404960
Short name	T594
Test name
Test status
Simulation time	43598362 ps
CPU time	1.41 seconds
Started	Sep 09 08:47:49 PM UTC 24
Finished	Sep 09 08:47:51 PM UTC 24
Peak memory	229728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371404960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.3371404960 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/43.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/43.kmac_long_msg_and_output.3905579914
Short name	T588
Test name
Test status
Simulation time	1085945393 ps
CPU time	20.6 seconds
Started	Sep 09 08:47:18 PM UTC 24
Finished	Sep 09 08:47:40 PM UTC 24
Peak memory	251816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905579914 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_and_output.3905579914 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/43.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/43.kmac_sideload.4208281676
Short name	T587
Test name
Test status
Simulation time	336360136 ps
CPU time	8.34 seconds
Started	Sep 09 08:47:20 PM UTC 24
Finished	Sep 09 08:47:29 PM UTC 24
Peak memory	232596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208281676 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.4208281676 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/43.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/43.kmac_smoke.2449171475
Short name	T586
Test name
Test status
Simulation time	810281203 ps
CPU time	10.83 seconds
Started	Sep 09 08:47:16 PM UTC 24
Finished	Sep 09 08:47:27 PM UTC 24
Peak memory	230800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449171475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.2449171475 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/43.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/43.kmac_stress_all.530284628
Short name	T682
Test name
Test status
Simulation time	45406491076 ps
CPU time	668.41 seconds
Started	Sep 09 08:47:50 PM UTC 24
Finished	Sep 09 08:59:07 PM UTC 24
Peak memory	381040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530284628 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.530284628 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/43.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/44.kmac_alert_test.1859968036
Short name	T606
Test name
Test status
Simulation time	26616988 ps
CPU time	1.2 seconds
Started	Sep 09 08:49:43 PM UTC 24
Finished	Sep 09 08:49:46 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859968036 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.1859968036 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/44.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/44.kmac_app.4234752226
Short name	T663
Test name
Test status
Simulation time	4674780850 ps
CPU time	321.33 seconds
Started	Sep 09 08:48:46 PM UTC 24
Finished	Sep 09 08:54:12 PM UTC 24
Peak memory	329848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234752226 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.4234752226 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/44.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/44.kmac_entropy_refresh.4285999697
Short name	T605
Test name
Test status
Simulation time	3054558924 ps
CPU time	52.33 seconds
Started	Sep 09 08:48:50 PM UTC 24
Finished	Sep 09 08:49:44 PM UTC 24
Peak memory	268144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285999697 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.4285999697 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/44.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/44.kmac_error.628169596
Short name	T613
Test name
Test status
Simulation time	7940285657 ps
CPU time	74.45 seconds
Started	Sep 09 08:49:10 PM UTC 24
Finished	Sep 09 08:50:26 PM UTC 24
Peak memory	278452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628169596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.628169596 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/44.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/44.kmac_key_error.2760508649
Short name	T603
Test name
Test status
Simulation time	1173335257 ps
CPU time	12.96 seconds
Started	Sep 09 08:49:17 PM UTC 24
Finished	Sep 09 08:49:31 PM UTC 24
Peak memory	230652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760508649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.2760508649 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/44.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/44.kmac_lc_escalation.1388701161
Short name	T609
Test name
Test status
Simulation time	3595252528 ps
CPU time	25.82 seconds
Started	Sep 09 08:49:28 PM UTC 24
Finished	Sep 09 08:49:55 PM UTC 24
Peak memory	253740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388701161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.1388701161 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/44.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/44.kmac_long_msg_and_output.4163966630
Short name	T712
Test name
Test status
Simulation time	41511488809 ps
CPU time	2027.52 seconds
Started	Sep 09 08:47:53 PM UTC 24
Finished	Sep 09 09:22:04 PM UTC 24
Peak memory	1539808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163966630 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_and_output.4163966630 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/44.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/44.kmac_sideload.101869757
Short name	T660
Test name
Test status
Simulation time	36870978932 ps
CPU time	347.71 seconds
Started	Sep 09 08:48:07 PM UTC 24
Finished	Sep 09 08:54:00 PM UTC 24
Peak memory	374632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101869757 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.101869757 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/44.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/44.kmac_smoke.2772912097
Short name	T596
Test name
Test status
Simulation time	1341857579 ps
CPU time	11.44 seconds
Started	Sep 09 08:47:52 PM UTC 24
Finished	Sep 09 08:48:05 PM UTC 24
Peak memory	230596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772912097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.2772912097 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/44.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/44.kmac_stress_all.3646985038
Short name	T710
Test name
Test status
Simulation time	96792900124 ps
CPU time	1708.17 seconds
Started	Sep 09 08:49:32 PM UTC 24
Finished	Sep 09 09:18:20 PM UTC 24
Peak memory	1425464 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646985038 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.3646985038 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/44.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/45.kmac_alert_test.581500895
Short name	T616
Test name
Test status
Simulation time	50383414 ps
CPU time	1.25 seconds
Started	Sep 09 08:50:31 PM UTC 24
Finished	Sep 09 08:50:33 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581500895 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.581500895 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/45.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/45.kmac_app.3226405101
Short name	T618
Test name
Test status
Simulation time	1044652946 ps
CPU time	39.98 seconds
Started	Sep 09 08:49:56 PM UTC 24
Finished	Sep 09 08:50:38 PM UTC 24
Peak memory	251628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226405101 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.3226405101 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/45.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/45.kmac_burst_write.1146629040
Short name	T687
Test name
Test status
Simulation time	29205233806 ps
CPU time	682.12 seconds
Started	Sep 09 08:49:49 PM UTC 24
Finished	Sep 09 09:01:20 PM UTC 24
Peak memory	247596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146629040 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.1146629040 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/45.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/45.kmac_entropy_refresh.3519733362
Short name	T644
Test name
Test status
Simulation time	39505332414 ps
CPU time	167.55 seconds
Started	Sep 09 08:49:58 PM UTC 24
Finished	Sep 09 08:52:49 PM UTC 24
Peak memory	337912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519733362 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.3519733362 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/45.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/45.kmac_error.3050023736
Short name	T617
Test name
Test status
Simulation time	1360298736 ps
CPU time	30.73 seconds
Started	Sep 09 08:50:02 PM UTC 24
Finished	Sep 09 08:50:35 PM UTC 24
Peak memory	261888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050023736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.3050023736 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/45.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/45.kmac_key_error.1509681890
Short name	T614
Test name
Test status
Simulation time	1724208612 ps
CPU time	7.68 seconds
Started	Sep 09 08:50:19 PM UTC 24
Finished	Sep 09 08:50:27 PM UTC 24
Peak memory	230388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509681890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.1509681890 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/45.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/45.kmac_long_msg_and_output.3036840346
Short name	T707
Test name
Test status
Simulation time	28566688597 ps
CPU time	1233.37 seconds
Started	Sep 09 08:49:47 PM UTC 24
Finished	Sep 09 09:10:34 PM UTC 24
Peak memory	1078996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036840346 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_and_output.3036840346 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/45.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/45.kmac_sideload.3413080576
Short name	T615
Test name
Test status
Simulation time	2441689303 ps
CPU time	42.96 seconds
Started	Sep 09 08:49:48 PM UTC 24
Finished	Sep 09 08:50:32 PM UTC 24
Peak memory	247872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413080576 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.3413080576 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/45.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/45.kmac_smoke.3860175699
Short name	T608
Test name
Test status
Simulation time	58070318 ps
CPU time	1.73 seconds
Started	Sep 09 08:49:45 PM UTC 24
Finished	Sep 09 08:49:48 PM UTC 24
Peak memory	229684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860175699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.3860175699 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/45.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/45.kmac_stress_all.145791077
Short name	T717
Test name
Test status
Simulation time	180126701106 ps
CPU time	2387.89 seconds
Started	Sep 09 08:50:28 PM UTC 24
Finished	Sep 09 09:30:44 PM UTC 24
Peak memory	1429504 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145791077 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.145791077 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/45.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/46.kmac_alert_test.2444086422
Short name	T627
Test name
Test status
Simulation time	26793434 ps
CPU time	1.16 seconds
Started	Sep 09 08:51:20 PM UTC 24
Finished	Sep 09 08:51:23 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444086422 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.2444086422 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/46.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/46.kmac_app.3654078900
Short name	T641
Test name
Test status
Simulation time	4600372539 ps
CPU time	115.02 seconds
Started	Sep 09 08:50:39 PM UTC 24
Finished	Sep 09 08:52:36 PM UTC 24
Peak memory	325684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654078900 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.3654078900 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/46.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/46.kmac_burst_write.448376245
Short name	T692
Test name
Test status
Simulation time	29001095929 ps
CPU time	678.09 seconds
Started	Sep 09 08:50:39 PM UTC 24
Finished	Sep 09 09:02:06 PM UTC 24
Peak memory	249628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448376245 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.448376245 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/46.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/46.kmac_entropy_refresh.327487926
Short name	T653
Test name
Test status
Simulation time	15043485472 ps
CPU time	153.15 seconds
Started	Sep 09 08:50:39 PM UTC 24
Finished	Sep 09 08:53:15 PM UTC 24
Peak memory	347892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327487926 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.327487926 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/46.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/46.kmac_error.176247879
Short name	T630
Test name
Test status
Simulation time	2520077017 ps
CPU time	70.93 seconds
Started	Sep 09 08:50:41 PM UTC 24
Finished	Sep 09 08:51:54 PM UTC 24
Peak memory	300784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176247879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.176247879 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/46.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/46.kmac_key_error.254336908
Short name	T626
Test name
Test status
Simulation time	4053626352 ps
CPU time	13.84 seconds
Started	Sep 09 08:51:05 PM UTC 24
Finished	Sep 09 08:51:20 PM UTC 24
Peak memory	230456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254336908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.254336908 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/46.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/46.kmac_lc_escalation.1418137067
Short name	T624
Test name
Test status
Simulation time	146550122 ps
CPU time	2.07 seconds
Started	Sep 09 08:51:12 PM UTC 24
Finished	Sep 09 08:51:16 PM UTC 24
Peak memory	232432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418137067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.1418137067 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/46.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/46.kmac_long_msg_and_output.976827671
Short name	T666
Test name
Test status
Simulation time	30828782862 ps
CPU time	229.8 seconds
Started	Sep 09 08:50:34 PM UTC 24
Finished	Sep 09 08:54:29 PM UTC 24
Peak memory	475180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976827671 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_and_output.976827671 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/46.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/46.kmac_sideload.2975683528
Short name	T655
Test name
Test status
Simulation time	7388383950 ps
CPU time	159.53 seconds
Started	Sep 09 08:50:36 PM UTC 24
Finished	Sep 09 08:53:18 PM UTC 24
Peak memory	339884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975683528 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.2975683528 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/46.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/46.kmac_smoke.366508204
Short name	T622
Test name
Test status
Simulation time	460773575 ps
CPU time	29.91 seconds
Started	Sep 09 08:50:33 PM UTC 24
Finished	Sep 09 08:51:04 PM UTC 24
Peak memory	230788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366508204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.366508204 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/46.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/46.kmac_stress_all.2343318056
Short name	T677
Test name
Test status
Simulation time	67544740332 ps
CPU time	397.93 seconds
Started	Sep 09 08:51:17 PM UTC 24
Finished	Sep 09 08:58:01 PM UTC 24
Peak memory	395320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343318056 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.2343318056 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/46.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/47.kmac_alert_test.2581763678
Short name	T639
Test name
Test status
Simulation time	117892246 ps
CPU time	1.21 seconds
Started	Sep 09 08:52:08 PM UTC 24
Finished	Sep 09 08:52:10 PM UTC 24
Peak memory	216232 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581763678 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.2581763678 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/47.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/47.kmac_app.584297494
Short name	T634
Test name
Test status
Simulation time	520230522 ps
CPU time	9.49 seconds
Started	Sep 09 08:51:55 PM UTC 24
Finished	Sep 09 08:52:05 PM UTC 24
Peak memory	232708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584297494 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.584297494 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/47.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/47.kmac_burst_write.1986401678
Short name	T672
Test name
Test status
Simulation time	18491219771 ps
CPU time	257.8 seconds
Started	Sep 09 08:51:45 PM UTC 24
Finished	Sep 09 08:56:06 PM UTC 24
Peak memory	239532 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986401678 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.1986401678 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/47.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/47.kmac_entropy_refresh.399614719
Short name	T643
Test name
Test status
Simulation time	1084108593 ps
CPU time	44.12 seconds
Started	Sep 09 08:51:57 PM UTC 24
Finished	Sep 09 08:52:43 PM UTC 24
Peak memory	239528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399614719 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.399614719 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/47.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/47.kmac_error.1668038549
Short name	T673
Test name
Test status
Simulation time	8357090961 ps
CPU time	277.22 seconds
Started	Sep 09 08:52:01 PM UTC 24
Finished	Sep 09 08:56:42 PM UTC 24
Peak memory	370424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668038549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.1668038549 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/47.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/47.kmac_key_error.3327367353
Short name	T637
Test name
Test status
Simulation time	39894864 ps
CPU time	1.52 seconds
Started	Sep 09 08:52:05 PM UTC 24
Finished	Sep 09 08:52:08 PM UTC 24
Peak memory	229860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327367353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.3327367353 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/47.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/47.kmac_lc_escalation.3213572111
Short name	T638
Test name
Test status
Simulation time	50267166 ps
CPU time	1.99 seconds
Started	Sep 09 08:52:07 PM UTC 24
Finished	Sep 09 08:52:10 PM UTC 24
Peak memory	231852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213572111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.3213572111 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/47.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/47.kmac_long_msg_and_output.2620609364
Short name	T642
Test name
Test status
Simulation time	1249436876 ps
CPU time	70.57 seconds
Started	Sep 09 08:51:23 PM UTC 24
Finished	Sep 09 08:52:36 PM UTC 24
Peak memory	272236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620609364 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_and_output.2620609364 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/47.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/47.kmac_sideload.3449094947
Short name	T668
Test name
Test status
Simulation time	38358389828 ps
CPU time	220.48 seconds
Started	Sep 09 08:51:32 PM UTC 24
Finished	Sep 09 08:55:17 PM UTC 24
Peak memory	399152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449094947 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.3449094947 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/47.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/47.kmac_smoke.1643425781
Short name	T633
Test name
Test status
Simulation time	1272012641 ps
CPU time	41.6 seconds
Started	Sep 09 08:51:21 PM UTC 24
Finished	Sep 09 08:52:04 PM UTC 24
Peak memory	230528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643425781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.1643425781 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/47.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/47.kmac_stress_all.3242651439
Short name	T699
Test name
Test status
Simulation time	36483093084 ps
CPU time	821.55 seconds
Started	Sep 09 08:52:07 PM UTC 24
Finished	Sep 09 09:05:58 PM UTC 24
Peak memory	620340 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242651439 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.3242651439 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/47.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/48.kmac_alert_test.2938459197
Short name	T649
Test name
Test status
Simulation time	34529180 ps
CPU time	1.14 seconds
Started	Sep 09 08:52:59 PM UTC 24
Finished	Sep 09 08:53:01 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938459197 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.2938459197 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/48.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/48.kmac_app.1272223396
Short name	T658
Test name
Test status
Simulation time	2765766976 ps
CPU time	73.76 seconds
Started	Sep 09 08:52:38 PM UTC 24
Finished	Sep 09 08:53:53 PM UTC 24
Peak memory	284724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272223396 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.1272223396 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/48.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/48.kmac_burst_write.334840761
Short name	T706
Test name
Test status
Simulation time	136889855402 ps
CPU time	1072.7 seconds
Started	Sep 09 08:52:19 PM UTC 24
Finished	Sep 09 09:10:25 PM UTC 24
Peak memory	272112 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334840761 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.334840761 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/48.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/48.kmac_entropy_refresh.3336532302
Short name	T671
Test name
Test status
Simulation time	11936532226 ps
CPU time	185.38 seconds
Started	Sep 09 08:52:38 PM UTC 24
Finished	Sep 09 08:55:47 PM UTC 24
Peak memory	307056 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336532302 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.3336532302 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/48.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/48.kmac_error.3571838553
Short name	T665
Test name
Test status
Simulation time	10324740196 ps
CPU time	102.39 seconds
Started	Sep 09 08:52:44 PM UTC 24
Finished	Sep 09 08:54:29 PM UTC 24
Peak memory	301084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571838553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.3571838553 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/48.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/48.kmac_key_error.1655048313
Short name	T646
Test name
Test status
Simulation time	484398898 ps
CPU time	4.53 seconds
Started	Sep 09 08:52:49 PM UTC 24
Finished	Sep 09 08:52:55 PM UTC 24
Peak memory	230412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655048313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.1655048313 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/48.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/48.kmac_lc_escalation.2112628132
Short name	T647
Test name
Test status
Simulation time	104989608 ps
CPU time	1.79 seconds
Started	Sep 09 08:52:54 PM UTC 24
Finished	Sep 09 08:52:57 PM UTC 24
Peak memory	229796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112628132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.2112628132 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/48.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/48.kmac_long_msg_and_output.3129285400
Short name	T719
Test name
Test status
Simulation time	683358391215 ps
CPU time	3223.95 seconds
Started	Sep 09 08:52:10 PM UTC 24
Finished	Sep 09 09:46:28 PM UTC 24
Peak memory	3704556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129285400 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_and_output.3129285400 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/48.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/48.kmac_sideload.4021217164
Short name	T670
Test name
Test status
Simulation time	36424047884 ps
CPU time	191.71 seconds
Started	Sep 09 08:52:11 PM UTC 24
Finished	Sep 09 08:55:26 PM UTC 24
Peak memory	307168 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021217164 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.4021217164 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/48.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/48.kmac_smoke.3940852731
Short name	T657
Test name
Test status
Simulation time	9006113887 ps
CPU time	96.23 seconds
Started	Sep 09 08:52:09 PM UTC 24
Finished	Sep 09 08:53:47 PM UTC 24
Peak memory	235172 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940852731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.3940852731 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/48.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/48.kmac_stress_all.3956271960
Short name	T704
Test name
Test status
Simulation time	45867292178 ps
CPU time	954.24 seconds
Started	Sep 09 08:52:56 PM UTC 24
Finished	Sep 09 09:09:02 PM UTC 24
Peak memory	475124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956271960 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.3956271960 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/48.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/49.kmac_alert_test.3141951614
Short name	T659
Test name
Test status
Simulation time	47003966 ps
CPU time	1.17 seconds
Started	Sep 09 08:53:55 PM UTC 24
Finished	Sep 09 08:53:57 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141951614 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.3141951614 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/49.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/49.kmac_app.1639809619
Short name	T684
Test name
Test status
Simulation time	57946368738 ps
CPU time	382.16 seconds
Started	Sep 09 08:53:16 PM UTC 24
Finished	Sep 09 08:59:44 PM UTC 24
Peak memory	540464 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639809619 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.1639809619 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/49.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/49.kmac_burst_write.2559881668
Short name	T700
Test name
Test status
Simulation time	7327166859 ps
CPU time	762.87 seconds
Started	Sep 09 08:53:14 PM UTC 24
Finished	Sep 09 09:06:07 PM UTC 24
Peak memory	249616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559881668 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.2559881668 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/49.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/49.kmac_entropy_refresh.2289612068
Short name	T678
Test name
Test status
Simulation time	162027869657 ps
CPU time	305.33 seconds
Started	Sep 09 08:53:16 PM UTC 24
Finished	Sep 09 08:58:25 PM UTC 24
Peak memory	472884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289612068 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.2289612068 +enable_masking=0 +sw _key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/49.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/49.kmac_error.4194128242
Short name	T675
Test name
Test status
Simulation time	6276208286 ps
CPU time	242.25 seconds
Started	Sep 09 08:53:16 PM UTC 24
Finished	Sep 09 08:57:22 PM UTC 24
Peak memory	343860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194128242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.4194128242 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/49.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/49.kmac_key_error.359879679
Short name	T656
Test name
Test status
Simulation time	1721927558 ps
CPU time	15.81 seconds
Started	Sep 09 08:53:19 PM UTC 24
Finished	Sep 09 08:53:36 PM UTC 24
Peak memory	230644 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359879679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.359879679 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/49.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/49.kmac_lc_escalation.3535535559
Short name	T662
Test name
Test status
Simulation time	3261586750 ps
CPU time	27.87 seconds
Started	Sep 09 08:53:37 PM UTC 24
Finished	Sep 09 08:54:06 PM UTC 24
Peak memory	251616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535535559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.3535535559 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/49.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/49.kmac_long_msg_and_output.695334138
Short name	T709
Test name
Test status
Simulation time	14056321815 ps
CPU time	1355.96 seconds
Started	Sep 09 08:53:02 PM UTC 24
Finished	Sep 09 09:15:54 PM UTC 24
Peak memory	1101540 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695334138 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_and_output.695334138 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/49.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/49.kmac_sideload.1388757638
Short name	T674
Test name
Test status
Simulation time	8162419771 ps
CPU time	224.39 seconds
Started	Sep 09 08:53:06 PM UTC 24
Finished	Sep 09 08:56:54 PM UTC 24
Peak memory	450528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388757638 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.1388757638 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/49.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/49.kmac_smoke.2796875371
Short name	T654
Test name
Test status
Simulation time	2204827911 ps
CPU time	13.97 seconds
Started	Sep 09 08:52:59 PM UTC 24
Finished	Sep 09 08:53:15 PM UTC 24
Peak memory	230528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796875371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.2796875371 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/49.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/49.kmac_stress_all.1108304966
Short name	T667
Test name
Test status
Simulation time	12414826873 ps
CPU time	84.74 seconds
Started	Sep 09 08:53:48 PM UTC 24
Finished	Sep 09 08:55:15 PM UTC 24
Peak memory	272564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108304966 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.1108304966 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/49.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/5.kmac_alert_test.2482291663
Short name	T136
Test name
Test status
Simulation time	22600584 ps
CPU time	1.11 seconds
Started	Sep 09 08:05:02 PM UTC 24
Finished	Sep 09 08:05:04 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482291663 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.2482291663 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/5.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/5.kmac_app.2847018968
Short name	T141
Test name
Test status
Simulation time	2089750731 ps
CPU time	126.79 seconds
Started	Sep 09 08:03:59 PM UTC 24
Finished	Sep 09 08:06:08 PM UTC 24
Peak memory	276220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847018968 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.2847018968 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/5.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/5.kmac_app_with_partial_data.1962438853
Short name	T174
Test name
Test status
Simulation time	7097206286 ps
CPU time	198.1 seconds
Started	Sep 09 08:04:24 PM UTC 24
Finished	Sep 09 08:07:46 PM UTC 24
Peak memory	323368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962438853 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.1962438853 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/5.kmac_app_with_partial_data/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/5.kmac_burst_write.3932423200
Short name	T132
Test name
Test status
Simulation time	73190476865 ps
CPU time	487.73 seconds
Started	Sep 09 08:03:55 PM UTC 24
Finished	Sep 09 08:12:09 PM UTC 24
Peak memory	249580 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932423200 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.3932423200 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/5.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/5.kmac_edn_timeout_error.1831207094
Short name	T139
Test name
Test status
Simulation time	3642420741 ps
CPU time	33.31 seconds
Started	Sep 09 08:04:50 PM UTC 24
Finished	Sep 09 08:05:24 PM UTC 24
Peak memory	235364 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831207094 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.1831207094 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/5.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_mode_error.3248290884
Short name	T137
Test name
Test status
Simulation time	717701244 ps
CPU time	19.77 seconds
Started	Sep 09 08:04:50 PM UTC 24
Finished	Sep 09 08:05:11 PM UTC 24
Peak memory	235376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248290884 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.3248290884 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/5.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_ready_error.179323851
Short name	T138
Test name
Test status
Simulation time	16228250595 ps
CPU time	22.9 seconds
Started	Sep 09 08:04:51 PM UTC 24
Finished	Sep 09 08:05:15 PM UTC 24
Peak memory	230868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179323851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_u nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.179323851 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/5.kmac_entropy_ready_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_refresh.4191037692
Short name	T135
Test name
Test status
Simulation time	1763036537 ps
CPU time	34.88 seconds
Started	Sep 09 08:04:24 PM UTC 24
Finished	Sep 09 08:05:01 PM UTC 24
Peak memory	260000 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191037692 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.4191037692 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/5.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/5.kmac_error.2652629418
Short name	T31
Test name
Test status
Simulation time	13909048953 ps
CPU time	189.47 seconds
Started	Sep 09 08:04:29 PM UTC 24
Finished	Sep 09 08:07:41 PM UTC 24
Peak memory	386856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652629418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.2652629418 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/5.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/5.kmac_key_error.943885841
Short name	T61
Test name
Test status
Simulation time	1713813081 ps
CPU time	16.92 seconds
Started	Sep 09 08:04:32 PM UTC 24
Finished	Sep 09 08:04:50 PM UTC 24
Peak memory	230388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943885841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.943885841 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/5.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/5.kmac_lc_escalation.2226353336
Short name	T7
Test name
Test status
Simulation time	1060802536 ps
CPU time	24.22 seconds
Started	Sep 09 08:04:55 PM UTC 24
Finished	Sep 09 08:05:20 PM UTC 24
Peak memory	249656 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226353336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.2226353336 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/5.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/5.kmac_long_msg_and_output.3402723808
Short name	T333
Test name
Test status
Simulation time	27281857754 ps
CPU time	1020.63 seconds
Started	Sep 09 08:03:47 PM UTC 24
Finished	Sep 09 08:21:00 PM UTC 24
Peak memory	1505052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402723808 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and_output.3402723808 +enable_mas king=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/5.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/5.kmac_mubi.1865610256
Short name	T79
Test name
Test status
Simulation time	7629481174 ps
CPU time	131.56 seconds
Started	Sep 09 08:04:26 PM UTC 24
Finished	Sep 09 08:06:40 PM UTC 24
Peak memory	278592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865610256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.1865610256 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/5.kmac_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/5.kmac_sideload.3661066456
Short name	T197
Test name
Test status
Simulation time	4253134639 ps
CPU time	166.31 seconds
Started	Sep 09 08:03:47 PM UTC 24
Finished	Sep 09 08:06:37 PM UTC 24
Peak memory	339744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661066456 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.3661066456 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/5.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/5.kmac_smoke.2771872800
Short name	T193
Test name
Test status
Simulation time	195680713 ps
CPU time	8.86 seconds
Started	Sep 09 08:03:47 PM UTC 24
Finished	Sep 09 08:03:58 PM UTC 24
Peak memory	232496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771872800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.2771872800 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/5.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/5.kmac_stress_all.1132504003
Short name	T456
Test name
Test status
Simulation time	19339802410 ps
CPU time	1844.99 seconds
Started	Sep 09 08:04:58 PM UTC 24
Finished	Sep 09 08:36:05 PM UTC 24
Peak memory	765952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132504003 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.1132504003 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/5.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/5.kmac_stress_all_with_rand_reset.3719566749
Short name	T114
Test name
Test status
Simulation time	4265943464 ps
CPU time	185.48 seconds
Started	Sep 09 08:04:59 PM UTC 24
Finished	Sep 09 08:08:08 PM UTC 24
Peak memory	313248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3719566749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all_ with_rand_reset.3719566749 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/6.kmac_alert_test.302976221
Short name	T200
Test name
Test status
Simulation time	18941115 ps
CPU time	1.29 seconds
Started	Sep 09 08:06:54 PM UTC 24
Finished	Sep 09 08:06:56 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302976221 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.302976221 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/6.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/6.kmac_app.3266591917
Short name	T211
Test name
Test status
Simulation time	11956626472 ps
CPU time	213.69 seconds
Started	Sep 09 08:05:22 PM UTC 24
Finished	Sep 09 08:08:59 PM UTC 24
Peak memory	374504 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266591917 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.3266591917 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/6.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/6.kmac_app_with_partial_data.515042190
Short name	T199
Test name
Test status
Simulation time	2315396379 ps
CPU time	81.04 seconds
Started	Sep 09 08:05:25 PM UTC 24
Finished	Sep 09 08:06:48 PM UTC 24
Peak memory	255716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515042190 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.515042190 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/6.kmac_app_with_partial_data/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/6.kmac_burst_write.3689004286
Short name	T299
Test name
Test status
Simulation time	88495469168 ps
CPU time	775.58 seconds
Started	Sep 09 08:05:18 PM UTC 24
Finished	Sep 09 08:18:23 PM UTC 24
Peak memory	249644 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689004286 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.3689004286 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/6.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/6.kmac_edn_timeout_error.3595160406
Short name	T198
Test name
Test status
Simulation time	408631380 ps
CPU time	10.82 seconds
Started	Sep 09 08:06:30 PM UTC 24
Finished	Sep 09 08:06:42 PM UTC 24
Peak memory	235024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595160406 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.3595160406 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/6.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_mode_error.55586436
Short name	T201
Test name
Test status
Simulation time	330891768 ps
CPU time	31.01 seconds
Started	Sep 09 08:06:40 PM UTC 24
Finished	Sep 09 08:07:12 PM UTC 24
Peak memory	235088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55586436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.55586436 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/6.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_ready_error.2103217195
Short name	T202
Test name
Test status
Simulation time	2942317679 ps
CPU time	24.38 seconds
Started	Sep 09 08:06:52 PM UTC 24
Finished	Sep 09 08:07:18 PM UTC 24
Peak memory	230588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103217195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.2103217195 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/6.kmac_entropy_ready_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_refresh.967158113
Short name	T216
Test name
Test status
Simulation time	22314459916 ps
CPU time	236.27 seconds
Started	Sep 09 08:05:46 PM UTC 24
Finished	Sep 09 08:09:46 PM UTC 24
Peak memory	423704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967158113 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.967158113 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/6.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/6.kmac_error.3038097196
Short name	T205
Test name
Test status
Simulation time	2763454457 ps
CPU time	109.34 seconds
Started	Sep 09 08:06:21 PM UTC 24
Finished	Sep 09 08:08:13 PM UTC 24
Peak memory	317224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038097196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.3038097196 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/6.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/6.kmac_key_error.2332868369
Short name	T62
Test name
Test status
Simulation time	316134986 ps
CPU time	2.44 seconds
Started	Sep 09 08:06:26 PM UTC 24
Finished	Sep 09 08:06:30 PM UTC 24
Peak memory	230340 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332868369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.2332868369 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/6.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/6.kmac_lc_escalation.3519490199
Short name	T36
Test name
Test status
Simulation time	179271731 ps
CPU time	4.97 seconds
Started	Sep 09 08:06:52 PM UTC 24
Finished	Sep 09 08:06:59 PM UTC 24
Peak memory	235152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519490199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.3519490199 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/6.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/6.kmac_long_msg_and_output.1985342553
Short name	T480
Test name
Test status
Simulation time	36528186482 ps
CPU time	1960.52 seconds
Started	Sep 09 08:05:16 PM UTC 24
Finished	Sep 09 08:38:20 PM UTC 24
Peak memory	1379924 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985342553 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and_output.1985342553 +enable_mas king=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/6.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/6.kmac_mubi.1373438841
Short name	T81
Test name
Test status
Simulation time	9009038424 ps
CPU time	216.48 seconds
Started	Sep 09 08:06:09 PM UTC 24
Finished	Sep 09 08:09:49 PM UTC 24
Peak memory	329972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373438841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.1373438841 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/6.kmac_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/6.kmac_sideload.737523647
Short name	T142
Test name
Test status
Simulation time	8156827774 ps
CPU time	61.57 seconds
Started	Sep 09 08:05:17 PM UTC 24
Finished	Sep 09 08:06:21 PM UTC 24
Peak memory	286500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737523647 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.737523647 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/6.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/6.kmac_smoke.3030628833
Short name	T140
Test name
Test status
Simulation time	1125182830 ps
CPU time	27.43 seconds
Started	Sep 09 08:05:16 PM UTC 24
Finished	Sep 09 08:05:45 PM UTC 24
Peak memory	230136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030628833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.3030628833 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/6.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/6.kmac_stress_all.1580544258
Short name	T130
Test name
Test status
Simulation time	54037186468 ps
CPU time	259.17 seconds
Started	Sep 09 08:06:53 PM UTC 24
Finished	Sep 09 08:11:16 PM UTC 24
Peak memory	344364 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580544258 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.1580544258 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/6.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/6.kmac_stress_all_with_rand_reset.9562727
Short name	T80
Test name
Test status
Simulation time	10003778029 ps
CPU time	86.95 seconds
Started	Sep 09 08:06:54 PM UTC 24
Finished	Sep 09 08:08:23 PM UTC 24
Peak memory	278708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=9562727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all_wit h_rand_reset.9562727 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/7.kmac_alert_test.804212030
Short name	T206
Test name
Test status
Simulation time	45559370 ps
CPU time	1.21 seconds
Started	Sep 09 08:08:14 PM UTC 24
Finished	Sep 09 08:08:17 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804212030 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.804212030 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/7.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/7.kmac_app.50459841
Short name	T214
Test name
Test status
Simulation time	11985109307 ps
CPU time	142.22 seconds
Started	Sep 09 08:07:09 PM UTC 24
Finished	Sep 09 08:09:34 PM UTC 24
Peak memory	292576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50459841 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.50459841 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/7.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/7.kmac_app_with_partial_data.1093853620
Short name	T225
Test name
Test status
Simulation time	8414462587 ps
CPU time	213.25 seconds
Started	Sep 09 08:07:14 PM UTC 24
Finished	Sep 09 08:10:51 PM UTC 24
Peak memory	419804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093853620 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.1093853620 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/7.kmac_app_with_partial_data/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/7.kmac_edn_timeout_error.214815241
Short name	T204
Test name
Test status
Simulation time	692260834 ps
CPU time	24.65 seconds
Started	Sep 09 08:07:42 PM UTC 24
Finished	Sep 09 08:08:08 PM UTC 24
Peak memory	235248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214815241 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.214815241 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/7.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_mode_error.633193101
Short name	T209
Test name
Test status
Simulation time	22615831763 ps
CPU time	54.85 seconds
Started	Sep 09 08:07:47 PM UTC 24
Finished	Sep 09 08:08:43 PM UTC 24
Peak memory	235136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633193101 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.633193101 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/7.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_ready_error.1219457171
Short name	T208
Test name
Test status
Simulation time	5883682164 ps
CPU time	49.09 seconds
Started	Sep 09 08:07:50 PM UTC 24
Finished	Sep 09 08:08:41 PM UTC 24
Peak memory	230772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219457171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.1219457171 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/7.kmac_entropy_ready_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_refresh.1840264595
Short name	T226
Test name
Test status
Simulation time	10475883541 ps
CPU time	214.43 seconds
Started	Sep 09 08:07:14 PM UTC 24
Finished	Sep 09 08:10:52 PM UTC 24
Peak memory	389228 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840264595 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.1840264595 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/7.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/7.kmac_error.1622500175
Short name	T147
Test name
Test status
Simulation time	49929840739 ps
CPU time	412.88 seconds
Started	Sep 09 08:07:24 PM UTC 24
Finished	Sep 09 08:14:22 PM UTC 24
Peak memory	548652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622500175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.1622500175 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/7.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/7.kmac_key_error.226585435
Short name	T63
Test name
Test status
Simulation time	2679868442 ps
CPU time	9.61 seconds
Started	Sep 09 08:07:41 PM UTC 24
Finished	Sep 09 08:07:52 PM UTC 24
Peak memory	232440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226585435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.226585435 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/7.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/7.kmac_lc_escalation.1213690602
Short name	T207
Test name
Test status
Simulation time	921053486 ps
CPU time	31.03 seconds
Started	Sep 09 08:07:52 PM UTC 24
Finished	Sep 09 08:08:24 PM UTC 24
Peak memory	255776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213690602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.1213690602 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/7.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/7.kmac_long_msg_and_output.1264910860
Short name	T534
Test name
Test status
Simulation time	498388508159 ps
CPU time	2156.85 seconds
Started	Sep 09 08:07:00 PM UTC 24
Finished	Sep 09 08:43:20 PM UTC 24
Peak memory	2781044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264910860 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_and_output.1264910860 +enable_mas king=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/7.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/7.kmac_mubi.3122120403
Short name	T231
Test name
Test status
Simulation time	46823291295 ps
CPU time	265.57 seconds
Started	Sep 09 08:07:20 PM UTC 24
Finished	Sep 09 08:11:49 PM UTC 24
Peak memory	444484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122120403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.3122120403 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/7.kmac_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/7.kmac_sideload.4095322580
Short name	T203
Test name
Test status
Simulation time	3404980988 ps
CPU time	48.06 seconds
Started	Sep 09 08:07:00 PM UTC 24
Finished	Sep 09 08:07:49 PM UTC 24
Peak memory	262128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095322580 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.4095322580 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/7.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/7.kmac_smoke.3985955070
Short name	T173
Test name
Test status
Simulation time	7477735758 ps
CPU time	43.97 seconds
Started	Sep 09 08:06:55 PM UTC 24
Finished	Sep 09 08:07:40 PM UTC 24
Peak memory	235420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985955070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.3985955070 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/7.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/7.kmac_stress_all.599681275
Short name	T267
Test name
Test status
Simulation time	19086520139 ps
CPU time	428.48 seconds
Started	Sep 09 08:08:08 PM UTC 24
Finished	Sep 09 08:15:22 PM UTC 24
Peak memory	446692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599681275 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.599681275 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/7.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/8.kmac_alert_test.447067466
Short name	T217
Test name
Test status
Simulation time	89008833 ps
CPU time	0.98 seconds
Started	Sep 09 08:09:47 PM UTC 24
Finished	Sep 09 08:09:49 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447067466 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.447067466 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/8.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/8.kmac_app.3554969682
Short name	T243
Test name
Test status
Simulation time	10097031551 ps
CPU time	299.83 seconds
Started	Sep 09 08:08:30 PM UTC 24
Finished	Sep 09 08:13:34 PM UTC 24
Peak memory	337640 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554969682 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.3554969682 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/8.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/8.kmac_app_with_partial_data.2604136172
Short name	T219
Test name
Test status
Simulation time	12567657452 ps
CPU time	93.47 seconds
Started	Sep 09 08:08:42 PM UTC 24
Finished	Sep 09 08:10:17 PM UTC 24
Peak memory	263976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604136172 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.2604136172 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/8.kmac_app_with_partial_data/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/8.kmac_burst_write.61094297
Short name	T129
Test name
Test status
Simulation time	6824992576 ps
CPU time	132.18 seconds
Started	Sep 09 08:08:27 PM UTC 24
Finished	Sep 09 08:10:41 PM UTC 24
Peak memory	237552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61094297 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.61094297 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/8.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/8.kmac_edn_timeout_error.3583061367
Short name	T213
Test name
Test status
Simulation time	439400289 ps
CPU time	13.21 seconds
Started	Sep 09 08:09:13 PM UTC 24
Finished	Sep 09 08:09:28 PM UTC 24
Peak memory	234976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583061367 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.3583061367 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/8.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_mode_error.198348754
Short name	T220
Test name
Test status
Simulation time	8815247780 ps
CPU time	49.96 seconds
Started	Sep 09 08:09:28 PM UTC 24
Finished	Sep 09 08:10:20 PM UTC 24
Peak memory	235236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198348754 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.198348754 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/8.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_ready_error.69543424
Short name	T218
Test name
Test status
Simulation time	2142608915 ps
CPU time	30.57 seconds
Started	Sep 09 08:09:31 PM UTC 24
Finished	Sep 09 08:10:03 PM UTC 24
Peak memory	230516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69543424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_un masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.69543424 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/8.kmac_entropy_ready_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_refresh.51804636
Short name	T144
Test name
Test status
Simulation time	85911540300 ps
CPU time	437.05 seconds
Started	Sep 09 08:08:44 PM UTC 24
Finished	Sep 09 08:16:07 PM UTC 24
Peak memory	544524 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51804636 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.51804636 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/8.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/8.kmac_error.3551620808
Short name	T252
Test name
Test status
Simulation time	3265086851 ps
CPU time	298.23 seconds
Started	Sep 09 08:09:00 PM UTC 24
Finished	Sep 09 08:14:03 PM UTC 24
Peak memory	341912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551620808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.3551620808 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/8.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/8.kmac_key_error.1055341762
Short name	T64
Test name
Test status
Simulation time	3588636248 ps
CPU time	6.26 seconds
Started	Sep 09 08:09:05 PM UTC 24
Finished	Sep 09 08:09:13 PM UTC 24
Peak memory	232660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055341762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.1055341762 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/8.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/8.kmac_lc_escalation.1478872669
Short name	T37
Test name
Test status
Simulation time	123132403 ps
CPU time	1.96 seconds
Started	Sep 09 08:09:35 PM UTC 24
Finished	Sep 09 08:09:38 PM UTC 24
Peak memory	229676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478872669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.1478872669 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/8.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/8.kmac_long_msg_and_output.2396006287
Short name	T582
Test name
Test status
Simulation time	47340552157 ps
CPU time	2303.17 seconds
Started	Sep 09 08:08:24 PM UTC 24
Finished	Sep 09 08:47:11 PM UTC 24
Peak memory	1670992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396006287 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_and_output.2396006287 +enable_mas king=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/8.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/8.kmac_mubi.707005702
Short name	T82
Test name
Test status
Simulation time	5628338238 ps
CPU time	100.33 seconds
Started	Sep 09 08:08:52 PM UTC 24
Finished	Sep 09 08:10:34 PM UTC 24
Peak memory	309296 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707005702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.707005702 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/8.kmac_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/8.kmac_sideload.185078178
Short name	T242
Test name
Test status
Simulation time	46443464219 ps
CPU time	296.19 seconds
Started	Sep 09 08:08:26 PM UTC 24
Finished	Sep 09 08:13:26 PM UTC 24
Peak memory	462652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185078178 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.185078178 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/8.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/8.kmac_smoke.1865384871
Short name	T212
Test name
Test status
Simulation time	6065594545 ps
CPU time	45.02 seconds
Started	Sep 09 08:08:17 PM UTC 24
Finished	Sep 09 08:09:04 PM UTC 24
Peak memory	234684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865384871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.1865384871 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/8.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/8.kmac_stress_all.4235150656
Short name	T393
Test name
Test status
Simulation time	14106278881 ps
CPU time	1100.45 seconds
Started	Sep 09 08:09:37 PM UTC 24
Finished	Sep 09 08:28:10 PM UTC 24
Peak memory	677716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235150656 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.4235150656 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/8.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/8.kmac_stress_all_with_rand_reset.955498074
Short name	T46
Test name
Test status
Simulation time	9217899354 ps
CPU time	274.71 seconds
Started	Sep 09 08:09:39 PM UTC 24
Finished	Sep 09 08:14:18 PM UTC 24
Peak memory	294820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=955498074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all_w ith_rand_reset.955498074 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/9.kmac_alert_test.4079641365
Short name	T227
Test name
Test status
Simulation time	20519220 ps
CPU time	1.3 seconds
Started	Sep 09 08:11:04 PM UTC 24
Finished	Sep 09 08:11:06 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079641365 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.4079641365 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/9.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/9.kmac_app.2694276020
Short name	T253
Test name
Test status
Simulation time	10057423723 ps
CPU time	237.39 seconds
Started	Sep 09 08:10:18 PM UTC 24
Finished	Sep 09 08:14:19 PM UTC 24
Peak memory	403444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694276020 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.2694276020 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/9.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/9.kmac_app_with_partial_data.4228931151
Short name	T237
Test name
Test status
Simulation time	5305746104 ps
CPU time	117.36 seconds
Started	Sep 09 08:10:21 PM UTC 24
Finished	Sep 09 08:12:21 PM UTC 24
Peak memory	282352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228931151 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.4228931151 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/9.kmac_app_with_partial_data/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/9.kmac_burst_write.685303940
Short name	T292
Test name
Test status
Simulation time	13889376828 ps
CPU time	443.13 seconds
Started	Sep 09 08:10:05 PM UTC 24
Finished	Sep 09 08:17:35 PM UTC 24
Peak memory	249584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685303940 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.685303940 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/9.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/9.kmac_edn_timeout_error.142819475
Short name	T228
Test name
Test status
Simulation time	316556358 ps
CPU time	24.14 seconds
Started	Sep 09 08:10:44 PM UTC 24
Finished	Sep 09 08:11:09 PM UTC 24
Peak memory	235044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142819475 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.142819475 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/9.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_mode_error.1601729777
Short name	T229
Test name
Test status
Simulation time	1316051404 ps
CPU time	35.24 seconds
Started	Sep 09 08:10:44 PM UTC 24
Finished	Sep 09 08:11:20 PM UTC 24
Peak memory	232592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601729777 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.1601729777 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/9.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_ready_error.3469124097
Short name	T230
Test name
Test status
Simulation time	5024179131 ps
CPU time	42.34 seconds
Started	Sep 09 08:10:50 PM UTC 24
Finished	Sep 09 08:11:34 PM UTC 24
Peak memory	230580 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469124097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.3469124097 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/9.kmac_entropy_ready_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_refresh.1091665051
Short name	T222
Test name
Test status
Simulation time	584828098 ps
CPU time	6.06 seconds
Started	Sep 09 08:10:35 PM UTC 24
Finished	Sep 09 08:10:42 PM UTC 24
Peak memory	234640 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091665051 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.1091665051 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/9.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/9.kmac_error.3520187900
Short name	T273
Test name
Test status
Simulation time	47015802830 ps
CPU time	301.61 seconds
Started	Sep 09 08:10:43 PM UTC 24
Finished	Sep 09 08:15:49 PM UTC 24
Peak memory	346080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520187900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.3520187900 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/9.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/9.kmac_key_error.3806456118
Short name	T65
Test name
Test status
Simulation time	1787508181 ps
CPU time	3.87 seconds
Started	Sep 09 08:10:44 PM UTC 24
Finished	Sep 09 08:10:49 PM UTC 24
Peak memory	230548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806456118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.3806456118 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/9.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/9.kmac_lc_escalation.2559266803
Short name	T91
Test name
Test status
Simulation time	176497817 ps
CPU time	1.52 seconds
Started	Sep 09 08:10:52 PM UTC 24
Finished	Sep 09 08:10:54 PM UTC 24
Peak memory	229680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559266803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.2559266803 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/9.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/9.kmac_long_msg_and_output.2122524109
Short name	T289
Test name
Test status
Simulation time	4424533787 ps
CPU time	451.18 seconds
Started	Sep 09 08:09:50 PM UTC 24
Finished	Sep 09 08:17:27 PM UTC 24
Peak memory	497456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122524109 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and_output.2122524109 +enable_mas king=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/9.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/9.kmac_mubi.696804610
Short name	T251
Test name
Test status
Simulation time	14734014619 ps
CPU time	191.2 seconds
Started	Sep 09 08:10:41 PM UTC 24
Finished	Sep 09 08:13:56 PM UTC 24
Peak memory	362540 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696804610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.696804610 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/9.kmac_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/9.kmac_sideload.1543085758
Short name	T223
Test name
Test status
Simulation time	3580484031 ps
CPU time	37.1 seconds
Started	Sep 09 08:10:04 PM UTC 24
Finished	Sep 09 08:10:43 PM UTC 24
Peak memory	249624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543085758 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.1543085758 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/9.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/9.kmac_smoke.1216204830
Short name	T224
Test name
Test status
Simulation time	2412531134 ps
CPU time	51.46 seconds
Started	Sep 09 08:09:50 PM UTC 24
Finished	Sep 09 08:10:43 PM UTC 24
Peak memory	235484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216204830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.1216204830 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/9.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default/9.kmac_stress_all.1908588942
Short name	T463
Test name
Test status
Simulation time	372604862029 ps
CPU time	1539.33 seconds
Started	Sep 09 08:10:53 PM UTC 24
Finished	Sep 09 08:36:50 PM UTC 24
Peak memory	1241268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908588942 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.1908588942 +enable_masking=0 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/9.kmac_stress_all/latest