Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	17558533	1			T1	284		T2	149		T3	118
all_values[1]	17558533	1			T1	284		T2	149		T3	118
all_values[2]	17558533	1			T1	284		T2	149		T3	118

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

537508

1

T1

26

T2

81

T3

62

auto[1]

52138091

1

T1

826

T2

366

T3

292

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52444599

1

T1

744

T2

435

T3

342

auto[1]

231000

1

T1

108

T2

12

T3

12

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	188152	1			T1	9		T2	4		T77	1
all_values[0]	auto[0]	auto[1]	1430	1			T1	4		T2	2		T77	2
all_values[0]	auto[1]	auto[0]	17293381	1			T1	239		T2	141		T3	114
all_values[0]	auto[1]	auto[1]	75570	1			T1	32		T2	2		T3	4
all_values[1]	auto[0]	auto[0]	174269	1			T2	72		T12	4		T16	224
all_values[1]	auto[0]	auto[1]	1031	1			T2	3		T12	3		T16	2
all_values[1]	auto[1]	auto[0]	17307264	1			T1	248		T2	73		T3	114
all_values[1]	auto[1]	auto[1]	75969	1			T1	36		T2	1		T3	4
all_values[2]	auto[0]	auto[0]	171649	1			T1	9		T3	60		T13	7
all_values[2]	auto[0]	auto[1]	977	1			T1	4		T3	2		T13	4
all_values[2]	auto[1]	auto[0]	17309884	1			T1	239		T2	145		T3	54
all_values[2]	auto[1]	auto[1]	76023	1			T1	32		T2	4		T3	2