Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
59754 |
1 |
|
|
T1 |
50 |
|
T2 |
6 |
|
T3 |
2 |
auto[1] |
57490 |
1 |
|
|
T3 |
4 |
|
T12 |
208 |
|
T16 |
76 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
29311 |
1 |
|
|
T1 |
10 |
|
T2 |
2 |
|
T3 |
2 |
lower_val |
28988 |
1 |
|
|
T1 |
14 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
930 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
58868 |
1 |
|
|
T1 |
24 |
|
T2 |
4 |
|
T3 |
4 |
lower_val |
58372 |
1 |
|
|
T1 |
26 |
|
T2 |
2 |
|
T3 |
2 |
zero_val |
4 |
1 |
|
|
T152 |
2 |
|
T153 |
2 |
|
- |
- |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
6 |
12 |
66.67 |
6 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
* |
[zero_val] |
* |
-- |
-- |
6 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
7486 |
1 |
|
|
T1 |
7 |
|
T2 |
1 |
|
T12 |
1 |
higher_val |
higher_val |
auto[1] |
7249 |
1 |
|
|
T3 |
1 |
|
T12 |
23 |
|
T16 |
13 |
higher_val |
lower_val |
auto[0] |
7378 |
1 |
|
|
T1 |
3 |
|
T2 |
1 |
|
T13 |
29 |
higher_val |
lower_val |
auto[1] |
7198 |
1 |
|
|
T3 |
1 |
|
T12 |
36 |
|
T16 |
16 |
lower_val |
higher_val |
auto[0] |
7318 |
1 |
|
|
T1 |
5 |
|
T2 |
1 |
|
T13 |
40 |
lower_val |
higher_val |
auto[1] |
7215 |
1 |
|
|
T12 |
21 |
|
T16 |
8 |
|
T18 |
29 |
lower_val |
lower_val |
auto[0] |
7443 |
1 |
|
|
T1 |
9 |
|
T13 |
34 |
|
T16 |
1 |
lower_val |
lower_val |
auto[1] |
7012 |
1 |
|
|
T3 |
1 |
|
T12 |
21 |
|
T16 |
11 |
zero_val |
higher_val |
auto[0] |
390 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
higher_val |
auto[1] |
87 |
1 |
|
|
T18 |
1 |
|
T48 |
1 |
|
T59 |
3 |
zero_val |
lower_val |
auto[0] |
344 |
1 |
|
|
T13 |
1 |
|
T4 |
1 |
|
T16 |
1 |
zero_val |
lower_val |
auto[1] |
109 |
1 |
|
|
T18 |
1 |
|
T48 |
1 |
|
T83 |
2 |