Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	17558533	1			T1	284		T2	149		T3	118
all_pins[1]	17558533	1			T1	284		T2	149		T3	118
all_pins[2]	17558533	1			T1	284		T2	149		T3	118

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	52310986	1			T1	820		T2	445		T3	350
values[0x1]	364613	1			T1	32		T2	2		T3	4
transitions[0x0=>0x1]	362760	1			T1	32		T2	2		T3	4
transitions[0x1=>0x0]	362784	1			T1	32		T2	2		T3	4

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	17482963	1			T1	252		T2	147		T3	114
all_pins[0]	values[0x1]	75570	1			T1	32		T2	2		T3	4
all_pins[0]	transitions[0x0=>0x1]	75558	1			T1	32		T2	2		T3	4
all_pins[0]	transitions[0x1=>0x0]	71	1			T164	6		T165	2		T166	7
all_pins[1]	values[0x0]	17558450	1			T1	284		T2	149		T3	118
all_pins[1]	values[0x1]	83	1			T164	6		T165	2		T166	7
all_pins[1]	transitions[0x0=>0x1]	70	1			T164	6		T165	2		T166	7
all_pins[1]	transitions[0x1=>0x0]	288947	1			T16	3951		T49	484		T33	769
all_pins[2]	values[0x0]	17269573	1			T1	284		T2	149		T3	118
all_pins[2]	values[0x1]	288960	1			T16	3951		T49	484		T33	769
all_pins[2]	transitions[0x0=>0x1]	287132	1			T16	3925		T49	484		T33	769
all_pins[2]	transitions[0x1=>0x0]	73766	1			T1	32		T2	2		T3	4