Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	668	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5729	1			T16	2		T47	3		T29	3
len_601_800	13306	1			T16	14		T47	5		T29	9
len_401_600	8785	1			T16	5		T29	2		T22	14
len_201_400	4437	1			T16	3		T47	2		T29	1
len_65_200	7747	1			T1	12		T16	2		T48	85
len_min_for_xof_require_squeeze	91	1			T48	1		T185	9		T186	1
len_keccak_block_sizes[72]	65	1			T185	9		T182	2		T187	9
len_keccak_block_sizes[104]	77	1			T48	1		T185	9		T182	2
len_keccak_block_sizes[136]	79	1			T48	1		T185	9		T182	2
len_keccak_block_sizes[144]	40	1			T188	5		T144	1		T189	1
len_keccak_block_sizes[168]	47	1			T1	1		T29	1		T190	1
len_datapath_width	1061	1			T2	3		T3	3		T48	5
len_2_63	15799	1			T1	13		T12	105		T13	145
len_1	48	1			T48	4		T182	1		T186	2