Group : kmac_env_pkg::kmac_env_cov::sideload_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : kmac_env_pkg::kmac_env_cov::sideload_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv


Summary for Group kmac_env_pkg::kmac_env_cov::sideload_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::sideload_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
in_app_keymgr 2 0 2 100.00 100 1 1 2
kmac_mode 2 0 2 100.00 100 1 1 2
sideload 2 0 2 100.00 100 1 1 2


Crosses for Group kmac_env_pkg::kmac_env_cov::sideload_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sideload_cross 4 0 4 100.00 100 1 1 0


Summary for Variable in_app_keymgr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for in_app_keymgr

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 61659 1 T1 24 T2 3 T3 3
auto[1] 3699 1 T14 1 T4 1 T16 4


Summary for Variable kmac_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for kmac_mode

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 27734 1 T1 8 T12 104 T13 139
auto[1] 37624 1 T1 16 T2 3 T3 3


Summary for Variable sideload

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sideload

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 50892 1 T1 24 T2 3 T3 3
auto[1] 14466 1 T14 1 T4 1 T16 9


Summary for Cross sideload_cross

Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
User Defined Cross Bins 4 0 4 100.00


User Defined Cross Bins for sideload_cross

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
sw_kmac_valid_sideload 14466 1 T14 1 T4 1 T16 9
sw_kmac_invalid_sideload 50892 1 T1 24 T2 3 T3 3
app_valid_sideload 14466 1 T14 1 T4 1 T16 9
app_invalid_sideload 50892 1 T1 24 T2 3 T3 3