Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 272 1 T122 7 T124 7 T158 4
all_values[1] 272 1 T122 7 T124 7 T158 4
all_values[2] 272 1 T122 7 T124 7 T158 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 435 1 T122 13 T124 18 T158 4
auto[1] 381 1 T122 8 T124 3 T158 8


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 372 1 T122 11 T124 8 T158 4
auto[1] 444 1 T122 10 T124 13 T158 8


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 483 1 T122 12 T124 12 T158 6
auto[1] 333 1 T122 9 T124 9 T158 6


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 59 1 T122 4 T124 2 T159 2
all_values[0] auto[0] auto[0] auto[1] 25 1 T124 1 T158 1 T160 2
all_values[0] auto[0] auto[1] auto[0] 57 1 T122 2 T124 1 T158 1
all_values[0] auto[0] auto[1] auto[1] 28 1 T124 1 T161 2 T159 1
all_values[0] auto[1] auto[0] auto[1] 56 1 T124 2 T158 1 T161 2
all_values[0] auto[1] auto[1] auto[1] 47 1 T122 1 T158 1 T162 2
all_values[1] auto[0] auto[0] auto[0] 83 1 T122 3 T124 3 T161 2
all_values[1] auto[0] auto[1] auto[0] 77 1 T158 2 T161 1 T159 1
all_values[1] auto[1] auto[0] auto[1] 67 1 T122 1 T124 4 T158 2
all_values[1] auto[1] auto[1] auto[1] 45 1 T122 3 T159 1 T163 2
all_values[2] auto[0] auto[0] auto[0] 60 1 T122 2 T124 1 T161 1
all_values[2] auto[0] auto[0] auto[1] 20 1 T124 2 T161 1 T159 1
all_values[2] auto[0] auto[1] auto[0] 36 1 T124 1 T158 1 T159 1
all_values[2] auto[0] auto[1] auto[1] 38 1 T122 1 T158 1 T159 1
all_values[2] auto[1] auto[0] auto[1] 65 1 T122 3 T124 3 T161 2
all_values[2] auto[1] auto[1] auto[1] 53 1 T122 1 T158 2 T159 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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