| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 92.27 | 95.89 | 92.30 | 100.00 | 68.60 | 94.11 | 98.84 | 96.15 |
| T769 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.345684028 | Sep 11 01:55:46 PM UTC 24 | Sep 11 01:55:50 PM UTC 24 | 124670809 ps | ||
| T168 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.3139916362 | Sep 11 01:55:46 PM UTC 24 | Sep 11 01:55:51 PM UTC 24 | 435357088 ps | ||
| T770 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.2719732011 | Sep 11 01:55:48 PM UTC 24 | Sep 11 01:55:52 PM UTC 24 | 134337668 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.296299069 | Sep 11 01:55:49 PM UTC 24 | Sep 11 01:55:52 PM UTC 24 | 28829368 ps | ||
| T771 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.2600420027 | Sep 11 01:55:50 PM UTC 24 | Sep 11 01:55:53 PM UTC 24 | 18064593 ps | ||
| T772 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.797074176 | Sep 11 01:55:24 PM UTC 24 | Sep 11 01:55:53 PM UTC 24 | 3567449378 ps | ||
| T773 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.342344448 | Sep 11 01:55:49 PM UTC 24 | Sep 11 01:55:53 PM UTC 24 | 58539061 ps | ||
| T774 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.3166560408 | Sep 11 01:55:50 PM UTC 24 | Sep 11 01:55:53 PM UTC 24 | 19265123 ps | ||
| T775 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3453005677 | Sep 11 01:55:47 PM UTC 24 | Sep 11 01:55:53 PM UTC 24 | 1790894729 ps | ||
| T776 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.746705745 | Sep 11 01:55:46 PM UTC 24 | Sep 11 01:55:53 PM UTC 24 | 663032985 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.3060765159 | Sep 11 01:55:49 PM UTC 24 | Sep 11 01:55:54 PM UTC 24 | 2480001477 ps | ||
| T777 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.1525270141 | Sep 11 01:55:49 PM UTC 24 | Sep 11 01:55:55 PM UTC 24 | 50592097 ps | ||
| T778 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.604984618 | Sep 11 01:55:52 PM UTC 24 | Sep 11 01:55:55 PM UTC 24 | 222879394 ps | ||
| T106 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.635249299 | Sep 11 01:55:53 PM UTC 24 | Sep 11 01:55:55 PM UTC 24 | 22116717 ps | ||
| T779 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.4102697099 | Sep 11 01:55:53 PM UTC 24 | Sep 11 01:55:56 PM UTC 24 | 45412072 ps | ||
| T109 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.834585068 | Sep 11 01:55:53 PM UTC 24 | Sep 11 01:55:56 PM UTC 24 | 48156323 ps | ||
| T780 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.3985414280 | Sep 11 01:55:54 PM UTC 24 | Sep 11 01:55:56 PM UTC 24 | 16044476 ps | ||
| T781 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.261626009 | Sep 11 01:55:54 PM UTC 24 | Sep 11 01:55:57 PM UTC 24 | 15588416 ps | ||
| T782 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.4103812560 | Sep 11 01:55:54 PM UTC 24 | Sep 11 01:55:58 PM UTC 24 | 139758839 ps | ||
| T107 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.1938826480 | Sep 11 01:55:55 PM UTC 24 | Sep 11 01:55:58 PM UTC 24 | 164725245 ps | ||
| T783 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.613132753 | Sep 11 01:55:54 PM UTC 24 | Sep 11 01:55:59 PM UTC 24 | 97860423 ps | ||
| T784 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.1232922004 | Sep 11 01:55:56 PM UTC 24 | Sep 11 01:55:59 PM UTC 24 | 43711441 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.792646954 | Sep 11 01:55:54 PM UTC 24 | Sep 11 01:55:59 PM UTC 24 | 178342102 ps | ||
| T785 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.1354890016 | Sep 11 01:55:57 PM UTC 24 | Sep 11 01:55:59 PM UTC 24 | 31405905 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.3249845712 | Sep 11 01:55:56 PM UTC 24 | Sep 11 01:56:00 PM UTC 24 | 194727089 ps | ||
| T786 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.606408309 | Sep 11 01:55:57 PM UTC 24 | Sep 11 01:56:00 PM UTC 24 | 101108598 ps | ||
| T787 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2766022420 | Sep 11 01:55:57 PM UTC 24 | Sep 11 01:56:00 PM UTC 24 | 44371027 ps | ||
| T788 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1999249813 | Sep 11 01:55:57 PM UTC 24 | Sep 11 01:56:01 PM UTC 24 | 116919826 ps | ||
| T789 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.4018008416 | Sep 11 01:55:59 PM UTC 24 | Sep 11 01:56:01 PM UTC 24 | 30222116 ps | ||
| T790 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.2684532645 | Sep 11 01:55:56 PM UTC 24 | Sep 11 01:56:02 PM UTC 24 | 765985331 ps | ||
| T791 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.3993431886 | Sep 11 01:55:59 PM UTC 24 | Sep 11 01:56:02 PM UTC 24 | 104503418 ps | ||
| T792 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.2708927013 | Sep 11 01:56:00 PM UTC 24 | Sep 11 01:56:02 PM UTC 24 | 21255193 ps | ||
| T793 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.2309805239 | Sep 11 01:55:54 PM UTC 24 | Sep 11 01:56:02 PM UTC 24 | 165496648 ps | ||
| T794 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.90032108 | Sep 11 01:56:00 PM UTC 24 | Sep 11 01:56:02 PM UTC 24 | 30213156 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.1575851830 | Sep 11 01:55:59 PM UTC 24 | Sep 11 01:56:03 PM UTC 24 | 195881459 ps | ||
| T795 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1884502248 | Sep 11 01:56:00 PM UTC 24 | Sep 11 01:56:03 PM UTC 24 | 63511508 ps | ||
| T796 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.3306196057 | Sep 11 01:56:01 PM UTC 24 | Sep 11 01:56:03 PM UTC 24 | 16486946 ps | ||
| T797 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1954461549 | Sep 11 01:56:00 PM UTC 24 | Sep 11 01:56:04 PM UTC 24 | 679286845 ps | ||
| T798 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.364428370 | Sep 11 01:56:01 PM UTC 24 | Sep 11 01:56:04 PM UTC 24 | 123703008 ps | ||
| T799 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.1832525141 | Sep 11 01:55:59 PM UTC 24 | Sep 11 01:56:05 PM UTC 24 | 505107028 ps | ||
| T800 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.2249987603 | Sep 11 01:56:02 PM UTC 24 | Sep 11 01:56:05 PM UTC 24 | 16334960 ps | ||
| T801 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.209890101 | Sep 11 01:56:01 PM UTC 24 | Sep 11 01:56:06 PM UTC 24 | 509446357 ps | ||
| T802 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.3127540700 | Sep 11 01:56:01 PM UTC 24 | Sep 11 01:56:06 PM UTC 24 | 336674081 ps | ||
| T803 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1697785482 | Sep 11 01:56:03 PM UTC 24 | Sep 11 01:56:06 PM UTC 24 | 79708939 ps | ||
| T804 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.732491892 | Sep 11 01:56:03 PM UTC 24 | Sep 11 01:56:07 PM UTC 24 | 72667688 ps | ||
| T805 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1959654679 | Sep 11 01:56:03 PM UTC 24 | Sep 11 01:56:07 PM UTC 24 | 48290265 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.1452490075 | Sep 11 01:56:01 PM UTC 24 | Sep 11 01:56:07 PM UTC 24 | 116565553 ps | ||
| T806 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.3274479014 | Sep 11 01:56:05 PM UTC 24 | Sep 11 01:56:07 PM UTC 24 | 17918202 ps | ||
| T807 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.3667730643 | Sep 11 01:56:05 PM UTC 24 | Sep 11 01:56:07 PM UTC 24 | 21683851 ps | ||
| T808 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.2256012251 | Sep 11 01:56:02 PM UTC 24 | Sep 11 01:56:08 PM UTC 24 | 123260600 ps | ||
| T809 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.4146633381 | Sep 11 01:56:04 PM UTC 24 | Sep 11 01:56:08 PM UTC 24 | 444946046 ps | ||
| T810 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.811431581 | Sep 11 01:56:05 PM UTC 24 | Sep 11 01:56:08 PM UTC 24 | 26435405 ps | ||
| T811 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.2620823914 | Sep 11 01:56:04 PM UTC 24 | Sep 11 01:56:08 PM UTC 24 | 78646106 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1300356396 | Sep 11 01:56:06 PM UTC 24 | Sep 11 01:56:09 PM UTC 24 | 48402495 ps | ||
| T160 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.3810694349 | Sep 11 01:56:07 PM UTC 24 | Sep 11 01:56:09 PM UTC 24 | 16026806 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1228670071 | Sep 11 01:56:06 PM UTC 24 | Sep 11 01:56:10 PM UTC 24 | 835675027 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.4081248931 | Sep 11 01:56:08 PM UTC 24 | Sep 11 01:56:11 PM UTC 24 | 184667324 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2708501073 | Sep 11 01:56:08 PM UTC 24 | Sep 11 01:56:11 PM UTC 24 | 41531396 ps | ||
| T100 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.236057793 | Sep 11 01:56:07 PM UTC 24 | Sep 11 01:56:11 PM UTC 24 | 51079842 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1949778946 | Sep 11 01:56:08 PM UTC 24 | Sep 11 01:56:11 PM UTC 24 | 41788345 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.3662380395 | Sep 11 01:56:07 PM UTC 24 | Sep 11 01:56:11 PM UTC 24 | 362866968 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.4230889546 | Sep 11 01:56:10 PM UTC 24 | Sep 11 01:56:12 PM UTC 24 | 17339400 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.240609009 | Sep 11 01:56:07 PM UTC 24 | Sep 11 01:56:12 PM UTC 24 | 91164340 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.2198735704 | Sep 11 01:56:10 PM UTC 24 | Sep 11 01:56:12 PM UTC 24 | 37696044 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.756787195 | Sep 11 01:56:08 PM UTC 24 | Sep 11 01:56:12 PM UTC 24 | 34367985 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.3120726937 | Sep 11 01:56:10 PM UTC 24 | Sep 11 01:56:13 PM UTC 24 | 107087912 ps | ||
| T108 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.3306570955 | Sep 11 01:56:08 PM UTC 24 | Sep 11 01:56:14 PM UTC 24 | 547427873 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.602670009 | Sep 11 01:56:09 PM UTC 24 | Sep 11 01:56:14 PM UTC 24 | 86731260 ps | ||
| T101 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1276393059 | Sep 11 01:56:12 PM UTC 24 | Sep 11 01:56:14 PM UTC 24 | 39832534 ps | ||
| T823 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.3970099907 | Sep 11 01:56:18 PM UTC 24 | Sep 11 01:56:20 PM UTC 24 | 52131419 ps | ||
| T824 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1148852212 | Sep 11 01:56:11 PM UTC 24 | Sep 11 01:56:15 PM UTC 24 | 173940402 ps | ||
| T825 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.871430985 | Sep 11 01:56:12 PM UTC 24 | Sep 11 01:56:15 PM UTC 24 | 95593725 ps | ||
| T826 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2805982502 | Sep 11 01:56:12 PM UTC 24 | Sep 11 01:56:15 PM UTC 24 | 203305799 ps | ||
| T827 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.651488135 | Sep 11 01:56:13 PM UTC 24 | Sep 11 01:56:15 PM UTC 24 | 19787051 ps | ||
| T828 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.2864521959 | Sep 11 01:56:13 PM UTC 24 | Sep 11 01:56:15 PM UTC 24 | 15283951 ps | ||
| T829 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.1613750577 | Sep 11 01:56:13 PM UTC 24 | Sep 11 01:56:16 PM UTC 24 | 55922011 ps | ||
| T830 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.657525356 | Sep 11 01:56:13 PM UTC 24 | Sep 11 01:56:16 PM UTC 24 | 88043625 ps | ||
| T831 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.267935285 | Sep 11 01:56:13 PM UTC 24 | Sep 11 01:56:16 PM UTC 24 | 96088949 ps | ||
| T832 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.2094466029 | Sep 11 01:56:12 PM UTC 24 | Sep 11 01:56:18 PM UTC 24 | 585311983 ps | ||
| T833 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.3663559784 | Sep 11 01:56:15 PM UTC 24 | Sep 11 01:56:18 PM UTC 24 | 20098701 ps | ||
| T834 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.1438045557 | Sep 11 01:56:16 PM UTC 24 | Sep 11 01:56:18 PM UTC 24 | 21007752 ps | ||
| T835 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.3714682690 | Sep 11 01:56:15 PM UTC 24 | Sep 11 01:56:19 PM UTC 24 | 129168320 ps | ||
| T836 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.2803273975 | Sep 11 01:56:14 PM UTC 24 | Sep 11 01:56:18 PM UTC 24 | 198759776 ps | ||
| T837 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.2911697821 | Sep 11 01:56:12 PM UTC 24 | Sep 11 01:56:18 PM UTC 24 | 188547873 ps | ||
| T838 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.475232205 | Sep 11 01:56:17 PM UTC 24 | Sep 11 01:56:19 PM UTC 24 | 52228852 ps | ||
| T839 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1872621585 | Sep 11 01:56:17 PM UTC 24 | Sep 11 01:56:20 PM UTC 24 | 204730943 ps | ||
| T840 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.1133411737 | Sep 11 01:56:17 PM UTC 24 | Sep 11 01:56:20 PM UTC 24 | 212865441 ps | ||
| T841 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.2389259735 | Sep 11 01:56:18 PM UTC 24 | Sep 11 01:56:21 PM UTC 24 | 125082242 ps | ||
| T842 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2234485169 | Sep 11 01:56:17 PM UTC 24 | Sep 11 01:56:21 PM UTC 24 | 38708884 ps | ||
| T843 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.55034723 | Sep 11 01:56:19 PM UTC 24 | Sep 11 01:56:22 PM UTC 24 | 76639685 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.586926549 | Sep 11 01:56:15 PM UTC 24 | Sep 11 01:56:22 PM UTC 24 | 231887958 ps | ||
| T844 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.2657821727 | Sep 11 01:56:17 PM UTC 24 | Sep 11 01:56:22 PM UTC 24 | 555569609 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.2877921149 | Sep 11 01:56:17 PM UTC 24 | Sep 11 01:56:22 PM UTC 24 | 393907221 ps | ||
| T845 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.3099867165 | Sep 11 01:56:19 PM UTC 24 | Sep 11 01:56:22 PM UTC 24 | 108854643 ps | ||
| T102 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.250712209 | Sep 11 01:56:19 PM UTC 24 | Sep 11 01:56:23 PM UTC 24 | 53117035 ps | ||
| T846 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.2466175839 | Sep 11 01:56:21 PM UTC 24 | Sep 11 01:56:24 PM UTC 24 | 16338481 ps | ||
| T847 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.1709808885 | Sep 11 01:56:22 PM UTC 24 | Sep 11 01:56:24 PM UTC 24 | 27603893 ps | ||
| T848 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.3603189188 | Sep 11 01:56:19 PM UTC 24 | Sep 11 01:56:24 PM UTC 24 | 34348783 ps | ||
| T849 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.2189701081 | Sep 11 01:56:21 PM UTC 24 | Sep 11 01:56:24 PM UTC 24 | 25179354 ps | ||
| T850 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1705494286 | Sep 11 01:56:22 PM UTC 24 | Sep 11 01:56:25 PM UTC 24 | 52050815 ps | ||
| T851 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.957751346 | Sep 11 01:56:20 PM UTC 24 | Sep 11 01:56:25 PM UTC 24 | 78955097 ps | ||
| T852 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.428619341 | Sep 11 01:56:23 PM UTC 24 | Sep 11 01:56:25 PM UTC 24 | 44939341 ps | ||
| T853 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.771314830 | Sep 11 01:56:23 PM UTC 24 | Sep 11 01:56:25 PM UTC 24 | 24769938 ps | ||
| T854 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.1981834802 | Sep 11 01:56:23 PM UTC 24 | Sep 11 01:56:25 PM UTC 24 | 21296115 ps | ||
| T855 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.652394380 | Sep 11 01:56:24 PM UTC 24 | Sep 11 01:56:26 PM UTC 24 | 23150435 ps | ||
| T856 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.269812809 | Sep 11 01:56:24 PM UTC 24 | Sep 11 01:56:26 PM UTC 24 | 32985834 ps | ||
| T857 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.1882939208 | Sep 11 01:56:24 PM UTC 24 | Sep 11 01:56:26 PM UTC 24 | 20671971 ps | ||
| T858 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2917087718 | Sep 11 01:56:22 PM UTC 24 | Sep 11 01:56:27 PM UTC 24 | 127318067 ps | ||
| T859 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.2375286753 | Sep 11 01:56:25 PM UTC 24 | Sep 11 01:56:27 PM UTC 24 | 15175484 ps | ||
| T860 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.1959564151 | Sep 11 01:56:25 PM UTC 24 | Sep 11 01:56:27 PM UTC 24 | 47344646 ps | ||
| T861 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.784316773 | Sep 11 01:56:20 PM UTC 24 | Sep 11 01:56:27 PM UTC 24 | 212682143 ps | ||
| T862 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.2493070133 | Sep 11 01:56:25 PM UTC 24 | Sep 11 01:56:28 PM UTC 24 | 41679479 ps | ||
| T863 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.2198476981 | Sep 11 01:56:25 PM UTC 24 | Sep 11 01:56:28 PM UTC 24 | 18445045 ps | ||
| T864 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.89672451 | Sep 11 01:56:25 PM UTC 24 | Sep 11 01:56:28 PM UTC 24 | 19046477 ps | ||
| T865 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.3584915912 | Sep 11 01:56:26 PM UTC 24 | Sep 11 01:56:29 PM UTC 24 | 31406543 ps | ||
| T866 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.1366216482 | Sep 11 01:56:26 PM UTC 24 | Sep 11 01:56:29 PM UTC 24 | 49972193 ps | ||
| T867 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.172960819 | Sep 11 01:56:26 PM UTC 24 | Sep 11 01:56:29 PM UTC 24 | 16295014 ps | ||
| T868 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.591212149 | Sep 11 01:56:26 PM UTC 24 | Sep 11 01:56:29 PM UTC 24 | 29455908 ps | ||
| T869 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.2624984209 | Sep 11 01:56:28 PM UTC 24 | Sep 11 01:56:30 PM UTC 24 | 23099443 ps | ||
| T870 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.1173183578 | Sep 11 01:56:28 PM UTC 24 | Sep 11 01:56:30 PM UTC 24 | 37030449 ps | ||
| T871 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.1311582412 | Sep 11 01:56:28 PM UTC 24 | Sep 11 01:56:30 PM UTC 24 | 13466734 ps | ||
| T872 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.1425112469 | Sep 11 01:56:28 PM UTC 24 | Sep 11 01:56:30 PM UTC 24 | 13644770 ps | ||
| T873 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.2404906039 | Sep 11 01:56:29 PM UTC 24 | Sep 11 01:56:31 PM UTC 24 | 45370527 ps | ||
| T874 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.1417540278 | Sep 11 01:56:29 PM UTC 24 | Sep 11 01:56:31 PM UTC 24 | 41270799 ps | ||
| T875 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.1308534107 | Sep 11 01:56:29 PM UTC 24 | Sep 11 01:56:31 PM UTC 24 | 46090435 ps | ||
| T876 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.1194417273 | Sep 11 01:56:29 PM UTC 24 | Sep 11 01:56:31 PM UTC 24 | 14744935 ps | ||
| T877 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.1957062611 | Sep 11 01:56:29 PM UTC 24 | Sep 11 01:56:31 PM UTC 24 | 70217963 ps | ||
| T878 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.1447439359 | Sep 11 01:56:29 PM UTC 24 | Sep 11 01:56:31 PM UTC 24 | 12536029 ps | ||
| T879 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.555311989 | Sep 11 01:56:30 PM UTC 24 | Sep 11 01:56:32 PM UTC 24 | 13611066 ps | ||
| T880 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.2831265238 | Sep 11 01:56:30 PM UTC 24 | Sep 11 01:56:32 PM UTC 24 | 13822315 ps | ||
| T881 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.1529224347 | Sep 11 01:56:30 PM UTC 24 | Sep 11 01:56:32 PM UTC 24 | 12510554 ps | ||
| T882 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.960837633 | Sep 11 01:56:30 PM UTC 24 | Sep 11 01:56:32 PM UTC 24 | 111190737 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/0.kmac_mubi.2418135216 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 27420803838 ps |
| CPU time | 65.49 seconds |
| Started | Sep 11 03:50:54 PM UTC 24 |
| Finished | Sep 11 03:52:01 PM UTC 24 |
| Peak memory | 288868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418135216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.2418135216 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_intg_err.3736660943 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 233454906 ps |
| CPU time | 7.23 seconds |
| Started | Sep 11 01:54:50 PM UTC 24 |
| Finished | Sep 11 01:54:59 PM UTC 24 |
| Peak memory | 219224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736660943 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.3736660943 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/0.kmac_sec_cm.4077728592 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 13177751323 ps |
| CPU time | 63.68 seconds |
| Started | Sep 11 03:51:36 PM UTC 24 |
| Finished | Sep 11 03:52:42 PM UTC 24 |
| Peak memory | 267112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077728592 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.4077728592 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/6.kmac_stress_all_with_rand_reset.1989604802 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 28818366197 ps |
| CPU time | 170.7 seconds |
| Started | Sep 11 04:02:44 PM UTC 24 |
| Finished | Sep 11 04:05:38 PM UTC 24 |
| Peak memory | 295156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1989604802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all_ with_rand_reset.1989604802 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/0.kmac_app_with_partial_data.2656457103 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 8577547046 ps |
| CPU time | 280.13 seconds |
| Started | Sep 11 03:50:45 PM UTC 24 |
| Finished | Sep 11 03:55:30 PM UTC 24 |
| Peak memory | 341804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656457103 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.2656457103 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/0.kmac_key_error.113965259 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 2183453734 ps |
| CPU time | 11.22 seconds |
| Started | Sep 11 03:51:21 PM UTC 24 |
| Finished | Sep 11 03:51:33 PM UTC 24 |
| Peak memory | 230388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113965259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.113965259 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/9.kmac_lc_escalation.1440982208 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 134163728 ps |
| CPU time | 2.32 seconds |
| Started | Sep 11 04:06:29 PM UTC 24 |
| Finished | Sep 11 04:06:32 PM UTC 24 |
| Peak memory | 230312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440982208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.1440982208 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/9.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/0.kmac_error.519463270 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 25885550418 ps |
| CPU time | 186.37 seconds |
| Started | Sep 11 03:51:01 PM UTC 24 |
| Finished | Sep 11 03:54:11 PM UTC 24 |
| Peak memory | 362220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519463270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.519463270 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/27.kmac_lc_escalation.2754621417 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 513778593 ps |
| CPU time | 27.31 seconds |
| Started | Sep 11 04:25:54 PM UTC 24 |
| Finished | Sep 11 04:26:23 PM UTC 24 |
| Peak memory | 247520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754621417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.2754621417 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/27.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.635249299 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 22116717 ps |
| CPU time | 1.53 seconds |
| Started | Sep 11 01:55:53 PM UTC 24 |
| Finished | Sep 11 01:55:55 PM UTC 24 |
| Peak memory | 228732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635249299 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors.635249299 +enable_masking =0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_intr_test.1681866499 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 14730093 ps |
| CPU time | 1.12 seconds |
| Started | Sep 11 01:55:02 PM UTC 24 |
| Finished | Sep 11 01:55:05 PM UTC 24 |
| Peak memory | 219040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681866499 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.1681866499 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/0.kmac_lc_escalation.1221860073 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 70265873 ps |
| CPU time | 2.19 seconds |
| Started | Sep 11 03:51:32 PM UTC 24 |
| Finished | Sep 11 03:51:35 PM UTC 24 |
| Peak memory | 230384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221860073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.1221860073 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/32.kmac_lc_escalation.4156412529 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 157265115 ps |
| CPU time | 1.61 seconds |
| Started | Sep 11 04:32:20 PM UTC 24 |
| Finished | Sep 11 04:32:23 PM UTC 24 |
| Peak memory | 231836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156412529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.4156412529 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/32.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/1.kmac_smoke.887032515 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 885269397 ps |
| CPU time | 51.43 seconds |
| Started | Sep 11 03:51:49 PM UTC 24 |
| Finished | Sep 11 03:52:42 PM UTC 24 |
| Peak memory | 230508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887032515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.887032515 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/5.kmac_error.2371553156 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 4510318690 ps |
| CPU time | 293.95 seconds |
| Started | Sep 11 04:00:23 PM UTC 24 |
| Finished | Sep 11 04:05:22 PM UTC 24 |
| Peak memory | 343860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371553156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.2371553156 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/5.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.2353340822 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 147899277 ps |
| CPU time | 3.52 seconds |
| Started | Sep 11 01:54:58 PM UTC 24 |
| Finished | Sep 11 01:55:03 PM UTC 24 |
| Peak memory | 229872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353340822 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors_with_csr_rw. 2353340822 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_partial_access.2236456175 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 19856963 ps |
| CPU time | 2.2 seconds |
| Started | Sep 11 01:54:49 PM UTC 24 |
| Finished | Sep 11 01:54:52 PM UTC 24 |
| Peak memory | 229444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236456175 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial_access.2236456175 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/46.kmac_lc_escalation.3643762991 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 56351492 ps |
| CPU time | 1.34 seconds |
| Started | Sep 11 04:48:51 PM UTC 24 |
| Finished | Sep 11 04:48:54 PM UTC 24 |
| Peak memory | 231768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643762991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.3643762991 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/46.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/0.kmac_alert_test.2657769168 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 96496489 ps |
| CPU time | 1.2 seconds |
| Started | Sep 11 03:51:48 PM UTC 24 |
| Finished | Sep 11 03:51:50 PM UTC 24 |
| Peak memory | 216340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657769168 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.2657769168 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.1938826480 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 164725245 ps |
| CPU time | 1.53 seconds |
| Started | Sep 11 01:55:55 PM UTC 24 |
| Finished | Sep 11 01:55:58 PM UTC 24 |
| Peak memory | 228796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938826480 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors.1938826480 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.2708927013 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 21255193 ps |
| CPU time | 1.1 seconds |
| Started | Sep 11 01:56:00 PM UTC 24 |
| Finished | Sep 11 01:56:02 PM UTC 24 |
| Peak memory | 218928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708927013 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.2708927013 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/11.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_256.1657146852 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 2389162963 ps |
| CPU time | 41.18 seconds |
| Started | Sep 11 03:52:05 PM UTC 24 |
| Finished | Sep 11 03:52:47 PM UTC 24 |
| Peak memory | 230568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657146852 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.1657146852 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.1575851830 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 195881459 ps |
| CPU time | 2.89 seconds |
| Started | Sep 11 01:55:59 PM UTC 24 |
| Finished | Sep 11 01:56:03 PM UTC 24 |
| Peak memory | 219392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575851830 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.1575851830 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/11.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_256.2735293462 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 43925824985 ps |
| CPU time | 490.02 seconds |
| Started | Sep 11 03:54:28 PM UTC 24 |
| Finished | Sep 11 04:02:45 PM UTC 24 |
| Peak memory | 362376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735293462 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.2735293 462 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.236057793 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 51079842 ps |
| CPU time | 2.91 seconds |
| Started | Sep 11 01:56:07 PM UTC 24 |
| Finished | Sep 11 01:56:11 PM UTC 24 |
| Peak memory | 237004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236057793 -asse rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors_with_csr_rw. 236057793 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/14.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.2877921149 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 393907221 ps |
| CPU time | 4.26 seconds |
| Started | Sep 11 01:56:17 PM UTC 24 |
| Finished | Sep 11 01:56:22 PM UTC 24 |
| Peak memory | 229568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877921149 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.2877921149 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/18.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/4.kmac_app.2776331094 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 124831067652 ps |
| CPU time | 203.69 seconds |
| Started | Sep 11 03:58:37 PM UTC 24 |
| Finished | Sep 11 04:02:04 PM UTC 24 |
| Peak memory | 417500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776331094 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.2776331094 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/4.kmac_error.1937594731 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 39636758875 ps |
| CPU time | 444.75 seconds |
| Started | Sep 11 03:58:46 PM UTC 24 |
| Finished | Sep 11 04:06:17 PM UTC 24 |
| Peak memory | 644900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937594731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.1937594731 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/4.kmac_burst_write.1385468459 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 8304616715 ps |
| CPU time | 163.59 seconds |
| Started | Sep 11 03:58:09 PM UTC 24 |
| Finished | Sep 11 04:00:56 PM UTC 24 |
| Peak memory | 237292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385468459 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.1385468459 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.586926549 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 231887958 ps |
| CPU time | 5.41 seconds |
| Started | Sep 11 01:56:15 PM UTC 24 |
| Finished | Sep 11 01:56:22 PM UTC 24 |
| Peak memory | 229444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586926549 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.586926549 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/17.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.1227958306 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 201783071 ps |
| CPU time | 3.68 seconds |
| Started | Sep 11 01:55:30 PM UTC 24 |
| Finished | Sep 11 01:55:35 PM UTC 24 |
| Peak memory | 229572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227958306 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.1227958306 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_256.800990274 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 362902217455 ps |
| CPU time | 2799.64 seconds |
| Started | Sep 11 03:50:32 PM UTC 24 |
| Finished | Sep 11 04:37:45 PM UTC 24 |
| Peak memory | 3011816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800990274 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.80099027 4 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_ready_error.3493970750 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 3312735918 ps |
| CPU time | 46.55 seconds |
| Started | Sep 11 03:51:32 PM UTC 24 |
| Finished | Sep 11 03:52:20 PM UTC 24 |
| Peak memory | 230828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493970750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.3493970750 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors.1565306985 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 51173819 ps |
| CPU time | 1.85 seconds |
| Started | Sep 11 01:54:57 PM UTC 24 |
| Finished | Sep 11 01:55:00 PM UTC 24 |
| Peak memory | 228792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565306985 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors.1565306985 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_aliasing.2128077469 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 130873827 ps |
| CPU time | 7.33 seconds |
| Started | Sep 11 01:54:56 PM UTC 24 |
| Finished | Sep 11 01:55:05 PM UTC 24 |
| Peak memory | 219200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128077469 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.2128077469 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.816575602 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 5327790099 ps |
| CPU time | 33.15 seconds |
| Started | Sep 11 01:54:55 PM UTC 24 |
| Finished | Sep 11 01:55:30 PM UTC 24 |
| Peak memory | 219336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816575602 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.816575602 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_hw_reset.3905730358 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 22660758 ps |
| CPU time | 1.38 seconds |
| Started | Sep 11 01:54:51 PM UTC 24 |
| Finished | Sep 11 01:54:54 PM UTC 24 |
| Peak memory | 218984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905730358 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.3905730358 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.369653485 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 265257734 ps |
| CPU time | 3.95 seconds |
| Started | Sep 11 01:54:56 PM UTC 24 |
| Finished | Sep 11 01:55:01 PM UTC 24 |
| Peak memory | 231500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=369653485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_m em_rw_with_rand_reset.369653485 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_rw.2320787033 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 28358326 ps |
| CPU time | 1.61 seconds |
| Started | Sep 11 01:54:55 PM UTC 24 |
| Finished | Sep 11 01:54:58 PM UTC 24 |
| Peak memory | 218940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320787033 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.2320787033 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_intr_test.3594638640 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 80199923 ps |
| CPU time | 0.97 seconds |
| Started | Sep 11 01:54:51 PM UTC 24 |
| Finished | Sep 11 01:54:53 PM UTC 24 |
| Peak memory | 219040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594638640 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.3594638640 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_walk.2452177432 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 36825328 ps |
| CPU time | 1.13 seconds |
| Started | Sep 11 01:54:47 PM UTC 24 |
| Finished | Sep 11 01:54:49 PM UTC 24 |
| Peak memory | 218588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452177432 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.2452177432 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_same_csr_outstanding.975795535 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 231279066 ps |
| CPU time | 2.4 seconds |
| Started | Sep 11 01:54:56 PM UTC 24 |
| Finished | Sep 11 01:55:00 PM UTC 24 |
| Peak memory | 229572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975795535 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_outstanding.975795535 +enable_m asking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors.1629386298 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 135538349 ps |
| CPU time | 2.15 seconds |
| Started | Sep 11 01:54:46 PM UTC 24 |
| Finished | Sep 11 01:54:49 PM UTC 24 |
| Peak memory | 229900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629386298 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors.1629386298 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.2515821022 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 80481033 ps |
| CPU time | 3.16 seconds |
| Started | Sep 11 01:54:47 PM UTC 24 |
| Finished | Sep 11 01:54:51 PM UTC 24 |
| Peak memory | 229792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515821022 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors_with_csr_rw. 2515821022 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_errors.1894456982 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 112475215 ps |
| CPU time | 5.07 seconds |
| Started | Sep 11 01:54:50 PM UTC 24 |
| Finished | Sep 11 01:54:56 PM UTC 24 |
| Peak memory | 229692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894456982 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.1894456982 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_aliasing.626227862 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 142888086 ps |
| CPU time | 9.74 seconds |
| Started | Sep 11 01:55:06 PM UTC 24 |
| Finished | Sep 11 01:55:17 PM UTC 24 |
| Peak memory | 218920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626227862 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.626227862 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.1067117740 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 3011487710 ps |
| CPU time | 15.28 seconds |
| Started | Sep 11 01:55:06 PM UTC 24 |
| Finished | Sep 11 01:55:22 PM UTC 24 |
| Peak memory | 218980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067117740 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.1067117740 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_hw_reset.614148939 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 28501366 ps |
| CPU time | 1.62 seconds |
| Started | Sep 11 01:55:04 PM UTC 24 |
| Finished | Sep 11 01:55:06 PM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614148939 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.614148939 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.3371914755 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 180347979 ps |
| CPU time | 2.16 seconds |
| Started | Sep 11 01:55:07 PM UTC 24 |
| Finished | Sep 11 01:55:10 PM UTC 24 |
| Peak memory | 229452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3371914755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_ mem_rw_with_rand_reset.3371914755 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_rw.2046493320 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 79788296 ps |
| CPU time | 1.44 seconds |
| Started | Sep 11 01:55:04 PM UTC 24 |
| Finished | Sep 11 01:55:06 PM UTC 24 |
| Peak memory | 218980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046493320 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.2046493320 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_partial_access.3639106469 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 51838024 ps |
| CPU time | 1.56 seconds |
| Started | Sep 11 01:55:00 PM UTC 24 |
| Finished | Sep 11 01:55:03 PM UTC 24 |
| Peak memory | 228864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639106469 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial_access.3639106469 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_walk.3874486608 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 12304063 ps |
| CPU time | 1.09 seconds |
| Started | Sep 11 01:54:59 PM UTC 24 |
| Finished | Sep 11 01:55:02 PM UTC 24 |
| Peak memory | 219048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874486608 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.3874486608 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_same_csr_outstanding.3907897713 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 109299888 ps |
| CPU time | 2.56 seconds |
| Started | Sep 11 01:55:07 PM UTC 24 |
| Finished | Sep 11 01:55:10 PM UTC 24 |
| Peak memory | 229444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907897713 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_outstanding.3907897713 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_errors.3707344136 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 137578669 ps |
| CPU time | 4.71 seconds |
| Started | Sep 11 01:55:01 PM UTC 24 |
| Finished | Sep 11 01:55:07 PM UTC 24 |
| Peak memory | 229500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707344136 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.3707344136 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_intg_err.3614630220 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 224714630 ps |
| CPU time | 2.98 seconds |
| Started | Sep 11 01:55:02 PM UTC 24 |
| Finished | Sep 11 01:55:07 PM UTC 24 |
| Peak memory | 229572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614630220 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.3614630220 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2766022420 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 44371027 ps |
| CPU time | 1.83 seconds |
| Started | Sep 11 01:55:57 PM UTC 24 |
| Finished | Sep 11 01:56:00 PM UTC 24 |
| Peak memory | 228984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2766022420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr _mem_rw_with_rand_reset.2766022420 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/10.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.606408309 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 101108598 ps |
| CPU time | 1.62 seconds |
| Started | Sep 11 01:55:57 PM UTC 24 |
| Finished | Sep 11 01:56:00 PM UTC 24 |
| Peak memory | 218860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606408309 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.606408309 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/10.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.1354890016 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 31405905 ps |
| CPU time | 1.04 seconds |
| Started | Sep 11 01:55:57 PM UTC 24 |
| Finished | Sep 11 01:55:59 PM UTC 24 |
| Peak memory | 218864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354890016 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.1354890016 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/10.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1999249813 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 116919826 ps |
| CPU time | 2.33 seconds |
| Started | Sep 11 01:55:57 PM UTC 24 |
| Finished | Sep 11 01:56:01 PM UTC 24 |
| Peak memory | 229440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999249813 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr_outstanding.1999249813 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/10.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.1232922004 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 43711441 ps |
| CPU time | 2.11 seconds |
| Started | Sep 11 01:55:56 PM UTC 24 |
| Finished | Sep 11 01:55:59 PM UTC 24 |
| Peak memory | 219280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232922004 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors_with_csr_rw .1232922004 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.2684532645 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 765985331 ps |
| CPU time | 5.01 seconds |
| Started | Sep 11 01:55:56 PM UTC 24 |
| Finished | Sep 11 01:56:02 PM UTC 24 |
| Peak memory | 229492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684532645 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.2684532645 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/10.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.3249845712 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 194727089 ps |
| CPU time | 2.94 seconds |
| Started | Sep 11 01:55:56 PM UTC 24 |
| Finished | Sep 11 01:56:00 PM UTC 24 |
| Peak memory | 229540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249845712 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.3249845712 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/10.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1954461549 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 679286845 ps |
| CPU time | 2.58 seconds |
| Started | Sep 11 01:56:00 PM UTC 24 |
| Finished | Sep 11 01:56:04 PM UTC 24 |
| Peak memory | 229440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1954461549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr _mem_rw_with_rand_reset.1954461549 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/11.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.90032108 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 30213156 ps |
| CPU time | 1.39 seconds |
| Started | Sep 11 01:56:00 PM UTC 24 |
| Finished | Sep 11 01:56:02 PM UTC 24 |
| Peak memory | 218988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90032108 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.90032108 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/11.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1884502248 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 63511508 ps |
| CPU time | 1.85 seconds |
| Started | Sep 11 01:56:00 PM UTC 24 |
| Finished | Sep 11 01:56:03 PM UTC 24 |
| Peak memory | 228924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884502248 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr_outstanding.1884502248 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/11.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.4018008416 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 30222116 ps |
| CPU time | 1.16 seconds |
| Started | Sep 11 01:55:59 PM UTC 24 |
| Finished | Sep 11 01:56:01 PM UTC 24 |
| Peak memory | 218680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018008416 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors.4018008416 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/11.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.3993431886 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 104503418 ps |
| CPU time | 2.26 seconds |
| Started | Sep 11 01:55:59 PM UTC 24 |
| Finished | Sep 11 01:56:02 PM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993431886 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors_with_csr_rw .3993431886 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.1832525141 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 505107028 ps |
| CPU time | 4.87 seconds |
| Started | Sep 11 01:55:59 PM UTC 24 |
| Finished | Sep 11 01:56:05 PM UTC 24 |
| Peak memory | 229552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832525141 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.1832525141 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/11.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1959654679 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 48290265 ps |
| CPU time | 2.21 seconds |
| Started | Sep 11 01:56:03 PM UTC 24 |
| Finished | Sep 11 01:56:07 PM UTC 24 |
| Peak memory | 236644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1959654679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr _mem_rw_with_rand_reset.1959654679 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/12.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.2249987603 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 16334960 ps |
| CPU time | 1.43 seconds |
| Started | Sep 11 01:56:02 PM UTC 24 |
| Finished | Sep 11 01:56:05 PM UTC 24 |
| Peak memory | 218988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249987603 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.2249987603 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/12.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.3306196057 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 16486946 ps |
| CPU time | 1.13 seconds |
| Started | Sep 11 01:56:01 PM UTC 24 |
| Finished | Sep 11 01:56:03 PM UTC 24 |
| Peak memory | 218928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306196057 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.3306196057 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/12.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.2256012251 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 123260600 ps |
| CPU time | 3.89 seconds |
| Started | Sep 11 01:56:02 PM UTC 24 |
| Finished | Sep 11 01:56:08 PM UTC 24 |
| Peak memory | 229544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256012251 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr_outstanding.2256012251 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/12.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.364428370 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 123703008 ps |
| CPU time | 1.59 seconds |
| Started | Sep 11 01:56:01 PM UTC 24 |
| Finished | Sep 11 01:56:04 PM UTC 24 |
| Peak memory | 228668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364428370 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors.364428370 +enable_maskin g=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/12.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.3127540700 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 336674081 ps |
| CPU time | 3.43 seconds |
| Started | Sep 11 01:56:01 PM UTC 24 |
| Finished | Sep 11 01:56:06 PM UTC 24 |
| Peak memory | 237024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127540700 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors_with_csr_rw .3127540700 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.209890101 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 509446357 ps |
| CPU time | 3.17 seconds |
| Started | Sep 11 01:56:01 PM UTC 24 |
| Finished | Sep 11 01:56:06 PM UTC 24 |
| Peak memory | 229684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209890101 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.209890101 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/12.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.1452490075 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 116565553 ps |
| CPU time | 4.56 seconds |
| Started | Sep 11 01:56:01 PM UTC 24 |
| Finished | Sep 11 01:56:07 PM UTC 24 |
| Peak memory | 229380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452490075 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.1452490075 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/12.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1228670071 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 835675027 ps |
| CPU time | 3.38 seconds |
| Started | Sep 11 01:56:06 PM UTC 24 |
| Finished | Sep 11 01:56:10 PM UTC 24 |
| Peak memory | 231488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1228670071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr _mem_rw_with_rand_reset.1228670071 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/13.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.3667730643 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 21683851 ps |
| CPU time | 1.21 seconds |
| Started | Sep 11 01:56:05 PM UTC 24 |
| Finished | Sep 11 01:56:07 PM UTC 24 |
| Peak memory | 218988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667730643 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.3667730643 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/13.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.3274479014 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 17918202 ps |
| CPU time | 1.16 seconds |
| Started | Sep 11 01:56:05 PM UTC 24 |
| Finished | Sep 11 01:56:07 PM UTC 24 |
| Peak memory | 218928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274479014 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.3274479014 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/13.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.811431581 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 26435405 ps |
| CPU time | 2.12 seconds |
| Started | Sep 11 01:56:05 PM UTC 24 |
| Finished | Sep 11 01:56:08 PM UTC 24 |
| Peak memory | 229432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811431581 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr_outstanding.811431581 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/13.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1697785482 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 79708939 ps |
| CPU time | 1.24 seconds |
| Started | Sep 11 01:56:03 PM UTC 24 |
| Finished | Sep 11 01:56:06 PM UTC 24 |
| Peak memory | 228732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697785482 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors.1697785482 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/13.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.732491892 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 72667688 ps |
| CPU time | 1.92 seconds |
| Started | Sep 11 01:56:03 PM UTC 24 |
| Finished | Sep 11 01:56:07 PM UTC 24 |
| Peak memory | 228796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732491892 -asse rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors_with_csr_rw. 732491892 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.2620823914 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 78646106 ps |
| CPU time | 3.71 seconds |
| Started | Sep 11 01:56:04 PM UTC 24 |
| Finished | Sep 11 01:56:08 PM UTC 24 |
| Peak memory | 229704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620823914 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.2620823914 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/13.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.4146633381 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 444946046 ps |
| CPU time | 3.25 seconds |
| Started | Sep 11 01:56:04 PM UTC 24 |
| Finished | Sep 11 01:56:08 PM UTC 24 |
| Peak memory | 229568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146633381 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.4146633381 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/13.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1949778946 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 41788345 ps |
| CPU time | 1.88 seconds |
| Started | Sep 11 01:56:08 PM UTC 24 |
| Finished | Sep 11 01:56:11 PM UTC 24 |
| Peak memory | 228984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1949778946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr _mem_rw_with_rand_reset.1949778946 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/14.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.4081248931 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 184667324 ps |
| CPU time | 1.27 seconds |
| Started | Sep 11 01:56:08 PM UTC 24 |
| Finished | Sep 11 01:56:11 PM UTC 24 |
| Peak memory | 218988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081248931 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.4081248931 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/14.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.3810694349 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 16026806 ps |
| CPU time | 1.19 seconds |
| Started | Sep 11 01:56:07 PM UTC 24 |
| Finished | Sep 11 01:56:09 PM UTC 24 |
| Peak memory | 218928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810694349 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.3810694349 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/14.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.756787195 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 34367985 ps |
| CPU time | 2.8 seconds |
| Started | Sep 11 01:56:08 PM UTC 24 |
| Finished | Sep 11 01:56:12 PM UTC 24 |
| Peak memory | 229432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756787195 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr_outstanding.756787195 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/14.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1300356396 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 48402495 ps |
| CPU time | 1.59 seconds |
| Started | Sep 11 01:56:06 PM UTC 24 |
| Finished | Sep 11 01:56:09 PM UTC 24 |
| Peak memory | 218636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300356396 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors.1300356396 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/14.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.3662380395 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 362866968 ps |
| CPU time | 3.25 seconds |
| Started | Sep 11 01:56:07 PM UTC 24 |
| Finished | Sep 11 01:56:11 PM UTC 24 |
| Peak memory | 229704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662380395 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.3662380395 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/14.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.240609009 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 91164340 ps |
| CPU time | 3.46 seconds |
| Started | Sep 11 01:56:07 PM UTC 24 |
| Finished | Sep 11 01:56:12 PM UTC 24 |
| Peak memory | 229572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240609009 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.240609009 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/14.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.871430985 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 95593725 ps |
| CPU time | 2.22 seconds |
| Started | Sep 11 01:56:12 PM UTC 24 |
| Finished | Sep 11 01:56:15 PM UTC 24 |
| Peak memory | 229576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=871430985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_ mem_rw_with_rand_reset.871430985 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/15.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.2198735704 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 37696044 ps |
| CPU time | 1.39 seconds |
| Started | Sep 11 01:56:10 PM UTC 24 |
| Finished | Sep 11 01:56:12 PM UTC 24 |
| Peak memory | 218984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198735704 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.2198735704 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/15.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.4230889546 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 17339400 ps |
| CPU time | 1.05 seconds |
| Started | Sep 11 01:56:10 PM UTC 24 |
| Finished | Sep 11 01:56:12 PM UTC 24 |
| Peak memory | 218988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230889546 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.4230889546 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/15.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1148852212 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 173940402 ps |
| CPU time | 3.06 seconds |
| Started | Sep 11 01:56:11 PM UTC 24 |
| Finished | Sep 11 01:56:15 PM UTC 24 |
| Peak memory | 229380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148852212 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr_outstanding.1148852212 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/15.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2708501073 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 41531396 ps |
| CPU time | 1.26 seconds |
| Started | Sep 11 01:56:08 PM UTC 24 |
| Finished | Sep 11 01:56:11 PM UTC 24 |
| Peak memory | 228732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708501073 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors.2708501073 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/15.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.3306570955 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 547427873 ps |
| CPU time | 4.47 seconds |
| Started | Sep 11 01:56:08 PM UTC 24 |
| Finished | Sep 11 01:56:14 PM UTC 24 |
| Peak memory | 229852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306570955 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors_with_csr_rw .3306570955 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.602670009 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 86731260 ps |
| CPU time | 3.84 seconds |
| Started | Sep 11 01:56:09 PM UTC 24 |
| Finished | Sep 11 01:56:14 PM UTC 24 |
| Peak memory | 229644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602670009 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.602670009 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/15.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.3120726937 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 107087912 ps |
| CPU time | 2.61 seconds |
| Started | Sep 11 01:56:10 PM UTC 24 |
| Finished | Sep 11 01:56:13 PM UTC 24 |
| Peak memory | 229636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120726937 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.3120726937 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/15.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.267935285 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 96088949 ps |
| CPU time | 2.2 seconds |
| Started | Sep 11 01:56:13 PM UTC 24 |
| Finished | Sep 11 01:56:16 PM UTC 24 |
| Peak memory | 229448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=267935285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_ mem_rw_with_rand_reset.267935285 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/16.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.2864521959 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 15283951 ps |
| CPU time | 1.36 seconds |
| Started | Sep 11 01:56:13 PM UTC 24 |
| Finished | Sep 11 01:56:15 PM UTC 24 |
| Peak memory | 228800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864521959 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.2864521959 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/16.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.651488135 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 19787051 ps |
| CPU time | 1.09 seconds |
| Started | Sep 11 01:56:13 PM UTC 24 |
| Finished | Sep 11 01:56:15 PM UTC 24 |
| Peak memory | 218760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651488135 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.651488135 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/16.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.657525356 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 88043625 ps |
| CPU time | 2.02 seconds |
| Started | Sep 11 01:56:13 PM UTC 24 |
| Finished | Sep 11 01:56:16 PM UTC 24 |
| Peak memory | 228920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657525356 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr_outstanding.657525356 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/16.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1276393059 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 39832534 ps |
| CPU time | 1.6 seconds |
| Started | Sep 11 01:56:12 PM UTC 24 |
| Finished | Sep 11 01:56:14 PM UTC 24 |
| Peak memory | 228796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276393059 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors.1276393059 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/16.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2805982502 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 203305799 ps |
| CPU time | 2.19 seconds |
| Started | Sep 11 01:56:12 PM UTC 24 |
| Finished | Sep 11 01:56:15 PM UTC 24 |
| Peak memory | 229792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805982502 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors_with_csr_rw .2805982502 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.2094466029 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 585311983 ps |
| CPU time | 4.52 seconds |
| Started | Sep 11 01:56:12 PM UTC 24 |
| Finished | Sep 11 01:56:18 PM UTC 24 |
| Peak memory | 233648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094466029 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.2094466029 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/16.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.2911697821 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 188547873 ps |
| CPU time | 5.15 seconds |
| Started | Sep 11 01:56:12 PM UTC 24 |
| Finished | Sep 11 01:56:18 PM UTC 24 |
| Peak memory | 229440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911697821 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.2911697821 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/16.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1872621585 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 204730943 ps |
| CPU time | 2.22 seconds |
| Started | Sep 11 01:56:17 PM UTC 24 |
| Finished | Sep 11 01:56:20 PM UTC 24 |
| Peak memory | 229440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1872621585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr _mem_rw_with_rand_reset.1872621585 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/17.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.1438045557 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 21007752 ps |
| CPU time | 1.48 seconds |
| Started | Sep 11 01:56:16 PM UTC 24 |
| Finished | Sep 11 01:56:18 PM UTC 24 |
| Peak memory | 218984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438045557 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.1438045557 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/17.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.3663559784 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 20098701 ps |
| CPU time | 1.16 seconds |
| Started | Sep 11 01:56:15 PM UTC 24 |
| Finished | Sep 11 01:56:18 PM UTC 24 |
| Peak memory | 218928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663559784 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.3663559784 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/17.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2234485169 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 38708884 ps |
| CPU time | 2.92 seconds |
| Started | Sep 11 01:56:17 PM UTC 24 |
| Finished | Sep 11 01:56:21 PM UTC 24 |
| Peak memory | 229356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234485169 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr_outstanding.2234485169 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/17.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.1613750577 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 55922011 ps |
| CPU time | 1.69 seconds |
| Started | Sep 11 01:56:13 PM UTC 24 |
| Finished | Sep 11 01:56:16 PM UTC 24 |
| Peak memory | 228732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613750577 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors.1613750577 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/17.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.2803273975 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 198759776 ps |
| CPU time | 2.53 seconds |
| Started | Sep 11 01:56:14 PM UTC 24 |
| Finished | Sep 11 01:56:18 PM UTC 24 |
| Peak memory | 229852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803273975 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors_with_csr_rw .2803273975 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.3714682690 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 129168320 ps |
| CPU time | 2.83 seconds |
| Started | Sep 11 01:56:15 PM UTC 24 |
| Finished | Sep 11 01:56:19 PM UTC 24 |
| Peak memory | 229712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714682690 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.3714682690 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/17.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.3603189188 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 34348783 ps |
| CPU time | 3.77 seconds |
| Started | Sep 11 01:56:19 PM UTC 24 |
| Finished | Sep 11 01:56:24 PM UTC 24 |
| Peak memory | 231500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3603189188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr _mem_rw_with_rand_reset.3603189188 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/18.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.2389259735 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 125082242 ps |
| CPU time | 1.58 seconds |
| Started | Sep 11 01:56:18 PM UTC 24 |
| Finished | Sep 11 01:56:21 PM UTC 24 |
| Peak memory | 218948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389259735 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.2389259735 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/18.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.3970099907 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 52131419 ps |
| CPU time | 1.27 seconds |
| Started | Sep 11 01:56:18 PM UTC 24 |
| Finished | Sep 11 01:56:20 PM UTC 24 |
| Peak memory | 218928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970099907 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.3970099907 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/18.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.3099867165 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 108854643 ps |
| CPU time | 2.18 seconds |
| Started | Sep 11 01:56:19 PM UTC 24 |
| Finished | Sep 11 01:56:22 PM UTC 24 |
| Peak memory | 229380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099867165 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr_outstanding.3099867165 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/18.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.475232205 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 52228852 ps |
| CPU time | 1.36 seconds |
| Started | Sep 11 01:56:17 PM UTC 24 |
| Finished | Sep 11 01:56:19 PM UTC 24 |
| Peak memory | 228800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475232205 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors.475232205 +enable_maskin g=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/18.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.1133411737 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 212865441 ps |
| CPU time | 2.5 seconds |
| Started | Sep 11 01:56:17 PM UTC 24 |
| Finished | Sep 11 01:56:20 PM UTC 24 |
| Peak memory | 236556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133411737 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors_with_csr_rw .1133411737 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.2657821727 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 555569609 ps |
| CPU time | 4.02 seconds |
| Started | Sep 11 01:56:17 PM UTC 24 |
| Finished | Sep 11 01:56:22 PM UTC 24 |
| Peak memory | 233672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657821727 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.2657821727 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/18.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2917087718 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 127318067 ps |
| CPU time | 3.82 seconds |
| Started | Sep 11 01:56:22 PM UTC 24 |
| Finished | Sep 11 01:56:27 PM UTC 24 |
| Peak memory | 231500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2917087718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr _mem_rw_with_rand_reset.2917087718 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/19.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.2189701081 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 25179354 ps |
| CPU time | 1.58 seconds |
| Started | Sep 11 01:56:21 PM UTC 24 |
| Finished | Sep 11 01:56:24 PM UTC 24 |
| Peak memory | 218776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189701081 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.2189701081 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/19.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.2466175839 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 16338481 ps |
| CPU time | 1.06 seconds |
| Started | Sep 11 01:56:21 PM UTC 24 |
| Finished | Sep 11 01:56:24 PM UTC 24 |
| Peak memory | 218988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466175839 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.2466175839 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/19.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1705494286 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 52050815 ps |
| CPU time | 1.97 seconds |
| Started | Sep 11 01:56:22 PM UTC 24 |
| Finished | Sep 11 01:56:25 PM UTC 24 |
| Peak memory | 228920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705494286 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr_outstanding.1705494286 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/19.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.55034723 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 76639685 ps |
| CPU time | 1.36 seconds |
| Started | Sep 11 01:56:19 PM UTC 24 |
| Finished | Sep 11 01:56:22 PM UTC 24 |
| Peak memory | 218684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55034723 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors.55034723 +enable_masking= 0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/19.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.250712209 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 53117035 ps |
| CPU time | 2.4 seconds |
| Started | Sep 11 01:56:19 PM UTC 24 |
| Finished | Sep 11 01:56:23 PM UTC 24 |
| Peak memory | 236880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250712209 -asse rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors_with_csr_rw. 250712209 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.957751346 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 78955097 ps |
| CPU time | 3.52 seconds |
| Started | Sep 11 01:56:20 PM UTC 24 |
| Finished | Sep 11 01:56:25 PM UTC 24 |
| Peak memory | 229684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957751346 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.957751346 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/19.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.784316773 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 212682143 ps |
| CPU time | 5.95 seconds |
| Started | Sep 11 01:56:20 PM UTC 24 |
| Finished | Sep 11 01:56:27 PM UTC 24 |
| Peak memory | 229444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784316773 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.784316773 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/19.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.797115215 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 275553860 ps |
| CPU time | 7.74 seconds |
| Started | Sep 11 01:55:16 PM UTC 24 |
| Finished | Sep 11 01:55:25 PM UTC 24 |
| Peak memory | 219144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797115215 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.797115215 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.4234999928 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 1329876553 ps |
| CPU time | 25.79 seconds |
| Started | Sep 11 01:55:15 PM UTC 24 |
| Finished | Sep 11 01:55:42 PM UTC 24 |
| Peak memory | 219268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234999928 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.4234999928 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_hw_reset.1926978234 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 78106139 ps |
| CPU time | 1.39 seconds |
| Started | Sep 11 01:55:14 PM UTC 24 |
| Finished | Sep 11 01:55:16 PM UTC 24 |
| Peak memory | 218984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926978234 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.1926978234 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.4042202954 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 38008844 ps |
| CPU time | 3.35 seconds |
| Started | Sep 11 01:55:17 PM UTC 24 |
| Finished | Sep 11 01:55:22 PM UTC 24 |
| Peak memory | 231500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4042202954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_ mem_rw_with_rand_reset.4042202954 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_rw.1906687991 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 99998721 ps |
| CPU time | 1.73 seconds |
| Started | Sep 11 01:55:14 PM UTC 24 |
| Finished | Sep 11 01:55:17 PM UTC 24 |
| Peak memory | 218936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906687991 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.1906687991 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_intr_test.295678358 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 122591084 ps |
| CPU time | 1.18 seconds |
| Started | Sep 11 01:55:13 PM UTC 24 |
| Finished | Sep 11 01:55:15 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295678358 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.295678358 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_partial_access.2807799159 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 27809462 ps |
| CPU time | 1.65 seconds |
| Started | Sep 11 01:55:11 PM UTC 24 |
| Finished | Sep 11 01:55:13 PM UTC 24 |
| Peak memory | 228864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807799159 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial_access.2807799159 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_walk.3257222768 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 38071021 ps |
| CPU time | 1.07 seconds |
| Started | Sep 11 01:55:11 PM UTC 24 |
| Finished | Sep 11 01:55:13 PM UTC 24 |
| Peak memory | 219048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257222768 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.3257222768 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_same_csr_outstanding.799989398 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 259802719 ps |
| CPU time | 4.62 seconds |
| Started | Sep 11 01:55:17 PM UTC 24 |
| Finished | Sep 11 01:55:23 PM UTC 24 |
| Peak memory | 229444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799989398 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_outstanding.799989398 +enable_m asking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors.911781560 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 50704633 ps |
| CPU time | 2.11 seconds |
| Started | Sep 11 01:55:08 PM UTC 24 |
| Finished | Sep 11 01:55:11 PM UTC 24 |
| Peak memory | 229980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911781560 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors.911781560 +enable_masking =0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.2551343885 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 213311610 ps |
| CPU time | 3.31 seconds |
| Started | Sep 11 01:55:08 PM UTC 24 |
| Finished | Sep 11 01:55:12 PM UTC 24 |
| Peak memory | 229460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551343885 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors_with_csr_rw. 2551343885 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_errors.1383090887 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 39891992 ps |
| CPU time | 2.77 seconds |
| Started | Sep 11 01:55:11 PM UTC 24 |
| Finished | Sep 11 01:55:15 PM UTC 24 |
| Peak memory | 229500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383090887 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.1383090887 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_intg_err.1831738687 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 235350850 ps |
| CPU time | 3.5 seconds |
| Started | Sep 11 01:55:12 PM UTC 24 |
| Finished | Sep 11 01:55:16 PM UTC 24 |
| Peak memory | 219336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831738687 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.1831738687 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.1709808885 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 27603893 ps |
| CPU time | 1.11 seconds |
| Started | Sep 11 01:56:22 PM UTC 24 |
| Finished | Sep 11 01:56:24 PM UTC 24 |
| Peak memory | 218988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709808885 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.1709808885 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/20.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.1981834802 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 21296115 ps |
| CPU time | 1.26 seconds |
| Started | Sep 11 01:56:23 PM UTC 24 |
| Finished | Sep 11 01:56:25 PM UTC 24 |
| Peak memory | 218984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981834802 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.1981834802 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/21.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.428619341 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 44939341 ps |
| CPU time | 1.04 seconds |
| Started | Sep 11 01:56:23 PM UTC 24 |
| Finished | Sep 11 01:56:25 PM UTC 24 |
| Peak memory | 218928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428619341 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.428619341 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/22.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.771314830 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 24769938 ps |
| CPU time | 1.13 seconds |
| Started | Sep 11 01:56:23 PM UTC 24 |
| Finished | Sep 11 01:56:25 PM UTC 24 |
| Peak memory | 218912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771314830 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.771314830 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/23.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.269812809 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 32985834 ps |
| CPU time | 1.14 seconds |
| Started | Sep 11 01:56:24 PM UTC 24 |
| Finished | Sep 11 01:56:26 PM UTC 24 |
| Peak memory | 218868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269812809 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.269812809 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/24.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.652394380 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 23150435 ps |
| CPU time | 1.19 seconds |
| Started | Sep 11 01:56:24 PM UTC 24 |
| Finished | Sep 11 01:56:26 PM UTC 24 |
| Peak memory | 218948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652394380 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.652394380 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/25.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.1882939208 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 20671971 ps |
| CPU time | 1.19 seconds |
| Started | Sep 11 01:56:24 PM UTC 24 |
| Finished | Sep 11 01:56:26 PM UTC 24 |
| Peak memory | 218988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882939208 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.1882939208 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/26.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.2198476981 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 18445045 ps |
| CPU time | 1.23 seconds |
| Started | Sep 11 01:56:25 PM UTC 24 |
| Finished | Sep 11 01:56:28 PM UTC 24 |
| Peak memory | 218928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198476981 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.2198476981 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/27.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.2493070133 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 41679479 ps |
| CPU time | 1.15 seconds |
| Started | Sep 11 01:56:25 PM UTC 24 |
| Finished | Sep 11 01:56:28 PM UTC 24 |
| Peak memory | 218872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493070133 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.2493070133 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/28.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.2375286753 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 15175484 ps |
| CPU time | 1.11 seconds |
| Started | Sep 11 01:56:25 PM UTC 24 |
| Finished | Sep 11 01:56:27 PM UTC 24 |
| Peak memory | 218988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375286753 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.2375286753 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/29.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.176049563 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 210675793 ps |
| CPU time | 11.24 seconds |
| Started | Sep 11 01:55:26 PM UTC 24 |
| Finished | Sep 11 01:55:38 PM UTC 24 |
| Peak memory | 229384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176049563 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.176049563 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.797074176 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 3567449378 ps |
| CPU time | 27.5 seconds |
| Started | Sep 11 01:55:24 PM UTC 24 |
| Finished | Sep 11 01:55:53 PM UTC 24 |
| Peak memory | 219336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797074176 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.797074176 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_hw_reset.3239850475 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 53797886 ps |
| CPU time | 1.27 seconds |
| Started | Sep 11 01:55:23 PM UTC 24 |
| Finished | Sep 11 01:55:25 PM UTC 24 |
| Peak memory | 218984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239850475 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.3239850475 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.1773845869 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 164497069 ps |
| CPU time | 3.75 seconds |
| Started | Sep 11 01:55:26 PM UTC 24 |
| Finished | Sep 11 01:55:31 PM UTC 24 |
| Peak memory | 231444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1773845869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_ mem_rw_with_rand_reset.1773845869 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_rw.3131628101 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 102506555 ps |
| CPU time | 1.7 seconds |
| Started | Sep 11 01:55:24 PM UTC 24 |
| Finished | Sep 11 01:55:26 PM UTC 24 |
| Peak memory | 228920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131628101 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.3131628101 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_intr_test.185921354 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 13522007 ps |
| CPU time | 1.13 seconds |
| Started | Sep 11 01:55:23 PM UTC 24 |
| Finished | Sep 11 01:55:25 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185921354 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.185921354 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_partial_access.4192161502 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 32977670 ps |
| CPU time | 2.13 seconds |
| Started | Sep 11 01:55:21 PM UTC 24 |
| Finished | Sep 11 01:55:25 PM UTC 24 |
| Peak memory | 229572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192161502 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial_access.4192161502 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_walk.3328648000 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 30722099 ps |
| CPU time | 1.06 seconds |
| Started | Sep 11 01:55:21 PM UTC 24 |
| Finished | Sep 11 01:55:23 PM UTC 24 |
| Peak memory | 219048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328648000 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.3328648000 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_same_csr_outstanding.190015023 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 91489885 ps |
| CPU time | 2.2 seconds |
| Started | Sep 11 01:55:26 PM UTC 24 |
| Finished | Sep 11 01:55:29 PM UTC 24 |
| Peak memory | 229384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190015023 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_outstanding.190015023 +enable_m asking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors.2153113904 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 52288629 ps |
| CPU time | 1.45 seconds |
| Started | Sep 11 01:55:17 PM UTC 24 |
| Finished | Sep 11 01:55:20 PM UTC 24 |
| Peak memory | 228860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153113904 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors.2153113904 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.1060416663 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 121473735 ps |
| CPU time | 3.32 seconds |
| Started | Sep 11 01:55:17 PM UTC 24 |
| Finished | Sep 11 01:55:22 PM UTC 24 |
| Peak memory | 237056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060416663 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors_with_csr_rw. 1060416663 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_errors.1390795098 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 31744196 ps |
| CPU time | 2.57 seconds |
| Started | Sep 11 01:55:21 PM UTC 24 |
| Finished | Sep 11 01:55:25 PM UTC 24 |
| Peak memory | 229560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390795098 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.1390795098 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_intg_err.1255284730 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 311012352 ps |
| CPU time | 5.18 seconds |
| Started | Sep 11 01:55:23 PM UTC 24 |
| Finished | Sep 11 01:55:29 PM UTC 24 |
| Peak memory | 231492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255284730 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.1255284730 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.1959564151 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 47344646 ps |
| CPU time | 1.04 seconds |
| Started | Sep 11 01:56:25 PM UTC 24 |
| Finished | Sep 11 01:56:27 PM UTC 24 |
| Peak memory | 219048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959564151 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.1959564151 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/30.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.89672451 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 19046477 ps |
| CPU time | 1.19 seconds |
| Started | Sep 11 01:56:25 PM UTC 24 |
| Finished | Sep 11 01:56:28 PM UTC 24 |
| Peak memory | 219052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89672451 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.89672451 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/31.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.172960819 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 16295014 ps |
| CPU time | 1.21 seconds |
| Started | Sep 11 01:56:26 PM UTC 24 |
| Finished | Sep 11 01:56:29 PM UTC 24 |
| Peak memory | 218928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172960819 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.172960819 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/32.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.3584915912 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 31406543 ps |
| CPU time | 1.18 seconds |
| Started | Sep 11 01:56:26 PM UTC 24 |
| Finished | Sep 11 01:56:29 PM UTC 24 |
| Peak memory | 218988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584915912 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.3584915912 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/33.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.1366216482 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 49972193 ps |
| CPU time | 1.09 seconds |
| Started | Sep 11 01:56:26 PM UTC 24 |
| Finished | Sep 11 01:56:29 PM UTC 24 |
| Peak memory | 218988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366216482 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.1366216482 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/34.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.591212149 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 29455908 ps |
| CPU time | 1.17 seconds |
| Started | Sep 11 01:56:26 PM UTC 24 |
| Finished | Sep 11 01:56:29 PM UTC 24 |
| Peak memory | 218928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591212149 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.591212149 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/35.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.1173183578 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 37030449 ps |
| CPU time | 1.18 seconds |
| Started | Sep 11 01:56:28 PM UTC 24 |
| Finished | Sep 11 01:56:30 PM UTC 24 |
| Peak memory | 218988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173183578 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.1173183578 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/36.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.1425112469 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 13644770 ps |
| CPU time | 1.18 seconds |
| Started | Sep 11 01:56:28 PM UTC 24 |
| Finished | Sep 11 01:56:30 PM UTC 24 |
| Peak memory | 218988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425112469 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.1425112469 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/37.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.2624984209 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 23099443 ps |
| CPU time | 1.11 seconds |
| Started | Sep 11 01:56:28 PM UTC 24 |
| Finished | Sep 11 01:56:30 PM UTC 24 |
| Peak memory | 218988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624984209 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.2624984209 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/38.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.1311582412 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 13466734 ps |
| CPU time | 1.16 seconds |
| Started | Sep 11 01:56:28 PM UTC 24 |
| Finished | Sep 11 01:56:30 PM UTC 24 |
| Peak memory | 218988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311582412 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.1311582412 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/39.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.639919581 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 838462726 ps |
| CPU time | 7.21 seconds |
| Started | Sep 11 01:55:33 PM UTC 24 |
| Finished | Sep 11 01:55:41 PM UTC 24 |
| Peak memory | 219332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639919581 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.639919581 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.932154779 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 2901240419 ps |
| CPU time | 15.64 seconds |
| Started | Sep 11 01:55:32 PM UTC 24 |
| Finished | Sep 11 01:55:48 PM UTC 24 |
| Peak memory | 219208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932154779 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.932154779 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_hw_reset.679779459 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 18826005 ps |
| CPU time | 1.67 seconds |
| Started | Sep 11 01:55:30 PM UTC 24 |
| Finished | Sep 11 01:55:33 PM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679779459 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.679779459 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.596779935 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 25649841 ps |
| CPU time | 2.09 seconds |
| Started | Sep 11 01:55:36 PM UTC 24 |
| Finished | Sep 11 01:55:39 PM UTC 24 |
| Peak memory | 229452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=596779935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_m em_rw_with_rand_reset.596779935 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.368600312 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 16985076 ps |
| CPU time | 1.73 seconds |
| Started | Sep 11 01:55:30 PM UTC 24 |
| Finished | Sep 11 01:55:33 PM UTC 24 |
| Peak memory | 218900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368600312 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.368600312 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_intr_test.268556283 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 16854285 ps |
| CPU time | 1.16 seconds |
| Started | Sep 11 01:55:30 PM UTC 24 |
| Finished | Sep 11 01:55:33 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268556283 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.268556283 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_partial_access.1440591103 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 20227702 ps |
| CPU time | 1.64 seconds |
| Started | Sep 11 01:55:29 PM UTC 24 |
| Finished | Sep 11 01:55:32 PM UTC 24 |
| Peak memory | 228860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440591103 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial_access.1440591103 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_walk.3426136665 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 11629051 ps |
| CPU time | 1.03 seconds |
| Started | Sep 11 01:55:27 PM UTC 24 |
| Finished | Sep 11 01:55:29 PM UTC 24 |
| Peak memory | 219048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426136665 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.3426136665 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.3895953683 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 23769090 ps |
| CPU time | 2.07 seconds |
| Started | Sep 11 01:55:36 PM UTC 24 |
| Finished | Sep 11 01:55:39 PM UTC 24 |
| Peak memory | 229324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895953683 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_outstanding.3895953683 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors.2343488165 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 28494634 ps |
| CPU time | 1.39 seconds |
| Started | Sep 11 01:55:26 PM UTC 24 |
| Finished | Sep 11 01:55:28 PM UTC 24 |
| Peak memory | 218628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343488165 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors.2343488165 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.3026280244 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 36460115 ps |
| CPU time | 2.1 seconds |
| Started | Sep 11 01:55:26 PM UTC 24 |
| Finished | Sep 11 01:55:29 PM UTC 24 |
| Peak memory | 229768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026280244 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors_with_csr_rw. 3026280244 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.3802022255 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 52240764 ps |
| CPU time | 4.87 seconds |
| Started | Sep 11 01:55:29 PM UTC 24 |
| Finished | Sep 11 01:55:35 PM UTC 24 |
| Peak memory | 229500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802022255 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.3802022255 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.1308534107 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 46090435 ps |
| CPU time | 1.19 seconds |
| Started | Sep 11 01:56:29 PM UTC 24 |
| Finished | Sep 11 01:56:31 PM UTC 24 |
| Peak memory | 218988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308534107 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.1308534107 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/40.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.1417540278 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 41270799 ps |
| CPU time | 1.11 seconds |
| Started | Sep 11 01:56:29 PM UTC 24 |
| Finished | Sep 11 01:56:31 PM UTC 24 |
| Peak memory | 219048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417540278 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.1417540278 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/41.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.2404906039 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 45370527 ps |
| CPU time | 1.07 seconds |
| Started | Sep 11 01:56:29 PM UTC 24 |
| Finished | Sep 11 01:56:31 PM UTC 24 |
| Peak memory | 219048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404906039 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.2404906039 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/42.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.1194417273 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 14744935 ps |
| CPU time | 1.07 seconds |
| Started | Sep 11 01:56:29 PM UTC 24 |
| Finished | Sep 11 01:56:31 PM UTC 24 |
| Peak memory | 218988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194417273 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.1194417273 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/43.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.1447439359 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 12536029 ps |
| CPU time | 1.09 seconds |
| Started | Sep 11 01:56:29 PM UTC 24 |
| Finished | Sep 11 01:56:31 PM UTC 24 |
| Peak memory | 218988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447439359 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.1447439359 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/44.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.1957062611 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 70217963 ps |
| CPU time | 1.07 seconds |
| Started | Sep 11 01:56:29 PM UTC 24 |
| Finished | Sep 11 01:56:31 PM UTC 24 |
| Peak memory | 218988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957062611 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.1957062611 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/45.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.1529224347 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 12510554 ps |
| CPU time | 1.1 seconds |
| Started | Sep 11 01:56:30 PM UTC 24 |
| Finished | Sep 11 01:56:32 PM UTC 24 |
| Peak memory | 218924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529224347 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.1529224347 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/46.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.2831265238 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 13822315 ps |
| CPU time | 1.1 seconds |
| Started | Sep 11 01:56:30 PM UTC 24 |
| Finished | Sep 11 01:56:32 PM UTC 24 |
| Peak memory | 218924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831265238 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.2831265238 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/47.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.960837633 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 111190737 ps |
| CPU time | 1.15 seconds |
| Started | Sep 11 01:56:30 PM UTC 24 |
| Finished | Sep 11 01:56:32 PM UTC 24 |
| Peak memory | 218988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960837633 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.960837633 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/48.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.555311989 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 13611066 ps |
| CPU time | 0.9 seconds |
| Started | Sep 11 01:56:30 PM UTC 24 |
| Finished | Sep 11 01:56:32 PM UTC 24 |
| Peak memory | 218928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555311989 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.555311989 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/49.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.49523943 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 139884009 ps |
| CPU time | 3.86 seconds |
| Started | Sep 11 01:55:41 PM UTC 24 |
| Finished | Sep 11 01:55:46 PM UTC 24 |
| Peak memory | 236520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=49523943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_me m_rw_with_rand_reset.49523943 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/5.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_rw.1383064695 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 115509145 ps |
| CPU time | 1.55 seconds |
| Started | Sep 11 01:55:39 PM UTC 24 |
| Finished | Sep 11 01:55:42 PM UTC 24 |
| Peak memory | 218800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383064695 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.1383064695 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/5.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.2056537030 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 16320085 ps |
| CPU time | 1.26 seconds |
| Started | Sep 11 01:55:39 PM UTC 24 |
| Finished | Sep 11 01:55:41 PM UTC 24 |
| Peak memory | 218856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056537030 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.2056537030 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/5.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_same_csr_outstanding.2168648495 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 54858840 ps |
| CPU time | 2.36 seconds |
| Started | Sep 11 01:55:41 PM UTC 24 |
| Finished | Sep 11 01:55:44 PM UTC 24 |
| Peak memory | 229384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168648495 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_outstanding.2168648495 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/5.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.2622125679 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 120517511 ps |
| CPU time | 1.89 seconds |
| Started | Sep 11 01:55:36 PM UTC 24 |
| Finished | Sep 11 01:55:39 PM UTC 24 |
| Peak memory | 228792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622125679 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors.2622125679 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2225841841 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 755748621 ps |
| CPU time | 3.18 seconds |
| Started | Sep 11 01:55:36 PM UTC 24 |
| Finished | Sep 11 01:55:40 PM UTC 24 |
| Peak memory | 229520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225841841 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors_with_csr_rw. 2225841841 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.3205118072 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 621563005 ps |
| CPU time | 4.83 seconds |
| Started | Sep 11 01:55:36 PM UTC 24 |
| Finished | Sep 11 01:55:42 PM UTC 24 |
| Peak memory | 229500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205118072 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.3205118072 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/5.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.2828832191 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 357929930 ps |
| CPU time | 4.21 seconds |
| Started | Sep 11 01:55:36 PM UTC 24 |
| Finished | Sep 11 01:55:41 PM UTC 24 |
| Peak memory | 229444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828832191 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.2828832191 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/5.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.975191073 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 70465893 ps |
| CPU time | 3.55 seconds |
| Started | Sep 11 01:55:44 PM UTC 24 |
| Finished | Sep 11 01:55:48 PM UTC 24 |
| Peak memory | 231496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=975191073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_m em_rw_with_rand_reset.975191073 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/6.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_rw.3562097968 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 63166000 ps |
| CPU time | 1.32 seconds |
| Started | Sep 11 01:55:43 PM UTC 24 |
| Finished | Sep 11 01:55:45 PM UTC 24 |
| Peak memory | 218980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562097968 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.3562097968 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/6.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_intr_test.1410579888 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 37639795 ps |
| CPU time | 1.17 seconds |
| Started | Sep 11 01:55:42 PM UTC 24 |
| Finished | Sep 11 01:55:45 PM UTC 24 |
| Peak memory | 218988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410579888 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.1410579888 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/6.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.202891556 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 293810555 ps |
| CPU time | 2.28 seconds |
| Started | Sep 11 01:55:43 PM UTC 24 |
| Finished | Sep 11 01:55:46 PM UTC 24 |
| Peak memory | 229568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202891556 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_outstanding.202891556 +enable_m asking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/6.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3195669114 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 322802031 ps |
| CPU time | 2.17 seconds |
| Started | Sep 11 01:55:41 PM UTC 24 |
| Finished | Sep 11 01:55:44 PM UTC 24 |
| Peak memory | 229796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195669114 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors.3195669114 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.2196581914 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 32290966 ps |
| CPU time | 2.22 seconds |
| Started | Sep 11 01:55:41 PM UTC 24 |
| Finished | Sep 11 01:55:45 PM UTC 24 |
| Peak memory | 229852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196581914 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors_with_csr_rw. 2196581914 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.1235922167 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 51617401 ps |
| CPU time | 4.58 seconds |
| Started | Sep 11 01:55:42 PM UTC 24 |
| Finished | Sep 11 01:55:48 PM UTC 24 |
| Peak memory | 229504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235922167 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.1235922167 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/6.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.2580342017 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 57767847 ps |
| CPU time | 3.16 seconds |
| Started | Sep 11 01:55:42 PM UTC 24 |
| Finished | Sep 11 01:55:47 PM UTC 24 |
| Peak memory | 229592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580342017 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.2580342017 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/6.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.2719732011 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 134337668 ps |
| CPU time | 2.57 seconds |
| Started | Sep 11 01:55:48 PM UTC 24 |
| Finished | Sep 11 01:55:52 PM UTC 24 |
| Peak memory | 231500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2719732011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_ mem_rw_with_rand_reset.2719732011 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/7.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.4067957990 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 16476207 ps |
| CPU time | 1.28 seconds |
| Started | Sep 11 01:55:47 PM UTC 24 |
| Finished | Sep 11 01:55:49 PM UTC 24 |
| Peak memory | 218980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067957990 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.4067957990 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/7.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.1314979133 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 20763877 ps |
| CPU time | 1.15 seconds |
| Started | Sep 11 01:55:46 PM UTC 24 |
| Finished | Sep 11 01:55:48 PM UTC 24 |
| Peak memory | 219040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314979133 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.1314979133 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/7.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3453005677 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 1790894729 ps |
| CPU time | 4.83 seconds |
| Started | Sep 11 01:55:47 PM UTC 24 |
| Finished | Sep 11 01:55:53 PM UTC 24 |
| Peak memory | 229384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453005677 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_outstanding.3453005677 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/7.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors.3150218899 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 67175897 ps |
| CPU time | 2.36 seconds |
| Started | Sep 11 01:55:46 PM UTC 24 |
| Finished | Sep 11 01:55:49 PM UTC 24 |
| Peak memory | 229796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150218899 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors.3150218899 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.345684028 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 124670809 ps |
| CPU time | 3.2 seconds |
| Started | Sep 11 01:55:46 PM UTC 24 |
| Finished | Sep 11 01:55:50 PM UTC 24 |
| Peak memory | 229800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345684028 -asse rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors_with_csr_rw.3 45684028 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.746705745 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 663032985 ps |
| CPU time | 6.21 seconds |
| Started | Sep 11 01:55:46 PM UTC 24 |
| Finished | Sep 11 01:55:53 PM UTC 24 |
| Peak memory | 229704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746705745 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.746705745 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/7.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.3139916362 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 435357088 ps |
| CPU time | 4.14 seconds |
| Started | Sep 11 01:55:46 PM UTC 24 |
| Finished | Sep 11 01:55:51 PM UTC 24 |
| Peak memory | 229464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139916362 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.3139916362 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/7.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.4102697099 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 45412072 ps |
| CPU time | 2.26 seconds |
| Started | Sep 11 01:55:53 PM UTC 24 |
| Finished | Sep 11 01:55:56 PM UTC 24 |
| Peak memory | 229452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4102697099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_ mem_rw_with_rand_reset.4102697099 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/8.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.3166560408 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 19265123 ps |
| CPU time | 1.48 seconds |
| Started | Sep 11 01:55:50 PM UTC 24 |
| Finished | Sep 11 01:55:53 PM UTC 24 |
| Peak memory | 228920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166560408 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.3166560408 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/8.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.2600420027 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 18064593 ps |
| CPU time | 1.1 seconds |
| Started | Sep 11 01:55:50 PM UTC 24 |
| Finished | Sep 11 01:55:53 PM UTC 24 |
| Peak memory | 219040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600420027 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.2600420027 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/8.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.604984618 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 222879394 ps |
| CPU time | 2.28 seconds |
| Started | Sep 11 01:55:52 PM UTC 24 |
| Finished | Sep 11 01:55:55 PM UTC 24 |
| Peak memory | 229356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604984618 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_outstanding.604984618 +enable_m asking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/8.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.296299069 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 28829368 ps |
| CPU time | 1.71 seconds |
| Started | Sep 11 01:55:49 PM UTC 24 |
| Finished | Sep 11 01:55:52 PM UTC 24 |
| Peak memory | 228664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296299069 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors.296299069 +enable_masking =0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.342344448 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 58539061 ps |
| CPU time | 2.5 seconds |
| Started | Sep 11 01:55:49 PM UTC 24 |
| Finished | Sep 11 01:55:53 PM UTC 24 |
| Peak memory | 229764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342344448 -asse rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors_with_csr_rw.3 42344448 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.1525270141 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 50592097 ps |
| CPU time | 4.31 seconds |
| Started | Sep 11 01:55:49 PM UTC 24 |
| Finished | Sep 11 01:55:55 PM UTC 24 |
| Peak memory | 229692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525270141 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.1525270141 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/8.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.3060765159 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 2480001477 ps |
| CPU time | 4.11 seconds |
| Started | Sep 11 01:55:49 PM UTC 24 |
| Finished | Sep 11 01:55:54 PM UTC 24 |
| Peak memory | 219288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060765159 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.3060765159 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/8.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.4103812560 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 139758839 ps |
| CPU time | 2.6 seconds |
| Started | Sep 11 01:55:54 PM UTC 24 |
| Finished | Sep 11 01:55:58 PM UTC 24 |
| Peak memory | 231500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4103812560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_ mem_rw_with_rand_reset.4103812560 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/9.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.261626009 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 15588416 ps |
| CPU time | 1.67 seconds |
| Started | Sep 11 01:55:54 PM UTC 24 |
| Finished | Sep 11 01:55:57 PM UTC 24 |
| Peak memory | 228924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261626009 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.261626009 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/9.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.3985414280 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 16044476 ps |
| CPU time | 1.15 seconds |
| Started | Sep 11 01:55:54 PM UTC 24 |
| Finished | Sep 11 01:55:56 PM UTC 24 |
| Peak memory | 219040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985414280 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.3985414280 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/9.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.613132753 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 97860423 ps |
| CPU time | 3.59 seconds |
| Started | Sep 11 01:55:54 PM UTC 24 |
| Finished | Sep 11 01:55:59 PM UTC 24 |
| Peak memory | 229512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613132753 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_outstanding.613132753 +enable_m asking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/9.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.834585068 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 48156323 ps |
| CPU time | 2.3 seconds |
| Started | Sep 11 01:55:53 PM UTC 24 |
| Finished | Sep 11 01:55:56 PM UTC 24 |
| Peak memory | 229776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834585068 -asse rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors_with_csr_rw.8 34585068 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.2309805239 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 165496648 ps |
| CPU time | 7.31 seconds |
| Started | Sep 11 01:55:54 PM UTC 24 |
| Finished | Sep 11 01:56:02 PM UTC 24 |
| Peak memory | 229536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309805239 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.2309805239 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/9.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.792646954 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 178342102 ps |
| CPU time | 4.21 seconds |
| Started | Sep 11 01:55:54 PM UTC 24 |
| Finished | Sep 11 01:55:59 PM UTC 24 |
| Peak memory | 229444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792646954 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.792646954 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/9.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/0.kmac_app.1026228231 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 12860412703 ps |
| CPU time | 135.81 seconds |
| Started | Sep 11 03:50:44 PM UTC 24 |
| Finished | Sep 11 03:53:03 PM UTC 24 |
| Peak memory | 364328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026228231 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.1026228231 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/0.kmac_burst_write.4119074194 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 137384047993 ps |
| CPU time | 628.72 seconds |
| Started | Sep 11 03:50:08 PM UTC 24 |
| Finished | Sep 11 04:00:45 PM UTC 24 |
| Peak memory | 259984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119074194 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.4119074194 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/0.kmac_edn_timeout_error.113402597 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 1845891181 ps |
| CPU time | 23.88 seconds |
| Started | Sep 11 03:51:23 PM UTC 24 |
| Finished | Sep 11 03:51:48 PM UTC 24 |
| Peak memory | 232316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113402597 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.113402597 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_mode_error.2969976983 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3224912941 ps |
| CPU time | 34.38 seconds |
| Started | Sep 11 03:51:28 PM UTC 24 |
| Finished | Sep 11 03:52:03 PM UTC 24 |
| Peak memory | 232448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969976983 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.2969976983 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_refresh.540644724 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 14191329269 ps |
| CPU time | 344.51 seconds |
| Started | Sep 11 03:50:48 PM UTC 24 |
| Finished | Sep 11 03:56:37 PM UTC 24 |
| Peak memory | 475172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540644724 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.540644724 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/0.kmac_long_msg_and_output.2872662142 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1450605910 ps |
| CPU time | 140.64 seconds |
| Started | Sep 11 03:50:00 PM UTC 24 |
| Finished | Sep 11 03:52:23 PM UTC 24 |
| Peak memory | 305048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872662142 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_and_output.2872662142 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/0.kmac_sideload.1503600302 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 55814829729 ps |
| CPU time | 329.67 seconds |
| Started | Sep 11 03:50:08 PM UTC 24 |
| Finished | Sep 11 03:55:43 PM UTC 24 |
| Peak memory | 503796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503600302 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.1503600302 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/0.kmac_smoke.2114805784 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1517239567 ps |
| CPU time | 13.74 seconds |
| Started | Sep 11 03:49:54 PM UTC 24 |
| Finished | Sep 11 03:50:09 PM UTC 24 |
| Peak memory | 232616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114805784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.2114805784 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/0.kmac_stress_all.2950306758 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 374251253067 ps |
| CPU time | 2542.75 seconds |
| Started | Sep 11 03:51:33 PM UTC 24 |
| Finished | Sep 11 04:34:24 PM UTC 24 |
| Peak memory | 1397092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950306758 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.2950306758 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac.4044260968 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 86537464 ps |
| CPU time | 3.83 seconds |
| Started | Sep 11 03:50:34 PM UTC 24 |
| Finished | Sep 11 03:50:40 PM UTC 24 |
| Peak memory | 230464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044260968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac.4044260968 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac_xof.3970689323 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 44310631 ps |
| CPU time | 2.88 seconds |
| Started | Sep 11 03:50:40 PM UTC 24 |
| Finished | Sep 11 03:50:44 PM UTC 24 |
| Peak memory | 230464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970689323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.3970689323 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_224.798591449 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 653529175 ps |
| CPU time | 40.22 seconds |
| Started | Sep 11 03:50:11 PM UTC 24 |
| Finished | Sep 11 03:50:53 PM UTC 24 |
| Peak memory | 232256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798591449 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.798591449 + enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_256.701414698 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 17264858656 ps |
| CPU time | 1708.03 seconds |
| Started | Sep 11 03:50:11 PM UTC 24 |
| Finished | Sep 11 04:18:59 PM UTC 24 |
| Peak memory | 1125600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701414698 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.701414698 + enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_384.153593373 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 867340221 ps |
| CPU time | 32.97 seconds |
| Started | Sep 11 03:50:12 PM UTC 24 |
| Finished | Sep 11 03:50:46 PM UTC 24 |
| Peak memory | 228588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153593373 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.153593373 + enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_512.4167045008 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 46646692898 ps |
| CPU time | 1211.06 seconds |
| Started | Sep 11 03:50:16 PM UTC 24 |
| Finished | Sep 11 04:10:41 PM UTC 24 |
| Peak memory | 1715860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167045008 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.4167045008 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_128.2837371276 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 13919843617 ps |
| CPU time | 256.45 seconds |
| Started | Sep 11 03:50:28 PM UTC 24 |
| Finished | Sep 11 03:54:49 PM UTC 24 |
| Peak memory | 280272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837371276 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.2837371 276 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/1.kmac_alert_test.3200336659 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 22160660 ps |
| CPU time | 1.3 seconds |
| Started | Sep 11 03:53:38 PM UTC 24 |
| Finished | Sep 11 03:53:40 PM UTC 24 |
| Peak memory | 216280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200336659 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.3200336659 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/1.kmac_app.1804465892 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 29517194190 ps |
| CPU time | 305.97 seconds |
| Started | Sep 11 03:52:45 PM UTC 24 |
| Finished | Sep 11 03:57:55 PM UTC 24 |
| Peak memory | 509704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804465892 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.1804465892 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/1.kmac_app_with_partial_data.1182078237 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3247652614 ps |
| CPU time | 122.12 seconds |
| Started | Sep 11 03:52:47 PM UTC 24 |
| Finished | Sep 11 03:54:51 PM UTC 24 |
| Peak memory | 274156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182078237 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.1182078237 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/1.kmac_burst_write.2992972601 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 45657148655 ps |
| CPU time | 803.98 seconds |
| Started | Sep 11 03:51:57 PM UTC 24 |
| Finished | Sep 11 04:05:32 PM UTC 24 |
| Peak memory | 261868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992972601 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.2992972601 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/1.kmac_edn_timeout_error.2668424002 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 1113259429 ps |
| CPU time | 43.93 seconds |
| Started | Sep 11 03:52:54 PM UTC 24 |
| Finished | Sep 11 03:53:39 PM UTC 24 |
| Peak memory | 232504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668424002 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.2668424002 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_mode_error.651158686 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 1187088799 ps |
| CPU time | 12.75 seconds |
| Started | Sep 11 03:52:58 PM UTC 24 |
| Finished | Sep 11 03:53:12 PM UTC 24 |
| Peak memory | 232496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651158686 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.651158686 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_ready_error.864869604 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 4985009895 ps |
| CPU time | 56.12 seconds |
| Started | Sep 11 03:53:03 PM UTC 24 |
| Finished | Sep 11 03:54:01 PM UTC 24 |
| Peak memory | 230660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864869604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_u nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.864869604 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_refresh.2202101457 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 30176931930 ps |
| CPU time | 347.96 seconds |
| Started | Sep 11 03:52:47 PM UTC 24 |
| Finished | Sep 11 03:58:40 PM UTC 24 |
| Peak memory | 462756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202101457 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.2202101457 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/1.kmac_error.81783907 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9258686103 ps |
| CPU time | 301.64 seconds |
| Started | Sep 11 03:52:48 PM UTC 24 |
| Finished | Sep 11 03:57:54 PM UTC 24 |
| Peak memory | 472852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81783907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.81783907 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/1.kmac_key_error.3927389627 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 121489418 ps |
| CPU time | 2.18 seconds |
| Started | Sep 11 03:52:54 PM UTC 24 |
| Finished | Sep 11 03:52:57 PM UTC 24 |
| Peak memory | 230444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927389627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.3927389627 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/1.kmac_lc_escalation.27964923 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 45727865 ps |
| CPU time | 2.04 seconds |
| Started | Sep 11 03:53:13 PM UTC 24 |
| Finished | Sep 11 03:53:16 PM UTC 24 |
| Peak memory | 230340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27964923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.27964923 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/1.kmac_long_msg_and_output.157531001 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 6814755113 ps |
| CPU time | 246 seconds |
| Started | Sep 11 03:51:51 PM UTC 24 |
| Finished | Sep 11 03:56:01 PM UTC 24 |
| Peak memory | 550616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157531001 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_and_output.157531001 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/1.kmac_mubi.3421386829 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 26028127560 ps |
| CPU time | 331.47 seconds |
| Started | Sep 11 03:52:48 PM UTC 24 |
| Finished | Sep 11 03:58:24 PM UTC 24 |
| Peak memory | 526380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421386829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.3421386829 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/1.kmac_sec_cm.1110050089 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 26304136271 ps |
| CPU time | 65.41 seconds |
| Started | Sep 11 03:53:25 PM UTC 24 |
| Finished | Sep 11 03:54:33 PM UTC 24 |
| Peak memory | 277408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110050089 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.1110050089 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/1.kmac_sideload.357190933 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3579663513 ps |
| CPU time | 50.5 seconds |
| Started | Sep 11 03:51:53 PM UTC 24 |
| Finished | Sep 11 03:52:46 PM UTC 24 |
| Peak memory | 261876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357190933 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.357190933 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/1.kmac_stress_all.1828521759 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 107033582593 ps |
| CPU time | 1377.17 seconds |
| Started | Sep 11 03:53:17 PM UTC 24 |
| Finished | Sep 11 04:16:31 PM UTC 24 |
| Peak memory | 706736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828521759 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.1828521759 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac.362738346 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 83032267 ps |
| CPU time | 2.68 seconds |
| Started | Sep 11 03:52:42 PM UTC 24 |
| Finished | Sep 11 03:52:46 PM UTC 24 |
| Peak memory | 230452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362738346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_ve ctors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac.362738346 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac_xof.1021625081 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 80289741 ps |
| CPU time | 2.65 seconds |
| Started | Sep 11 03:52:44 PM UTC 24 |
| Finished | Sep 11 03:52:47 PM UTC 24 |
| Peak memory | 230548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021625081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.1021625081 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_224.423201624 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 2575672136 ps |
| CPU time | 40.18 seconds |
| Started | Sep 11 03:52:02 PM UTC 24 |
| Finished | Sep 11 03:52:44 PM UTC 24 |
| Peak memory | 232540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423201624 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.423201624 + enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_384.3388491528 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 62962806904 ps |
| CPU time | 1298.07 seconds |
| Started | Sep 11 03:52:21 PM UTC 24 |
| Finished | Sep 11 04:14:15 PM UTC 24 |
| Peak memory | 902800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388491528 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.3388491528 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_512.3909608691 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 8875540305 ps |
| CPU time | 737.4 seconds |
| Started | Sep 11 03:52:24 PM UTC 24 |
| Finished | Sep 11 04:04:50 PM UTC 24 |
| Peak memory | 698000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909608691 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.3909608691 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_128.1214981374 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 7145208330 ps |
| CPU time | 238.98 seconds |
| Started | Sep 11 03:52:27 PM UTC 24 |
| Finished | Sep 11 03:56:31 PM UTC 24 |
| Peak memory | 241308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214981374 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.1214981 374 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_256.1951708801 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 7210598335 ps |
| CPU time | 146.76 seconds |
| Started | Sep 11 03:52:30 PM UTC 24 |
| Finished | Sep 11 03:55:00 PM UTC 24 |
| Peak memory | 358092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951708801 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.1951708 801 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/10.kmac_alert_test.3526884 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 15102726 ps |
| CPU time | 1.27 seconds |
| Started | Sep 11 04:07:37 PM UTC 24 |
| Finished | Sep 11 04:07:39 PM UTC 24 |
| Peak memory | 216344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526884 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.3526884 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/10.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/10.kmac_app.2214246383 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 54063478837 ps |
| CPU time | 322.65 seconds |
| Started | Sep 11 04:07:12 PM UTC 24 |
| Finished | Sep 11 04:12:39 PM UTC 24 |
| Peak memory | 448252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214246383 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.2214246383 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/10.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/10.kmac_burst_write.2231728548 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 36809998657 ps |
| CPU time | 326.15 seconds |
| Started | Sep 11 04:07:11 PM UTC 24 |
| Finished | Sep 11 04:12:42 PM UTC 24 |
| Peak memory | 245532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231728548 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.2231728548 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/10.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/10.kmac_edn_timeout_error.2266196726 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 1523310702 ps |
| CPU time | 46.27 seconds |
| Started | Sep 11 04:07:22 PM UTC 24 |
| Finished | Sep 11 04:08:10 PM UTC 24 |
| Peak memory | 245404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266196726 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.2266196726 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/10.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/10.kmac_entropy_mode_error.2457988423 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 2409924503 ps |
| CPU time | 19.45 seconds |
| Started | Sep 11 04:07:22 PM UTC 24 |
| Finished | Sep 11 04:07:43 PM UTC 24 |
| Peak memory | 234436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457988423 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.2457988423 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/10.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/10.kmac_entropy_refresh.3472276919 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 5609678482 ps |
| CPU time | 198.53 seconds |
| Started | Sep 11 04:07:12 PM UTC 24 |
| Finished | Sep 11 04:10:34 PM UTC 24 |
| Peak memory | 306892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472276919 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.3472276919 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/10.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/10.kmac_error.3708134509 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 47317888674 ps |
| CPU time | 360.82 seconds |
| Started | Sep 11 04:07:14 PM UTC 24 |
| Finished | Sep 11 04:13:19 PM UTC 24 |
| Peak memory | 564976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708134509 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.3708134509 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/10.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/10.kmac_key_error.2204747409 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 2175406320 ps |
| CPU time | 16.03 seconds |
| Started | Sep 11 04:07:19 PM UTC 24 |
| Finished | Sep 11 04:07:36 PM UTC 24 |
| Peak memory | 230516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204747409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.2204747409 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/10.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/10.kmac_lc_escalation.2872065292 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 121938588 ps |
| CPU time | 2.1 seconds |
| Started | Sep 11 04:07:31 PM UTC 24 |
| Finished | Sep 11 04:07:34 PM UTC 24 |
| Peak memory | 230640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872065292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.2872065292 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/10.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/10.kmac_long_msg_and_output.1677602754 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 152487305545 ps |
| CPU time | 2619.44 seconds |
| Started | Sep 11 04:06:43 PM UTC 24 |
| Finished | Sep 11 04:50:51 PM UTC 24 |
| Peak memory | 1851232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677602754 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_and_output.1677602754 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/10.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/10.kmac_sideload.1697898513 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 21832885813 ps |
| CPU time | 142.47 seconds |
| Started | Sep 11 04:06:51 PM UTC 24 |
| Finished | Sep 11 04:09:17 PM UTC 24 |
| Peak memory | 378596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697898513 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.1697898513 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/10.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/10.kmac_smoke.280576084 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 3083406256 ps |
| CPU time | 35.98 seconds |
| Started | Sep 11 04:06:40 PM UTC 24 |
| Finished | Sep 11 04:07:17 PM UTC 24 |
| Peak memory | 234952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280576084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.280576084 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/10.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/10.kmac_stress_all.986118632 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 90719878586 ps |
| CPU time | 2094.07 seconds |
| Started | Sep 11 04:07:35 PM UTC 24 |
| Finished | Sep 11 04:42:52 PM UTC 24 |
| Peak memory | 1202196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986118632 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.986118632 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/10.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/11.kmac_alert_test.2606371287 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 48070631 ps |
| CPU time | 1.25 seconds |
| Started | Sep 11 04:08:42 PM UTC 24 |
| Finished | Sep 11 04:08:44 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606371287 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.2606371287 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/11.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/11.kmac_app.150254116 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 2807664020 ps |
| CPU time | 97.06 seconds |
| Started | Sep 11 04:08:07 PM UTC 24 |
| Finished | Sep 11 04:09:46 PM UTC 24 |
| Peak memory | 266144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150254116 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.150254116 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/11.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/11.kmac_burst_write.83217626 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 9656003466 ps |
| CPU time | 877.71 seconds |
| Started | Sep 11 04:08:03 PM UTC 24 |
| Finished | Sep 11 04:22:52 PM UTC 24 |
| Peak memory | 251692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83217626 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.83217626 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/11.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/11.kmac_edn_timeout_error.678477775 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 2064118475 ps |
| CPU time | 20.66 seconds |
| Started | Sep 11 04:08:27 PM UTC 24 |
| Finished | Sep 11 04:08:49 PM UTC 24 |
| Peak memory | 228268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678477775 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.678477775 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/11.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/11.kmac_entropy_mode_error.4209529038 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 4935544775 ps |
| CPU time | 40.83 seconds |
| Started | Sep 11 04:08:29 PM UTC 24 |
| Finished | Sep 11 04:09:11 PM UTC 24 |
| Peak memory | 242656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209529038 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.4209529038 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/11.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/11.kmac_entropy_refresh.3932347160 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 34795263269 ps |
| CPU time | 183.55 seconds |
| Started | Sep 11 04:08:10 PM UTC 24 |
| Finished | Sep 11 04:11:17 PM UTC 24 |
| Peak memory | 388876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932347160 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.3932347160 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/11.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/11.kmac_error.20097305 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 79097888735 ps |
| CPU time | 438.78 seconds |
| Started | Sep 11 04:08:13 PM UTC 24 |
| Finished | Sep 11 04:15:38 PM UTC 24 |
| Peak memory | 597920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20097305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.20097305 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/11.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/11.kmac_key_error.4281994701 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 1394113140 ps |
| CPU time | 7.29 seconds |
| Started | Sep 11 04:08:17 PM UTC 24 |
| Finished | Sep 11 04:08:26 PM UTC 24 |
| Peak memory | 230384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281994701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.4281994701 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/11.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/11.kmac_lc_escalation.3674551987 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 98890712 ps |
| CPU time | 1.9 seconds |
| Started | Sep 11 04:08:34 PM UTC 24 |
| Finished | Sep 11 04:08:37 PM UTC 24 |
| Peak memory | 229628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674551987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.3674551987 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/11.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/11.kmac_long_msg_and_output.32149396 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 18863443724 ps |
| CPU time | 464.83 seconds |
| Started | Sep 11 04:07:43 PM UTC 24 |
| Finished | Sep 11 04:15:34 PM UTC 24 |
| Peak memory | 872216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32149396 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_and_output.32149396 +enable_maskin g=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/11.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/11.kmac_sideload.2046608785 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 168323137162 ps |
| CPU time | 436.72 seconds |
| Started | Sep 11 04:07:56 PM UTC 24 |
| Finished | Sep 11 04:15:18 PM UTC 24 |
| Peak memory | 638692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046608785 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.2046608785 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/11.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/11.kmac_smoke.1941619397 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 3109926897 ps |
| CPU time | 59.16 seconds |
| Started | Sep 11 04:07:40 PM UTC 24 |
| Finished | Sep 11 04:08:41 PM UTC 24 |
| Peak memory | 230632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941619397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.1941619397 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/11.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/11.kmac_stress_all.2445227097 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 114430768859 ps |
| CPU time | 2478.67 seconds |
| Started | Sep 11 04:08:38 PM UTC 24 |
| Finished | Sep 11 04:50:25 PM UTC 24 |
| Peak memory | 1769256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445227097 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.2445227097 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/11.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/12.kmac_alert_test.2082903454 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 36549127 ps |
| CPU time | 1.25 seconds |
| Started | Sep 11 04:09:54 PM UTC 24 |
| Finished | Sep 11 04:09:56 PM UTC 24 |
| Peak memory | 216284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082903454 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.2082903454 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/12.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/12.kmac_app.3120867735 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 20358973398 ps |
| CPU time | 236.75 seconds |
| Started | Sep 11 04:09:13 PM UTC 24 |
| Finished | Sep 11 04:13:13 PM UTC 24 |
| Peak memory | 341796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120867735 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.3120867735 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/12.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/12.kmac_burst_write.1255651435 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 27306156441 ps |
| CPU time | 405.81 seconds |
| Started | Sep 11 04:09:12 PM UTC 24 |
| Finished | Sep 11 04:16:03 PM UTC 24 |
| Peak memory | 247900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255651435 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.1255651435 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/12.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/12.kmac_edn_timeout_error.1231057082 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 830726357 ps |
| CPU time | 20.79 seconds |
| Started | Sep 11 04:09:36 PM UTC 24 |
| Finished | Sep 11 04:09:58 PM UTC 24 |
| Peak memory | 235096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231057082 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.1231057082 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/12.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/12.kmac_entropy_mode_error.2326742704 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 119056987 ps |
| CPU time | 4.08 seconds |
| Started | Sep 11 04:09:48 PM UTC 24 |
| Finished | Sep 11 04:09:54 PM UTC 24 |
| Peak memory | 228404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326742704 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.2326742704 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/12.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/12.kmac_entropy_refresh.479019450 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 13432159950 ps |
| CPU time | 297.17 seconds |
| Started | Sep 11 04:09:19 PM UTC 24 |
| Finished | Sep 11 04:14:21 PM UTC 24 |
| Peak memory | 480996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479019450 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.479019450 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/12.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/12.kmac_error.2205611208 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 160680247049 ps |
| CPU time | 492.47 seconds |
| Started | Sep 11 04:09:19 PM UTC 24 |
| Finished | Sep 11 04:17:38 PM UTC 24 |
| Peak memory | 640792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205611208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.2205611208 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/12.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/12.kmac_key_error.1611133308 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 2969403656 ps |
| CPU time | 3.83 seconds |
| Started | Sep 11 04:09:29 PM UTC 24 |
| Finished | Sep 11 04:09:35 PM UTC 24 |
| Peak memory | 230384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611133308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.1611133308 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/12.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/12.kmac_lc_escalation.1420561270 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 88621002 ps |
| CPU time | 2.09 seconds |
| Started | Sep 11 04:09:50 PM UTC 24 |
| Finished | Sep 11 04:09:53 PM UTC 24 |
| Peak memory | 232504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420561270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.1420561270 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/12.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/12.kmac_long_msg_and_output.1451386705 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 85239232254 ps |
| CPU time | 3156.15 seconds |
| Started | Sep 11 04:08:49 PM UTC 24 |
| Finished | Sep 11 05:02:00 PM UTC 24 |
| Peak memory | 3760052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451386705 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_and_output.1451386705 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/12.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/12.kmac_sideload.3630438349 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 2332561217 ps |
| CPU time | 195.67 seconds |
| Started | Sep 11 04:09:12 PM UTC 24 |
| Finished | Sep 11 04:12:31 PM UTC 24 |
| Peak memory | 313204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630438349 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.3630438349 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/12.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/12.kmac_smoke.1007651887 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 6299334685 ps |
| CPU time | 65.39 seconds |
| Started | Sep 11 04:08:45 PM UTC 24 |
| Finished | Sep 11 04:09:53 PM UTC 24 |
| Peak memory | 230524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007651887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.1007651887 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/12.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/12.kmac_stress_all.2002511894 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 410066871723 ps |
| CPU time | 640.79 seconds |
| Started | Sep 11 04:09:54 PM UTC 24 |
| Finished | Sep 11 04:20:42 PM UTC 24 |
| Peak memory | 798732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002511894 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.2002511894 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/12.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/13.kmac_alert_test.76075697 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 42742724 ps |
| CPU time | 1.17 seconds |
| Started | Sep 11 04:11:19 PM UTC 24 |
| Finished | Sep 11 04:11:21 PM UTC 24 |
| Peak memory | 216280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76075697 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.76075697 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/13.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/13.kmac_app.2828802298 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 9743395824 ps |
| CPU time | 277.11 seconds |
| Started | Sep 11 04:10:05 PM UTC 24 |
| Finished | Sep 11 04:14:46 PM UTC 24 |
| Peak memory | 458484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828802298 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.2828802298 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/13.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/13.kmac_burst_write.429942062 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 12682917866 ps |
| CPU time | 523.13 seconds |
| Started | Sep 11 04:10:04 PM UTC 24 |
| Finished | Sep 11 04:18:54 PM UTC 24 |
| Peak memory | 251664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429942062 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.429942062 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/13.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/13.kmac_edn_timeout_error.497991967 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 971646677 ps |
| CPU time | 34.76 seconds |
| Started | Sep 11 04:10:41 PM UTC 24 |
| Finished | Sep 11 04:11:18 PM UTC 24 |
| Peak memory | 235156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497991967 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.497991967 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/13.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/13.kmac_entropy_mode_error.2303379028 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 703989082 ps |
| CPU time | 17.25 seconds |
| Started | Sep 11 04:10:58 PM UTC 24 |
| Finished | Sep 11 04:11:16 PM UTC 24 |
| Peak memory | 234352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303379028 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.2303379028 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/13.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/13.kmac_entropy_refresh.2907840864 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 23444619888 ps |
| CPU time | 294.37 seconds |
| Started | Sep 11 04:10:17 PM UTC 24 |
| Finished | Sep 11 04:15:16 PM UTC 24 |
| Peak memory | 403172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907840864 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.2907840864 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/13.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/13.kmac_error.1874967489 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 14429477135 ps |
| CPU time | 284.6 seconds |
| Started | Sep 11 04:10:34 PM UTC 24 |
| Finished | Sep 11 04:15:23 PM UTC 24 |
| Peak memory | 382756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874967489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.1874967489 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/13.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/13.kmac_key_error.2507011627 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 2682751641 ps |
| CPU time | 13.9 seconds |
| Started | Sep 11 04:10:41 PM UTC 24 |
| Finished | Sep 11 04:10:56 PM UTC 24 |
| Peak memory | 230436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507011627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.2507011627 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/13.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/13.kmac_lc_escalation.1100950665 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 27160110 ps |
| CPU time | 1.92 seconds |
| Started | Sep 11 04:11:17 PM UTC 24 |
| Finished | Sep 11 04:11:20 PM UTC 24 |
| Peak memory | 229672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100950665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.1100950665 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/13.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/13.kmac_long_msg_and_output.2067226157 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 24396528033 ps |
| CPU time | 2540.61 seconds |
| Started | Sep 11 04:09:57 PM UTC 24 |
| Finished | Sep 11 04:52:47 PM UTC 24 |
| Peak memory | 1781532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067226157 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_and_output.2067226157 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/13.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/13.kmac_sideload.3024753878 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 280564725 ps |
| CPU time | 4.34 seconds |
| Started | Sep 11 04:09:59 PM UTC 24 |
| Finished | Sep 11 04:10:04 PM UTC 24 |
| Peak memory | 230396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024753878 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.3024753878 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/13.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/13.kmac_smoke.205415535 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 5832797274 ps |
| CPU time | 43.92 seconds |
| Started | Sep 11 04:09:55 PM UTC 24 |
| Finished | Sep 11 04:10:40 PM UTC 24 |
| Peak memory | 230848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205415535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.205415535 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/13.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/13.kmac_stress_all.3370139144 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 42959621432 ps |
| CPU time | 568.14 seconds |
| Started | Sep 11 04:11:18 PM UTC 24 |
| Finished | Sep 11 04:20:54 PM UTC 24 |
| Peak memory | 577656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370139144 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.3370139144 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/13.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/14.kmac_alert_test.2400994672 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 18162911 ps |
| CPU time | 1.3 seconds |
| Started | Sep 11 04:12:55 PM UTC 24 |
| Finished | Sep 11 04:12:57 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400994672 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.2400994672 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/14.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/14.kmac_app.577927363 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 7437375348 ps |
| CPU time | 182.05 seconds |
| Started | Sep 11 04:12:09 PM UTC 24 |
| Finished | Sep 11 04:15:14 PM UTC 24 |
| Peak memory | 306964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577927363 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.577927363 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/14.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/14.kmac_burst_write.209263288 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 9062396480 ps |
| CPU time | 104.49 seconds |
| Started | Sep 11 04:12:02 PM UTC 24 |
| Finished | Sep 11 04:13:49 PM UTC 24 |
| Peak memory | 235236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209263288 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.209263288 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/14.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/14.kmac_edn_timeout_error.3753259797 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 200208166 ps |
| CPU time | 14.25 seconds |
| Started | Sep 11 04:12:39 PM UTC 24 |
| Finished | Sep 11 04:12:54 PM UTC 24 |
| Peak memory | 234364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753259797 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.3753259797 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/14.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/14.kmac_entropy_mode_error.556521487 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 3245744805 ps |
| CPU time | 31.17 seconds |
| Started | Sep 11 04:12:40 PM UTC 24 |
| Finished | Sep 11 04:13:12 PM UTC 24 |
| Peak memory | 230596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556521487 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.556521487 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/14.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/14.kmac_entropy_refresh.459447963 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 4241234582 ps |
| CPU time | 192.5 seconds |
| Started | Sep 11 04:12:19 PM UTC 24 |
| Finished | Sep 11 04:15:34 PM UTC 24 |
| Peak memory | 311080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459447963 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.459447963 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/14.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/14.kmac_error.3632054381 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 17630232732 ps |
| CPU time | 240.34 seconds |
| Started | Sep 11 04:12:32 PM UTC 24 |
| Finished | Sep 11 04:16:36 PM UTC 24 |
| Peak memory | 327396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632054381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.3632054381 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/14.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/14.kmac_key_error.1594550805 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 445511120 ps |
| CPU time | 4.45 seconds |
| Started | Sep 11 04:12:33 PM UTC 24 |
| Finished | Sep 11 04:12:38 PM UTC 24 |
| Peak memory | 230368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594550805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.1594550805 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/14.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/14.kmac_lc_escalation.2007699332 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 163718865 ps |
| CPU time | 2.15 seconds |
| Started | Sep 11 04:12:42 PM UTC 24 |
| Finished | Sep 11 04:12:45 PM UTC 24 |
| Peak memory | 232684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007699332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.2007699332 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/14.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/14.kmac_long_msg_and_output.21135518 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 120517039491 ps |
| CPU time | 1034.65 seconds |
| Started | Sep 11 04:11:22 PM UTC 24 |
| Finished | Sep 11 04:28:49 PM UTC 24 |
| Peak memory | 1605404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21135518 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_and_output.21135518 +enable_maskin g=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/14.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/14.kmac_sideload.2294021980 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 16175536250 ps |
| CPU time | 320.72 seconds |
| Started | Sep 11 04:11:46 PM UTC 24 |
| Finished | Sep 11 04:17:12 PM UTC 24 |
| Peak memory | 360172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294021980 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.2294021980 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/14.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/14.kmac_smoke.2291575040 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 6951561203 ps |
| CPU time | 39.19 seconds |
| Started | Sep 11 04:11:21 PM UTC 24 |
| Finished | Sep 11 04:12:02 PM UTC 24 |
| Peak memory | 230528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291575040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.2291575040 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/14.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/14.kmac_stress_all.2878119713 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 108301966234 ps |
| CPU time | 3236.8 seconds |
| Started | Sep 11 04:12:46 PM UTC 24 |
| Finished | Sep 11 05:07:20 PM UTC 24 |
| Peak memory | 1863796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878119713 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.2878119713 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/14.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/15.kmac_alert_test.2587014075 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 37746318 ps |
| CPU time | 1.2 seconds |
| Started | Sep 11 04:14:36 PM UTC 24 |
| Finished | Sep 11 04:14:39 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587014075 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.2587014075 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/15.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/15.kmac_app.1056767447 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 34157842326 ps |
| CPU time | 151.21 seconds |
| Started | Sep 11 04:13:21 PM UTC 24 |
| Finished | Sep 11 04:15:55 PM UTC 24 |
| Peak memory | 284392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056767447 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.1056767447 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/15.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/15.kmac_burst_write.1933022203 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 6555479511 ps |
| CPU time | 598.94 seconds |
| Started | Sep 11 04:13:14 PM UTC 24 |
| Finished | Sep 11 04:23:21 PM UTC 24 |
| Peak memory | 247656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933022203 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.1933022203 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/15.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/15.kmac_edn_timeout_error.1044990365 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 860804719 ps |
| CPU time | 19.66 seconds |
| Started | Sep 11 04:14:20 PM UTC 24 |
| Finished | Sep 11 04:14:41 PM UTC 24 |
| Peak memory | 230320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044990365 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.1044990365 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/15.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/15.kmac_entropy_mode_error.2055324029 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 368638633 ps |
| CPU time | 14.57 seconds |
| Started | Sep 11 04:14:20 PM UTC 24 |
| Finished | Sep 11 04:14:36 PM UTC 24 |
| Peak memory | 235144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055324029 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.2055324029 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/15.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/15.kmac_entropy_refresh.227681334 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 28734031282 ps |
| CPU time | 144.58 seconds |
| Started | Sep 11 04:13:49 PM UTC 24 |
| Finished | Sep 11 04:16:16 PM UTC 24 |
| Peak memory | 329444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227681334 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.227681334 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/15.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/15.kmac_error.925407096 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 937906844 ps |
| CPU time | 28.15 seconds |
| Started | Sep 11 04:13:50 PM UTC 24 |
| Finished | Sep 11 04:14:19 PM UTC 24 |
| Peak memory | 251624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925407096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.925407096 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/15.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/15.kmac_key_error.2261392289 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 75531809 ps |
| CPU time | 1.89 seconds |
| Started | Sep 11 04:14:16 PM UTC 24 |
| Finished | Sep 11 04:14:19 PM UTC 24 |
| Peak memory | 229852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261392289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.2261392289 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/15.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/15.kmac_lc_escalation.3805389296 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 56982304 ps |
| CPU time | 1.67 seconds |
| Started | Sep 11 04:14:21 PM UTC 24 |
| Finished | Sep 11 04:14:24 PM UTC 24 |
| Peak memory | 231780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805389296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.3805389296 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/15.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/15.kmac_long_msg_and_output.3542616056 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 138923622664 ps |
| CPU time | 2098.26 seconds |
| Started | Sep 11 04:12:58 PM UTC 24 |
| Finished | Sep 11 04:48:20 PM UTC 24 |
| Peak memory | 2568040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542616056 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_and_output.3542616056 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/15.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/15.kmac_sideload.1440924439 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 2060856434 ps |
| CPU time | 105.16 seconds |
| Started | Sep 11 04:13:13 PM UTC 24 |
| Finished | Sep 11 04:15:01 PM UTC 24 |
| Peak memory | 263844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440924439 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.1440924439 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/15.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/15.kmac_smoke.2390636113 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 5072119543 ps |
| CPU time | 50.6 seconds |
| Started | Sep 11 04:12:56 PM UTC 24 |
| Finished | Sep 11 04:13:48 PM UTC 24 |
| Peak memory | 230844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390636113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.2390636113 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/15.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/15.kmac_stress_all.2122389150 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 60487899728 ps |
| CPU time | 1608.28 seconds |
| Started | Sep 11 04:14:24 PM UTC 24 |
| Finished | Sep 11 04:41:31 PM UTC 24 |
| Peak memory | 671968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122389150 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.2122389150 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/15.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/16.kmac_alert_test.3755386445 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 112753155 ps |
| CPU time | 1.35 seconds |
| Started | Sep 11 04:15:25 PM UTC 24 |
| Finished | Sep 11 04:15:28 PM UTC 24 |
| Peak memory | 216280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755386445 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.3755386445 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/16.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/16.kmac_app.2821662032 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 3348975314 ps |
| CPU time | 166.17 seconds |
| Started | Sep 11 04:15:00 PM UTC 24 |
| Finished | Sep 11 04:17:49 PM UTC 24 |
| Peak memory | 305080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821662032 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.2821662032 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/16.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/16.kmac_burst_write.3835032689 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 91168497963 ps |
| CPU time | 979.7 seconds |
| Started | Sep 11 04:14:48 PM UTC 24 |
| Finished | Sep 11 04:31:20 PM UTC 24 |
| Peak memory | 263892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835032689 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.3835032689 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/16.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/16.kmac_edn_timeout_error.498856907 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 5476897266 ps |
| CPU time | 34.67 seconds |
| Started | Sep 11 04:15:17 PM UTC 24 |
| Finished | Sep 11 04:15:53 PM UTC 24 |
| Peak memory | 235100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498856907 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.498856907 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/16.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/16.kmac_entropy_mode_error.1956326356 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 818422842 ps |
| CPU time | 25.62 seconds |
| Started | Sep 11 04:15:19 PM UTC 24 |
| Finished | Sep 11 04:15:46 PM UTC 24 |
| Peak memory | 247280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956326356 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.1956326356 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/16.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/16.kmac_entropy_refresh.636810072 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 16275882472 ps |
| CPU time | 257.21 seconds |
| Started | Sep 11 04:15:02 PM UTC 24 |
| Finished | Sep 11 04:19:23 PM UTC 24 |
| Peak memory | 337704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636810072 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.636810072 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/16.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/16.kmac_error.2101699868 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 16110460738 ps |
| CPU time | 453.91 seconds |
| Started | Sep 11 04:15:10 PM UTC 24 |
| Finished | Sep 11 04:22:50 PM UTC 24 |
| Peak memory | 575208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101699868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.2101699868 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/16.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/16.kmac_key_error.1724968029 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 1631253100 ps |
| CPU time | 4.77 seconds |
| Started | Sep 11 04:15:15 PM UTC 24 |
| Finished | Sep 11 04:15:21 PM UTC 24 |
| Peak memory | 230344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724968029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.1724968029 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/16.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/16.kmac_lc_escalation.2664352177 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 124105049 ps |
| CPU time | 2.55 seconds |
| Started | Sep 11 04:15:21 PM UTC 24 |
| Finished | Sep 11 04:15:25 PM UTC 24 |
| Peak memory | 230384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664352177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.2664352177 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/16.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/16.kmac_long_msg_and_output.2170357305 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 308139266258 ps |
| CPU time | 3279.94 seconds |
| Started | Sep 11 04:14:42 PM UTC 24 |
| Finished | Sep 11 05:09:57 PM UTC 24 |
| Peak memory | 3692320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170357305 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_and_output.2170357305 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/16.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/16.kmac_sideload.4291188739 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 25852280216 ps |
| CPU time | 313.13 seconds |
| Started | Sep 11 04:14:48 PM UTC 24 |
| Finished | Sep 11 04:20:05 PM UTC 24 |
| Peak memory | 524064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291188739 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.4291188739 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/16.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/16.kmac_smoke.1505042223 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 2450423819 ps |
| CPU time | 18.71 seconds |
| Started | Sep 11 04:14:39 PM UTC 24 |
| Finished | Sep 11 04:14:59 PM UTC 24 |
| Peak memory | 230840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505042223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.1505042223 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/16.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/16.kmac_stress_all.1227317936 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 188698324771 ps |
| CPU time | 1512.88 seconds |
| Started | Sep 11 04:15:23 PM UTC 24 |
| Finished | Sep 11 04:40:55 PM UTC 24 |
| Peak memory | 1026096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227317936 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.1227317936 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/16.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/17.kmac_alert_test.82633921 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 51777469 ps |
| CPU time | 1.21 seconds |
| Started | Sep 11 04:16:13 PM UTC 24 |
| Finished | Sep 11 04:16:15 PM UTC 24 |
| Peak memory | 216280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82633921 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.82633921 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/17.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/17.kmac_app.1238538490 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 16775868392 ps |
| CPU time | 76.97 seconds |
| Started | Sep 11 04:15:43 PM UTC 24 |
| Finished | Sep 11 04:17:02 PM UTC 24 |
| Peak memory | 300812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238538490 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.1238538490 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/17.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/17.kmac_burst_write.1960360848 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 17066353065 ps |
| CPU time | 751.68 seconds |
| Started | Sep 11 04:15:39 PM UTC 24 |
| Finished | Sep 11 04:28:20 PM UTC 24 |
| Peak memory | 253736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960360848 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.1960360848 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/17.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/17.kmac_edn_timeout_error.3379990736 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 1950677000 ps |
| CPU time | 43.09 seconds |
| Started | Sep 11 04:16:01 PM UTC 24 |
| Finished | Sep 11 04:16:45 PM UTC 24 |
| Peak memory | 235160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379990736 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.3379990736 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/17.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/17.kmac_entropy_mode_error.4267600663 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 211536068 ps |
| CPU time | 7.48 seconds |
| Started | Sep 11 04:16:04 PM UTC 24 |
| Finished | Sep 11 04:16:12 PM UTC 24 |
| Peak memory | 228332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267600663 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.4267600663 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/17.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/17.kmac_entropy_refresh.1930884148 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 70869928006 ps |
| CPU time | 139.76 seconds |
| Started | Sep 11 04:15:47 PM UTC 24 |
| Finished | Sep 11 04:18:10 PM UTC 24 |
| Peak memory | 321260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930884148 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.1930884148 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/17.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/17.kmac_error.806732689 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 24743074852 ps |
| CPU time | 115.38 seconds |
| Started | Sep 11 04:15:54 PM UTC 24 |
| Finished | Sep 11 04:17:52 PM UTC 24 |
| Peak memory | 321320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806732689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.806732689 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/17.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/17.kmac_key_error.324822916 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 1320005601 ps |
| CPU time | 8.44 seconds |
| Started | Sep 11 04:15:55 PM UTC 24 |
| Finished | Sep 11 04:16:05 PM UTC 24 |
| Peak memory | 230372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324822916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.324822916 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/17.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/17.kmac_lc_escalation.2592219664 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 152541235 ps |
| CPU time | 2.12 seconds |
| Started | Sep 11 04:16:06 PM UTC 24 |
| Finished | Sep 11 04:16:09 PM UTC 24 |
| Peak memory | 230652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592219664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.2592219664 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/17.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/17.kmac_long_msg_and_output.1306848031 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 37778046753 ps |
| CPU time | 1834.42 seconds |
| Started | Sep 11 04:15:34 PM UTC 24 |
| Finished | Sep 11 04:46:30 PM UTC 24 |
| Peak memory | 1376228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306848031 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_and_output.1306848031 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/17.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/17.kmac_sideload.4252141884 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 2902738693 ps |
| CPU time | 74.78 seconds |
| Started | Sep 11 04:15:35 PM UTC 24 |
| Finished | Sep 11 04:16:51 PM UTC 24 |
| Peak memory | 309020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252141884 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.4252141884 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/17.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/17.kmac_smoke.391708282 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 17827631016 ps |
| CPU time | 57.46 seconds |
| Started | Sep 11 04:15:28 PM UTC 24 |
| Finished | Sep 11 04:16:27 PM UTC 24 |
| Peak memory | 234684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391708282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.391708282 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/17.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/17.kmac_stress_all.3073510767 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 10992743358 ps |
| CPU time | 278.79 seconds |
| Started | Sep 11 04:16:10 PM UTC 24 |
| Finished | Sep 11 04:20:53 PM UTC 24 |
| Peak memory | 274344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073510767 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.3073510767 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/17.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/18.kmac_alert_test.1512076720 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 27789642 ps |
| CPU time | 1.18 seconds |
| Started | Sep 11 04:17:14 PM UTC 24 |
| Finished | Sep 11 04:17:16 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512076720 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.1512076720 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/18.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/18.kmac_app.409889760 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 8763176891 ps |
| CPU time | 151.63 seconds |
| Started | Sep 11 04:16:31 PM UTC 24 |
| Finished | Sep 11 04:19:06 PM UTC 24 |
| Peak memory | 368416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409889760 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.409889760 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/18.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/18.kmac_burst_write.3994133605 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 17484912939 ps |
| CPU time | 544.59 seconds |
| Started | Sep 11 04:16:28 PM UTC 24 |
| Finished | Sep 11 04:25:40 PM UTC 24 |
| Peak memory | 253640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994133605 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.3994133605 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/18.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/18.kmac_edn_timeout_error.3770040749 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 1817981047 ps |
| CPU time | 35.61 seconds |
| Started | Sep 11 04:17:02 PM UTC 24 |
| Finished | Sep 11 04:17:39 PM UTC 24 |
| Peak memory | 235036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770040749 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.3770040749 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/18.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/18.kmac_entropy_mode_error.3981039666 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 181959862 ps |
| CPU time | 4.94 seconds |
| Started | Sep 11 04:17:03 PM UTC 24 |
| Finished | Sep 11 04:17:09 PM UTC 24 |
| Peak memory | 228216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981039666 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.3981039666 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/18.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/18.kmac_entropy_refresh.1694004313 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 68135906287 ps |
| CPU time | 348.57 seconds |
| Started | Sep 11 04:16:36 PM UTC 24 |
| Finished | Sep 11 04:22:30 PM UTC 24 |
| Peak memory | 532264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694004313 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.1694004313 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/18.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/18.kmac_error.2870228723 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 22886492506 ps |
| CPU time | 298.91 seconds |
| Started | Sep 11 04:16:46 PM UTC 24 |
| Finished | Sep 11 04:21:50 PM UTC 24 |
| Peak memory | 474920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870228723 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.2870228723 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/18.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/18.kmac_key_error.1541397530 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 2450727939 ps |
| CPU time | 7.21 seconds |
| Started | Sep 11 04:16:53 PM UTC 24 |
| Finished | Sep 11 04:17:01 PM UTC 24 |
| Peak memory | 232768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541397530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.1541397530 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/18.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/18.kmac_lc_escalation.3767442436 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 248182576 ps |
| CPU time | 1.77 seconds |
| Started | Sep 11 04:17:10 PM UTC 24 |
| Finished | Sep 11 04:17:13 PM UTC 24 |
| Peak memory | 231780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767442436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.3767442436 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/18.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/18.kmac_long_msg_and_output.340750095 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 77125860005 ps |
| CPU time | 1809.52 seconds |
| Started | Sep 11 04:16:17 PM UTC 24 |
| Finished | Sep 11 04:46:46 PM UTC 24 |
| Peak memory | 2537192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340750095 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_and_output.340750095 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/18.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/18.kmac_sideload.283434720 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 4774384560 ps |
| CPU time | 165.32 seconds |
| Started | Sep 11 04:16:24 PM UTC 24 |
| Finished | Sep 11 04:19:13 PM UTC 24 |
| Peak memory | 298860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283434720 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.283434720 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/18.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/18.kmac_smoke.732686550 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 1436258296 ps |
| CPU time | 6.35 seconds |
| Started | Sep 11 04:16:16 PM UTC 24 |
| Finished | Sep 11 04:16:23 PM UTC 24 |
| Peak memory | 230700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732686550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.732686550 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/18.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/18.kmac_stress_all.2601748552 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 59003534693 ps |
| CPU time | 955.51 seconds |
| Started | Sep 11 04:17:13 PM UTC 24 |
| Finished | Sep 11 04:33:20 PM UTC 24 |
| Peak memory | 579784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601748552 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.2601748552 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/18.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/19.kmac_alert_test.346923443 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 26943768 ps |
| CPU time | 1.14 seconds |
| Started | Sep 11 04:18:27 PM UTC 24 |
| Finished | Sep 11 04:18:29 PM UTC 24 |
| Peak memory | 216280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346923443 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.346923443 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/19.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/19.kmac_app.2659285554 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 4595479611 ps |
| CPU time | 276.74 seconds |
| Started | Sep 11 04:17:39 PM UTC 24 |
| Finished | Sep 11 04:22:20 PM UTC 24 |
| Peak memory | 329500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659285554 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.2659285554 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/19.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/19.kmac_burst_write.3554924763 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 4743264416 ps |
| CPU time | 475.88 seconds |
| Started | Sep 11 04:17:37 PM UTC 24 |
| Finished | Sep 11 04:25:39 PM UTC 24 |
| Peak memory | 245476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554924763 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.3554924763 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/19.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/19.kmac_edn_timeout_error.3586066202 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 1835821194 ps |
| CPU time | 50.76 seconds |
| Started | Sep 11 04:17:53 PM UTC 24 |
| Finished | Sep 11 04:18:46 PM UTC 24 |
| Peak memory | 232488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586066202 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.3586066202 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/19.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/19.kmac_entropy_mode_error.1785099242 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 6107710039 ps |
| CPU time | 55.03 seconds |
| Started | Sep 11 04:17:56 PM UTC 24 |
| Finished | Sep 11 04:18:53 PM UTC 24 |
| Peak memory | 235224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785099242 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.1785099242 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/19.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/19.kmac_entropy_refresh.791608138 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 7050826417 ps |
| CPU time | 109.57 seconds |
| Started | Sep 11 04:17:39 PM UTC 24 |
| Finished | Sep 11 04:19:31 PM UTC 24 |
| Peak memory | 274272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791608138 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.791608138 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/19.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/19.kmac_error.147471691 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 11995222462 ps |
| CPU time | 212.09 seconds |
| Started | Sep 11 04:17:39 PM UTC 24 |
| Finished | Sep 11 04:21:14 PM UTC 24 |
| Peak memory | 468716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147471691 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.147471691 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/19.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/19.kmac_lc_escalation.1704757929 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 67450760 ps |
| CPU time | 1.67 seconds |
| Started | Sep 11 04:18:10 PM UTC 24 |
| Finished | Sep 11 04:18:13 PM UTC 24 |
| Peak memory | 229728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704757929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.1704757929 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/19.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/19.kmac_long_msg_and_output.778401668 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 93773387901 ps |
| CPU time | 2254.07 seconds |
| Started | Sep 11 04:17:21 PM UTC 24 |
| Finished | Sep 11 04:55:21 PM UTC 24 |
| Peak memory | 1644264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778401668 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_and_output.778401668 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/19.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/19.kmac_sideload.3019084571 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 66373504609 ps |
| CPU time | 448.52 seconds |
| Started | Sep 11 04:17:23 PM UTC 24 |
| Finished | Sep 11 04:24:57 PM UTC 24 |
| Peak memory | 593692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019084571 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.3019084571 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/19.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/19.kmac_smoke.1285137567 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 270639872 ps |
| CPU time | 17.66 seconds |
| Started | Sep 11 04:17:17 PM UTC 24 |
| Finished | Sep 11 04:17:36 PM UTC 24 |
| Peak memory | 230464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285137567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.1285137567 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/19.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/19.kmac_stress_all.795115643 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 11943786409 ps |
| CPU time | 365.54 seconds |
| Started | Sep 11 04:18:14 PM UTC 24 |
| Finished | Sep 11 04:24:25 PM UTC 24 |
| Peak memory | 278256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795115643 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.795115643 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/19.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/2.kmac_alert_test.2605631090 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 47706308 ps |
| CPU time | 1.18 seconds |
| Started | Sep 11 03:55:09 PM UTC 24 |
| Finished | Sep 11 03:55:12 PM UTC 24 |
| Peak memory | 216280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605631090 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.2605631090 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/2.kmac_app.1729560817 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 2930375367 ps |
| CPU time | 78.98 seconds |
| Started | Sep 11 03:54:37 PM UTC 24 |
| Finished | Sep 11 03:55:58 PM UTC 24 |
| Peak memory | 286420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729560817 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.1729560817 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/2.kmac_app_with_partial_data.3096485668 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 27646502126 ps |
| CPU time | 311.02 seconds |
| Started | Sep 11 03:54:38 PM UTC 24 |
| Finished | Sep 11 03:59:54 PM UTC 24 |
| Peak memory | 331740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096485668 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.3096485668 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/2.kmac_burst_write.2412137876 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 78036992102 ps |
| CPU time | 788.47 seconds |
| Started | Sep 11 03:53:53 PM UTC 24 |
| Finished | Sep 11 04:07:11 PM UTC 24 |
| Peak memory | 264204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412137876 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.2412137876 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/2.kmac_edn_timeout_error.1500298659 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 3868268040 ps |
| CPU time | 32.5 seconds |
| Started | Sep 11 03:54:50 PM UTC 24 |
| Finished | Sep 11 03:55:24 PM UTC 24 |
| Peak memory | 235036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500298659 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.1500298659 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_mode_error.3876287241 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 111105098 ps |
| CPU time | 8.75 seconds |
| Started | Sep 11 03:54:52 PM UTC 24 |
| Finished | Sep 11 03:55:02 PM UTC 24 |
| Peak memory | 228292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876287241 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.3876287241 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_ready_error.2717747142 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 8694651909 ps |
| CPU time | 56.44 seconds |
| Started | Sep 11 03:54:59 PM UTC 24 |
| Finished | Sep 11 03:55:57 PM UTC 24 |
| Peak memory | 230528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717747142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.2717747142 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_refresh.3276202908 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 5048526252 ps |
| CPU time | 95.31 seconds |
| Started | Sep 11 03:54:39 PM UTC 24 |
| Finished | Sep 11 03:56:17 PM UTC 24 |
| Peak memory | 313340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276202908 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.3276202908 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/2.kmac_error.1094456315 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 5301669445 ps |
| CPU time | 209.55 seconds |
| Started | Sep 11 03:54:46 PM UTC 24 |
| Finished | Sep 11 03:58:19 PM UTC 24 |
| Peak memory | 317224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094456315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.1094456315 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/2.kmac_key_error.1799783926 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 14152176061 ps |
| CPU time | 8.57 seconds |
| Started | Sep 11 03:54:50 PM UTC 24 |
| Finished | Sep 11 03:54:59 PM UTC 24 |
| Peak memory | 230644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799783926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.1799783926 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/2.kmac_lc_escalation.1199639496 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 808951553 ps |
| CPU time | 6.4 seconds |
| Started | Sep 11 03:55:01 PM UTC 24 |
| Finished | Sep 11 03:55:08 PM UTC 24 |
| Peak memory | 230544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199639496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.1199639496 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/2.kmac_long_msg_and_output.444076316 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 35184393520 ps |
| CPU time | 1812.57 seconds |
| Started | Sep 11 03:53:41 PM UTC 24 |
| Finished | Sep 11 04:24:15 PM UTC 24 |
| Peak memory | 1318884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444076316 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and_output.444076316 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/2.kmac_mubi.2368816056 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 72348016796 ps |
| CPU time | 415.22 seconds |
| Started | Sep 11 03:54:43 PM UTC 24 |
| Finished | Sep 11 04:01:44 PM UTC 24 |
| Peak memory | 544804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368816056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.2368816056 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/2.kmac_sec_cm.992435946 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1696023400 ps |
| CPU time | 40.35 seconds |
| Started | Sep 11 03:55:02 PM UTC 24 |
| Finished | Sep 11 03:55:44 PM UTC 24 |
| Peak memory | 264756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992435946 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.992435946 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/2.kmac_sideload.3402844317 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 4765889966 ps |
| CPU time | 52.52 seconds |
| Started | Sep 11 03:53:42 PM UTC 24 |
| Finished | Sep 11 03:54:36 PM UTC 24 |
| Peak memory | 260132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402844317 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.3402844317 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/2.kmac_smoke.2016045344 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 2738847046 ps |
| CPU time | 77.88 seconds |
| Started | Sep 11 03:53:41 PM UTC 24 |
| Finished | Sep 11 03:55:00 PM UTC 24 |
| Peak memory | 232744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016045344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.2016045344 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/2.kmac_stress_all.700649822 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 97056936539 ps |
| CPU time | 891.4 seconds |
| Started | Sep 11 03:55:01 PM UTC 24 |
| Finished | Sep 11 04:10:03 PM UTC 24 |
| Peak memory | 972260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700649822 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.700649822 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac.3846419476 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 111052049 ps |
| CPU time | 2.71 seconds |
| Started | Sep 11 03:54:33 PM UTC 24 |
| Finished | Sep 11 03:54:37 PM UTC 24 |
| Peak memory | 230608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846419476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac.3846419476 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac_xof.3771563942 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 132905684 ps |
| CPU time | 3.16 seconds |
| Started | Sep 11 03:54:34 PM UTC 24 |
| Finished | Sep 11 03:54:38 PM UTC 24 |
| Peak memory | 230520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771563942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.3771563942 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_224.3359944860 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 364925211135 ps |
| CPU time | 2556.78 seconds |
| Started | Sep 11 03:53:58 PM UTC 24 |
| Finished | Sep 11 04:37:05 PM UTC 24 |
| Peak memory | 3147412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359944860 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.3359944860 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_256.4036217133 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 282772630722 ps |
| CPU time | 1596.73 seconds |
| Started | Sep 11 03:54:02 PM UTC 24 |
| Finished | Sep 11 04:20:58 PM UTC 24 |
| Peak memory | 1150608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036217133 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.4036217133 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_384.1957809289 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 187542527030 ps |
| CPU time | 1581.43 seconds |
| Started | Sep 11 03:54:07 PM UTC 24 |
| Finished | Sep 11 04:20:46 PM UTC 24 |
| Peak memory | 2385556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957809289 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.1957809289 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_512.3933317966 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 267679589544 ps |
| CPU time | 1436.09 seconds |
| Started | Sep 11 03:54:12 PM UTC 24 |
| Finished | Sep 11 04:18:25 PM UTC 24 |
| Peak memory | 1762964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933317966 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.3933317966 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_128.3941731846 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 239210014214 ps |
| CPU time | 2657.97 seconds |
| Started | Sep 11 03:54:23 PM UTC 24 |
| Finished | Sep 11 04:39:11 PM UTC 24 |
| Peak memory | 3673844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941731846 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.3941731 846 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/20.kmac_alert_test.730362816 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 14900587 ps |
| CPU time | 1.18 seconds |
| Started | Sep 11 04:19:16 PM UTC 24 |
| Finished | Sep 11 04:19:18 PM UTC 24 |
| Peak memory | 215844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730362816 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.730362816 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/20.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/20.kmac_app.427973584 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 498680586 ps |
| CPU time | 15.74 seconds |
| Started | Sep 11 04:18:54 PM UTC 24 |
| Finished | Sep 11 04:19:11 PM UTC 24 |
| Peak memory | 235156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427973584 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.427973584 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/20.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/20.kmac_burst_write.3245595625 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 82578163820 ps |
| CPU time | 669.98 seconds |
| Started | Sep 11 04:18:54 PM UTC 24 |
| Finished | Sep 11 04:30:13 PM UTC 24 |
| Peak memory | 253708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245595625 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.3245595625 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/20.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/20.kmac_entropy_refresh.1021853330 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 2859433502 ps |
| CPU time | 24.82 seconds |
| Started | Sep 11 04:18:55 PM UTC 24 |
| Finished | Sep 11 04:19:21 PM UTC 24 |
| Peak memory | 239388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021853330 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.1021853330 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/20.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/20.kmac_error.3210002457 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 2254667118 ps |
| CPU time | 166.67 seconds |
| Started | Sep 11 04:19:00 PM UTC 24 |
| Finished | Sep 11 04:21:50 PM UTC 24 |
| Peak memory | 315112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210002457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.3210002457 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/20.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/20.kmac_key_error.1552886847 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 8154345610 ps |
| CPU time | 12.08 seconds |
| Started | Sep 11 04:19:07 PM UTC 24 |
| Finished | Sep 11 04:19:21 PM UTC 24 |
| Peak memory | 230484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552886847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.1552886847 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/20.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/20.kmac_lc_escalation.1287599147 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 92060872 ps |
| CPU time | 1.77 seconds |
| Started | Sep 11 04:19:11 PM UTC 24 |
| Finished | Sep 11 04:19:14 PM UTC 24 |
| Peak memory | 231836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287599147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.1287599147 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/20.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/20.kmac_long_msg_and_output.2337921648 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 412733001457 ps |
| CPU time | 2120.57 seconds |
| Started | Sep 11 04:18:32 PM UTC 24 |
| Finished | Sep 11 04:54:15 PM UTC 24 |
| Peak memory | 2922248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337921648 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_and_output.2337921648 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/20.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/20.kmac_sideload.3501564853 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 6549691114 ps |
| CPU time | 48.01 seconds |
| Started | Sep 11 04:18:47 PM UTC 24 |
| Finished | Sep 11 04:19:36 PM UTC 24 |
| Peak memory | 274212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501564853 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.3501564853 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/20.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/20.kmac_smoke.3939591006 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 1456178093 ps |
| CPU time | 43.46 seconds |
| Started | Sep 11 04:18:30 PM UTC 24 |
| Finished | Sep 11 04:19:15 PM UTC 24 |
| Peak memory | 234736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939591006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.3939591006 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/20.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/20.kmac_stress_all.391332758 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 28617225139 ps |
| CPU time | 467.86 seconds |
| Started | Sep 11 04:19:13 PM UTC 24 |
| Finished | Sep 11 04:27:08 PM UTC 24 |
| Peak memory | 329572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391332758 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.391332758 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/20.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/21.kmac_alert_test.2591698083 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 15820877 ps |
| CPU time | 1.25 seconds |
| Started | Sep 11 04:20:06 PM UTC 24 |
| Finished | Sep 11 04:20:09 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591698083 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.2591698083 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/21.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/21.kmac_app.142066555 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 704261768 ps |
| CPU time | 55.15 seconds |
| Started | Sep 11 04:19:22 PM UTC 24 |
| Finished | Sep 11 04:20:19 PM UTC 24 |
| Peak memory | 247536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142066555 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.142066555 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/21.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/21.kmac_burst_write.2450460091 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 9152856933 ps |
| CPU time | 409.98 seconds |
| Started | Sep 11 04:19:22 PM UTC 24 |
| Finished | Sep 11 04:26:17 PM UTC 24 |
| Peak memory | 243552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450460091 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.2450460091 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/21.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/21.kmac_entropy_refresh.1339411676 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 10961818252 ps |
| CPU time | 340.13 seconds |
| Started | Sep 11 04:19:24 PM UTC 24 |
| Finished | Sep 11 04:25:09 PM UTC 24 |
| Peak memory | 452396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339411676 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.1339411676 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/21.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/21.kmac_error.4081575031 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 37755494312 ps |
| CPU time | 162.58 seconds |
| Started | Sep 11 04:19:32 PM UTC 24 |
| Finished | Sep 11 04:22:18 PM UTC 24 |
| Peak memory | 382752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081575031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.4081575031 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/21.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/21.kmac_key_error.592450254 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 824821154 ps |
| CPU time | 9.39 seconds |
| Started | Sep 11 04:19:37 PM UTC 24 |
| Finished | Sep 11 04:19:48 PM UTC 24 |
| Peak memory | 230320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592450254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.592450254 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/21.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/21.kmac_lc_escalation.2955486393 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 125664857 ps |
| CPU time | 1.87 seconds |
| Started | Sep 11 04:19:48 PM UTC 24 |
| Finished | Sep 11 04:19:51 PM UTC 24 |
| Peak memory | 229732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955486393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.2955486393 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/21.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/21.kmac_long_msg_and_output.276664495 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 30475442301 ps |
| CPU time | 407.77 seconds |
| Started | Sep 11 04:19:19 PM UTC 24 |
| Finished | Sep 11 04:26:12 PM UTC 24 |
| Peak memory | 788516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276664495 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_and_output.276664495 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/21.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/21.kmac_sideload.475260000 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 775891695 ps |
| CPU time | 58.86 seconds |
| Started | Sep 11 04:19:21 PM UTC 24 |
| Finished | Sep 11 04:20:21 PM UTC 24 |
| Peak memory | 253668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475260000 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.475260000 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/21.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/21.kmac_smoke.353644155 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 39874666 ps |
| CPU time | 3.54 seconds |
| Started | Sep 11 04:19:16 PM UTC 24 |
| Finished | Sep 11 04:19:20 PM UTC 24 |
| Peak memory | 230716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353644155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.353644155 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/21.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/21.kmac_stress_all.168661859 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 383910885891 ps |
| CPU time | 1156.87 seconds |
| Started | Sep 11 04:19:52 PM UTC 24 |
| Finished | Sep 11 04:39:23 PM UTC 24 |
| Peak memory | 1214460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168661859 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.168661859 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/21.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/22.kmac_alert_test.1866600328 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 15110790 ps |
| CPU time | 1.18 seconds |
| Started | Sep 11 04:21:02 PM UTC 24 |
| Finished | Sep 11 04:21:05 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866600328 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.1866600328 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/22.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/22.kmac_app.3469706001 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 20637601919 ps |
| CPU time | 127.41 seconds |
| Started | Sep 11 04:20:44 PM UTC 24 |
| Finished | Sep 11 04:22:54 PM UTC 24 |
| Peak memory | 329580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469706001 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.3469706001 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/22.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/22.kmac_burst_write.2728607615 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 25368734946 ps |
| CPU time | 777.98 seconds |
| Started | Sep 11 04:20:23 PM UTC 24 |
| Finished | Sep 11 04:33:30 PM UTC 24 |
| Peak memory | 265992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728607615 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.2728607615 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/22.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/22.kmac_entropy_refresh.166036138 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 51750474767 ps |
| CPU time | 125.05 seconds |
| Started | Sep 11 04:20:47 PM UTC 24 |
| Finished | Sep 11 04:22:54 PM UTC 24 |
| Peak memory | 313120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166036138 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.166036138 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/22.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/22.kmac_error.4170555749 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 61596527507 ps |
| CPU time | 132.75 seconds |
| Started | Sep 11 04:20:54 PM UTC 24 |
| Finished | Sep 11 04:23:09 PM UTC 24 |
| Peak memory | 347948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170555749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.4170555749 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/22.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/22.kmac_key_error.2186227496 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 3219501224 ps |
| CPU time | 4.89 seconds |
| Started | Sep 11 04:20:55 PM UTC 24 |
| Finished | Sep 11 04:21:01 PM UTC 24 |
| Peak memory | 230396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186227496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.2186227496 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/22.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/22.kmac_lc_escalation.1224927061 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 747801941 ps |
| CPU time | 15.58 seconds |
| Started | Sep 11 04:20:58 PM UTC 24 |
| Finished | Sep 11 04:21:15 PM UTC 24 |
| Peak memory | 251820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224927061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.1224927061 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/22.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/22.kmac_long_msg_and_output.2518264019 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 98664820142 ps |
| CPU time | 2595.15 seconds |
| Started | Sep 11 04:20:20 PM UTC 24 |
| Finished | Sep 11 05:04:03 PM UTC 24 |
| Peak memory | 3210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518264019 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_and_output.2518264019 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/22.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/22.kmac_sideload.3516338404 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 25291871683 ps |
| CPU time | 293.71 seconds |
| Started | Sep 11 04:20:22 PM UTC 24 |
| Finished | Sep 11 04:25:20 PM UTC 24 |
| Peak memory | 352056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516338404 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.3516338404 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/22.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/22.kmac_smoke.1991771966 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 300034340 ps |
| CPU time | 10.27 seconds |
| Started | Sep 11 04:20:09 PM UTC 24 |
| Finished | Sep 11 04:20:21 PM UTC 24 |
| Peak memory | 230508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991771966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.1991771966 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/22.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/22.kmac_stress_all.1405378593 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 83643884219 ps |
| CPU time | 1327.89 seconds |
| Started | Sep 11 04:21:00 PM UTC 24 |
| Finished | Sep 11 04:43:23 PM UTC 24 |
| Peak memory | 1300760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405378593 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.1405378593 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/22.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/23.kmac_alert_test.4258187110 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 41344253 ps |
| CPU time | 1.18 seconds |
| Started | Sep 11 04:22:08 PM UTC 24 |
| Finished | Sep 11 04:22:10 PM UTC 24 |
| Peak memory | 216284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258187110 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.4258187110 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/23.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/23.kmac_app.2239852670 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 28578360490 ps |
| CPU time | 155.94 seconds |
| Started | Sep 11 04:21:26 PM UTC 24 |
| Finished | Sep 11 04:24:05 PM UTC 24 |
| Peak memory | 352092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239852670 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.2239852670 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/23.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/23.kmac_burst_write.2317058824 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 876214627 ps |
| CPU time | 31.08 seconds |
| Started | Sep 11 04:21:16 PM UTC 24 |
| Finished | Sep 11 04:21:48 PM UTC 24 |
| Peak memory | 230440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317058824 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.2317058824 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/23.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/23.kmac_entropy_refresh.4039243681 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 2392894245 ps |
| CPU time | 36.92 seconds |
| Started | Sep 11 04:21:49 PM UTC 24 |
| Finished | Sep 11 04:22:27 PM UTC 24 |
| Peak memory | 247516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039243681 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.4039243681 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/23.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/23.kmac_error.1678606331 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1131176507 ps |
| CPU time | 91.85 seconds |
| Started | Sep 11 04:21:50 PM UTC 24 |
| Finished | Sep 11 04:23:24 PM UTC 24 |
| Peak memory | 278184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678606331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.1678606331 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/23.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/23.kmac_key_error.677593082 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 195498806 ps |
| CPU time | 2.51 seconds |
| Started | Sep 11 04:21:51 PM UTC 24 |
| Finished | Sep 11 04:21:55 PM UTC 24 |
| Peak memory | 230504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677593082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.677593082 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/23.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/23.kmac_lc_escalation.594078931 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 124495571 ps |
| CPU time | 2.46 seconds |
| Started | Sep 11 04:21:55 PM UTC 24 |
| Finished | Sep 11 04:21:59 PM UTC 24 |
| Peak memory | 235028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594078931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.594078931 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/23.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/23.kmac_long_msg_and_output.4095236067 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 133266963953 ps |
| CPU time | 1987.27 seconds |
| Started | Sep 11 04:21:06 PM UTC 24 |
| Finished | Sep 11 04:54:36 PM UTC 24 |
| Peak memory | 2565976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095236067 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_and_output.4095236067 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/23.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/23.kmac_sideload.10151523 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 87347828620 ps |
| CPU time | 264.7 seconds |
| Started | Sep 11 04:21:15 PM UTC 24 |
| Finished | Sep 11 04:25:43 PM UTC 24 |
| Peak memory | 460584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10151523 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.10151523 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/23.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/23.kmac_smoke.3566381019 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 704369334 ps |
| CPU time | 21.36 seconds |
| Started | Sep 11 04:21:03 PM UTC 24 |
| Finished | Sep 11 04:21:25 PM UTC 24 |
| Peak memory | 232508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566381019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.3566381019 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/23.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/23.kmac_stress_all.3725552289 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 24097990615 ps |
| CPU time | 785.78 seconds |
| Started | Sep 11 04:21:59 PM UTC 24 |
| Finished | Sep 11 04:35:15 PM UTC 24 |
| Peak memory | 360164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725552289 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.3725552289 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/23.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/24.kmac_alert_test.4215843998 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 28253737 ps |
| CPU time | 1.23 seconds |
| Started | Sep 11 04:22:58 PM UTC 24 |
| Finished | Sep 11 04:23:01 PM UTC 24 |
| Peak memory | 215876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215843998 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.4215843998 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/24.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/24.kmac_app.1514506471 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 4664386012 ps |
| CPU time | 114.21 seconds |
| Started | Sep 11 04:22:31 PM UTC 24 |
| Finished | Sep 11 04:24:28 PM UTC 24 |
| Peak memory | 327440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514506471 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.1514506471 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/24.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/24.kmac_burst_write.571986239 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 6486558067 ps |
| CPU time | 221.69 seconds |
| Started | Sep 11 04:22:28 PM UTC 24 |
| Finished | Sep 11 04:26:13 PM UTC 24 |
| Peak memory | 239380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571986239 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.571986239 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/24.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/24.kmac_entropy_refresh.1766140308 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 13667206620 ps |
| CPU time | 70.31 seconds |
| Started | Sep 11 04:22:40 PM UTC 24 |
| Finished | Sep 11 04:23:52 PM UTC 24 |
| Peak memory | 278300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766140308 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.1766140308 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/24.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/24.kmac_error.3269141154 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 10688087773 ps |
| CPU time | 323.49 seconds |
| Started | Sep 11 04:22:51 PM UTC 24 |
| Finished | Sep 11 04:28:19 PM UTC 24 |
| Peak memory | 532396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269141154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.3269141154 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/24.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/24.kmac_key_error.3890778265 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 1804567189 ps |
| CPU time | 4.57 seconds |
| Started | Sep 11 04:22:52 PM UTC 24 |
| Finished | Sep 11 04:22:58 PM UTC 24 |
| Peak memory | 230564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890778265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.3890778265 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/24.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/24.kmac_lc_escalation.2225727837 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 87497399 ps |
| CPU time | 1.73 seconds |
| Started | Sep 11 04:22:55 PM UTC 24 |
| Finished | Sep 11 04:22:58 PM UTC 24 |
| Peak memory | 231716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225727837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.2225727837 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/24.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/24.kmac_long_msg_and_output.1964563964 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 347865212126 ps |
| CPU time | 4056.23 seconds |
| Started | Sep 11 04:22:19 PM UTC 24 |
| Finished | Sep 11 05:30:40 PM UTC 24 |
| Peak memory | 4290500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964563964 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_and_output.1964563964 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/24.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/24.kmac_sideload.2854006104 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 42862002392 ps |
| CPU time | 351.99 seconds |
| Started | Sep 11 04:22:21 PM UTC 24 |
| Finished | Sep 11 04:28:18 PM UTC 24 |
| Peak memory | 524072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854006104 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.2854006104 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/24.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/24.kmac_smoke.1855809038 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 453778217 ps |
| CPU time | 27.64 seconds |
| Started | Sep 11 04:22:11 PM UTC 24 |
| Finished | Sep 11 04:22:40 PM UTC 24 |
| Peak memory | 232568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855809038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.1855809038 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/24.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/24.kmac_stress_all.1067418984 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 22417823044 ps |
| CPU time | 140.82 seconds |
| Started | Sep 11 04:22:55 PM UTC 24 |
| Finished | Sep 11 04:25:19 PM UTC 24 |
| Peak memory | 311004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067418984 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.1067418984 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/24.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/25.kmac_alert_test.335240740 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 89376675 ps |
| CPU time | 1.15 seconds |
| Started | Sep 11 04:24:16 PM UTC 24 |
| Finished | Sep 11 04:24:18 PM UTC 24 |
| Peak memory | 216280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335240740 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.335240740 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/25.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/25.kmac_app.68830961 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 4831646570 ps |
| CPU time | 69.51 seconds |
| Started | Sep 11 04:23:22 PM UTC 24 |
| Finished | Sep 11 04:24:33 PM UTC 24 |
| Peak memory | 274224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68830961 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.68830961 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/25.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/25.kmac_burst_write.951365585 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 62744126117 ps |
| CPU time | 654.64 seconds |
| Started | Sep 11 04:23:13 PM UTC 24 |
| Finished | Sep 11 04:34:16 PM UTC 24 |
| Peak memory | 255980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951365585 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.951365585 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/25.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/25.kmac_entropy_refresh.1539154589 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 23391314280 ps |
| CPU time | 243.99 seconds |
| Started | Sep 11 04:23:25 PM UTC 24 |
| Finished | Sep 11 04:27:33 PM UTC 24 |
| Peak memory | 337720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539154589 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.1539154589 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/25.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/25.kmac_error.504027105 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 1180933940 ps |
| CPU time | 29.26 seconds |
| Started | Sep 11 04:23:53 PM UTC 24 |
| Finished | Sep 11 04:24:23 PM UTC 24 |
| Peak memory | 261864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504027105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.504027105 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/25.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/25.kmac_key_error.1449115517 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 2466741638 ps |
| CPU time | 4.4 seconds |
| Started | Sep 11 04:24:06 PM UTC 24 |
| Finished | Sep 11 04:24:11 PM UTC 24 |
| Peak memory | 230448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449115517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.1449115517 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/25.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/25.kmac_lc_escalation.1410359338 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 55456573 ps |
| CPU time | 1.65 seconds |
| Started | Sep 11 04:24:12 PM UTC 24 |
| Finished | Sep 11 04:24:15 PM UTC 24 |
| Peak memory | 229672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410359338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.1410359338 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/25.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/25.kmac_long_msg_and_output.4082419897 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 38169538326 ps |
| CPU time | 1786.86 seconds |
| Started | Sep 11 04:23:02 PM UTC 24 |
| Finished | Sep 11 04:53:08 PM UTC 24 |
| Peak memory | 1411044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082419897 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_and_output.4082419897 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/25.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/25.kmac_sideload.535119632 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 50888637253 ps |
| CPU time | 336.86 seconds |
| Started | Sep 11 04:23:10 PM UTC 24 |
| Finished | Sep 11 04:28:51 PM UTC 24 |
| Peak memory | 562976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535119632 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.535119632 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/25.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/25.kmac_smoke.3252753628 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 18967843571 ps |
| CPU time | 74.54 seconds |
| Started | Sep 11 04:22:59 PM UTC 24 |
| Finished | Sep 11 04:24:15 PM UTC 24 |
| Peak memory | 234624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252753628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.3252753628 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/25.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/25.kmac_stress_all.1971043193 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 41045253303 ps |
| CPU time | 227.96 seconds |
| Started | Sep 11 04:24:15 PM UTC 24 |
| Finished | Sep 11 04:28:07 PM UTC 24 |
| Peak memory | 350188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971043193 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.1971043193 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/25.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/26.kmac_alert_test.3066192901 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 15104390 ps |
| CPU time | 1.17 seconds |
| Started | Sep 11 04:25:18 PM UTC 24 |
| Finished | Sep 11 04:25:20 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066192901 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.3066192901 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/26.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/26.kmac_app.254059741 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 9100465288 ps |
| CPU time | 113.22 seconds |
| Started | Sep 11 04:24:29 PM UTC 24 |
| Finished | Sep 11 04:26:24 PM UTC 24 |
| Peak memory | 278288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254059741 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.254059741 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/26.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/26.kmac_burst_write.287326564 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 12406438391 ps |
| CPU time | 372.25 seconds |
| Started | Sep 11 04:24:27 PM UTC 24 |
| Finished | Sep 11 04:30:44 PM UTC 24 |
| Peak memory | 241380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287326564 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.287326564 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/26.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/26.kmac_entropy_refresh.1129948112 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 9935148102 ps |
| CPU time | 48.14 seconds |
| Started | Sep 11 04:24:34 PM UTC 24 |
| Finished | Sep 11 04:25:23 PM UTC 24 |
| Peak memory | 247592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129948112 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.1129948112 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/26.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/26.kmac_error.4232163963 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 53436867911 ps |
| CPU time | 390.42 seconds |
| Started | Sep 11 04:24:58 PM UTC 24 |
| Finished | Sep 11 04:31:34 PM UTC 24 |
| Peak memory | 581480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232163963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.4232163963 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/26.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/26.kmac_key_error.4038748027 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 905916779 ps |
| CPU time | 5.93 seconds |
| Started | Sep 11 04:25:10 PM UTC 24 |
| Finished | Sep 11 04:25:17 PM UTC 24 |
| Peak memory | 230600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038748027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.4038748027 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/26.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/26.kmac_lc_escalation.2916770046 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 78557654 ps |
| CPU time | 1.65 seconds |
| Started | Sep 11 04:25:14 PM UTC 24 |
| Finished | Sep 11 04:25:17 PM UTC 24 |
| Peak memory | 231768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916770046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.2916770046 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/26.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/26.kmac_long_msg_and_output.2968217672 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 27953167397 ps |
| CPU time | 1045.14 seconds |
| Started | Sep 11 04:24:19 PM UTC 24 |
| Finished | Sep 11 04:41:57 PM UTC 24 |
| Peak memory | 1554264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968217672 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_and_output.2968217672 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/26.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/26.kmac_sideload.895025263 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 29648616902 ps |
| CPU time | 459.59 seconds |
| Started | Sep 11 04:24:24 PM UTC 24 |
| Finished | Sep 11 04:32:10 PM UTC 24 |
| Peak memory | 634976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895025263 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.895025263 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/26.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/26.kmac_smoke.410041080 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 2459619364 ps |
| CPU time | 55.53 seconds |
| Started | Sep 11 04:24:16 PM UTC 24 |
| Finished | Sep 11 04:25:13 PM UTC 24 |
| Peak memory | 235220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410041080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.410041080 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/26.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/26.kmac_stress_all.1183605941 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 87122110862 ps |
| CPU time | 792.39 seconds |
| Started | Sep 11 04:25:17 PM UTC 24 |
| Finished | Sep 11 04:38:39 PM UTC 24 |
| Peak memory | 581416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183605941 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.1183605941 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/26.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/27.kmac_alert_test.1812393803 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 17799000 ps |
| CPU time | 1.28 seconds |
| Started | Sep 11 04:26:13 PM UTC 24 |
| Finished | Sep 11 04:26:16 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812393803 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.1812393803 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/27.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/27.kmac_app.4190799947 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 621269297 ps |
| CPU time | 29.46 seconds |
| Started | Sep 11 04:25:40 PM UTC 24 |
| Finished | Sep 11 04:26:11 PM UTC 24 |
| Peak memory | 235236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190799947 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.4190799947 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/27.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/27.kmac_burst_write.308471907 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 25657430541 ps |
| CPU time | 726.64 seconds |
| Started | Sep 11 04:25:25 PM UTC 24 |
| Finished | Sep 11 04:37:41 PM UTC 24 |
| Peak memory | 247664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308471907 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.308471907 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/27.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/27.kmac_entropy_refresh.563828108 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 57069099076 ps |
| CPU time | 242.37 seconds |
| Started | Sep 11 04:25:41 PM UTC 24 |
| Finished | Sep 11 04:29:47 PM UTC 24 |
| Peak memory | 460572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563828108 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.563828108 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/27.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/27.kmac_error.3039795364 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 10951366103 ps |
| CPU time | 224.06 seconds |
| Started | Sep 11 04:25:42 PM UTC 24 |
| Finished | Sep 11 04:29:29 PM UTC 24 |
| Peak memory | 325392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039795364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.3039795364 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/27.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/27.kmac_key_error.2106360950 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 865363832 ps |
| CPU time | 8.42 seconds |
| Started | Sep 11 04:25:44 PM UTC 24 |
| Finished | Sep 11 04:25:53 PM UTC 24 |
| Peak memory | 230308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106360950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.2106360950 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/27.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/27.kmac_long_msg_and_output.3495707459 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 1441679128 ps |
| CPU time | 19.87 seconds |
| Started | Sep 11 04:25:20 PM UTC 24 |
| Finished | Sep 11 04:25:41 PM UTC 24 |
| Peak memory | 257752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495707459 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_and_output.3495707459 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/27.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/27.kmac_sideload.2756763462 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 8887374221 ps |
| CPU time | 242.48 seconds |
| Started | Sep 11 04:25:21 PM UTC 24 |
| Finished | Sep 11 04:29:27 PM UTC 24 |
| Peak memory | 481072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756763462 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.2756763462 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/27.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/27.kmac_smoke.2246978963 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 8651777087 ps |
| CPU time | 63.91 seconds |
| Started | Sep 11 04:25:19 PM UTC 24 |
| Finished | Sep 11 04:26:25 PM UTC 24 |
| Peak memory | 232628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246978963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.2246978963 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/27.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/27.kmac_stress_all.2586794459 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 105946967251 ps |
| CPU time | 1178.02 seconds |
| Started | Sep 11 04:26:11 PM UTC 24 |
| Finished | Sep 11 04:46:04 PM UTC 24 |
| Peak memory | 1214520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586794459 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.2586794459 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/27.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/28.kmac_alert_test.3740119067 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 18423467 ps |
| CPU time | 1.3 seconds |
| Started | Sep 11 04:27:09 PM UTC 24 |
| Finished | Sep 11 04:27:11 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740119067 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.3740119067 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/28.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/28.kmac_app.3995546931 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 547453028 ps |
| CPU time | 16.72 seconds |
| Started | Sep 11 04:26:26 PM UTC 24 |
| Finished | Sep 11 04:26:44 PM UTC 24 |
| Peak memory | 235296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995546931 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.3995546931 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/28.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/28.kmac_burst_write.334217944 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 45623917672 ps |
| CPU time | 259.14 seconds |
| Started | Sep 11 04:26:24 PM UTC 24 |
| Finished | Sep 11 04:30:46 PM UTC 24 |
| Peak memory | 241644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334217944 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.334217944 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/28.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/28.kmac_entropy_refresh.3327462926 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 2777854321 ps |
| CPU time | 42.18 seconds |
| Started | Sep 11 04:26:26 PM UTC 24 |
| Finished | Sep 11 04:27:09 PM UTC 24 |
| Peak memory | 241512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327462926 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.3327462926 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/28.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/28.kmac_error.215130147 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 130400894109 ps |
| CPU time | 349.47 seconds |
| Started | Sep 11 04:26:40 PM UTC 24 |
| Finished | Sep 11 04:32:34 PM UTC 24 |
| Peak memory | 559148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215130147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.215130147 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/28.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/28.kmac_key_error.3545932477 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 466842266 ps |
| CPU time | 5.14 seconds |
| Started | Sep 11 04:26:45 PM UTC 24 |
| Finished | Sep 11 04:26:51 PM UTC 24 |
| Peak memory | 230520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545932477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.3545932477 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/28.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/28.kmac_lc_escalation.696661781 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 991632495 ps |
| CPU time | 14.37 seconds |
| Started | Sep 11 04:26:52 PM UTC 24 |
| Finished | Sep 11 04:27:08 PM UTC 24 |
| Peak memory | 245736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696661781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.696661781 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/28.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/28.kmac_long_msg_and_output.818270737 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 267229445374 ps |
| CPU time | 2762.1 seconds |
| Started | Sep 11 04:26:16 PM UTC 24 |
| Finished | Sep 11 05:12:53 PM UTC 24 |
| Peak memory | 3219248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818270737 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_and_output.818270737 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/28.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/28.kmac_sideload.361184066 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 13213691587 ps |
| CPU time | 298.48 seconds |
| Started | Sep 11 04:26:18 PM UTC 24 |
| Finished | Sep 11 04:31:22 PM UTC 24 |
| Peak memory | 505696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361184066 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.361184066 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/28.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/28.kmac_smoke.1502299521 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 3912373394 ps |
| CPU time | 23.52 seconds |
| Started | Sep 11 04:26:14 PM UTC 24 |
| Finished | Sep 11 04:26:39 PM UTC 24 |
| Peak memory | 234892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502299521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.1502299521 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/28.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/28.kmac_stress_all.1385042110 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 622574453127 ps |
| CPU time | 2096.04 seconds |
| Started | Sep 11 04:27:08 PM UTC 24 |
| Finished | Sep 11 05:02:28 PM UTC 24 |
| Peak memory | 1601488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385042110 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.1385042110 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/28.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/29.kmac_alert_test.2916754003 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 54224280 ps |
| CPU time | 1.27 seconds |
| Started | Sep 11 04:28:42 PM UTC 24 |
| Finished | Sep 11 04:28:44 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916754003 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.2916754003 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/29.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/29.kmac_app.693383125 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 3577231542 ps |
| CPU time | 218.77 seconds |
| Started | Sep 11 04:28:08 PM UTC 24 |
| Finished | Sep 11 04:31:50 PM UTC 24 |
| Peak memory | 329636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693383125 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.693383125 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/29.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/29.kmac_burst_write.4085914918 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 71559803870 ps |
| CPU time | 1186.23 seconds |
| Started | Sep 11 04:27:34 PM UTC 24 |
| Finished | Sep 11 04:47:34 PM UTC 24 |
| Peak memory | 274212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085914918 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.4085914918 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/29.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/29.kmac_entropy_refresh.3075555146 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 9718089791 ps |
| CPU time | 238.49 seconds |
| Started | Sep 11 04:28:19 PM UTC 24 |
| Finished | Sep 11 04:32:21 PM UTC 24 |
| Peak memory | 335636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075555146 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.3075555146 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/29.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/29.kmac_error.3869330358 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 457237160 ps |
| CPU time | 34.41 seconds |
| Started | Sep 11 04:28:20 PM UTC 24 |
| Finished | Sep 11 04:28:56 PM UTC 24 |
| Peak memory | 251600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869330358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.3869330358 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/29.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/29.kmac_key_error.3408565511 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 10047473139 ps |
| CPU time | 20 seconds |
| Started | Sep 11 04:28:20 PM UTC 24 |
| Finished | Sep 11 04:28:41 PM UTC 24 |
| Peak memory | 230640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408565511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.3408565511 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/29.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/29.kmac_lc_escalation.2589918466 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 99827741 ps |
| CPU time | 2.06 seconds |
| Started | Sep 11 04:28:29 PM UTC 24 |
| Finished | Sep 11 04:28:32 PM UTC 24 |
| Peak memory | 230524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589918466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.2589918466 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/29.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/29.kmac_long_msg_and_output.3599014671 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 27991047639 ps |
| CPU time | 2723.73 seconds |
| Started | Sep 11 04:27:12 PM UTC 24 |
| Finished | Sep 11 05:13:07 PM UTC 24 |
| Peak memory | 1920812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599014671 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_and_output.3599014671 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/29.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/29.kmac_sideload.3632636501 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 2947029225 ps |
| CPU time | 100.45 seconds |
| Started | Sep 11 04:27:18 PM UTC 24 |
| Finished | Sep 11 04:29:01 PM UTC 24 |
| Peak memory | 304928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632636501 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.3632636501 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/29.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/29.kmac_smoke.3280068397 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 269699344 ps |
| CPU time | 5.93 seconds |
| Started | Sep 11 04:27:10 PM UTC 24 |
| Finished | Sep 11 04:27:17 PM UTC 24 |
| Peak memory | 230464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280068397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.3280068397 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/29.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/29.kmac_stress_all.1027463996 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 23521293289 ps |
| CPU time | 347.99 seconds |
| Started | Sep 11 04:28:33 PM UTC 24 |
| Finished | Sep 11 04:34:26 PM UTC 24 |
| Peak memory | 362344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027463996 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.1027463996 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/29.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/3.kmac_alert_test.1859304411 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 32351206 ps |
| CPU time | 1.34 seconds |
| Started | Sep 11 03:57:55 PM UTC 24 |
| Finished | Sep 11 03:57:58 PM UTC 24 |
| Peak memory | 216280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859304411 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.1859304411 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/3.kmac_app.2494398013 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 10921622045 ps |
| CPU time | 193.98 seconds |
| Started | Sep 11 03:56:27 PM UTC 24 |
| Finished | Sep 11 03:59:44 PM UTC 24 |
| Peak memory | 415520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494398013 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.2494398013 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/3.kmac_app_with_partial_data.1217476002 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 2746515595 ps |
| CPU time | 28.19 seconds |
| Started | Sep 11 03:56:28 PM UTC 24 |
| Finished | Sep 11 03:56:58 PM UTC 24 |
| Peak memory | 245544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217476002 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.1217476002 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/3.kmac_burst_write.2675885269 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 9255654434 ps |
| CPU time | 363.42 seconds |
| Started | Sep 11 03:55:44 PM UTC 24 |
| Finished | Sep 11 04:01:52 PM UTC 24 |
| Peak memory | 247840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675885269 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.2675885269 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/3.kmac_edn_timeout_error.1298112470 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 886794016 ps |
| CPU time | 16.16 seconds |
| Started | Sep 11 03:56:50 PM UTC 24 |
| Finished | Sep 11 03:57:08 PM UTC 24 |
| Peak memory | 232392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298112470 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.1298112470 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_mode_error.3540993913 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 2005058146 ps |
| CPU time | 54.44 seconds |
| Started | Sep 11 03:56:58 PM UTC 24 |
| Finished | Sep 11 03:57:55 PM UTC 24 |
| Peak memory | 234368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540993913 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.3540993913 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_ready_error.3463966233 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 5674844965 ps |
| CPU time | 68.53 seconds |
| Started | Sep 11 03:56:58 PM UTC 24 |
| Finished | Sep 11 03:58:09 PM UTC 24 |
| Peak memory | 230776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463966233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.3463966233 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_refresh.104530137 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 63954412740 ps |
| CPU time | 421.98 seconds |
| Started | Sep 11 03:56:31 PM UTC 24 |
| Finished | Sep 11 04:03:39 PM UTC 24 |
| Peak memory | 511776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104530137 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.104530137 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/3.kmac_error.2483262321 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 3031197960 ps |
| CPU time | 89.97 seconds |
| Started | Sep 11 03:56:38 PM UTC 24 |
| Finished | Sep 11 03:58:10 PM UTC 24 |
| Peak memory | 311276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483262321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.2483262321 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/3.kmac_key_error.3468131337 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 872769347 ps |
| CPU time | 7.83 seconds |
| Started | Sep 11 03:56:40 PM UTC 24 |
| Finished | Sep 11 03:56:49 PM UTC 24 |
| Peak memory | 230592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468131337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.3468131337 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/3.kmac_lc_escalation.1398669919 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 2742465724 ps |
| CPU time | 17.54 seconds |
| Started | Sep 11 03:57:09 PM UTC 24 |
| Finished | Sep 11 03:57:27 PM UTC 24 |
| Peak memory | 247596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398669919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.1398669919 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/3.kmac_long_msg_and_output.92988369 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 21356400745 ps |
| CPU time | 1015.18 seconds |
| Started | Sep 11 03:55:24 PM UTC 24 |
| Finished | Sep 11 04:12:32 PM UTC 24 |
| Peak memory | 894948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92988369 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_and_output.92988369 +enable_masking =0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/3.kmac_mubi.154598077 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 142116558833 ps |
| CPU time | 264.2 seconds |
| Started | Sep 11 03:56:32 PM UTC 24 |
| Finished | Sep 11 04:01:00 PM UTC 24 |
| Peak memory | 419840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154598077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.154598077 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/3.kmac_sec_cm.1864680831 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 42253884073 ps |
| CPU time | 46.5 seconds |
| Started | Sep 11 03:57:51 PM UTC 24 |
| Finished | Sep 11 03:58:39 PM UTC 24 |
| Peak memory | 273332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864680831 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.1864680831 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/3.kmac_sideload.3382011888 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 76034044234 ps |
| CPU time | 457.4 seconds |
| Started | Sep 11 03:55:31 PM UTC 24 |
| Finished | Sep 11 04:03:15 PM UTC 24 |
| Peak memory | 614392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382011888 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.3382011888 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/3.kmac_smoke.931565788 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 1613143747 ps |
| CPU time | 40.07 seconds |
| Started | Sep 11 03:55:12 PM UTC 24 |
| Finished | Sep 11 03:55:54 PM UTC 24 |
| Peak memory | 234732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931565788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.931565788 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/3.kmac_stress_all.1366253110 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 118182515378 ps |
| CPU time | 1396.97 seconds |
| Started | Sep 11 03:57:28 PM UTC 24 |
| Finished | Sep 11 04:21:01 PM UTC 24 |
| Peak memory | 1349708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366253110 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.1366253110 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac.2207880279 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 103815476 ps |
| CPU time | 2.87 seconds |
| Started | Sep 11 03:56:18 PM UTC 24 |
| Finished | Sep 11 03:56:22 PM UTC 24 |
| Peak memory | 230568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207880279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac.2207880279 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac_xof.3851741914 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 34027405 ps |
| CPU time | 2.54 seconds |
| Started | Sep 11 03:56:23 PM UTC 24 |
| Finished | Sep 11 03:56:27 PM UTC 24 |
| Peak memory | 230484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851741914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.3851741914 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_224.1764741956 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 12641420674 ps |
| CPU time | 53.4 seconds |
| Started | Sep 11 03:55:45 PM UTC 24 |
| Finished | Sep 11 03:56:40 PM UTC 24 |
| Peak memory | 257784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764741956 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.1764741956 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_256.565666068 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 6914994573 ps |
| CPU time | 61.37 seconds |
| Started | Sep 11 03:55:55 PM UTC 24 |
| Finished | Sep 11 03:56:58 PM UTC 24 |
| Peak memory | 253636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565666068 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.565666068 + enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_384.1745226707 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 72641890406 ps |
| CPU time | 1269.7 seconds |
| Started | Sep 11 03:55:58 PM UTC 24 |
| Finished | Sep 11 04:17:22 PM UTC 24 |
| Peak memory | 935568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745226707 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.1745226707 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_512.43586095 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 1116310026 ps |
| CPU time | 26.43 seconds |
| Started | Sep 11 03:55:59 PM UTC 24 |
| Finished | Sep 11 03:56:27 PM UTC 24 |
| Peak memory | 230388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43586095 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.43586095 +en able_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_128.3579914394 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 40963673841 ps |
| CPU time | 2290.67 seconds |
| Started | Sep 11 03:56:02 PM UTC 24 |
| Finished | Sep 11 04:34:40 PM UTC 24 |
| Peak memory | 1341072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579914394 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.3579914 394 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_256.2150530561 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 239895941407 ps |
| CPU time | 2369.39 seconds |
| Started | Sep 11 03:56:02 PM UTC 24 |
| Finished | Sep 11 04:36:00 PM UTC 24 |
| Peak memory | 2985600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150530561 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.2150530 561 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/3.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/30.kmac_alert_test.2349497516 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 71574228 ps |
| CPU time | 1.28 seconds |
| Started | Sep 11 04:29:37 PM UTC 24 |
| Finished | Sep 11 04:29:40 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349497516 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.2349497516 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/30.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/30.kmac_app.148865054 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 67499981416 ps |
| CPU time | 337.66 seconds |
| Started | Sep 11 04:29:02 PM UTC 24 |
| Finished | Sep 11 04:34:44 PM UTC 24 |
| Peak memory | 542748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148865054 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.148865054 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/30.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/30.kmac_burst_write.390601016 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 24738310533 ps |
| CPU time | 652.59 seconds |
| Started | Sep 11 04:28:57 PM UTC 24 |
| Finished | Sep 11 04:39:57 PM UTC 24 |
| Peak memory | 249644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390601016 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.390601016 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/30.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/30.kmac_entropy_refresh.3957453752 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 5989521302 ps |
| CPU time | 170 seconds |
| Started | Sep 11 04:29:26 PM UTC 24 |
| Finished | Sep 11 04:32:19 PM UTC 24 |
| Peak memory | 313076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957453752 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.3957453752 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/30.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/30.kmac_error.824664871 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 10074136181 ps |
| CPU time | 78.18 seconds |
| Started | Sep 11 04:29:28 PM UTC 24 |
| Finished | Sep 11 04:30:48 PM UTC 24 |
| Peak memory | 300900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824664871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.824664871 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/30.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/30.kmac_key_error.3253180837 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 1868020502 ps |
| CPU time | 5.51 seconds |
| Started | Sep 11 04:29:30 PM UTC 24 |
| Finished | Sep 11 04:29:37 PM UTC 24 |
| Peak memory | 230328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253180837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.3253180837 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/30.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/30.kmac_lc_escalation.2077288410 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 35843421 ps |
| CPU time | 1.86 seconds |
| Started | Sep 11 04:29:33 PM UTC 24 |
| Finished | Sep 11 04:29:36 PM UTC 24 |
| Peak memory | 229732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077288410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.2077288410 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/30.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/30.kmac_long_msg_and_output.2680437756 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 87323512342 ps |
| CPU time | 714.4 seconds |
| Started | Sep 11 04:28:49 PM UTC 24 |
| Finished | Sep 11 04:40:52 PM UTC 24 |
| Peak memory | 1234716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680437756 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_and_output.2680437756 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/30.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/30.kmac_sideload.4114405589 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 1023171130 ps |
| CPU time | 68.99 seconds |
| Started | Sep 11 04:28:52 PM UTC 24 |
| Finished | Sep 11 04:30:02 PM UTC 24 |
| Peak memory | 251616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114405589 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.4114405589 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/30.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/30.kmac_smoke.544360367 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 3352603234 ps |
| CPU time | 45.2 seconds |
| Started | Sep 11 04:28:45 PM UTC 24 |
| Finished | Sep 11 04:29:32 PM UTC 24 |
| Peak memory | 230604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544360367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.544360367 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/30.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/30.kmac_stress_all.241111164 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 60489792767 ps |
| CPU time | 1240.76 seconds |
| Started | Sep 11 04:29:37 PM UTC 24 |
| Finished | Sep 11 04:50:32 PM UTC 24 |
| Peak memory | 823076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241111164 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.241111164 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/30.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/31.kmac_alert_test.4064104432 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 25878963 ps |
| CPU time | 1.1 seconds |
| Started | Sep 11 04:31:20 PM UTC 24 |
| Finished | Sep 11 04:31:23 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064104432 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.4064104432 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/31.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/31.kmac_app.689923752 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 10893903330 ps |
| CPU time | 314.3 seconds |
| Started | Sep 11 04:30:40 PM UTC 24 |
| Finished | Sep 11 04:35:59 PM UTC 24 |
| Peak memory | 458608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689923752 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.689923752 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/31.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/31.kmac_burst_write.1373485403 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 12863619790 ps |
| CPU time | 441.81 seconds |
| Started | Sep 11 04:30:14 PM UTC 24 |
| Finished | Sep 11 04:37:42 PM UTC 24 |
| Peak memory | 249548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373485403 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.1373485403 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/31.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/31.kmac_entropy_refresh.1466971379 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 3986732228 ps |
| CPU time | 224.01 seconds |
| Started | Sep 11 04:30:45 PM UTC 24 |
| Finished | Sep 11 04:34:32 PM UTC 24 |
| Peak memory | 319272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466971379 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.1466971379 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/31.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/31.kmac_error.755463750 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 14357140960 ps |
| CPU time | 335.31 seconds |
| Started | Sep 11 04:30:47 PM UTC 24 |
| Finished | Sep 11 04:36:27 PM UTC 24 |
| Peak memory | 352244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755463750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.755463750 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/31.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/31.kmac_key_error.1568222516 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 7077281581 ps |
| CPU time | 10.04 seconds |
| Started | Sep 11 04:30:49 PM UTC 24 |
| Finished | Sep 11 04:31:00 PM UTC 24 |
| Peak memory | 230708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568222516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.1568222516 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/31.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/31.kmac_lc_escalation.1676327823 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 2883549591 ps |
| CPU time | 32.15 seconds |
| Started | Sep 11 04:31:01 PM UTC 24 |
| Finished | Sep 11 04:31:35 PM UTC 24 |
| Peak memory | 251620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676327823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.1676327823 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/31.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/31.kmac_long_msg_and_output.2974423210 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 178483063643 ps |
| CPU time | 1345.73 seconds |
| Started | Sep 11 04:29:47 PM UTC 24 |
| Finished | Sep 11 04:52:29 PM UTC 24 |
| Peak memory | 1982176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974423210 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_and_output.2974423210 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/31.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/31.kmac_sideload.213651922 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 23814206267 ps |
| CPU time | 286.68 seconds |
| Started | Sep 11 04:30:04 PM UTC 24 |
| Finished | Sep 11 04:34:55 PM UTC 24 |
| Peak memory | 343768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213651922 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.213651922 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/31.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/31.kmac_smoke.3321548330 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 2085557265 ps |
| CPU time | 56.92 seconds |
| Started | Sep 11 04:29:40 PM UTC 24 |
| Finished | Sep 11 04:30:39 PM UTC 24 |
| Peak memory | 235412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321548330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.3321548330 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/31.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/31.kmac_stress_all.990505223 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 159538049286 ps |
| CPU time | 1663.95 seconds |
| Started | Sep 11 04:31:14 PM UTC 24 |
| Finished | Sep 11 04:59:18 PM UTC 24 |
| Peak memory | 1249260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990505223 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.990505223 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/31.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/32.kmac_alert_test.2018153317 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 17644457 ps |
| CPU time | 1.25 seconds |
| Started | Sep 11 04:32:24 PM UTC 24 |
| Finished | Sep 11 04:32:26 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018153317 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.2018153317 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/32.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/32.kmac_app.3546659872 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 3362169580 ps |
| CPU time | 16.81 seconds |
| Started | Sep 11 04:31:51 PM UTC 24 |
| Finished | Sep 11 04:32:09 PM UTC 24 |
| Peak memory | 235256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546659872 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.3546659872 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/32.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/32.kmac_burst_write.2259213998 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 25178332802 ps |
| CPU time | 789.98 seconds |
| Started | Sep 11 04:31:36 PM UTC 24 |
| Finished | Sep 11 04:44:56 PM UTC 24 |
| Peak memory | 261872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259213998 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.2259213998 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/32.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/32.kmac_entropy_refresh.2808299465 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 5628748081 ps |
| CPU time | 66.25 seconds |
| Started | Sep 11 04:32:10 PM UTC 24 |
| Finished | Sep 11 04:33:18 PM UTC 24 |
| Peak memory | 261944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808299465 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.2808299465 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/32.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/32.kmac_error.3136078889 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 9773872298 ps |
| CPU time | 323.73 seconds |
| Started | Sep 11 04:32:11 PM UTC 24 |
| Finished | Sep 11 04:37:40 PM UTC 24 |
| Peak memory | 495404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136078889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.3136078889 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/32.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/32.kmac_key_error.3365445903 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 5871058434 ps |
| CPU time | 7.46 seconds |
| Started | Sep 11 04:32:19 PM UTC 24 |
| Finished | Sep 11 04:32:28 PM UTC 24 |
| Peak memory | 232432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365445903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.3365445903 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/32.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/32.kmac_long_msg_and_output.2951689518 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 103211731817 ps |
| CPU time | 3485.73 seconds |
| Started | Sep 11 04:31:24 PM UTC 24 |
| Finished | Sep 11 05:30:07 PM UTC 24 |
| Peak memory | 4161504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951689518 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_and_output.2951689518 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/32.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/32.kmac_sideload.2872667367 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 10793956586 ps |
| CPU time | 249.8 seconds |
| Started | Sep 11 04:31:35 PM UTC 24 |
| Finished | Sep 11 04:35:49 PM UTC 24 |
| Peak memory | 331636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872667367 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.2872667367 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/32.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/32.kmac_smoke.972791189 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 2119096786 ps |
| CPU time | 54.78 seconds |
| Started | Sep 11 04:31:23 PM UTC 24 |
| Finished | Sep 11 04:32:20 PM UTC 24 |
| Peak memory | 230460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972791189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.972791189 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/32.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/32.kmac_stress_all.2629834917 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 55103001121 ps |
| CPU time | 869.57 seconds |
| Started | Sep 11 04:32:22 PM UTC 24 |
| Finished | Sep 11 04:47:01 PM UTC 24 |
| Peak memory | 1165264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629834917 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.2629834917 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/32.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/33.kmac_alert_test.380120902 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 50084354 ps |
| CPU time | 1.29 seconds |
| Started | Sep 11 04:34:27 PM UTC 24 |
| Finished | Sep 11 04:34:29 PM UTC 24 |
| Peak memory | 216280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380120902 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.380120902 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/33.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/33.kmac_app.516803581 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 7145030691 ps |
| CPU time | 70.79 seconds |
| Started | Sep 11 04:33:19 PM UTC 24 |
| Finished | Sep 11 04:34:32 PM UTC 24 |
| Peak memory | 263972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516803581 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.516803581 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/33.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/33.kmac_burst_write.3413557287 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 53154267735 ps |
| CPU time | 552.47 seconds |
| Started | Sep 11 04:32:58 PM UTC 24 |
| Finished | Sep 11 04:42:18 PM UTC 24 |
| Peak memory | 251624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413557287 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.3413557287 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/33.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/33.kmac_entropy_refresh.2212258504 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 16894573055 ps |
| CPU time | 218.04 seconds |
| Started | Sep 11 04:33:21 PM UTC 24 |
| Finished | Sep 11 04:37:03 PM UTC 24 |
| Peak memory | 360240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212258504 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.2212258504 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/33.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/33.kmac_error.133252190 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 34590477572 ps |
| CPU time | 198.7 seconds |
| Started | Sep 11 04:33:31 PM UTC 24 |
| Finished | Sep 11 04:36:53 PM UTC 24 |
| Peak memory | 436000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133252190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.133252190 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/33.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/33.kmac_key_error.4095763985 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 562643938 ps |
| CPU time | 6.15 seconds |
| Started | Sep 11 04:34:17 PM UTC 24 |
| Finished | Sep 11 04:34:24 PM UTC 24 |
| Peak memory | 230452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095763985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.4095763985 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/33.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/33.kmac_lc_escalation.2040113922 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 47009015 ps |
| CPU time | 2.71 seconds |
| Started | Sep 11 04:34:25 PM UTC 24 |
| Finished | Sep 11 04:34:29 PM UTC 24 |
| Peak memory | 235040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040113922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.2040113922 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/33.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/33.kmac_long_msg_and_output.1715808049 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 146160085125 ps |
| CPU time | 1219.07 seconds |
| Started | Sep 11 04:32:29 PM UTC 24 |
| Finished | Sep 11 04:53:02 PM UTC 24 |
| Peak memory | 1750756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715808049 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_and_output.1715808049 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/33.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/33.kmac_sideload.4043015487 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 137399121107 ps |
| CPU time | 501.48 seconds |
| Started | Sep 11 04:32:35 PM UTC 24 |
| Finished | Sep 11 04:41:03 PM UTC 24 |
| Peak memory | 646960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043015487 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.4043015487 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/33.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/33.kmac_smoke.2101471011 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 1720094431 ps |
| CPU time | 28.61 seconds |
| Started | Sep 11 04:32:27 PM UTC 24 |
| Finished | Sep 11 04:32:57 PM UTC 24 |
| Peak memory | 232508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101471011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.2101471011 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/33.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/33.kmac_stress_all.3414001786 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 2564332202 ps |
| CPU time | 5.27 seconds |
| Started | Sep 11 04:34:25 PM UTC 24 |
| Finished | Sep 11 04:34:31 PM UTC 24 |
| Peak memory | 232644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414001786 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.3414001786 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/33.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/34.kmac_alert_test.1704857765 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 15364830 ps |
| CPU time | 1.05 seconds |
| Started | Sep 11 04:34:54 PM UTC 24 |
| Finished | Sep 11 04:34:56 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704857765 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.1704857765 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/34.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/34.kmac_app.84492487 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 19835182446 ps |
| CPU time | 101.69 seconds |
| Started | Sep 11 04:34:33 PM UTC 24 |
| Finished | Sep 11 04:36:18 PM UTC 24 |
| Peak memory | 268076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84492487 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.84492487 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/34.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/34.kmac_burst_write.641492321 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 3775135039 ps |
| CPU time | 322.37 seconds |
| Started | Sep 11 04:34:32 PM UTC 24 |
| Finished | Sep 11 04:39:59 PM UTC 24 |
| Peak memory | 243488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641492321 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.641492321 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/34.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/34.kmac_entropy_refresh.721736003 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 12674141496 ps |
| CPU time | 227.17 seconds |
| Started | Sep 11 04:34:38 PM UTC 24 |
| Finished | Sep 11 04:38:30 PM UTC 24 |
| Peak memory | 431972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721736003 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.721736003 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/34.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/34.kmac_error.4256333183 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 220994829 ps |
| CPU time | 2.99 seconds |
| Started | Sep 11 04:34:40 PM UTC 24 |
| Finished | Sep 11 04:34:45 PM UTC 24 |
| Peak memory | 230372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256333183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.4256333183 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/34.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/34.kmac_key_error.1919743674 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 645138347 ps |
| CPU time | 7.03 seconds |
| Started | Sep 11 04:34:45 PM UTC 24 |
| Finished | Sep 11 04:34:53 PM UTC 24 |
| Peak memory | 230316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919743674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.1919743674 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/34.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/34.kmac_lc_escalation.1613778649 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 288299867 ps |
| CPU time | 2.26 seconds |
| Started | Sep 11 04:34:46 PM UTC 24 |
| Finished | Sep 11 04:34:49 PM UTC 24 |
| Peak memory | 232692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613778649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.1613778649 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/34.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/34.kmac_long_msg_and_output.3953267625 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 98312666389 ps |
| CPU time | 587.46 seconds |
| Started | Sep 11 04:34:30 PM UTC 24 |
| Finished | Sep 11 04:44:26 PM UTC 24 |
| Peak memory | 1017632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953267625 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_and_output.3953267625 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/34.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/34.kmac_sideload.2510895747 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 7959395698 ps |
| CPU time | 396.88 seconds |
| Started | Sep 11 04:34:32 PM UTC 24 |
| Finished | Sep 11 04:41:15 PM UTC 24 |
| Peak memory | 372268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510895747 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.2510895747 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/34.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/34.kmac_smoke.125136717 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 1098664592 ps |
| CPU time | 7.19 seconds |
| Started | Sep 11 04:34:29 PM UTC 24 |
| Finished | Sep 11 04:34:37 PM UTC 24 |
| Peak memory | 230600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125136717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.125136717 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/34.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/34.kmac_stress_all.3096965188 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 15078916854 ps |
| CPU time | 870.05 seconds |
| Started | Sep 11 04:34:50 PM UTC 24 |
| Finished | Sep 11 04:49:30 PM UTC 24 |
| Peak memory | 710876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096965188 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.3096965188 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/34.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/35.kmac_alert_test.949444591 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 70538864 ps |
| CPU time | 1.14 seconds |
| Started | Sep 11 04:36:19 PM UTC 24 |
| Finished | Sep 11 04:36:21 PM UTC 24 |
| Peak memory | 216280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949444591 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.949444591 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/35.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/35.kmac_app.1883939940 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 4912658169 ps |
| CPU time | 265.02 seconds |
| Started | Sep 11 04:35:49 PM UTC 24 |
| Finished | Sep 11 04:40:18 PM UTC 24 |
| Peak memory | 341836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883939940 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.1883939940 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/35.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/35.kmac_burst_write.177707066 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 65915040259 ps |
| CPU time | 1001.12 seconds |
| Started | Sep 11 04:35:16 PM UTC 24 |
| Finished | Sep 11 04:52:09 PM UTC 24 |
| Peak memory | 270120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177707066 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.177707066 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/35.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/35.kmac_entropy_refresh.515619624 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 46616271 ps |
| CPU time | 5.16 seconds |
| Started | Sep 11 04:35:59 PM UTC 24 |
| Finished | Sep 11 04:36:06 PM UTC 24 |
| Peak memory | 230452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515619624 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.515619624 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/35.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/35.kmac_error.3260371001 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 1351550088 ps |
| CPU time | 46.34 seconds |
| Started | Sep 11 04:36:00 PM UTC 24 |
| Finished | Sep 11 04:36:48 PM UTC 24 |
| Peak memory | 261808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260371001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.3260371001 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/35.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/35.kmac_key_error.2993716240 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 9879142731 ps |
| CPU time | 12.62 seconds |
| Started | Sep 11 04:36:07 PM UTC 24 |
| Finished | Sep 11 04:36:20 PM UTC 24 |
| Peak memory | 230388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993716240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.2993716240 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/35.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/35.kmac_lc_escalation.2806943546 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 177874585 ps |
| CPU time | 1.82 seconds |
| Started | Sep 11 04:36:12 PM UTC 24 |
| Finished | Sep 11 04:36:15 PM UTC 24 |
| Peak memory | 229736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806943546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.2806943546 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/35.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/35.kmac_long_msg_and_output.1224044952 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 18730607466 ps |
| CPU time | 1825.94 seconds |
| Started | Sep 11 04:34:57 PM UTC 24 |
| Finished | Sep 11 05:05:44 PM UTC 24 |
| Peak memory | 1324828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224044952 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_and_output.1224044952 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/35.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/35.kmac_sideload.3840186691 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 11394141952 ps |
| CPU time | 60.06 seconds |
| Started | Sep 11 04:35:09 PM UTC 24 |
| Finished | Sep 11 04:36:11 PM UTC 24 |
| Peak memory | 257832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840186691 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.3840186691 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/35.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/35.kmac_smoke.1535307528 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 729237293 ps |
| CPU time | 10.88 seconds |
| Started | Sep 11 04:34:56 PM UTC 24 |
| Finished | Sep 11 04:35:08 PM UTC 24 |
| Peak memory | 230736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535307528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.1535307528 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/35.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/35.kmac_stress_all.868112746 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 24973024923 ps |
| CPU time | 408.37 seconds |
| Started | Sep 11 04:36:16 PM UTC 24 |
| Finished | Sep 11 04:43:11 PM UTC 24 |
| Peak memory | 354204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868112746 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.868112746 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/35.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/36.kmac_alert_test.2568842613 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 39402120 ps |
| CPU time | 1.16 seconds |
| Started | Sep 11 04:37:42 PM UTC 24 |
| Finished | Sep 11 04:37:44 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568842613 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.2568842613 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/36.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/36.kmac_app.1100826319 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 16263229223 ps |
| CPU time | 297.14 seconds |
| Started | Sep 11 04:36:49 PM UTC 24 |
| Finished | Sep 11 04:41:50 PM UTC 24 |
| Peak memory | 356152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100826319 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.1100826319 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/36.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/36.kmac_burst_write.459584034 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 5522539326 ps |
| CPU time | 135.55 seconds |
| Started | Sep 11 04:36:46 PM UTC 24 |
| Finished | Sep 11 04:39:04 PM UTC 24 |
| Peak memory | 235248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459584034 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.459584034 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/36.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/36.kmac_entropy_refresh.2148651208 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 2167562580 ps |
| CPU time | 48.02 seconds |
| Started | Sep 11 04:36:54 PM UTC 24 |
| Finished | Sep 11 04:37:44 PM UTC 24 |
| Peak memory | 247588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148651208 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.2148651208 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/36.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/36.kmac_error.1889429758 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 46210724527 ps |
| CPU time | 331.72 seconds |
| Started | Sep 11 04:37:04 PM UTC 24 |
| Finished | Sep 11 04:42:41 PM UTC 24 |
| Peak memory | 464616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889429758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.1889429758 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/36.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/36.kmac_key_error.4069105694 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 34855938105 ps |
| CPU time | 16.86 seconds |
| Started | Sep 11 04:37:06 PM UTC 24 |
| Finished | Sep 11 04:37:24 PM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069105694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.4069105694 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/36.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/36.kmac_lc_escalation.4020202116 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 516824432 ps |
| CPU time | 20.39 seconds |
| Started | Sep 11 04:37:26 PM UTC 24 |
| Finished | Sep 11 04:37:47 PM UTC 24 |
| Peak memory | 247648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020202116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.4020202116 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/36.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/36.kmac_long_msg_and_output.703061649 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 8665405508 ps |
| CPU time | 780.65 seconds |
| Started | Sep 11 04:36:22 PM UTC 24 |
| Finished | Sep 11 04:49:32 PM UTC 24 |
| Peak memory | 767732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703061649 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_and_output.703061649 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/36.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/36.kmac_sideload.1753094953 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 77099949119 ps |
| CPU time | 493.31 seconds |
| Started | Sep 11 04:36:28 PM UTC 24 |
| Finished | Sep 11 04:44:49 PM UTC 24 |
| Peak memory | 624368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753094953 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.1753094953 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/36.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/36.kmac_smoke.1988969679 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 4221936632 ps |
| CPU time | 87.03 seconds |
| Started | Sep 11 04:36:21 PM UTC 24 |
| Finished | Sep 11 04:37:50 PM UTC 24 |
| Peak memory | 234880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988969679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.1988969679 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/36.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/36.kmac_stress_all.2608208705 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 66476744237 ps |
| CPU time | 1044.29 seconds |
| Started | Sep 11 04:37:41 PM UTC 24 |
| Finished | Sep 11 04:55:18 PM UTC 24 |
| Peak memory | 747548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608208705 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.2608208705 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/36.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/37.kmac_alert_test.3127169109 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 22884405 ps |
| CPU time | 1.21 seconds |
| Started | Sep 11 04:39:04 PM UTC 24 |
| Finished | Sep 11 04:39:06 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127169109 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.3127169109 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/37.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/37.kmac_app.1795250546 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 12800053286 ps |
| CPU time | 240.06 seconds |
| Started | Sep 11 04:37:48 PM UTC 24 |
| Finished | Sep 11 04:41:52 PM UTC 24 |
| Peak memory | 485216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795250546 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.1795250546 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/37.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/37.kmac_burst_write.593846693 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 4249685791 ps |
| CPU time | 527.27 seconds |
| Started | Sep 11 04:37:46 PM UTC 24 |
| Finished | Sep 11 04:46:41 PM UTC 24 |
| Peak memory | 248940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593846693 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.593846693 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/37.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/37.kmac_entropy_refresh.4081703054 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 61204296970 ps |
| CPU time | 90.8 seconds |
| Started | Sep 11 04:37:51 PM UTC 24 |
| Finished | Sep 11 04:39:25 PM UTC 24 |
| Peak memory | 253672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081703054 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.4081703054 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/37.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/37.kmac_error.2429378129 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 4281609732 ps |
| CPU time | 72.33 seconds |
| Started | Sep 11 04:38:00 PM UTC 24 |
| Finished | Sep 11 04:39:14 PM UTC 24 |
| Peak memory | 268264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429378129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.2429378129 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/37.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/37.kmac_key_error.1897335409 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 256638160 ps |
| CPU time | 2.03 seconds |
| Started | Sep 11 04:38:31 PM UTC 24 |
| Finished | Sep 11 04:38:34 PM UTC 24 |
| Peak memory | 230564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897335409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.1897335409 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/37.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/37.kmac_lc_escalation.1221635098 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 10039595849 ps |
| CPU time | 26.82 seconds |
| Started | Sep 11 04:38:35 PM UTC 24 |
| Finished | Sep 11 04:39:03 PM UTC 24 |
| Peak memory | 249636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221635098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.1221635098 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/37.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/37.kmac_long_msg_and_output.315489250 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 2160628094 ps |
| CPU time | 165.4 seconds |
| Started | Sep 11 04:37:45 PM UTC 24 |
| Finished | Sep 11 04:40:33 PM UTC 24 |
| Peak memory | 350172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315489250 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_and_output.315489250 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/37.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/37.kmac_sideload.621164840 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 13265832631 ps |
| CPU time | 452.92 seconds |
| Started | Sep 11 04:37:45 PM UTC 24 |
| Finished | Sep 11 04:45:24 PM UTC 24 |
| Peak memory | 583652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621164840 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.621164840 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/37.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/37.kmac_smoke.3167655102 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 304864831 ps |
| CPU time | 15.88 seconds |
| Started | Sep 11 04:37:43 PM UTC 24 |
| Finished | Sep 11 04:38:00 PM UTC 24 |
| Peak memory | 230456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167655102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.3167655102 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/37.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/37.kmac_stress_all.3356177230 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 245609205501 ps |
| CPU time | 2716.71 seconds |
| Started | Sep 11 04:38:40 PM UTC 24 |
| Finished | Sep 11 05:24:27 PM UTC 24 |
| Peak memory | 1267980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356177230 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.3356177230 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/37.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/38.kmac_alert_test.4115356377 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 27840975 ps |
| CPU time | 1.19 seconds |
| Started | Sep 11 04:40:12 PM UTC 24 |
| Finished | Sep 11 04:40:15 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115356377 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.4115356377 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/38.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/38.kmac_app.1199139300 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 40935865971 ps |
| CPU time | 264.38 seconds |
| Started | Sep 11 04:39:23 PM UTC 24 |
| Finished | Sep 11 04:43:52 PM UTC 24 |
| Peak memory | 425696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199139300 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.1199139300 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/38.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/38.kmac_burst_write.45511100 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 18810921167 ps |
| CPU time | 452.92 seconds |
| Started | Sep 11 04:39:15 PM UTC 24 |
| Finished | Sep 11 04:46:54 PM UTC 24 |
| Peak memory | 243632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45511100 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.45511100 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/38.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/38.kmac_entropy_refresh.1821018798 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 2699519686 ps |
| CPU time | 103.82 seconds |
| Started | Sep 11 04:39:26 PM UTC 24 |
| Finished | Sep 11 04:41:12 PM UTC 24 |
| Peak memory | 261996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821018798 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.1821018798 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/38.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/38.kmac_error.836676042 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 8070728218 ps |
| CPU time | 116.44 seconds |
| Started | Sep 11 04:39:30 PM UTC 24 |
| Finished | Sep 11 04:41:28 PM UTC 24 |
| Peak memory | 339936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836676042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.836676042 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/38.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/38.kmac_key_error.1778295556 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 1076325119 ps |
| CPU time | 11.24 seconds |
| Started | Sep 11 04:39:59 PM UTC 24 |
| Finished | Sep 11 04:40:11 PM UTC 24 |
| Peak memory | 230452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778295556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.1778295556 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/38.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/38.kmac_lc_escalation.3943040779 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 145331988 ps |
| CPU time | 2.12 seconds |
| Started | Sep 11 04:40:00 PM UTC 24 |
| Finished | Sep 11 04:40:03 PM UTC 24 |
| Peak memory | 230568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943040779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.3943040779 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/38.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/38.kmac_long_msg_and_output.3373506642 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 399634847981 ps |
| CPU time | 3593.73 seconds |
| Started | Sep 11 04:39:07 PM UTC 24 |
| Finished | Sep 11 05:39:40 PM UTC 24 |
| Peak memory | 4323144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373506642 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_and_output.3373506642 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/38.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/38.kmac_sideload.3036123162 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 6865007742 ps |
| CPU time | 217.09 seconds |
| Started | Sep 11 04:39:12 PM UTC 24 |
| Finished | Sep 11 04:42:53 PM UTC 24 |
| Peak memory | 405412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036123162 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.3036123162 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/38.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/38.kmac_smoke.489537521 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 357470209 ps |
| CPU time | 22.43 seconds |
| Started | Sep 11 04:39:05 PM UTC 24 |
| Finished | Sep 11 04:39:29 PM UTC 24 |
| Peak memory | 230700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489537521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.489537521 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/38.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/38.kmac_stress_all.1168834373 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 64691344292 ps |
| CPU time | 728.99 seconds |
| Started | Sep 11 04:40:04 PM UTC 24 |
| Finished | Sep 11 04:52:22 PM UTC 24 |
| Peak memory | 370712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168834373 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.1168834373 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/38.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/39.kmac_alert_test.1033968379 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 15862112 ps |
| CPU time | 1.17 seconds |
| Started | Sep 11 04:41:29 PM UTC 24 |
| Finished | Sep 11 04:41:31 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033968379 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.1033968379 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/39.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/39.kmac_app.2029887699 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 41801149303 ps |
| CPU time | 111.14 seconds |
| Started | Sep 11 04:40:56 PM UTC 24 |
| Finished | Sep 11 04:42:49 PM UTC 24 |
| Peak memory | 327524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029887699 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.2029887699 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/39.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/39.kmac_burst_write.2239337617 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 25378797668 ps |
| CPU time | 464.87 seconds |
| Started | Sep 11 04:40:53 PM UTC 24 |
| Finished | Sep 11 04:48:44 PM UTC 24 |
| Peak memory | 249636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239337617 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.2239337617 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/39.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/39.kmac_entropy_refresh.1387582917 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 11256349680 ps |
| CPU time | 278.35 seconds |
| Started | Sep 11 04:41:04 PM UTC 24 |
| Finished | Sep 11 04:45:47 PM UTC 24 |
| Peak memory | 323356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387582917 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.1387582917 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/39.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/39.kmac_error.247202199 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 4632505665 ps |
| CPU time | 105.39 seconds |
| Started | Sep 11 04:41:12 PM UTC 24 |
| Finished | Sep 11 04:43:00 PM UTC 24 |
| Peak memory | 333612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247202199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.247202199 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/39.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/39.kmac_key_error.1135904431 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 2006669138 ps |
| CPU time | 5.73 seconds |
| Started | Sep 11 04:41:15 PM UTC 24 |
| Finished | Sep 11 04:41:22 PM UTC 24 |
| Peak memory | 230576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135904431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.1135904431 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/39.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/39.kmac_lc_escalation.2883237710 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 40765552 ps |
| CPU time | 1.64 seconds |
| Started | Sep 11 04:41:24 PM UTC 24 |
| Finished | Sep 11 04:41:26 PM UTC 24 |
| Peak memory | 231716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883237710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.2883237710 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/39.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/39.kmac_long_msg_and_output.2902290913 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 3721447137 ps |
| CPU time | 99.48 seconds |
| Started | Sep 11 04:40:20 PM UTC 24 |
| Finished | Sep 11 04:42:01 PM UTC 24 |
| Peak memory | 360216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902290913 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_and_output.2902290913 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/39.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/39.kmac_sideload.2047585172 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 6057972231 ps |
| CPU time | 81.05 seconds |
| Started | Sep 11 04:40:34 PM UTC 24 |
| Finished | Sep 11 04:41:57 PM UTC 24 |
| Peak memory | 292648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047585172 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.2047585172 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/39.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/39.kmac_smoke.2294078201 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 12705865801 ps |
| CPU time | 71.04 seconds |
| Started | Sep 11 04:40:15 PM UTC 24 |
| Finished | Sep 11 04:41:28 PM UTC 24 |
| Peak memory | 235360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294078201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.2294078201 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/39.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/39.kmac_stress_all.3964116217 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 94136689501 ps |
| CPU time | 1911.9 seconds |
| Started | Sep 11 04:41:27 PM UTC 24 |
| Finished | Sep 11 05:13:41 PM UTC 24 |
| Peak memory | 774176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964116217 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.3964116217 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/39.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/4.kmac_alert_test.3562129309 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 67847607 ps |
| CPU time | 1.26 seconds |
| Started | Sep 11 03:59:33 PM UTC 24 |
| Finished | Sep 11 03:59:35 PM UTC 24 |
| Peak memory | 216280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562129309 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.3562129309 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/4.kmac_app_with_partial_data.2111745234 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 6653612193 ps |
| CPU time | 103.23 seconds |
| Started | Sep 11 03:58:37 PM UTC 24 |
| Finished | Sep 11 04:00:23 PM UTC 24 |
| Peak memory | 323564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111745234 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.2111745234 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/4.kmac_edn_timeout_error.3545697544 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 951295689 ps |
| CPU time | 21.24 seconds |
| Started | Sep 11 03:58:53 PM UTC 24 |
| Finished | Sep 11 03:59:15 PM UTC 24 |
| Peak memory | 228356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545697544 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.3545697544 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_mode_error.2277763954 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 869132460 ps |
| CPU time | 6.3 seconds |
| Started | Sep 11 03:58:59 PM UTC 24 |
| Finished | Sep 11 03:59:06 PM UTC 24 |
| Peak memory | 228464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277763954 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.2277763954 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_ready_error.3833772842 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 34616343747 ps |
| CPU time | 96.5 seconds |
| Started | Sep 11 03:59:01 PM UTC 24 |
| Finished | Sep 11 04:00:40 PM UTC 24 |
| Peak memory | 230520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833772842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.3833772842 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_refresh.4221101964 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 156861569772 ps |
| CPU time | 195.68 seconds |
| Started | Sep 11 03:58:41 PM UTC 24 |
| Finished | Sep 11 04:01:59 PM UTC 24 |
| Peak memory | 401164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221101964 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.4221101964 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/4.kmac_key_error.1031724983 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 4782613768 ps |
| CPU time | 10.91 seconds |
| Started | Sep 11 03:58:48 PM UTC 24 |
| Finished | Sep 11 03:59:00 PM UTC 24 |
| Peak memory | 230520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031724983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.1031724983 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/4.kmac_lc_escalation.4261114492 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1215803191 ps |
| CPU time | 27.95 seconds |
| Started | Sep 11 03:59:03 PM UTC 24 |
| Finished | Sep 11 03:59:32 PM UTC 24 |
| Peak memory | 245676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261114492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.4261114492 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/4.kmac_long_msg_and_output.762570391 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 265357685340 ps |
| CPU time | 1974.49 seconds |
| Started | Sep 11 03:57:56 PM UTC 24 |
| Finished | Sep 11 04:31:13 PM UTC 24 |
| Peak memory | 2684652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762570391 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and_output.762570391 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/4.kmac_mubi.50222771 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 930080547 ps |
| CPU time | 10.34 seconds |
| Started | Sep 11 03:58:41 PM UTC 24 |
| Finished | Sep 11 03:58:52 PM UTC 24 |
| Peak memory | 245736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50222771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.50222771 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/4.kmac_sec_cm.3573161979 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 5229217310 ps |
| CPU time | 89.21 seconds |
| Started | Sep 11 03:59:16 PM UTC 24 |
| Finished | Sep 11 04:00:48 PM UTC 24 |
| Peak memory | 287408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573161979 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.3573161979 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/4.kmac_sideload.449141065 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9853217206 ps |
| CPU time | 316.38 seconds |
| Started | Sep 11 03:57:58 PM UTC 24 |
| Finished | Sep 11 04:03:19 PM UTC 24 |
| Peak memory | 499556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449141065 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.449141065 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/4.kmac_smoke.3924208257 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 782216257 ps |
| CPU time | 25.7 seconds |
| Started | Sep 11 03:57:55 PM UTC 24 |
| Finished | Sep 11 03:58:22 PM UTC 24 |
| Peak memory | 230516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924208257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.3924208257 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/4.kmac_stress_all.678928054 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 53056218296 ps |
| CPU time | 1797.05 seconds |
| Started | Sep 11 03:59:07 PM UTC 24 |
| Finished | Sep 11 04:29:25 PM UTC 24 |
| Peak memory | 1069096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678928054 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.678928054 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac.3719569798 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 53380713 ps |
| CPU time | 2.61 seconds |
| Started | Sep 11 03:58:25 PM UTC 24 |
| Finished | Sep 11 03:58:29 PM UTC 24 |
| Peak memory | 230532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719569798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac.3719569798 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac_xof.643982264 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 121144361 ps |
| CPU time | 4.43 seconds |
| Started | Sep 11 03:58:30 PM UTC 24 |
| Finished | Sep 11 03:58:35 PM UTC 24 |
| Peak memory | 230568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643982264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_ve ctors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac_xof.643982264 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_224.11733766 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 647735484 ps |
| CPU time | 44.9 seconds |
| Started | Sep 11 03:58:12 PM UTC 24 |
| Finished | Sep 11 03:58:58 PM UTC 24 |
| Peak memory | 232432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11733766 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.11733766 +en able_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_256.351249982 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 2116343423 ps |
| CPU time | 55.43 seconds |
| Started | Sep 11 03:58:14 PM UTC 24 |
| Finished | Sep 11 03:59:11 PM UTC 24 |
| Peak memory | 253580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351249982 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.351249982 + enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_384.606670125 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 1734995694 ps |
| CPU time | 28.87 seconds |
| Started | Sep 11 03:58:16 PM UTC 24 |
| Finished | Sep 11 03:58:46 PM UTC 24 |
| Peak memory | 230448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606670125 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.606670125 + enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_512.1572839785 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 11736485190 ps |
| CPU time | 22.8 seconds |
| Started | Sep 11 03:58:21 PM UTC 24 |
| Finished | Sep 11 03:58:45 PM UTC 24 |
| Peak memory | 230496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572839785 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.1572839785 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_128.1753236105 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 140377980369 ps |
| CPU time | 2709.74 seconds |
| Started | Sep 11 03:58:21 PM UTC 24 |
| Finished | Sep 11 04:44:02 PM UTC 24 |
| Peak memory | 3594232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753236105 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.1753236 105 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_256.2101312379 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 6223557447 ps |
| CPU time | 123.99 seconds |
| Started | Sep 11 03:58:23 PM UTC 24 |
| Finished | Sep 11 04:00:30 PM UTC 24 |
| Peak memory | 263956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101312379 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.2101312 379 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/4.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/40.kmac_alert_test.2382782875 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 28858217 ps |
| CPU time | 1.19 seconds |
| Started | Sep 11 04:42:19 PM UTC 24 |
| Finished | Sep 11 04:42:22 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382782875 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.2382782875 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/40.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/40.kmac_app.2611232890 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 7873210152 ps |
| CPU time | 87.97 seconds |
| Started | Sep 11 04:41:53 PM UTC 24 |
| Finished | Sep 11 04:43:22 PM UTC 24 |
| Peak memory | 301048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611232890 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.2611232890 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/40.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/40.kmac_burst_write.3717138544 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 16198521529 ps |
| CPU time | 372.63 seconds |
| Started | Sep 11 04:41:51 PM UTC 24 |
| Finished | Sep 11 04:48:09 PM UTC 24 |
| Peak memory | 246904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717138544 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.3717138544 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/40.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/40.kmac_entropy_refresh.3496772367 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 19714152479 ps |
| CPU time | 418.67 seconds |
| Started | Sep 11 04:41:58 PM UTC 24 |
| Finished | Sep 11 04:49:02 PM UTC 24 |
| Peak memory | 563184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496772367 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.3496772367 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/40.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/40.kmac_error.1829516607 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 2516115556 ps |
| CPU time | 42.96 seconds |
| Started | Sep 11 04:41:58 PM UTC 24 |
| Finished | Sep 11 04:42:42 PM UTC 24 |
| Peak memory | 251816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829516607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.1829516607 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/40.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/40.kmac_key_error.3959559828 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 4007067575 ps |
| CPU time | 12.3 seconds |
| Started | Sep 11 04:41:59 PM UTC 24 |
| Finished | Sep 11 04:42:12 PM UTC 24 |
| Peak memory | 230708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959559828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.3959559828 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/40.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/40.kmac_lc_escalation.2117595899 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 4715442720 ps |
| CPU time | 25.26 seconds |
| Started | Sep 11 04:42:02 PM UTC 24 |
| Finished | Sep 11 04:42:29 PM UTC 24 |
| Peak memory | 251808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117595899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.2117595899 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/40.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/40.kmac_long_msg_and_output.3043448051 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 232234199181 ps |
| CPU time | 1650.98 seconds |
| Started | Sep 11 04:41:32 PM UTC 24 |
| Finished | Sep 11 05:09:23 PM UTC 24 |
| Peak memory | 2213660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043448051 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_and_output.3043448051 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/40.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/40.kmac_sideload.3796116102 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 38125811425 ps |
| CPU time | 320.3 seconds |
| Started | Sep 11 04:41:32 PM UTC 24 |
| Finished | Sep 11 04:46:57 PM UTC 24 |
| Peak memory | 345956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796116102 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.3796116102 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/40.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/40.kmac_smoke.1360805637 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 2942024297 ps |
| CPU time | 27.11 seconds |
| Started | Sep 11 04:41:30 PM UTC 24 |
| Finished | Sep 11 04:41:58 PM UTC 24 |
| Peak memory | 230572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360805637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.1360805637 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/40.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/40.kmac_stress_all.3016562599 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 6943153326 ps |
| CPU time | 269.62 seconds |
| Started | Sep 11 04:42:13 PM UTC 24 |
| Finished | Sep 11 04:46:47 PM UTC 24 |
| Peak memory | 278496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016562599 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.3016562599 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/40.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/41.kmac_alert_test.628962650 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 26973458 ps |
| CPU time | 1.27 seconds |
| Started | Sep 11 04:43:10 PM UTC 24 |
| Finished | Sep 11 04:43:12 PM UTC 24 |
| Peak memory | 216280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628962650 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.628962650 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/41.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/41.kmac_app.3607826570 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 14461273905 ps |
| CPU time | 414.81 seconds |
| Started | Sep 11 04:42:43 PM UTC 24 |
| Finished | Sep 11 04:49:43 PM UTC 24 |
| Peak memory | 583448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607826570 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.3607826570 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/41.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/41.kmac_burst_write.3594861528 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 19699919155 ps |
| CPU time | 430.7 seconds |
| Started | Sep 11 04:42:42 PM UTC 24 |
| Finished | Sep 11 04:49:58 PM UTC 24 |
| Peak memory | 245476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594861528 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.3594861528 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/41.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/41.kmac_entropy_refresh.151932723 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 21480707439 ps |
| CPU time | 202.62 seconds |
| Started | Sep 11 04:42:50 PM UTC 24 |
| Finished | Sep 11 04:46:16 PM UTC 24 |
| Peak memory | 387116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151932723 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.151932723 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/41.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/41.kmac_error.2447964078 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 7294571564 ps |
| CPU time | 205.77 seconds |
| Started | Sep 11 04:42:53 PM UTC 24 |
| Finished | Sep 11 04:46:22 PM UTC 24 |
| Peak memory | 376564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447964078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.2447964078 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/41.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/41.kmac_key_error.195792595 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 1451286506 ps |
| CPU time | 13.38 seconds |
| Started | Sep 11 04:42:54 PM UTC 24 |
| Finished | Sep 11 04:43:09 PM UTC 24 |
| Peak memory | 230384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195792595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.195792595 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/41.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/41.kmac_lc_escalation.1906372967 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 246161908 ps |
| CPU time | 2.99 seconds |
| Started | Sep 11 04:43:01 PM UTC 24 |
| Finished | Sep 11 04:43:05 PM UTC 24 |
| Peak memory | 230384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906372967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.1906372967 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/41.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/41.kmac_long_msg_and_output.3715181341 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 154798864877 ps |
| CPU time | 1588.44 seconds |
| Started | Sep 11 04:42:27 PM UTC 24 |
| Finished | Sep 11 05:09:14 PM UTC 24 |
| Peak memory | 1965856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715181341 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_and_output.3715181341 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/41.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/41.kmac_sideload.3313185241 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 6371222023 ps |
| CPU time | 228.62 seconds |
| Started | Sep 11 04:42:30 PM UTC 24 |
| Finished | Sep 11 04:46:22 PM UTC 24 |
| Peak memory | 337820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313185241 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.3313185241 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/41.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/41.kmac_smoke.549587029 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 96133072 ps |
| CPU time | 3.4 seconds |
| Started | Sep 11 04:42:22 PM UTC 24 |
| Finished | Sep 11 04:42:27 PM UTC 24 |
| Peak memory | 230500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549587029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.549587029 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/41.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/41.kmac_stress_all.3682434579 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 21854797188 ps |
| CPU time | 100.79 seconds |
| Started | Sep 11 04:43:06 PM UTC 24 |
| Finished | Sep 11 04:44:49 PM UTC 24 |
| Peak memory | 307040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682434579 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.3682434579 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/41.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/42.kmac_alert_test.4127887163 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 92442071 ps |
| CPU time | 1.18 seconds |
| Started | Sep 11 04:44:35 PM UTC 24 |
| Finished | Sep 11 04:44:37 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127887163 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.4127887163 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/42.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/42.kmac_app.2093881402 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 2045408695 ps |
| CPU time | 69.95 seconds |
| Started | Sep 11 04:43:35 PM UTC 24 |
| Finished | Sep 11 04:44:47 PM UTC 24 |
| Peak memory | 249632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093881402 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.2093881402 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/42.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/42.kmac_burst_write.1577054437 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 8040026253 ps |
| CPU time | 668.06 seconds |
| Started | Sep 11 04:43:24 PM UTC 24 |
| Finished | Sep 11 04:54:41 PM UTC 24 |
| Peak memory | 251680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577054437 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.1577054437 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/42.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/42.kmac_entropy_refresh.2984462891 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 21179561593 ps |
| CPU time | 164.31 seconds |
| Started | Sep 11 04:43:53 PM UTC 24 |
| Finished | Sep 11 04:46:41 PM UTC 24 |
| Peak memory | 290740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984462891 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.2984462891 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/42.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/42.kmac_error.3986633747 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 16312462763 ps |
| CPU time | 284.41 seconds |
| Started | Sep 11 04:44:03 PM UTC 24 |
| Finished | Sep 11 04:48:52 PM UTC 24 |
| Peak memory | 481192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986633747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.3986633747 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/42.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/42.kmac_key_error.2819406099 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 2996379004 ps |
| CPU time | 14.25 seconds |
| Started | Sep 11 04:44:19 PM UTC 24 |
| Finished | Sep 11 04:44:34 PM UTC 24 |
| Peak memory | 230516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819406099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.2819406099 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/42.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/42.kmac_lc_escalation.497840378 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 46007371 ps |
| CPU time | 1.58 seconds |
| Started | Sep 11 04:44:27 PM UTC 24 |
| Finished | Sep 11 04:44:29 PM UTC 24 |
| Peak memory | 231784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497840378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.497840378 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/42.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/42.kmac_long_msg_and_output.3176022239 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 170930266095 ps |
| CPU time | 2783.19 seconds |
| Started | Sep 11 04:43:13 PM UTC 24 |
| Finished | Sep 11 05:30:07 PM UTC 24 |
| Peak memory | 1984292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176022239 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_and_output.3176022239 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/42.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/42.kmac_sideload.34209306 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 96358313 ps |
| CPU time | 9.82 seconds |
| Started | Sep 11 04:43:23 PM UTC 24 |
| Finished | Sep 11 04:43:34 PM UTC 24 |
| Peak memory | 234612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34209306 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.34209306 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/42.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/42.kmac_smoke.3315835815 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 3100333737 ps |
| CPU time | 64.53 seconds |
| Started | Sep 11 04:43:12 PM UTC 24 |
| Finished | Sep 11 04:44:18 PM UTC 24 |
| Peak memory | 235556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315835815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.3315835815 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/42.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/42.kmac_stress_all.3219476153 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 17714405983 ps |
| CPU time | 908.9 seconds |
| Started | Sep 11 04:44:30 PM UTC 24 |
| Finished | Sep 11 04:59:50 PM UTC 24 |
| Peak memory | 538684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219476153 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.3219476153 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/42.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/43.kmac_alert_test.325140551 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 21670675 ps |
| CPU time | 1.18 seconds |
| Started | Sep 11 04:46:05 PM UTC 24 |
| Finished | Sep 11 04:46:07 PM UTC 24 |
| Peak memory | 216340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325140551 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.325140551 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/43.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/43.kmac_app.582236463 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 16213754472 ps |
| CPU time | 224.56 seconds |
| Started | Sep 11 04:44:57 PM UTC 24 |
| Finished | Sep 11 04:48:45 PM UTC 24 |
| Peak memory | 325332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582236463 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.582236463 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/43.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/43.kmac_burst_write.3912812799 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 2899312276 ps |
| CPU time | 154.65 seconds |
| Started | Sep 11 04:44:51 PM UTC 24 |
| Finished | Sep 11 04:47:28 PM UTC 24 |
| Peak memory | 235228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912812799 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.3912812799 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/43.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/43.kmac_entropy_refresh.1494884157 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 16561126013 ps |
| CPU time | 373.26 seconds |
| Started | Sep 11 04:45:25 PM UTC 24 |
| Finished | Sep 11 04:51:44 PM UTC 24 |
| Peak memory | 522028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494884157 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.1494884157 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/43.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/43.kmac_error.3406746264 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 3748036241 ps |
| CPU time | 42.92 seconds |
| Started | Sep 11 04:45:42 PM UTC 24 |
| Finished | Sep 11 04:46:27 PM UTC 24 |
| Peak memory | 284664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406746264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.3406746264 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/43.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/43.kmac_key_error.1529839176 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 2070435807 ps |
| CPU time | 11.48 seconds |
| Started | Sep 11 04:45:48 PM UTC 24 |
| Finished | Sep 11 04:46:01 PM UTC 24 |
| Peak memory | 230536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529839176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.1529839176 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/43.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/43.kmac_lc_escalation.2321444519 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 159052553 ps |
| CPU time | 1.64 seconds |
| Started | Sep 11 04:46:01 PM UTC 24 |
| Finished | Sep 11 04:46:04 PM UTC 24 |
| Peak memory | 229792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321444519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.2321444519 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/43.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/43.kmac_long_msg_and_output.4233445442 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 355029028995 ps |
| CPU time | 1485.15 seconds |
| Started | Sep 11 04:44:47 PM UTC 24 |
| Finished | Sep 11 05:09:50 PM UTC 24 |
| Peak memory | 2047964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233445442 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_and_output.4233445442 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/43.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/43.kmac_sideload.1056159497 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 80894736767 ps |
| CPU time | 462.63 seconds |
| Started | Sep 11 04:44:49 PM UTC 24 |
| Finished | Sep 11 04:52:38 PM UTC 24 |
| Peak memory | 679984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056159497 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.1056159497 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/43.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/43.kmac_smoke.89729181 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 3804390755 ps |
| CPU time | 61.73 seconds |
| Started | Sep 11 04:44:38 PM UTC 24 |
| Finished | Sep 11 04:45:42 PM UTC 24 |
| Peak memory | 230644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89729181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.89729181 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/43.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/43.kmac_stress_all.35349725 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 95603475511 ps |
| CPU time | 772.82 seconds |
| Started | Sep 11 04:46:05 PM UTC 24 |
| Finished | Sep 11 04:59:08 PM UTC 24 |
| Peak memory | 593928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35349725 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.35349725 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/43.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/44.kmac_alert_test.2395324885 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 23866342 ps |
| CPU time | 1.29 seconds |
| Started | Sep 11 04:46:48 PM UTC 24 |
| Finished | Sep 11 04:46:51 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395324885 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.2395324885 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/44.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/44.kmac_app.839371799 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 4464348445 ps |
| CPU time | 108.32 seconds |
| Started | Sep 11 04:46:23 PM UTC 24 |
| Finished | Sep 11 04:48:14 PM UTC 24 |
| Peak memory | 266016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839371799 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.839371799 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/44.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/44.kmac_burst_write.964118818 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 1958702687 ps |
| CPU time | 209.64 seconds |
| Started | Sep 11 04:46:23 PM UTC 24 |
| Finished | Sep 11 04:49:56 PM UTC 24 |
| Peak memory | 237284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964118818 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.964118818 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/44.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/44.kmac_entropy_refresh.235935390 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 8678669478 ps |
| CPU time | 255.82 seconds |
| Started | Sep 11 04:46:28 PM UTC 24 |
| Finished | Sep 11 04:50:47 PM UTC 24 |
| Peak memory | 339692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235935390 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.235935390 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/44.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/44.kmac_error.4036360098 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 1538337735 ps |
| CPU time | 24.13 seconds |
| Started | Sep 11 04:46:31 PM UTC 24 |
| Finished | Sep 11 04:46:56 PM UTC 24 |
| Peak memory | 251560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036360098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.4036360098 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/44.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/44.kmac_key_error.1775185555 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 6765082949 ps |
| CPU time | 19.94 seconds |
| Started | Sep 11 04:46:42 PM UTC 24 |
| Finished | Sep 11 04:47:03 PM UTC 24 |
| Peak memory | 230384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775185555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.1775185555 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/44.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/44.kmac_lc_escalation.1912300888 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 1850966215 ps |
| CPU time | 14.08 seconds |
| Started | Sep 11 04:46:42 PM UTC 24 |
| Finished | Sep 11 04:46:57 PM UTC 24 |
| Peak memory | 245708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912300888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.1912300888 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/44.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/44.kmac_long_msg_and_output.2440785531 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 46867967032 ps |
| CPU time | 1154.2 seconds |
| Started | Sep 11 04:46:17 PM UTC 24 |
| Finished | Sep 11 05:05:45 PM UTC 24 |
| Peak memory | 933660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440785531 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_and_output.2440785531 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/44.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/44.kmac_sideload.2313434499 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 11310009385 ps |
| CPU time | 220.16 seconds |
| Started | Sep 11 04:46:23 PM UTC 24 |
| Finished | Sep 11 04:50:07 PM UTC 24 |
| Peak memory | 454496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313434499 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.2313434499 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/44.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/44.kmac_smoke.3073985485 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 1022837105 ps |
| CPU time | 13.74 seconds |
| Started | Sep 11 04:46:08 PM UTC 24 |
| Finished | Sep 11 04:46:23 PM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073985485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.3073985485 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/44.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/44.kmac_stress_all.3467567210 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 89601366627 ps |
| CPU time | 751.6 seconds |
| Started | Sep 11 04:46:47 PM UTC 24 |
| Finished | Sep 11 04:59:29 PM UTC 24 |
| Peak memory | 379088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467567210 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.3467567210 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/44.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/45.kmac_alert_test.3042318747 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 24466331 ps |
| CPU time | 1.22 seconds |
| Started | Sep 11 04:47:29 PM UTC 24 |
| Finished | Sep 11 04:47:31 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042318747 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.3042318747 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/45.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/45.kmac_app.2313508827 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 23465509141 ps |
| CPU time | 162.82 seconds |
| Started | Sep 11 04:46:59 PM UTC 24 |
| Finished | Sep 11 04:49:45 PM UTC 24 |
| Peak memory | 344028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313508827 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.2313508827 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/45.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/45.kmac_burst_write.2844895151 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 201074081135 ps |
| CPU time | 1321.07 seconds |
| Started | Sep 11 04:46:58 PM UTC 24 |
| Finished | Sep 11 05:09:15 PM UTC 24 |
| Peak memory | 276176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844895151 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.2844895151 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/45.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/45.kmac_entropy_refresh.1726678715 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 70294146838 ps |
| CPU time | 311.04 seconds |
| Started | Sep 11 04:47:02 PM UTC 24 |
| Finished | Sep 11 04:52:17 PM UTC 24 |
| Peak memory | 472868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726678715 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.1726678715 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/45.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/45.kmac_error.1947215816 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 1747603594 ps |
| CPU time | 132.85 seconds |
| Started | Sep 11 04:47:03 PM UTC 24 |
| Finished | Sep 11 04:49:18 PM UTC 24 |
| Peak memory | 300948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947215816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.1947215816 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/45.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/45.kmac_key_error.733582728 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 3646837131 ps |
| CPU time | 10.5 seconds |
| Started | Sep 11 04:47:04 PM UTC 24 |
| Finished | Sep 11 04:47:16 PM UTC 24 |
| Peak memory | 230708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733582728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.733582728 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/45.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/45.kmac_lc_escalation.1488973568 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 125405235 ps |
| CPU time | 2.01 seconds |
| Started | Sep 11 04:47:16 PM UTC 24 |
| Finished | Sep 11 04:47:19 PM UTC 24 |
| Peak memory | 234404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488973568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.1488973568 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/45.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/45.kmac_long_msg_and_output.2114677278 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 144879120468 ps |
| CPU time | 1085.73 seconds |
| Started | Sep 11 04:46:55 PM UTC 24 |
| Finished | Sep 11 05:05:14 PM UTC 24 |
| Peak memory | 1654484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114677278 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_and_output.2114677278 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/45.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/45.kmac_sideload.2578387783 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 28044920572 ps |
| CPU time | 405.8 seconds |
| Started | Sep 11 04:46:58 PM UTC 24 |
| Finished | Sep 11 04:53:49 PM UTC 24 |
| Peak memory | 538480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578387783 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.2578387783 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/45.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/45.kmac_smoke.3637246321 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 1437921299 ps |
| CPU time | 9.45 seconds |
| Started | Sep 11 04:46:51 PM UTC 24 |
| Finished | Sep 11 04:47:02 PM UTC 24 |
| Peak memory | 230512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637246321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.3637246321 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/45.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/45.kmac_stress_all.2113518156 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 61198676591 ps |
| CPU time | 795 seconds |
| Started | Sep 11 04:47:21 PM UTC 24 |
| Finished | Sep 11 05:00:46 PM UTC 24 |
| Peak memory | 938000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113518156 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.2113518156 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/45.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/46.kmac_alert_test.3172277006 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 26905414 ps |
| CPU time | 1.25 seconds |
| Started | Sep 11 04:48:55 PM UTC 24 |
| Finished | Sep 11 04:48:57 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172277006 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.3172277006 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/46.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/46.kmac_app.66511900 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 3699330589 ps |
| CPU time | 99.56 seconds |
| Started | Sep 11 04:48:22 PM UTC 24 |
| Finished | Sep 11 04:50:04 PM UTC 24 |
| Peak memory | 315300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66511900 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.66511900 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/46.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/46.kmac_burst_write.452826813 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 14136292806 ps |
| CPU time | 107.77 seconds |
| Started | Sep 11 04:48:15 PM UTC 24 |
| Finished | Sep 11 04:50:05 PM UTC 24 |
| Peak memory | 235308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452826813 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.452826813 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/46.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/46.kmac_entropy_refresh.1663168706 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 11096566082 ps |
| CPU time | 197.03 seconds |
| Started | Sep 11 04:48:44 PM UTC 24 |
| Finished | Sep 11 04:52:04 PM UTC 24 |
| Peak memory | 431972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663168706 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.1663168706 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/46.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/46.kmac_error.1591155274 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 467134509 ps |
| CPU time | 39.04 seconds |
| Started | Sep 11 04:48:45 PM UTC 24 |
| Finished | Sep 11 04:49:26 PM UTC 24 |
| Peak memory | 251556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591155274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.1591155274 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/46.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/46.kmac_key_error.1672314276 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 574903661 ps |
| CPU time | 3.58 seconds |
| Started | Sep 11 04:48:46 PM UTC 24 |
| Finished | Sep 11 04:48:51 PM UTC 24 |
| Peak memory | 230368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672314276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.1672314276 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/46.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/46.kmac_long_msg_and_output.2946840848 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 234578368023 ps |
| CPU time | 1265.03 seconds |
| Started | Sep 11 04:47:35 PM UTC 24 |
| Finished | Sep 11 05:08:55 PM UTC 24 |
| Peak memory | 1896268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946840848 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_and_output.2946840848 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/46.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/46.kmac_sideload.3679966042 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 11046698995 ps |
| CPU time | 366.38 seconds |
| Started | Sep 11 04:48:11 PM UTC 24 |
| Finished | Sep 11 04:54:22 PM UTC 24 |
| Peak memory | 520104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679966042 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.3679966042 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/46.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/46.kmac_smoke.3281341640 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 4204398813 ps |
| CPU time | 69.76 seconds |
| Started | Sep 11 04:47:32 PM UTC 24 |
| Finished | Sep 11 04:48:43 PM UTC 24 |
| Peak memory | 234616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281341640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.3281341640 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/46.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/46.kmac_stress_all.5703865 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 65304462198 ps |
| CPU time | 695.55 seconds |
| Started | Sep 11 04:48:54 PM UTC 24 |
| Finished | Sep 11 05:00:39 PM UTC 24 |
| Peak memory | 823636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5703865 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.5703865 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/46.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/47.kmac_alert_test.2608292882 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 18409164 ps |
| CPU time | 1.12 seconds |
| Started | Sep 11 04:50:02 PM UTC 24 |
| Finished | Sep 11 04:50:04 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608292882 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.2608292882 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/47.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/47.kmac_app.819718598 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 36192244394 ps |
| CPU time | 181.72 seconds |
| Started | Sep 11 04:49:31 PM UTC 24 |
| Finished | Sep 11 04:52:36 PM UTC 24 |
| Peak memory | 389024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819718598 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.819718598 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/47.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/47.kmac_burst_write.3146323477 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 10572505557 ps |
| CPU time | 416.16 seconds |
| Started | Sep 11 04:49:27 PM UTC 24 |
| Finished | Sep 11 04:56:29 PM UTC 24 |
| Peak memory | 251680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146323477 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.3146323477 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/47.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/47.kmac_entropy_refresh.2390339078 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 2633247259 ps |
| CPU time | 72.04 seconds |
| Started | Sep 11 04:49:32 PM UTC 24 |
| Finished | Sep 11 04:50:47 PM UTC 24 |
| Peak memory | 278572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390339078 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.2390339078 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/47.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/47.kmac_error.3038089893 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 5297735142 ps |
| CPU time | 180.65 seconds |
| Started | Sep 11 04:49:45 PM UTC 24 |
| Finished | Sep 11 04:52:49 PM UTC 24 |
| Peak memory | 323304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038089893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.3038089893 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/47.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/47.kmac_key_error.383741107 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 1729456286 ps |
| CPU time | 14.26 seconds |
| Started | Sep 11 04:49:46 PM UTC 24 |
| Finished | Sep 11 04:50:02 PM UTC 24 |
| Peak memory | 230404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383741107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.383741107 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/47.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/47.kmac_lc_escalation.1026151978 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 1616781975 ps |
| CPU time | 20.23 seconds |
| Started | Sep 11 04:49:57 PM UTC 24 |
| Finished | Sep 11 04:50:18 PM UTC 24 |
| Peak memory | 249756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026151978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.1026151978 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/47.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/47.kmac_long_msg_and_output.3260951218 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 27548057084 ps |
| CPU time | 597.33 seconds |
| Started | Sep 11 04:49:03 PM UTC 24 |
| Finished | Sep 11 04:59:08 PM UTC 24 |
| Peak memory | 661408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260951218 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_and_output.3260951218 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/47.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/47.kmac_sideload.137164665 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 74374736400 ps |
| CPU time | 406.5 seconds |
| Started | Sep 11 04:49:19 PM UTC 24 |
| Finished | Sep 11 04:56:11 PM UTC 24 |
| Peak memory | 624488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137164665 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.137164665 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/47.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/47.kmac_smoke.2856759848 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 7030910469 ps |
| CPU time | 76.85 seconds |
| Started | Sep 11 04:48:58 PM UTC 24 |
| Finished | Sep 11 04:50:16 PM UTC 24 |
| Peak memory | 232852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856759848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.2856759848 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/47.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/47.kmac_stress_all.4015710859 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 26189964182 ps |
| CPU time | 1774.27 seconds |
| Started | Sep 11 04:49:59 PM UTC 24 |
| Finished | Sep 11 05:19:54 PM UTC 24 |
| Peak memory | 800524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015710859 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.4015710859 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/47.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/48.kmac_alert_test.3977978474 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 144696972 ps |
| CPU time | 1.16 seconds |
| Started | Sep 11 04:50:48 PM UTC 24 |
| Finished | Sep 11 04:50:50 PM UTC 24 |
| Peak memory | 216284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977978474 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.3977978474 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/48.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/48.kmac_app.2374231728 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 1733682829 ps |
| CPU time | 34.59 seconds |
| Started | Sep 11 04:50:18 PM UTC 24 |
| Finished | Sep 11 04:50:54 PM UTC 24 |
| Peak memory | 263916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374231728 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.2374231728 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/48.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/48.kmac_burst_write.2190758499 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 29643703054 ps |
| CPU time | 287.52 seconds |
| Started | Sep 11 04:50:08 PM UTC 24 |
| Finished | Sep 11 04:54:59 PM UTC 24 |
| Peak memory | 243528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190758499 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.2190758499 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/48.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/48.kmac_entropy_refresh.1578979416 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 43592205056 ps |
| CPU time | 172.89 seconds |
| Started | Sep 11 04:50:19 PM UTC 24 |
| Finished | Sep 11 04:53:15 PM UTC 24 |
| Peak memory | 360236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578979416 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.1578979416 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/48.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/48.kmac_error.215500256 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 11394112132 ps |
| CPU time | 208.53 seconds |
| Started | Sep 11 04:50:26 PM UTC 24 |
| Finished | Sep 11 04:53:58 PM UTC 24 |
| Peak memory | 321376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215500256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.215500256 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/48.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/48.kmac_key_error.3690270310 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 9167364640 ps |
| CPU time | 10.92 seconds |
| Started | Sep 11 04:50:33 PM UTC 24 |
| Finished | Sep 11 04:50:45 PM UTC 24 |
| Peak memory | 230640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690270310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.3690270310 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/48.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/48.kmac_lc_escalation.2003405395 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 85714667 ps |
| CPU time | 1.97 seconds |
| Started | Sep 11 04:50:47 PM UTC 24 |
| Finished | Sep 11 04:50:50 PM UTC 24 |
| Peak memory | 229628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003405395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.2003405395 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/48.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/48.kmac_long_msg_and_output.3544810852 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 486229205260 ps |
| CPU time | 4340.12 seconds |
| Started | Sep 11 04:50:06 PM UTC 24 |
| Finished | Sep 11 06:03:13 PM UTC 24 |
| Peak memory | 4710264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544810852 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_and_output.3544810852 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/48.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/48.kmac_sideload.427456549 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 10784076769 ps |
| CPU time | 291.4 seconds |
| Started | Sep 11 04:50:06 PM UTC 24 |
| Finished | Sep 11 04:55:01 PM UTC 24 |
| Peak memory | 501732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427456549 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.427456549 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/48.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/48.kmac_smoke.3479546528 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 7246468329 ps |
| CPU time | 59.41 seconds |
| Started | Sep 11 04:50:04 PM UTC 24 |
| Finished | Sep 11 04:51:05 PM UTC 24 |
| Peak memory | 234876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479546528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.3479546528 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/48.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/48.kmac_stress_all.1306784261 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 119415746723 ps |
| CPU time | 913.43 seconds |
| Started | Sep 11 04:50:48 PM UTC 24 |
| Finished | Sep 11 05:06:13 PM UTC 24 |
| Peak memory | 675900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306784261 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.1306784261 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/48.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/49.kmac_alert_test.2480033074 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 60944534 ps |
| CPU time | 1.2 seconds |
| Started | Sep 11 04:52:09 PM UTC 24 |
| Finished | Sep 11 04:52:12 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480033074 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.2480033074 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/49.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/49.kmac_app.2301596572 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 22931774368 ps |
| CPU time | 342.36 seconds |
| Started | Sep 11 04:50:55 PM UTC 24 |
| Finished | Sep 11 04:56:42 PM UTC 24 |
| Peak memory | 507868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301596572 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.2301596572 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/49.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/49.kmac_burst_write.1068784577 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 25098645307 ps |
| CPU time | 826 seconds |
| Started | Sep 11 04:50:52 PM UTC 24 |
| Finished | Sep 11 05:04:49 PM UTC 24 |
| Peak memory | 264208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068784577 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.1068784577 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/49.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/49.kmac_entropy_refresh.1720691787 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 2314200227 ps |
| CPU time | 93.08 seconds |
| Started | Sep 11 04:51:07 PM UTC 24 |
| Finished | Sep 11 04:52:42 PM UTC 24 |
| Peak memory | 259864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720691787 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.1720691787 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/49.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/49.kmac_error.864553829 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 72426479894 ps |
| CPU time | 251.51 seconds |
| Started | Sep 11 04:51:45 PM UTC 24 |
| Finished | Sep 11 04:56:00 PM UTC 24 |
| Peak memory | 454444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864553829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.864553829 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/49.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/49.kmac_key_error.3429834712 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 883677217 ps |
| CPU time | 4.88 seconds |
| Started | Sep 11 04:52:02 PM UTC 24 |
| Finished | Sep 11 04:52:08 PM UTC 24 |
| Peak memory | 230372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429834712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.3429834712 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/49.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/49.kmac_lc_escalation.1953226500 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 90957086 ps |
| CPU time | 1.85 seconds |
| Started | Sep 11 04:52:05 PM UTC 24 |
| Finished | Sep 11 04:52:08 PM UTC 24 |
| Peak memory | 231656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953226500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.1953226500 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/49.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/49.kmac_long_msg_and_output.2755126725 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 48799621914 ps |
| CPU time | 2419.43 seconds |
| Started | Sep 11 04:50:51 PM UTC 24 |
| Finished | Sep 11 05:31:39 PM UTC 24 |
| Peak memory | 1722128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755126725 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_and_output.2755126725 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/49.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/49.kmac_sideload.17691513 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 10638818005 ps |
| CPU time | 186.7 seconds |
| Started | Sep 11 04:50:51 PM UTC 24 |
| Finished | Sep 11 04:54:01 PM UTC 24 |
| Peak memory | 368596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17691513 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.17691513 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/49.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/49.kmac_smoke.3853643864 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 3288117529 ps |
| CPU time | 68.44 seconds |
| Started | Sep 11 04:50:51 PM UTC 24 |
| Finished | Sep 11 04:52:01 PM UTC 24 |
| Peak memory | 232560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853643864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.3853643864 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/49.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/49.kmac_stress_all.4119551912 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 21951205969 ps |
| CPU time | 297.55 seconds |
| Started | Sep 11 04:52:09 PM UTC 24 |
| Finished | Sep 11 04:57:11 PM UTC 24 |
| Peak memory | 301168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119551912 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.4119551912 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/49.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/5.kmac_alert_test.1456236612 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 17668269 ps |
| CPU time | 1.26 seconds |
| Started | Sep 11 04:00:55 PM UTC 24 |
| Finished | Sep 11 04:00:57 PM UTC 24 |
| Peak memory | 216280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456236612 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.1456236612 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/5.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/5.kmac_app.804779964 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1046735444 ps |
| CPU time | 18.24 seconds |
| Started | Sep 11 03:59:52 PM UTC 24 |
| Finished | Sep 11 04:00:12 PM UTC 24 |
| Peak memory | 235168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804779964 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.804779964 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/5.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/5.kmac_app_with_partial_data.2843119660 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 6062577204 ps |
| CPU time | 142.2 seconds |
| Started | Sep 11 03:59:54 PM UTC 24 |
| Finished | Sep 11 04:02:19 PM UTC 24 |
| Peak memory | 323496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843119660 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.2843119660 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/5.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/5.kmac_burst_write.3399952442 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 36246727212 ps |
| CPU time | 1134.23 seconds |
| Started | Sep 11 03:59:45 PM UTC 24 |
| Finished | Sep 11 04:18:53 PM UTC 24 |
| Peak memory | 270060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399952442 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.3399952442 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/5.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/5.kmac_edn_timeout_error.1263734149 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 3043766684 ps |
| CPU time | 31.34 seconds |
| Started | Sep 11 04:00:36 PM UTC 24 |
| Finished | Sep 11 04:01:09 PM UTC 24 |
| Peak memory | 232452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263734149 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.1263734149 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/5.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_mode_error.3738355638 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 401754124 ps |
| CPU time | 11.92 seconds |
| Started | Sep 11 04:00:40 PM UTC 24 |
| Finished | Sep 11 04:00:54 PM UTC 24 |
| Peak memory | 228356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738355638 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.3738355638 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/5.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_ready_error.2744286561 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 31875269721 ps |
| CPU time | 122.07 seconds |
| Started | Sep 11 04:00:46 PM UTC 24 |
| Finished | Sep 11 04:02:50 PM UTC 24 |
| Peak memory | 230572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744286561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.2744286561 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/5.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_refresh.787163444 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 1510972400 ps |
| CPU time | 44.76 seconds |
| Started | Sep 11 04:00:01 PM UTC 24 |
| Finished | Sep 11 04:00:51 PM UTC 24 |
| Peak memory | 249504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787163444 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.787163444 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/5.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/5.kmac_key_error.1284594914 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 610288330 ps |
| CPU time | 2.98 seconds |
| Started | Sep 11 04:00:31 PM UTC 24 |
| Finished | Sep 11 04:00:35 PM UTC 24 |
| Peak memory | 230404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284594914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.1284594914 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/5.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/5.kmac_lc_escalation.1742925408 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 168924566 ps |
| CPU time | 2.04 seconds |
| Started | Sep 11 04:00:49 PM UTC 24 |
| Finished | Sep 11 04:00:52 PM UTC 24 |
| Peak memory | 230316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742925408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.1742925408 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/5.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/5.kmac_long_msg_and_output.204248115 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 22666054745 ps |
| CPU time | 2206.58 seconds |
| Started | Sep 11 03:59:34 PM UTC 24 |
| Finished | Sep 11 04:36:45 PM UTC 24 |
| Peak memory | 1599280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204248115 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and_output.204248115 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/5.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/5.kmac_mubi.2195384864 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1971522612 ps |
| CPU time | 88.99 seconds |
| Started | Sep 11 04:00:12 PM UTC 24 |
| Finished | Sep 11 04:01:43 PM UTC 24 |
| Peak memory | 268264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195384864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.2195384864 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/5.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/5.kmac_sideload.3321904349 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 50624781481 ps |
| CPU time | 296.23 seconds |
| Started | Sep 11 03:59:36 PM UTC 24 |
| Finished | Sep 11 04:04:37 PM UTC 24 |
| Peak memory | 493388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321904349 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.3321904349 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/5.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/5.kmac_smoke.2943513729 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 242893129 ps |
| CPU time | 15.98 seconds |
| Started | Sep 11 03:59:34 PM UTC 24 |
| Finished | Sep 11 03:59:51 PM UTC 24 |
| Peak memory | 230508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943513729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.2943513729 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/5.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/5.kmac_stress_all.4120527760 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 6504343225 ps |
| CPU time | 267.49 seconds |
| Started | Sep 11 04:00:52 PM UTC 24 |
| Finished | Sep 11 04:05:23 PM UTC 24 |
| Peak memory | 425940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120527760 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.4120527760 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/5.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/5.kmac_stress_all_with_rand_reset.1248972199 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 6351851437 ps |
| CPU time | 120.69 seconds |
| Started | Sep 11 04:00:53 PM UTC 24 |
| Finished | Sep 11 04:02:56 PM UTC 24 |
| Peak memory | 285136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1248972199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all_ with_rand_reset.1248972199 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/6.kmac_alert_test.4158084483 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 27048152 ps |
| CPU time | 1.17 seconds |
| Started | Sep 11 04:02:46 PM UTC 24 |
| Finished | Sep 11 04:02:48 PM UTC 24 |
| Peak memory | 216280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158084483 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.4158084483 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/6.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/6.kmac_app.4272976016 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 11708508997 ps |
| CPU time | 261.65 seconds |
| Started | Sep 11 04:01:18 PM UTC 24 |
| Finished | Sep 11 04:05:44 PM UTC 24 |
| Peak memory | 487452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272976016 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.4272976016 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/6.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/6.kmac_app_with_partial_data.2566287717 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 13241391643 ps |
| CPU time | 291.96 seconds |
| Started | Sep 11 04:01:20 PM UTC 24 |
| Finished | Sep 11 04:06:17 PM UTC 24 |
| Peak memory | 331624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566287717 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.2566287717 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/6.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/6.kmac_burst_write.1688992245 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 8150899052 ps |
| CPU time | 299.13 seconds |
| Started | Sep 11 04:01:10 PM UTC 24 |
| Finished | Sep 11 04:06:14 PM UTC 24 |
| Peak memory | 245544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688992245 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.1688992245 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/6.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/6.kmac_edn_timeout_error.3528946947 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 439749803 ps |
| CPU time | 41.81 seconds |
| Started | Sep 11 04:02:00 PM UTC 24 |
| Finished | Sep 11 04:02:43 PM UTC 24 |
| Peak memory | 235168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528946947 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.3528946947 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/6.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_mode_error.2312210041 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 2383245720 ps |
| CPU time | 21.02 seconds |
| Started | Sep 11 04:02:05 PM UTC 24 |
| Finished | Sep 11 04:02:27 PM UTC 24 |
| Peak memory | 232444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312210041 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.2312210041 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/6.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_ready_error.3324635985 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 65551151997 ps |
| CPU time | 53.72 seconds |
| Started | Sep 11 04:02:06 PM UTC 24 |
| Finished | Sep 11 04:03:01 PM UTC 24 |
| Peak memory | 230632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324635985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.3324635985 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/6.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_refresh.203700714 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 115606528 ps |
| CPU time | 4.47 seconds |
| Started | Sep 11 04:01:44 PM UTC 24 |
| Finished | Sep 11 04:01:49 PM UTC 24 |
| Peak memory | 230660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203700714 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.203700714 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/6.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/6.kmac_error.4254149292 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 10870449059 ps |
| CPU time | 161.91 seconds |
| Started | Sep 11 04:01:50 PM UTC 24 |
| Finished | Sep 11 04:04:34 PM UTC 24 |
| Peak memory | 331552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254149292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.4254149292 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/6.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/6.kmac_key_error.3231654730 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1732415822 ps |
| CPU time | 11.09 seconds |
| Started | Sep 11 04:01:53 PM UTC 24 |
| Finished | Sep 11 04:02:05 PM UTC 24 |
| Peak memory | 230328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231654730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.3231654730 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/6.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/6.kmac_lc_escalation.114422636 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 6312346494 ps |
| CPU time | 23.73 seconds |
| Started | Sep 11 04:02:20 PM UTC 24 |
| Finished | Sep 11 04:02:45 PM UTC 24 |
| Peak memory | 249640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114422636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.114422636 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/6.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/6.kmac_long_msg_and_output.1332420588 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 441923372823 ps |
| CPU time | 4129.3 seconds |
| Started | Sep 11 04:00:58 PM UTC 24 |
| Finished | Sep 11 05:10:35 PM UTC 24 |
| Peak memory | 4308812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332420588 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and_output.1332420588 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/6.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/6.kmac_mubi.3140035187 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 73316782018 ps |
| CPU time | 249.56 seconds |
| Started | Sep 11 04:01:45 PM UTC 24 |
| Finished | Sep 11 04:05:58 PM UTC 24 |
| Peak memory | 440300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140035187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.3140035187 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/6.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/6.kmac_sideload.2794030839 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 56044022885 ps |
| CPU time | 309.74 seconds |
| Started | Sep 11 04:01:01 PM UTC 24 |
| Finished | Sep 11 04:06:15 PM UTC 24 |
| Peak memory | 526308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794030839 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.2794030839 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/6.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/6.kmac_smoke.3498619471 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 849793040 ps |
| CPU time | 19.47 seconds |
| Started | Sep 11 04:00:57 PM UTC 24 |
| Finished | Sep 11 04:01:18 PM UTC 24 |
| Peak memory | 230508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498619471 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.3498619471 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/6.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/6.kmac_stress_all.4067380418 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 28494888223 ps |
| CPU time | 899.04 seconds |
| Started | Sep 11 04:02:28 PM UTC 24 |
| Finished | Sep 11 04:17:38 PM UTC 24 |
| Peak memory | 1083304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067380418 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.4067380418 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/6.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/7.kmac_alert_test.1632967564 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 40329847 ps |
| CPU time | 1.23 seconds |
| Started | Sep 11 04:04:38 PM UTC 24 |
| Finished | Sep 11 04:04:40 PM UTC 24 |
| Peak memory | 216280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632967564 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.1632967564 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/7.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/7.kmac_app.2380295490 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 3885604936 ps |
| CPU time | 268.8 seconds |
| Started | Sep 11 04:02:57 PM UTC 24 |
| Finished | Sep 11 04:07:30 PM UTC 24 |
| Peak memory | 311060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380295490 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.2380295490 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/7.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/7.kmac_app_with_partial_data.3189114185 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 2555571204 ps |
| CPU time | 50.09 seconds |
| Started | Sep 11 04:03:01 PM UTC 24 |
| Finished | Sep 11 04:03:52 PM UTC 24 |
| Peak memory | 270104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189114185 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.3189114185 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/7.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/7.kmac_burst_write.497282813 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 8586517522 ps |
| CPU time | 704.52 seconds |
| Started | Sep 11 04:02:54 PM UTC 24 |
| Finished | Sep 11 04:14:47 PM UTC 24 |
| Peak memory | 251676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497282813 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.497282813 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/7.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/7.kmac_edn_timeout_error.1673319272 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 684087870 ps |
| CPU time | 30.99 seconds |
| Started | Sep 11 04:03:45 PM UTC 24 |
| Finished | Sep 11 04:04:18 PM UTC 24 |
| Peak memory | 232396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673319272 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.1673319272 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/7.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_mode_error.3901873511 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 31869113209 ps |
| CPU time | 59.33 seconds |
| Started | Sep 11 04:03:53 PM UTC 24 |
| Finished | Sep 11 04:04:55 PM UTC 24 |
| Peak memory | 235040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901873511 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.3901873511 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/7.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_ready_error.1534362082 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 8729114468 ps |
| CPU time | 24.19 seconds |
| Started | Sep 11 04:04:18 PM UTC 24 |
| Finished | Sep 11 04:04:44 PM UTC 24 |
| Peak memory | 230580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534362082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.1534362082 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/7.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_refresh.3865970161 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 30502870696 ps |
| CPU time | 321.1 seconds |
| Started | Sep 11 04:03:03 PM UTC 24 |
| Finished | Sep 11 04:08:28 PM UTC 24 |
| Peak memory | 505652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865970161 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.3865970161 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/7.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/7.kmac_error.134386477 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 27470015241 ps |
| CPU time | 185.48 seconds |
| Started | Sep 11 04:03:20 PM UTC 24 |
| Finished | Sep 11 04:06:28 PM UTC 24 |
| Peak memory | 384748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134386477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.134386477 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/7.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/7.kmac_key_error.736713227 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1529811387 ps |
| CPU time | 3.23 seconds |
| Started | Sep 11 04:03:40 PM UTC 24 |
| Finished | Sep 11 04:03:44 PM UTC 24 |
| Peak memory | 230324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736713227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.736713227 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/7.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/7.kmac_lc_escalation.2051874502 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 713524975 ps |
| CPU time | 13.91 seconds |
| Started | Sep 11 04:04:30 PM UTC 24 |
| Finished | Sep 11 04:04:46 PM UTC 24 |
| Peak memory | 242672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051874502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.2051874502 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/7.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/7.kmac_long_msg_and_output.797244207 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 7781211648 ps |
| CPU time | 376.49 seconds |
| Started | Sep 11 04:02:49 PM UTC 24 |
| Finished | Sep 11 04:09:10 PM UTC 24 |
| Peak memory | 475112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797244207 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_and_output.797244207 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/7.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/7.kmac_mubi.3800109722 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 6539669597 ps |
| CPU time | 82.76 seconds |
| Started | Sep 11 04:03:16 PM UTC 24 |
| Finished | Sep 11 04:04:41 PM UTC 24 |
| Peak memory | 262416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800109722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.3800109722 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/7.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/7.kmac_sideload.1755642890 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 4004965867 ps |
| CPU time | 96.05 seconds |
| Started | Sep 11 04:02:52 PM UTC 24 |
| Finished | Sep 11 04:04:30 PM UTC 24 |
| Peak memory | 261936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755642890 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.1755642890 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/7.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/7.kmac_smoke.828517221 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 146124110 ps |
| CPU time | 5.38 seconds |
| Started | Sep 11 04:02:47 PM UTC 24 |
| Finished | Sep 11 04:02:53 PM UTC 24 |
| Peak memory | 230508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828517221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.828517221 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/7.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/7.kmac_stress_all.2437926306 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 48446695959 ps |
| CPU time | 1038.81 seconds |
| Started | Sep 11 04:04:36 PM UTC 24 |
| Finished | Sep 11 04:22:06 PM UTC 24 |
| Peak memory | 571500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437926306 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.2437926306 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/7.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/8.kmac_alert_test.875475280 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 53655655 ps |
| CPU time | 1.2 seconds |
| Started | Sep 11 04:05:39 PM UTC 24 |
| Finished | Sep 11 04:05:41 PM UTC 24 |
| Peak memory | 216280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875475280 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.875475280 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/8.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/8.kmac_app.1887567060 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 6043951564 ps |
| CPU time | 113.65 seconds |
| Started | Sep 11 04:04:47 PM UTC 24 |
| Finished | Sep 11 04:06:43 PM UTC 24 |
| Peak memory | 337760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887567060 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.1887567060 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/8.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/8.kmac_app_with_partial_data.2281054667 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 37457129530 ps |
| CPU time | 273.93 seconds |
| Started | Sep 11 04:04:51 PM UTC 24 |
| Finished | Sep 11 04:09:29 PM UTC 24 |
| Peak memory | 405332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281054667 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.2281054667 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/8.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/8.kmac_burst_write.364877758 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 62366719726 ps |
| CPU time | 261.76 seconds |
| Started | Sep 11 04:04:45 PM UTC 24 |
| Finished | Sep 11 04:09:10 PM UTC 24 |
| Peak memory | 241452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364877758 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.364877758 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/8.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/8.kmac_edn_timeout_error.487115213 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 5528790867 ps |
| CPU time | 33.58 seconds |
| Started | Sep 11 04:05:24 PM UTC 24 |
| Finished | Sep 11 04:06:00 PM UTC 24 |
| Peak memory | 232628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487115213 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.487115213 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/8.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_mode_error.25603882 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 481084940 ps |
| CPU time | 13.48 seconds |
| Started | Sep 11 04:05:24 PM UTC 24 |
| Finished | Sep 11 04:05:39 PM UTC 24 |
| Peak memory | 234416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25603882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.25603882 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/8.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_ready_error.2772151503 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 10044773665 ps |
| CPU time | 13.25 seconds |
| Started | Sep 11 04:05:27 PM UTC 24 |
| Finished | Sep 11 04:05:41 PM UTC 24 |
| Peak memory | 230572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772151503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.2772151503 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/8.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_refresh.3291115286 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 31095516905 ps |
| CPU time | 134.93 seconds |
| Started | Sep 11 04:04:56 PM UTC 24 |
| Finished | Sep 11 04:07:13 PM UTC 24 |
| Peak memory | 323564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291115286 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.3291115286 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/8.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/8.kmac_error.3580950948 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 11680550573 ps |
| CPU time | 190.8 seconds |
| Started | Sep 11 04:05:19 PM UTC 24 |
| Finished | Sep 11 04:08:33 PM UTC 24 |
| Peak memory | 382748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580950948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.3580950948 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/8.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/8.kmac_key_error.4177229690 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1679612779 ps |
| CPU time | 9.19 seconds |
| Started | Sep 11 04:05:24 PM UTC 24 |
| Finished | Sep 11 04:05:35 PM UTC 24 |
| Peak memory | 232436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177229690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.4177229690 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/8.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/8.kmac_lc_escalation.1484993819 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 46443987 ps |
| CPU time | 2.79 seconds |
| Started | Sep 11 04:05:33 PM UTC 24 |
| Finished | Sep 11 04:05:36 PM UTC 24 |
| Peak memory | 230328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484993819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.1484993819 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/8.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/8.kmac_long_msg_and_output.963882277 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 109588644855 ps |
| CPU time | 3277.46 seconds |
| Started | Sep 11 04:04:41 PM UTC 24 |
| Finished | Sep 11 04:59:56 PM UTC 24 |
| Peak memory | 3933992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963882277 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_and_output.963882277 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/8.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/8.kmac_mubi.4149967433 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 2023488126 ps |
| CPU time | 139.08 seconds |
| Started | Sep 11 04:04:59 PM UTC 24 |
| Finished | Sep 11 04:07:21 PM UTC 24 |
| Peak memory | 278576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149967433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.4149967433 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/8.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/8.kmac_sideload.4202042422 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 3856154088 ps |
| CPU time | 328.14 seconds |
| Started | Sep 11 04:04:44 PM UTC 24 |
| Finished | Sep 11 04:10:16 PM UTC 24 |
| Peak memory | 362404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202042422 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.4202042422 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/8.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/8.kmac_smoke.3058352372 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 4670607519 ps |
| CPU time | 55.78 seconds |
| Started | Sep 11 04:04:41 PM UTC 24 |
| Finished | Sep 11 04:05:39 PM UTC 24 |
| Peak memory | 230528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058352372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.3058352372 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/8.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/8.kmac_stress_all.4018846586 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 84824329917 ps |
| CPU time | 766.22 seconds |
| Started | Sep 11 04:05:36 PM UTC 24 |
| Finished | Sep 11 04:18:31 PM UTC 24 |
| Peak memory | 772136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018846586 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.4018846586 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/8.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/8.kmac_stress_all_with_rand_reset.3806141392 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 21011186215 ps |
| CPU time | 431.02 seconds |
| Started | Sep 11 04:05:38 PM UTC 24 |
| Finished | Sep 11 04:12:55 PM UTC 24 |
| Peak memory | 333740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3806141392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all_ with_rand_reset.3806141392 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/9.kmac_alert_test.694304287 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 18019988 ps |
| CPU time | 1.16 seconds |
| Started | Sep 11 04:06:37 PM UTC 24 |
| Finished | Sep 11 04:06:39 PM UTC 24 |
| Peak memory | 216280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694304287 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.694304287 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/9.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/9.kmac_app.943893277 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 8497186493 ps |
| CPU time | 134.5 seconds |
| Started | Sep 11 04:05:45 PM UTC 24 |
| Finished | Sep 11 04:08:02 PM UTC 24 |
| Peak memory | 288856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943893277 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.943893277 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/9.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/9.kmac_app_with_partial_data.161877233 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 4946927536 ps |
| CPU time | 22.5 seconds |
| Started | Sep 11 04:05:58 PM UTC 24 |
| Finished | Sep 11 04:06:22 PM UTC 24 |
| Peak memory | 235232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161877233 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.161877233 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/9.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/9.kmac_burst_write.4071539570 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 85950289396 ps |
| CPU time | 905.88 seconds |
| Started | Sep 11 04:05:42 PM UTC 24 |
| Finished | Sep 11 04:20:59 PM UTC 24 |
| Peak memory | 251624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071539570 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.4071539570 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/9.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/9.kmac_edn_timeout_error.775832804 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 966385062 ps |
| CPU time | 17.57 seconds |
| Started | Sep 11 04:06:18 PM UTC 24 |
| Finished | Sep 11 04:06:37 PM UTC 24 |
| Peak memory | 235204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775832804 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.775832804 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/9.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_mode_error.3789677807 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 786162515 ps |
| CPU time | 26.31 seconds |
| Started | Sep 11 04:06:23 PM UTC 24 |
| Finished | Sep 11 04:06:50 PM UTC 24 |
| Peak memory | 232392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789677807 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.3789677807 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/9.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_ready_error.2172213993 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 5718633199 ps |
| CPU time | 53.73 seconds |
| Started | Sep 11 04:06:26 PM UTC 24 |
| Finished | Sep 11 04:07:21 PM UTC 24 |
| Peak memory | 230648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172213993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.2172213993 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/9.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_refresh.738950187 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 35404436119 ps |
| CPU time | 371.7 seconds |
| Started | Sep 11 04:06:00 PM UTC 24 |
| Finished | Sep 11 04:12:17 PM UTC 24 |
| Peak memory | 337644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738950187 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.738950187 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/9.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/9.kmac_error.3379014840 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 194847927531 ps |
| CPU time | 346.99 seconds |
| Started | Sep 11 04:06:17 PM UTC 24 |
| Finished | Sep 11 04:12:08 PM UTC 24 |
| Peak memory | 550700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379014840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.3379014840 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/9.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/9.kmac_key_error.896535022 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1555204656 ps |
| CPU time | 12.96 seconds |
| Started | Sep 11 04:06:18 PM UTC 24 |
| Finished | Sep 11 04:06:32 PM UTC 24 |
| Peak memory | 230660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896535022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.896535022 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/9.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/9.kmac_long_msg_and_output.1656632725 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 41239415800 ps |
| CPU time | 1352.35 seconds |
| Started | Sep 11 04:05:41 PM UTC 24 |
| Finished | Sep 11 04:28:29 PM UTC 24 |
| Peak memory | 2098992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656632725 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and_output.1656632725 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/9.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/9.kmac_mubi.149717440 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 835427817 ps |
| CPU time | 54.23 seconds |
| Started | Sep 11 04:06:14 PM UTC 24 |
| Finished | Sep 11 04:07:10 PM UTC 24 |
| Peak memory | 251944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149717440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.149717440 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/9.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/9.kmac_sideload.77745307 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 2690334441 ps |
| CPU time | 85.37 seconds |
| Started | Sep 11 04:05:42 PM UTC 24 |
| Finished | Sep 11 04:07:10 PM UTC 24 |
| Peak memory | 298844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77745307 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.77745307 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/9.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/9.kmac_smoke.134914347 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 1508078335 ps |
| CPU time | 43.75 seconds |
| Started | Sep 11 04:05:40 PM UTC 24 |
| Finished | Sep 11 04:06:26 PM UTC 24 |
| Peak memory | 235180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134914347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.134914347 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/9.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default/9.kmac_stress_all.3811644640 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 409588123939 ps |
| CPU time | 2627.78 seconds |
| Started | Sep 11 04:06:33 PM UTC 24 |
| Finished | Sep 11 04:50:50 PM UTC 24 |
| Peak memory | 2206004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811644640 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.3811644640 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/9.kmac_stress_all/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |